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Add the Analogix anx78xx driver so that the external display over HDMI
can be used on Nexus 5 phones.
Reviewed-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Brian Masney <masneyb@onstation.org>
Link: https://lore.kernel.org/r/20191024103140.10077-3-masneyb@onstation.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Add interconnect support for msm8974-based SoCs in order to support the
GPU on this platform.
Reviewed-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Brian Masney <masneyb@onstation.org>
Link: https://lore.kernel.org/r/20191024103140.10077-2-masneyb@onstation.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Commit 0e4a459f56c3 ("tracing: Remove unnecessary DEBUG_FS dependency")
removed select for DEBUG_FS but we still need it at least for enabling
deeper idle states for the SoCs.
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The TI_CPSW_SWITCHDEV definition in Kconfig was changed from "select
NET_SWITCHDEV" to "depends on NET_SWITCHDEV", and therefore it is required
to explicitelly enable NET_SWITCHDEV config option in omap2plus_defconfig.
Fixes: 3727d259ddaf ("arm: omap2plus_defconfig: enable new cpsw switchdev driver")
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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The phy mode should be rgmii-id. For some reason, it used to work with
rgmii-txid but doesn't any more.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
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Use aliases nodes to easy kizbox dts readability.
Signed-off-by: Kamel Bouhara <kamel.bouhara@bootlin.com>
Link: https://lore.kernel.org/r/20191205223021.1370083-1-kamel.bouhara@bootlin.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Specify the SoC SDCAL pin connection that is used in the
sama5d27c 128MiB SiP on the SAMA5D27 SOM1.
This will put in place a software workaround that would reduce power
consumption on all boards using this SoM, including the SAMA5D27 SOM1 EK.
Uses property introduced in 5cd41fe89704 ("dt-bindings: sdhci-of-at91:
add the microchip,sdcal-inverted property")
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20191205113604.9000-1-nicolas.ferre@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Pull-ups for SAM9 UART/USART TX lines were disabled in a previous
commit. However, several chips in the SAM9 family require pull-ups to
prevent the TX lines from falling (and causing an endless break
condition) when the transceiver is disabled.
From the SAM9G20 datasheet, 32.5.1: "To prevent the TXD line from
falling when the USART is disabled, the use of an internal pull up
is mandatory.". This commit reenables the pull-ups for all chips having
that sentence in their datasheets.
Fixes: 5e04822f7db5 ("ARM: dts: at91: fixes uart pinctrl, set pullup on rx, clear pullup on tx")
Signed-off-by: Ingo van Lil <inguin@gmx.de>
Cc: Peter Rosin <peda@axentia.se>
Link: https://lore.kernel.org/r/20191203142147.875227-1-inguin@gmx.de
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Add the Performance Monitoring Unit (PMU) device tree node to the H3
.dtsi, which tells DT users which interrupts are triggered by PMU
overflow events on each core. The numbers come from the manual and have
been checked in U-Boot and with perf in Linux.
Tested with perf record and taskset on an OrangePi Zero.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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Beelink X2 box comes with a remote. Add a mapping for it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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Emlid Neutis N5H3 is a version of Emlid Neutis SoM with H3 instead of H5
inside.
6eeb4180d4b9 ("ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device")
was used as reference.
Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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A new variant of Emlid Neutis has been inroduced. This one uses H3
instead of H5. The boards are essentially the same. This commit moves
non-SoC-specific parts out so that the common parts could be reused with
ease.
Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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<linux/vmalloc.h>
In the x86 MM code we'd like to untangle various types of historic
header dependency spaghetti, but for this we'd need to pass to
the generic vmalloc code various vmalloc related defines that
customarily come via the <asm/page.h> low level arch header.
Signed-off-by: Ingo Molnar <mingo@kernel.org>
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Signed-off-by: Ingo Molnar <mingo@kernel.org>
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Select DEBUG_AT91_RM9200_DBGU for SAM9X60 SoC.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1575035505-6310-8-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Move SAM9X60's PM part under SoC config flag. This allows the building
of SAM9X60 platform withouth depending on CONFIG_SOC_AT91SAM9 flag,
allowing us to select only necessary config flags for SAM9X60.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1575035505-6310-4-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Add config flag for SAM9X60 SoC.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/1575035505-6310-3-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Add SAM9X60's pll config flag. It was first used in
commit a436c2a447e5 ("clk: at91: add sam9x60 PLL driver").
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1575035505-6310-2-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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Set the frequency of the generated clock used by sdmmc devices in order
to not rely on the configuration done by previous components.
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Link: https://lore.kernel.org/r/20191128074522.69706-3-ludovic.desroches@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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The PMU registers are at least 0x18 bytes wide. Meson8b already uses a
size of 0x18. The structure of the PMU registers on Meson8 and Meson8b
is similar but not identical.
Meson8 and Meson8b have the following registers in common (starting at
AOBUS + 0xe0):
#define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2)
#define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2)
#define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2)
#define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2)
Meson8b additionally has these three registers:
#define AO_RTI_GEN_PWR_ACK0 0xf0 (0x3c << 2)
#define AO_RTI_PWR_A9_MEM_PD0 0xf4 (0x3d << 2)
#define AO_RTI_PWR_A9_MEM_PD1 0xf8 (0x3e << 2)
Thus we can assume that the register size of the PMU IP blocks is
identical on both SoCs (and Meson8 just contains some reserved registers
in that area) because the CEC registers start right after the PMU
(AO_RTI_*) registers at AOBUS + 0x100 (0x40 << 2).
The upcoming power domain driver will need to read and write the
AO_RTI_GEN_PWR_SLEEP0 and AO_RTI_GEN_PWR_ISO0 registers, so the updated
size is needed for that driver to work.
Fixes: 4a5a27116b447d ("ARM: dts: meson8: add support for booting the secondary CPU cores")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Add properties for i2c filters for i2c0 and i2c1 on sama5d27_som1_ek.
Noise is affecting communication on i2c for example when connecting i2c
camera sensors.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lore.kernel.org/r/1575531818-21332-1-git-send-email-eugen.hristev@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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This is the addition of a new Evaluation Kit the SAMA5D27-WLSOM1-EK.
It's based on the Microchip WireLess SoM which contains the
SAMA5D27 LPDDR2 2Gbits SiP.
[nicolas.ferre@microchip.com]: initial implementation
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
[eugen.hristev@microchip.com]: ported to new kernel version,
[eugen.hristev@microchip.com]: addition of peripherals (adc, pmic, qspi, uart)
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lore.kernel.org/r/1573543139-8533-4-git-send-email-eugen.hristev@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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The Security Module exposes the PIOBU pins which an be used
as regular GPIOs. The PIOBU pins are special because they do
not lose their voltage during suspend-to-mem.
This patch marks the secumod as a GPIO controller.
Signed-off-by: Andrei Stefanescu <andrei.stefanescu@microchip.com>
[razvan.stefanescu@microchip.com Updated title]
Signed-off-by: Razvan Stefanescu <razvan.stefanescu@microchip.com>
Link: https://lore.kernel.org/r/1573543139-8533-2-git-send-email-eugen.hristev@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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It will be enabled as needed by each board.
Signed-off-by: Razvan Stefanescu <razvan.stefanescu@microchip.com>
Link: https://lore.kernel.org/r/1573543139-8533-1-git-send-email-eugen.hristev@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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The MDIO node on Cygnus had an reversed #address-cells and
#size-cells properties, correct those.
Fixes: 40c26d3af60a ("ARM: dts: Cygnus: Add the ethernet switch and ethernet PHY")
Reported-by: Simon Horman <simon.horman@netronome.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Simon Horman <simon.horman@netronome.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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Raspberry Pi's firmware has a feature to select how much memory to
reserve for its GPU called 'gpu_mem'. The possible values go from 16MB
to 944MB, with a default of 64MB. This memory resides in the topmost
part of the lower 1GB memory area and grows bigger expanding towards the
begging of memory.
It turns out that with low 'gpu_mem' values (16MB and 32MB) the size of
the memory available to the system in the lower 1GB area can outgrow the
interconnect's dma-range as its size was selected based on the maximum
system memory available given the default gpu_mem configuration. This
makes that memory slice unavailable for DMA. And may cause nasty kernel
warnings if CMA happens to include it.
Change soc's dma-ranges to really reflect it's HW limitation, which is
being able to only DMA to the lower 1GB area.
Fixes: 7dbe8c62ceeb ("ARM: dts: Add minimal Raspberry Pi 4 support")
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Reviewed-by: Phil Elwell <phil@raspberrypi.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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Commit 9f532d26c75c ("ARM: exynos_defconfig: Trim and reorganize with
savedefconfig") removed explicit enable line for CONFIG_DEBUG_FS, because
that feature has been selected by other enabled options: CONFIG_TRACING,
which in turn had been selected by CONFIG_PERF_EVENTS and
CONFIG_PROVE_LOCKING.
In meantime, commit 0e4a459f56c3 ("tracing: Remove unnecessary DEBUG_FS
dependency") removed the dependency between CONFIG_DEBUG_FS and
CONFIG_TRACING, so CONFIG_DEBUG_FS is no longer enabled in default builds.
Enable it again explicitly, as debugfs support is essential for various
automated testing tools.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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The MDIO node on BCM5301X had an reversed #address-cells and
#size-cells properties, correct those, silencing checker warnings:
.../linux/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: mdio@18003000: #address-cells:0:0: 1 was expected
Reported-by: Simon Horman <simon.horman@netronome.com>
Fixes: 23f1eca6d59b ("ARM: dts: BCM5301X: Specify MDIO bus in the DT")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt
Samsung DTS ARM changes for v5.5, part 2
1. Cleanup by adjusting DTS to bindings,
2. Add touch-sensitive buttons to Midas (Galaxy S III family phones),
3. Add GPU/Mali to Exynos542x and Odroid XU3/XU4 family.
* tag 'samsung-dt-5.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: exynos: Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4
ARM: dts: exynos: Add support for the touch-sensitive buttons on Midas family
ARM: dts: exynos: Rename children of SysRAM node to "sram"
Link: https://lore.kernel.org/r/20191119142026.7190-1-krzk@kernel.org
Signed-off-by: Olof Johansson <olof@lixom.net>
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On stm32f7 family RTC node doesn't need clock-names property.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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On stm32f4 family RTC node doesn't need clock-names property.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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stm32mp15
When there is no activity on ethernet phy link, the ETH_GTX_CLK is cut.
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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ETH_MDIO slew-rate should be set to "0" instead of "2".
Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
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This reference design is very similar to the others just that
it has a different display mounted on the user interface
board, and some GPIOs where shuffled around.
As this is the first board that uses DB8520 we create the
DB8520-specific DTSI file here.
Cc: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20191126124738.77690-3-linus.walleij@linaro.org
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The TVK1281618 was made in R1, R2 and R3 variants. The most
commonly used variants are R2 and R3 so split out these to
their own files.
The R3 version has a totally different display than R1 and
R2 and a different set of sensors.
Cc: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20191126124738.77690-2-linus.walleij@linaro.org
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The DB8500 exists in an enhanced variant named DB8520
for some machines. To clearly distinguish between the
different machines, create an explicit db8500.dtsi
and move the operating points (only known difference so
far) to that file, so we can add an explicit db8520.dtsi
after this.
Cc: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191126124738.77690-1-linus.walleij@linaro.org
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The I2C block in the Ux500 uses internal pull-ups on the
SoC, in fact it has to: in HS mode, the I2C block will need
to autonomously take control over the pull-up line to do
its job. This can be clearly seen from the SoC manual which
states that the silicon has a line named "en_cspu_hs" which
enables current source pull-up for high speed mode. Another
hint is that the vendor code tree never enabled the pull
up on these lines, despite being deployed on boards that
lack external pull-up resistors.
Tested on the Ux500 reference designs without any problems.
Cc: Stephan Gerhold <stephan@gerhold.net>
Reported-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191126123116.56244-1-linus.walleij@linaro.org
Reviewed-by: Stephan Gerhold <stephan@gerhold.net>
Tested-by: Stephan Gerhold <stephan@gerhold.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The Ux500 device tree uses "arm,rtc-pl031" as compatible for PL031.
All other boards in Linux describe it using "arm,pl031" instead.
This works because the compatible is not actually used in Linux:
AMBA devices get probed based on "arm,primecell" and their peripheral ID.
Nevertheless, some other projects (e.g. U-Boot) rely on the compatible
to probe the device with the correct driver. Those will look for
"arm,pl031" instead of "arm,rtc-pl031", preventing the RTC from being
probed.
Change it to "arm,pl031" to match all other boards.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191124205110.48031-1-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The "soc" node in the Ux500 device tree does not need any special
handling - it is just a simple I/O bus that can be accessed without
additional configuration.
Therefore we can additionally describe it as compatible with "simple-bus".
This can be used by platforms to probe devices under the soc node without
special handling for our custom "stericsson,db8500" compatible
(e.g. in U-Boot).
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191124195728.32226-1-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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ux500_serial{0,1,2} are the only labels with ux500_ prefix in
ste-dbx5x0.dtsi, the other labels (gpio0, msp, ...) do not use
any prefix. Remove it for consistency.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125170428.76069-4-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Now that we have aliases for I2C and SPI in ste-dbx5x0.dtsi,
it does not make much sense to keep only the aliases for UART
separately in each board device tree.
Considering that all boards set the same aliases for the serial
ports there is no reason to keep them separated either.
Move them to ste-dbx5x0.dtsi and remove the aliases from the
board-specific device tree parts.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125170428.76069-3-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Now that we disable the I2C/SPI buses by default, is is even more
important to assign aliases to the I2C/SPI device nodes.
Otherwise, enabling/disabling one of them will potentially change
all device IDs, e.g. i2c2 will be named i2c-0 if it is the only
enabled I2C bus.
Add aliases for the I2C and SPI buses to avoid this.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125170428.76069-2-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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At the moment, all 5 I2C and 6 SPI buses are probed and exposed
to user-space by default - even if they are not muxed to any pins
on the board. This means that user-space sees an I2C/SPI bus that
cannot be actually used properly.
In some cases this was used to put the corresponding pins into
a low power sleep mode - but even then the pins first need to be
configured by the board-specific device tree part.
Avoid exposing unconfigured devices to user-space by disabling
the I2C/SPI buses by default. Enable them in the board device trees
when needed.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125170428.76069-1-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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ste-nomadik-pinctrl.dtsi already defines in_nopull and gpio_in_pu/pd,
but there is no node to configure a pin as GPIO without pull up/down.
Add a new &gpio_in_nopull node for this.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125122256.53482-5-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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UART1 can optionally be used with additional CTS/RTS pins.
The pinctrl driver has an extra "u1ctsrts_a_1" pin group for them.
Add a new pin configuration to configure them correctly if needed.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125122256.53482-4-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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SDI0/SDI1 can be used in configurations where some of the pins
(e.g. direction control) are not used. The pinctrl driver has
separate pin groups for them.
Add new pin configurations for:
- mc0_a_2: like mc0_a_1, but without CMDDIR/DAT0DIR/DAT2DIR
- mc1_a_2: like mc1_a_1, but without FBCLK
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125122256.53482-3-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Some components (e.g. SDI, I2C) can be used with different pin assignments.
Before we can add the alternative configurations, we need to rename the
current configurations to more generic names.
Each pin configuration usually configures one specific pin group.
Therefore we rename the configurations to use the pin group as name.
Make up for the slightly longer names by removing the "_mode" suffix.
Rename all existing uses to use the new labels.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125122256.53482-2-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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All existing Ux500 boards make use of ste-href-family-pinctrl.dtsi,
which contains shared pin configurations for UART, I2C and SDI.
Most of these can be also used for devices not based on HREF.
Move the generic pin configs into a new device tree include
"ste-dbx5x0-pinctrl.dtsi". There is no functional change (yet),
as a next step we will rename the pin configs to use more generic
names.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191125122256.53482-1-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Commit a435adbec264 ("ARM: dts: augment Ux500 to use DT cpufreq")
switched the Ux500 device tree to use the generic DT cpufreq driver
and removed the PRCMU cpufreq node.
The snowball DTS still references it, without effect, since cpufreq
is now enabled by default. Remove the unused node.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20191117222732.283673-1-stephan@gerhold.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This adds the IIO channels for the GPADC after converting it
to using the standard IIO ADC bindings and moving the driver
over to the IIO subsystem. We also add IIO hwmon standard
driver node to support reading channels in a standard manner.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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