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2020-07-21ARM: davinci: Replace HTTP links with HTTPS onesAlexander A. Klimov
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> [nsekhar@ti.com: drop obsolete hawkboard.org URL completeley fixup subject line prefix] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2020-07-21usb: ohci-omap: Convert to use GPIO descriptorsLinus Walleij
The OMAP1 OHCI driver is using the legacy GPIO API to grab some random GPIO lines. One is from the TPS65010 chip and used for power, another one is for overcurrent and while the driver picks this line it doesn't watch it at all. Convert the driver and the OMAP1 OSK board file to pass these two GPIOs as machine described GPIO descriptors. I noticed the overcurrent GPIO line is not really used in the code so dropped in a little comment for other developers. Cc: Janusz Krzysztofik <jmkrzyszt@gmail.com> Cc: Tony Lindgren <tony@atomide.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20200720135524.100374-2-linus.walleij@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2020-07-21asm/rwonce: Don't pull <asm/barrier.h> into 'asm-generic/rwonce.h'Will Deacon
Now that 'smp_read_barrier_depends()' has gone the way of the Norwegian Blue, drop the inclusion of <asm/barrier.h> in 'asm-generic/rwonce.h'. This requires fixups to some architecture vdso headers which were previously relying on 'asm/barrier.h' coming in via 'linux/compiler.h'. Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Will Deacon <will@kernel.org>
2020-07-21ARM: dts: stm32: enable usb-role-switch on USB OTG on stm32mp15xx-dkxAmelie Delaunay
Now that USB OTG driver supports usb role switch by overriding PHY input signals (A-Valid, B-Valid and Vbus-Valid), enable it on stm32mp15xx-dkx. dr_mode needn't to be forced to Peripheral anymore, it is set to OTG in SoC device tree. USB role (USB_ROLE_NONE, USB_ROLE_DEVICE, USB_ROLE_HOST) will be provided by STUSB1600 Type-C controller driver. This patch depends on "Add STUSB160x Type-C port controller support" series, which is under review. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-07-21ARM: dts: stm32: Add compatibles for syscon for stm32mp151Benjamin Gaignard
Syscon nodes needs at least 2 compatibles to be compliant why yaml documentation. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-07-21ARM: dts: stm32: Add compatibles for syscon for stm32h743Benjamin Gaignard
Syscon nodes needs at least 2 compatibles to be compliant why yaml documentation. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-07-21ARM: dts: stm32: Add compatibles for syscon for stm32f746Benjamin Gaignard
Syscon nodes needs at least 2 compatibles to be compliant why yaml documentation. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-07-21ARM: dts: stm32: Add compatibles for syscon for stm32f426Benjamin Gaignard
Syscon nodes needs at least 2 compatibles to be compliant why yaml documentation. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-07-21ARM: dts: stm32: Fix spi4 pins in stm32mp15-pinctrlPatrick Delaunay
Move spi4_pins_a nodes from pinctrl_z to pinctrl as the associated pins are not in BANK Z. Fixes: 498a7014989d ("ARM: dts: stm32: Add missing pinctrl entries for STM32MP15") Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-07-21ARM: dts: stm32: configure i2c5 support on stm32mp15xx-dkxFabrice Gasnier
Configure I2C5 on stm32mp15 DK boards. It's available and can be used on: - Arduino connector - GPIO expansion connector Keep it disabled by default, so the pins are kept in their initial state to lower power consumption. This way they can also be used as GPIO. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com> Signed-off-by: Alain Volmat <alain.volmat@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-07-21ARM: dts: stm32: add usart2 node to stm32mp157c-dk2Erwan Le Ray
Adds the usart2 node to stm32mp157c-dk2 board. usart2 pins are connected to Bluetooth component. usart2 is disabled by default. Signed-off-by: Erwan Le Ray <erwan.leray@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-07-21ARM: dts: stm32: add uart7 support to stm32mp15xx-dkx boardsErwan Le Ray
Adds uart7 node to stm32mp15xx-dkx and uart7 alias to stm32mp157a-dk1 and stm32mp157c-dk2 boards. uart7 pins are connected to Arduino connector. uart7 is disabled by default. Signed-off-by: Erwan Le Ray <erwan.leray@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-07-21ARM: dts: stm32: add usart3 node to stm32mp157c-ev1Erwan Le Ray
Adds the usart3 node to stm32mp157c-ev1 board. usart3 pins are connected to GPIO Expansion connector. usart3 is disabled by default. Signed-off-by: Erwan Le Ray <erwan.leray@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-07-21ARM: dts: stm32: add usart3 node to stm32mp15xx-dkx boardsErwan Le Ray
Adds usart3 node to stm32mp15xx-dkx and usart3 alias to stm32mp157a-dk1 and stm32mp157c-dk2 boards. usart3 pins are connected to GPIO Expansion connector. usart3 is disabled by default. Signed-off-by: Erwan Le Ray <erwan.leray@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-07-21ARM: dts: stm32: add usart2, usart3 and uart7 pins in stm32mp15-pinctrlErwan Le Ray
Adds usart2_pins_c, usart3_pins_b, usart3_pins_c and uart7_pins_c pins configurations in stm32mp15-pinctrl. - usart2_pins_c pins are connected to Bluetooth chip on dk2 board. - usart3_pins_b pins are connected to GPIO expansion connector on evx board. - usart3_pins_c pins are connected to GPIO expansion connector on dkx board. - uart7_pins_c pins are connected to Arduino Uno connector on dkx board. Signed-off-by: Erwan Le Ray <erwan.leray@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-07-21ARM: dts: stm32: cosmetic updates in stm32mp15-pinctrlPatrick Delaunay
Use tabs where possible and remove multiple blanks lines. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2020-07-20Merge tag 'sunxi-config-for-5.9-1' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/defconfig A bunch of patches to generally make sunxi_defconfig more helpful and add all the new drivers merged recently. * tag 'sunxi-config-for-5.9-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: configs: sunxi: Enable crypto related options ARM: sunxi: configs: Enable the Mailbox driver ARM: configs: sunxi: Enable the PS/2 controller ARM: configs: sunxi: Enable Lima ARM: configs: sunxi: Add DRM output-related options ARM: configs: sunxi: Enable ASoC options ARM: configs: sunxi: Enable Cedrus ARM: configs: sunxi: Enable the deinterlace and rotation engines ARM: configs: sunxi: Enable the CSI drivers ARM: configs: sunxi: Run savedefconfig Link: https://lore.kernel.org/r/c74e64c9-f1f2-40ee-b4cd-c1430d32cf8d.lettre@localhost Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-20Merge tag 'tegra-for-5.9-arm-defconfig' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/defconfig ARM: tegra: Default configuration changes for v5.9-rc1 Enables a few new configuration options that are useful on the new Nexus 7 and Acer A500 devices, as well as the userspace CPU frequency governor that's mainly used for testing. * tag 'tegra-for-5.9-arm-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra_defconfig: Enable options useful for Nexus 7 and Acer A500 ARM: tegra: Enable CPUFREQ userspace governor Link: https://lore.kernel.org/r/20200717161300.1661002-6-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-20ARM: dts: exynos: Replace HTTP links with HTTPS onesAlexander A. Klimov
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-07-20ARM: s3c24xx: Replace HTTP links with HTTPS onesAlexander A. Klimov
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-07-20ARM: dts: sunxi: bananapi-m2-plus-v1.2: Fix CPU supply voltagesChen-Yu Tsai
The Bananapi M2+ uses a GPIO line to change the effective resistance of the CPU supply regulator's feedback resistor network. The voltages described in the device tree were given directly by the vendor. This turns out to be slightly off compared to the real values. The updated voltages are based on calculations of the feedback resistor network, and verified down to three decimal places with a multi-meter. Fixes: 6eeb4180d4b9 ("ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device trees") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200717160053.31191-4-wens@kernel.org
2020-07-20ARM: dts: sunxi: bananapi-m2-plus-v1.2: Add regulator supply to all CPU coresChen-Yu Tsai
The device tree currently only assigns the a supply for the first CPU core, when in reality the regulator supply is shared by all four cores. This might cause an issue if the implementation does not realize the sharing of the supply. Assign the same regulator supply to the remaining CPU cores to address this. Fixes: 6eeb4180d4b9 ("ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device trees") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200717160053.31191-3-wens@kernel.org
2020-07-20ARM: dts: sunxi: libretech-all-h3-cc: Add regulator supply to all CPU coresChen-Yu Tsai
The device tree currently only assigns the a supply for the first CPU core, when in reality the regulator supply is shared by all four cores. This might cause an issue if the implementation does not realize the sharing of the supply. Assign the same regulator supply to the remaining CPU cores to address this. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200717160053.31191-2-wens@kernel.org
2020-07-20ARM: dts: at91: sama5d3_xplained: change phy-modeAlexandre Belloni
Since commit bcf3440c6dd7 ("net: phy: micrel: add phy-mode support for the KSZ9031 PHY"), networking is broken on sama5d3 xplained. The device tree has phy-mode = "rgmii" and this worked before, because KSZ9031 PHY started with default RGMII internal delays configuration (TX off, RX on 1.2 ns) and MAC provided TX delay. After above commit, the KSZ9031 PHY starts handling phy mode properly and disables RX delay, as result networking is become broken. Fix it by switching to phy-mode = "rgmii-rxid" to reflect previous behavior. Fixes: bcf3440c6dd78bfe ("net: phy: micrel: add phy-mode support for the KSZ9031 PHY") Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20200717233644.841080-1-alexandre.belloni@bootlin.com
2020-07-20ARM: dts: ux500-skomer: Correct accel mounting matrixLinus Walleij
This corrects the mounting matrix for the BMA254 accelerometer to what makes PostmarketOS actually orient the screen the right way on this device. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20200719201603.3610389-1-linus.walleij@linaro.org
2020-07-20ARM: dts: exynos: Disable frequency scaling for FSYS bus on Odroid XU3 familyMarek Szyprowski
Commit 1019fe2c7280 ("ARM: dts: exynos: Adjust bus related OPPs to the values correct for Exynos5422 Odroids") changed the parameters of the OPPs for the FSYS bus. Besides the frequency adjustments, it also removed the 'shared-opp' property from the OPP table used for FSYS_APB and FSYS busses. This revealed that in fact the FSYS bus frequency scaling never worked. When one OPP table is marked as 'opp-shared', only the first bus which selects the OPP sets the rate of its clock. Then OPP core assumes that the other busses have been changed to that OPP and no change to their clock rates are needed. Thus when FSYS_APB bus, which was registered first, set the rate for its clock, the OPP core did not change the FSYS bus clock later. The mentioned commit removed that behavior, what introduced a regression on some Odroid XU3 boards. Frequency scaling of the FSYS bus causes instability of the USB host operation, what can be observed as network hangs. To restore old behavior, simply disable frequency scaling for the FSYS bus. Reported-by: Willy Wolff <willy.mh.wolff.ml@gmail.com> Fixes: 1019fe2c7280 ("ARM: dts: exynos: Adjust bus related OPPs to the values correct for Exynos5422 Odroids") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2020-07-20ARM: dts: aspeed: tacoma: Fix gpio-key definitionsJoel Stanley
This patch was applied twice. Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-20ARM: dts: rainier: Configure ball Y23 as GPIOP7 for MCLR_VPPAndrew Jeffery
GPIOP7 is used in the Rainier design to manage the state of a microcontroller elsewhere in the system but its ball, Y23, is the driver of the heartbeat LED on the ast2600-evb and the SoC defaults Y23 at power-on to the pulse-train behaviour used to drive the LED. This causes much confusion for the micro in the Rainier system, so hog the line as early as possible. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-20ARM: dts: aspeed: rainier: Add second cfam on the hubEddie James
The hub FSI master can access the cfams on two other processors. Reflect this by adding a second cfam to the first hub description. Signed-off-by: Eddie James <eajames@linux.ibm.com> Tested-by: Andrew Geissler <geissonator@yahoo.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-20ARM: dts: aspeed: rainier: Add line-name checkstopBen Tyner
Rainier uses GPIO B6 as the checkstop GPIO. Define the line-name so that this GPIO can be found by name. Signed-off-by: Ben Tyner <ben.tyner@ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-20ARM: dts: aspeed: tacoma: Remove checkstop gpio-keyBen Tyner
The attention handler will monitor the checkstop gpio via the character device interface so it needs to not be defined. Signed-off-by: Ben Tyner <ben.tyner@ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-20ARM: dts: aspeed: tacoma: Enable XDMA engineEddie James
Add a reserved memory node for the VGA memory. Add the XDMA engine node, enable it, and point it's memory region to the VGA memory. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-20ARM: dts: aspeed: witherspoon: Enable XDMA engineEddie James
Add a reserved memory node for the VGA memory. Add the XDMA engine node, enable it, and point it's memory region to the VGA memory. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-20ARM: dts: aspeed: ast2600: Update XDMA engine nodeEddie James
Add the PCI-E root complex reset, correct the pcie-device property, and add the Aspeed SCU interrupt controller include. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-20ARM: dts: aspeed: ast2500: Update XDMA engine nodeEddie James
Correct the pcie-device property, and add the Aspeed SCU interrupt controller include. Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-07-20ARM: dts: imx6qdl-icore: Fix OTG_ID pin and sdcard detectMichael Trimarchi
The current pin muxing scheme muxes GPIO_1 pad for USB_OTG_ID because of which when card is inserted, usb otg is enumerated and the card is never detected. [ 64.492645] cfg80211: failed to load regulatory.db [ 64.492657] imx-sdma 20ec000.sdma: external firmware not found, using ROM firmware [ 76.343711] ci_hdrc ci_hdrc.0: EHCI Host Controller [ 76.349742] ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 2 [ 76.388862] ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00 [ 76.396650] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.08 [ 76.405412] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 [ 76.412763] usb usb2: Product: EHCI Host Controller [ 76.417666] usb usb2: Manufacturer: Linux 5.8.0-rc1-next-20200618 ehci_hcd [ 76.424623] usb usb2: SerialNumber: ci_hdrc.0 [ 76.431755] hub 2-0:1.0: USB hub found [ 76.435862] hub 2-0:1.0: 1 port detected The TRM mentions GPIO_1 pad should be muxed/assigned for card detect and ENET_RX_ER pad for USB_OTG_ID for proper operation. This patch fixes pin muxing as per TRM and is tested on a i.Core 1.5 MX6 DL SOM. [ 22.449165] mmc0: host does not support reading read-only switch, assuming write-enable [ 22.459992] mmc0: new high speed SDHC card at address 0001 [ 22.469725] mmcblk0: mmc0:0001 EB1QT 29.8 GiB [ 22.478856] mmcblk0: p1 p2 Fixes: 6df11287f7c9 ("ARM: dts: imx6q: Add Engicam i.CoreM6 Quad/Dual initial support") Cc: stable@vger.kernel.org Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-20ARM: dts: vf610-zii-ssmb-spu3: Add node for switch watchdogChris Healy
Add I2C child node for switch watchdog present on SPU3 Signed-off-by: Chris Healy <cphealy@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-20ARM: dts: vf610-zii-ssmb-dtu: Add no-sdio/no-sd propertiesChris Healy
esdhc0 is connected to an eMMC, so it is safe to pass the "no-sdio"/"no-sd" properties. esdhc1 is wired to a standard SD socket, so pass the "no-sdio" property. Signed-off-by: Chris Healy <cphealy@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-20ARM: dts: imx6sx-sabreauto: Fix the phy-mode on fec2Fabio Estevam
Commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode") fixed the phy-mode for fec1, but missed to fix it for the fec2 node. Fix fec2 to also use "rgmii-id" as the phy-mode. Cc: <stable@vger.kernel.org> Fixes: 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode") Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-20ARM: dts: imx6sx-sdb: Fix the phy-mode on fec2Fabio Estevam
Commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode") fixed the phy-mode for fec1, but missed to fix it for the fec2 node. Fix fec2 to also use "rgmii-id" as the phy-mode. Cc: <stable@vger.kernel.org> Fixes: 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode") Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-20ARM: dts: imx6q-tbs2910: Pass reset-assert-usFabio Estevam
According to the AR8035 datasheet: "When using crystal, the clock is generated internally after power is stable. For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied." Pass the 'reset-assert-us' property to describe such requirement. While at it, use the 'reset-gpios' property inside the the mdio node instead of the deprecated usage of 'phy-reset-gpios'. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Soeren Moch <smoch@web.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-20ARM: dts: imx6q-tbs2910: Add an mdio nodeFabio Estevam
imx6q-tbs2910 has an Atheros AR8035 Ethernet PHY at address 4. The AR8035 provides a 125MHz clock to the ENET_REF_CLK i.MX6 pin. Improve the Ethernet representation by adding an mdio node with such information. This fixes an Ethernet regression in U-Boot as U-Boot AR803X driver now expects the 'qca,clk-out-frequency' property to be passed via device tree. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Soeren Moch <smoch@web.de> Tested-by: Soeren Moch <smoch@web.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-20ARM: dts: imx6qdl-sabresd: Pass reset-assert-usFabio Estevam
According to the AR8031 datasheet: "When using crystal, clock is generated internally after the power is stable. In order to get reliable power-on-reset, it is recommended to keep asserting the reset low signal long enough (10 ms) to ensure the clock is stable and clock-to-reset (1 ms) requirement is satisfied." Pass the 'reset-assert-us' property to describe such requirement. While at it, use the 'reset-gpios' property inside the the mdio node instead of the deprecated usage of 'phy-reset-gpios'. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Soeren Moch <smoch@web.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-20ARM: dts: imx6qdl-sabresd: Add an mdio nodeFabio Estevam
imx6qdl-sabresd has an Atheros AR8031 Ethernet PHY at address 1. The AR8031 provides a 125MHz clock to the ENET_REF_CLK i.MX6 pin. Improve the Ethernet representation by adding an mdio node with such information. An advantage of adding the mdio node is that the AR8031 initialization code in the mx6sabresd board file in U-Boot can totally be removed. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Soeren Moch <smoch@web.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-20ARM: dts: imx6qdl-gw: add Gateworks System Controller supportTim Harvey
Add Gateworks System Controller support to Gateworks Ventana boards: - add dt bindings for GSC mfd driver and hwmon driver for ADC's and fan controllers. - add dt bindings for gpio-keys driver for push-button and interrupt events Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-07-19dma-mapping: make support for dma ops optionalChristoph Hellwig
Avoid the overhead of the dma ops support for tiny builds that only use the direct mapping. Signed-off-by: Christoph Hellwig <hch@lst.de> Tested-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
2020-07-18ARM: dts: socfpga: add the temperature sensor to the Arria10 devkitDinh Nguyen
Add the Maxim max1619 temp sensor that is on the Arria10 devkit. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2020-07-18arm: dts: socfpga: add reset-names to spi nodeDinh Nguyen
Add reset-names = "spi" to spi dts nodes. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2020-07-18ARM: dts: dlink-dns327l: fix reg-init PHYDaniel González Cabanelas
The marvell PHY reg-init registers for the D-Link DNS-327L are wrong. Currently the first field is used to set the page 2, but this is pointless. The usage is not correct, and we are setting the wrong registers. Fix it. Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-07-18ARM: orion/gpio: Make use of for_each_requested_gpio()Andy Shevchenko
Make use of for_each_requested_gpio() instead of home grown analogue. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Gregory Clement <gregory.clement@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
generated by cgit (git 2.34.1) at 2025-09-23 13:02:14 +0000