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2019-12-11ARM: net: bpf: Improve prologue code sequenceRussell King
Improve the prologue code sequence to be able to take advantage of 64-bit stores, changing the code from: push {r4, r5, r6, r7, r8, r9, fp, lr} mov fp, sp sub ip, sp, #80 ; 0x50 sub sp, sp, #600 ; 0x258 str ip, [fp, #-100] ; 0xffffff9c mov r6, #0 str r6, [fp, #-96] ; 0xffffffa0 mov r4, #0 mov r3, r4 mov r2, r0 str r4, [fp, #-104] ; 0xffffff98 str r4, [fp, #-108] ; 0xffffff94 to the tighter: push {r4, r5, r6, r7, r8, r9, fp, lr} mov fp, sp mov r3, #0 sub r2, sp, #80 ; 0x50 sub sp, sp, #600 ; 0x258 strd r2, [fp, #-100] ; 0xffffff9c mov r2, #0 strd r2, [fp, #-108] ; 0xffffff94 mov r2, r0 resulting in a saving of three instructions. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Link: https://lore.kernel.org/bpf/E1ieH2g-0004ih-Rb@rmk-PC.armlinux.org.uk
2019-12-11ARM: imx: Correct ocotp id for serial number support of i.MX6ULL/ULZ SoCsChristoph Niedermaier
After the commit 8267ff89b713 ("ARM: imx: Add serial number support for i.MX6/7 SoCs") the kernel doesn't start on i.MX6ULL/ULZ SoC. Tested on next-20191205. For i.MX6ULL/ULZ the variable "ocotp_compat" is set to "fsl,imx6ul-ocotp", but with commit ffbc34bf0e9c ("nvmem: imx-ocotp: Implement i.MX6ULL/ULZ support") and commit f243bc821ee3 ("ARM: dts: imx6ull: Fix i.MX6ULL/ULZ ocotp compatible") the value "fsl,imx6ull-ocotp" is already defined and set in device tree... By setting "ocotp_compat" to "fsl,imx6ull-ocotp" the kernel does boot. Fixes: 8267ff89b713 ("ARM: imx: Add serial number support for i.MX6/7 SoCs") Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-11ARM: configs: imx_v6_v7_defconfig: enable USB ACMPeter Chen
It is used for USB CDC ACM function. Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-11ARM: dts: imx7ulp-com: Add initial support for i.MX7UP COM boardFabio Estevam
The Embedded Artists COM board is based on NXP i.MX7ULP. It has a BD70528 PMIC from Rohm with discrete DCDC powering option and improved current observability (compared to the existing NXP i.MX7ULP EVK). Add the initial support for the board. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-12-10ARM: dts: rockchip: Add brcm bluetooth for rk3288-veyronAbhishek Pandit-Subedi
This enables the Broadcom uart bluetooth driver on uart0 and gives it ownership of its gpios. In order to use this, you must enable the following kconfig options: - CONFIG_BT_HCIUART_BCM - CONFIG_SERIAL_DEV This is applicable to rk3288-veyron series boards that use the bcm43540 wifi+bt chips. As part of this change, also refactor the pinctrl across the various boards. All the boards using broadcom bluetooth shouldn't touch the bt_dev_wake pin. Signed-off-by: Abhishek Pandit-Subedi <abhishekpandit@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/20191127223909.253873-2-abhishekpandit@chromium.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-12-10ARM: dts: bcm283x: Fix critical trip pointStefan Wahren
During definition of the CPU thermal zone of BCM283x SoC family there was a misunderstanding of the meaning "criticial trip point" and the thermal throttling range of the VideoCore firmware. The latter one takes effect when the core temperature is at least 85 degree celsius or higher So the current critical trip point doesn't make sense, because the thermal shutdown appears before the firmware has a chance to throttle the ARM core(s). Fix these unwanted shutdowns by increasing the critical trip point to a value which shouldn't be reached with working thermal throttling. Fixes: 0fe4d2181cc4 ("ARM: dts: bcm283x: Add CPU thermal zone with 1 trip point") Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-12-10ARM: dts: msm8974-FP2: Introduce the wcnss remoteproc nodeLuca Weiss
Enable the remoteproc node and add the necessary pinctrl states. Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20191104212302.105469-2-luca@z3ntu.xyz Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-10ARM: dts: msm8974: Introduce the wcnss remoteproc nodeBjorn Andersson
Signed-off-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Luca Weiss <luca@z3ntu.xyz> Link: https://lore.kernel.org/r/20191104212302.105469-1-luca@z3ntu.xyz Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-10ARM: dts: qcom: msm8974: add interconnect nodesBrian Masney
Add interconnect nodes that's needed to support bus scaling. Signed-off-by: Brian Masney <masneyb@onstation.org> Link: https://lore.kernel.org/r/20191024103140.10077-5-masneyb@onstation.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-10ARM: dts: qcom: msm8974: add ocmem nodeBrian Masney
Add ocmem node that is needed in order to support the GPU upstream. Signed-off-by: Brian Masney <masneyb@onstation.org> Link: https://lore.kernel.org/r/20191024103140.10077-4-masneyb@onstation.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-10ARM: qcom_defconfig: add anx78xx HDMI bridge supportBrian Masney
Add the Analogix anx78xx driver so that the external display over HDMI can be used on Nexus 5 phones. Reviewed-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Brian Masney <masneyb@onstation.org> Link: https://lore.kernel.org/r/20191024103140.10077-3-masneyb@onstation.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-10ARM: qcom_defconfig: add msm8974 interconnect supportBrian Masney
Add interconnect support for msm8974-based SoCs in order to support the GPU on this platform. Reviewed-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Brian Masney <masneyb@onstation.org> Link: https://lore.kernel.org/r/20191024103140.10077-2-masneyb@onstation.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2019-12-10ARM: omap2plus_defconfig: Add back DEBUG_FSTony Lindgren
Commit 0e4a459f56c3 ("tracing: Remove unnecessary DEBUG_FS dependency") removed select for DEBUG_FS but we still need it at least for enabling deeper idle states for the SoCs. Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-12-10ARM: omap2plus_defconfig: enable NET_SWITCHDEVGrygorii Strashko
The TI_CPSW_SWITCHDEV definition in Kconfig was changed from "select NET_SWITCHDEV" to "depends on NET_SWITCHDEV", and therefore it is required to explicitelly enable NET_SWITCHDEV config option in omap2plus_defconfig. Fixes: 3727d259ddaf ("arm: omap2plus_defconfig: enable new cpsw switchdev driver") Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-12-10ARM: dts: am335x-sancloud-bbe: fix phy modeMans Rullgard
The phy mode should be rgmii-id. For some reason, it used to work with rgmii-txid but doesn't any more. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-12-10ARM: dts: at91: rearrange kizbox dts using aliases nodesKamel Bouhara
Use aliases nodes to easy kizbox dts readability. Signed-off-by: Kamel Bouhara <kamel.bouhara@bootlin.com> Link: https://lore.kernel.org/r/20191205223021.1370083-1-kamel.bouhara@bootlin.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-10ARM: dts: at91: sama5d27_som1_ek: add the microchip,sdcal-inverted on sdmmc0Nicolas Ferre
Specify the SoC SDCAL pin connection that is used in the sama5d27c 128MiB SiP on the SAMA5D27 SOM1. This will put in place a software workaround that would reduce power consumption on all boards using this SoM, including the SAMA5D27 SOM1 EK. Uses property introduced in 5cd41fe89704 ("dt-bindings: sdhci-of-at91: add the microchip,sdcal-inverted property") Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20191205113604.9000-1-nicolas.ferre@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-10ARM: dts: at91: Reenable UART TX pull-upsIngo van Lil
Pull-ups for SAM9 UART/USART TX lines were disabled in a previous commit. However, several chips in the SAM9 family require pull-ups to prevent the TX lines from falling (and causing an endless break condition) when the transceiver is disabled. From the SAM9G20 datasheet, 32.5.1: "To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.". This commit reenables the pull-ups for all chips having that sentence in their datasheets. Fixes: 5e04822f7db5 ("ARM: dts: at91: fixes uart pinctrl, set pullup on rx, clear pullup on tx") Signed-off-by: Ingo van Lil <inguin@gmx.de> Cc: Peter Rosin <peda@axentia.se> Link: https://lore.kernel.org/r/20191203142147.875227-1-inguin@gmx.de Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-10arm: dts: allwinner: H3: Add PMU nodeAndre Przywara
Add the Performance Monitoring Unit (PMU) device tree node to the H3 .dtsi, which tells DT users which interrupts are triggered by PMU overflow events on each core. The numbers come from the manual and have been checked in U-Boot and with perf in Linux. Tested with perf record and taskset on an OrangePi Zero. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-10ARM: dts: sun8i: h3: Add rc map for Beelink X2Jernej Skrabec
Beelink X2 box comes with a remote. Add a mapping for it. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-10ARM: dts: sunxi: Add Neutis N5H3 supportGeorgii Staroselskii
Emlid Neutis N5H3 is a version of Emlid Neutis SoM with H3 instead of H5 inside. 6eeb4180d4b9 ("ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device") was used as reference. Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-10ARM: dts: allwinner: Split out non-SoC specific parts of Neutis N5Georgii Staroselskii
A new variant of Emlid Neutis has been inroduced. This one uses H3 instead of H5. The boards are essentially the same. This commit moves non-SoC-specific parts out so that the common parts could be reused with ease. Signed-off-by: Georgii Staroselskii <georgii.staroselskii@emlid.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
2019-12-10mm/vmalloc: Add empty <asm/vmalloc.h> headers and use them from ↵Ingo Molnar
<linux/vmalloc.h> In the x86 MM code we'd like to untangle various types of historic header dependency spaghetti, but for this we'd need to pass to the generic vmalloc code various vmalloc related defines that customarily come via the <asm/page.h> low level arch header. Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-12-10Merge tag 'v5.5-rc1' into core/kprobes, to resolve conflictsIngo Molnar
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2019-12-10ARM: debug-ll: select DEBUG_AT91_RM9200_DBGU for sam9x60Claudiu Beznea
Select DEBUG_AT91_RM9200_DBGU for SAM9X60 SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1575035505-6310-8-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-10ARM: at91: pm: move SAM9X60's PM under its own SoC config flagClaudiu Beznea
Move SAM9X60's PM part under SoC config flag. This allows the building of SAM9X60 platform withouth depending on CONFIG_SOC_AT91SAM9 flag, allowing us to select only necessary config flags for SAM9X60. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1575035505-6310-4-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-10ARM: at91: Kconfig: add config flag for SAM9X60 SoCClaudiu Beznea
Add config flag for SAM9X60 SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/1575035505-6310-3-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-10ARM: at91: Kconfig: add sam9x60 pll config flagClaudiu Beznea
Add SAM9X60's pll config flag. It was first used in commit a436c2a447e5 ("clk: at91: add sam9x60 PLL driver"). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1575035505-6310-2-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-10ARM: dts: at91: sama5d2: set the sdmmc gclk frequencyLudovic Desroches
Set the frequency of the generated clock used by sdmmc devices in order to not rely on the configuration done by previous components. Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20191128074522.69706-3-ludovic.desroches@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-09ARM: dts: meson8: fix the size of the PMU registersMartin Blumenstingl
The PMU registers are at least 0x18 bytes wide. Meson8b already uses a size of 0x18. The structure of the PMU registers on Meson8 and Meson8b is similar but not identical. Meson8 and Meson8b have the following registers in common (starting at AOBUS + 0xe0): #define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2) #define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2) #define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2) #define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2) Meson8b additionally has these three registers: #define AO_RTI_GEN_PWR_ACK0 0xf0 (0x3c << 2) #define AO_RTI_PWR_A9_MEM_PD0 0xf4 (0x3d << 2) #define AO_RTI_PWR_A9_MEM_PD1 0xf8 (0x3e << 2) Thus we can assume that the register size of the PMU IP blocks is identical on both SoCs (and Meson8 just contains some reserved registers in that area) because the CEC registers start right after the PMU (AO_RTI_*) registers at AOBUS + 0x100 (0x40 << 2). The upcoming power domain driver will need to read and write the AO_RTI_GEN_PWR_SLEEP0 and AO_RTI_GEN_PWR_ISO0 registers, so the updated size is needed for that driver to work. Fixes: 4a5a27116b447d ("ARM: dts: meson8: add support for booting the secondary CPU cores") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-12-09ARM: dts: at91: sama5d27_som1_ek: add i2c filters propertiesEugen Hristev
Add properties for i2c filters for i2c0 and i2c1 on sama5d27_som1_ek. Noise is affecting communication on i2c for example when connecting i2c camera sensors. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lore.kernel.org/r/1575531818-21332-1-git-send-email-eugen.hristev@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-09ARM: dts: at91: sama5d27_wlsom1: add SAMA5D27 wlsom1 and wlsom1-ekEugen Hristev
This is the addition of a new Evaluation Kit the SAMA5D27-WLSOM1-EK. It's based on the Microchip WireLess SoM which contains the SAMA5D27 LPDDR2 2Gbits SiP. [nicolas.ferre@microchip.com]: initial implementation Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> [eugen.hristev@microchip.com]: ported to new kernel version, [eugen.hristev@microchip.com]: addition of peripherals (adc, pmic, qspi, uart) Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lore.kernel.org/r/1573543139-8533-4-git-send-email-eugen.hristev@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-09ARM: dts: at91: sama5d2: mark secumod as a GPIO controllerAndrei Stefanescu
The Security Module exposes the PIOBU pins which an be used as regular GPIOs. The PIOBU pins are special because they do not lose their voltage during suspend-to-mem. This patch marks the secumod as a GPIO controller. Signed-off-by: Andrei Stefanescu <andrei.stefanescu@microchip.com> [razvan.stefanescu@microchip.com Updated title] Signed-off-by: Razvan Stefanescu <razvan.stefanescu@microchip.com> Link: https://lore.kernel.org/r/1573543139-8533-2-git-send-email-eugen.hristev@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-09ARM: dts: at91: sama5d2: disable pwm0 by defaultRazvan Stefanescu
It will be enabled as needed by each board. Signed-off-by: Razvan Stefanescu <razvan.stefanescu@microchip.com> Link: https://lore.kernel.org/r/1573543139-8533-1-git-send-email-eugen.hristev@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2019-12-09ARM: dts: Cygnus: Fix MDIO node address/size cellsFlorian Fainelli
The MDIO node on Cygnus had an reversed #address-cells and #size-cells properties, correct those. Fixes: 40c26d3af60a ("ARM: dts: Cygnus: Add the ethernet switch and ethernet PHY") Reported-by: Simon Horman <simon.horman@netronome.com> Reviewed-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Simon Horman <simon.horman@netronome.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-12-09ARM: dts: bcm2711: fix soc's node dma-rangesNicolas Saenz Julienne
Raspberry Pi's firmware has a feature to select how much memory to reserve for its GPU called 'gpu_mem'. The possible values go from 16MB to 944MB, with a default of 64MB. This memory resides in the topmost part of the lower 1GB memory area and grows bigger expanding towards the begging of memory. It turns out that with low 'gpu_mem' values (16MB and 32MB) the size of the memory available to the system in the lower 1GB area can outgrow the interconnect's dma-range as its size was selected based on the maximum system memory available given the default gpu_mem configuration. This makes that memory slice unavailable for DMA. And may cause nasty kernel warnings if CMA happens to include it. Change soc's dma-ranges to really reflect it's HW limitation, which is being able to only DMA to the lower 1GB area. Fixes: 7dbe8c62ceeb ("ARM: dts: Add minimal Raspberry Pi 4 support") Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Phil Elwell <phil@raspberrypi.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-12-09ARM: exynos_defconfig: Restore debugfs supportMarek Szyprowski
Commit 9f532d26c75c ("ARM: exynos_defconfig: Trim and reorganize with savedefconfig") removed explicit enable line for CONFIG_DEBUG_FS, because that feature has been selected by other enabled options: CONFIG_TRACING, which in turn had been selected by CONFIG_PERF_EVENTS and CONFIG_PROVE_LOCKING. In meantime, commit 0e4a459f56c3 ("tracing: Remove unnecessary DEBUG_FS dependency") removed the dependency between CONFIG_DEBUG_FS and CONFIG_TRACING, so CONFIG_DEBUG_FS is no longer enabled in default builds. Enable it again explicitly, as debugfs support is essential for various automated testing tools. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2019-12-09ARM: dts: BCM5301X: Fix MDIO node address/size cellsFlorian Fainelli
The MDIO node on BCM5301X had an reversed #address-cells and #size-cells properties, correct those, silencing checker warnings: .../linux/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dt.yaml: mdio@18003000: #address-cells:0:0: 1 was expected Reported-by: Simon Horman <simon.horman@netronome.com> Fixes: 23f1eca6d59b ("ARM: dts: BCM5301X: Specify MDIO bus in the DT") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2019-12-09Merge tag 'samsung-dt-5.5-2' of ↵Olof Johansson
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into arm/dt Samsung DTS ARM changes for v5.5, part 2 1. Cleanup by adjusting DTS to bindings, 2. Add touch-sensitive buttons to Midas (Galaxy S III family phones), 3. Add GPU/Mali to Exynos542x and Odroid XU3/XU4 family. * tag 'samsung-dt-5.5-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Add Mali/GPU node on Exynos5420 and enable it on Odroid XU3/4 ARM: dts: exynos: Add support for the touch-sensitive buttons on Midas family ARM: dts: exynos: Rename children of SysRAM node to "sram" Link: https://lore.kernel.org/r/20191119142026.7190-1-krzk@kernel.org Signed-off-by: Olof Johansson <olof@lixom.net>
2019-12-09ARM: dts: stm32: remove useless clock-names from RTC node on stm32f746Benjamin Gaignard
On stm32f7 family RTC node doesn't need clock-names property. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: remove useless clock-names from RTC node on stm32f429Benjamin Gaignard
On stm32f4 family RTC node doesn't need clock-names property. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: Enable MAC TX clock gating during TX low-power mode on ↵Christophe Roullier
stm32mp15 When there is no activity on ethernet phy link, the ETH_GTX_CLK is cut. Signed-off-by: Christophe Roullier <christophe.roullier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: stm32: adjust slew rate for Ethernet on stm32mp15Christophe Roullier
ETH_MDIO slew-rate should be set to "0" instead of "2". Signed-off-by: Christophe Roullier <christophe.roullier@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
2019-12-09ARM: dts: ux500: Add devicetree for HREF520Linus Walleij
This reference design is very similar to the others just that it has a different display mounted on the user interface board, and some GPIOs where shuffled around. As this is the first board that uses DB8520 we create the DB8520-specific DTSI file here. Cc: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191126124738.77690-3-linus.walleij@linaro.org
2019-12-09ARM: dts: ux500: Split TVK DTSI files in twoLinus Walleij
The TVK1281618 was made in R1, R2 and R3 variants. The most commonly used variants are R2 and R3 so split out these to their own files. The R3 version has a totally different display than R1 and R2 and a different set of sensors. Cc: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191126124738.77690-2-linus.walleij@linaro.org
2019-12-09ARM: dts: ux500: Break out DB8500 DTSILinus Walleij
The DB8500 exists in an enhanced variant named DB8520 for some machines. To clearly distinguish between the different machines, create an explicit db8500.dtsi and move the operating points (only known difference so far) to that file, so we can add an explicit db8520.dtsi after this. Cc: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191126124738.77690-1-linus.walleij@linaro.org Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Drop pulls on I2C busesLinus Walleij
The I2C block in the Ux500 uses internal pull-ups on the SoC, in fact it has to: in HS mode, the I2C block will need to autonomously take control over the pull-up line to do its job. This can be clearly seen from the SoC manual which states that the silicon has a line named "en_cspu_hs" which enables current source pull-up for high speed mode. Another hint is that the vendor code tree never enabled the pull up on these lines, despite being deployed on boards that lack external pull-up resistors. Tested on the Ux500 reference designs without any problems. Cc: Stephan Gerhold <stephan@gerhold.net> Reported-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191126123116.56244-1-linus.walleij@linaro.org Reviewed-by: Stephan Gerhold <stephan@gerhold.net> Tested-by: Stephan Gerhold <stephan@gerhold.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Use "arm,pl031" compatible for PL031Stephan Gerhold
The Ux500 device tree uses "arm,rtc-pl031" as compatible for PL031. All other boards in Linux describe it using "arm,pl031" instead. This works because the compatible is not actually used in Linux: AMBA devices get probed based on "arm,primecell" and their peripheral ID. Nevertheless, some other projects (e.g. U-Boot) rely on the compatible to probe the device with the correct driver. Those will look for "arm,pl031" instead of "arm,rtc-pl031", preventing the RTC from being probed. Change it to "arm,pl031" to match all other boards. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191124205110.48031-1-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Add "simple-bus" compatible to soc nodeStephan Gerhold
The "soc" node in the Ux500 device tree does not need any special handling - it is just a simple I/O bus that can be accessed without additional configuration. Therefore we can additionally describe it as compatible with "simple-bus". This can be used by platforms to probe devices under the soc node without special handling for our custom "stericsson,db8500" compatible (e.g. in U-Boot). Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191124195728.32226-1-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-12-09ARM: dts: ux500: Remove ux500_ prefix from ux500_serial* labelsStephan Gerhold
ux500_serial{0,1,2} are the only labels with ux500_ prefix in ste-dbx5x0.dtsi, the other labels (gpio0, msp, ...) do not use any prefix. Remove it for consistency. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20191125170428.76069-4-stephan@gerhold.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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