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2011-09-26ARM: mach-davinci: make DAVINCI_UART_INFO into a relative offsetNicolas Pitre
This is the first step to remove PLAT_PHYS_OFFSET usage from the debug UART code. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Kevin Hilman <khilman@ti.com>
2011-09-26ARM: mach-omap2: clean up debug-macro.SNicolas Pitre
This achieves two goals: 1) Get rid of omap_uart_v2p() and omap_uart_p2v() which were the last users of PLAT_PHYS_OFFSET. 2) Remove the probing of the M bit in the CP15 control reg and make the access to the .data variables completely position independent. There is a catch though: the busyuart macro needs to know where the LSR register is which might be at a different offset depending on the hardware. Given that this macro is given only two registers and that one of them must be preserved, the trick is to always pass the LSR register address around, and deduce the base address for the THR register by masking out the LSR offset in senduart instead. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
2011-09-26ARM: mach-omap1: clean up debug-macro.SNicolas Pitre
This achieves two goals: 1) Get rid of omap_uart_v2p() and omap_uart_p2v() which were the last users of PLAT_PHYS_OFFSET. 2) Remove the probing of the M bit in the CP15 control reg and make the access to the .data variables completely position independent. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
2011-09-26ARM: plat-omap: make OMAP_UART_INFO into a relative offsetNicolas Pitre
This is the first step to remove PLAT_PHYS_OFFSET usage from the debug UART code. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Tested-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Kevin Hilman <khilman@ti.com>
2011-09-26ARM: add an extra temp register to the low level debugging addruart macroNicolas Pitre
Some platforms (like OMAP not to name it) are doing rather complicated hacks just to determine the base UART address to use. Let's give their addruart macro some slack by providing an extra work register which will allow for much needed cleanups. This is basically a no-op as this commit is only adding the extra argument to the macro but no one is using it yet. Signed-off-by: nicolas Pitre <nicolas.pitre@linaro.org> Reviewed-by: Kevin Hilman <khilman@ti.com>
2011-09-26ARM: 7099/1: futex: preserve oldval in SMP __futex_atomic_opWill Deacon
The SMP implementation of __futex_atomic_op clobbers oldval with the status flag from the exclusive store. This causes it to always read as zero when performing the FUTEX_OP_CMP_* operation. This patch updates the ARM __futex_atomic_op implementations to take a tmp argument, allowing us to store the strex status flag without overwriting the register containing oldval. Cc: stable@kernel.org Reported-by: Minho Ban <mhban@samsung.com> Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-09-26ARM: 7094/1: arm/tegra: Move EN_VDD_1V05_GPIO to board-harmony.hStephen Warren
This centralizes all GPIO naming in one header. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-09-26ARM i.MX entry-macro.S: remove now unused codeSascha Hauer
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-09-26ARM i.MX boards: use CONFIG_MULTI_IRQ_HANDLERSascha Hauer
Also, add handle_irq callbacks to machine descriptors. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-09-26ARM i.MX tzic: add handle_irq functionSascha Hauer
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-09-26ARM i.MX avic: add handle_irq functionSascha Hauer
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-09-26ARM: dma-mapping: free allocated page if unable to mapRussell King
If the attempt to map a page for DMA fails (eg, because we're out of mapping space) then we must not hold on to the page we allocated for DMA - doing so will result in a memory leak. Cc: <stable@kernel.org> Reported-by: Bryan Phillippe <bp@darkforest.org> Tested-by: Bryan Phillippe <bp@darkforest.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2011-09-26Merge branch 'for_3_2/for-rmk/arm_cpu_pm' of ↵Russell King
git://gitorious.org/omap-sw-develoment/linux-omap-dev into devel-stable
2011-09-26ARM: S3C64xx: Add LDOVDD supply for CODEC on CragganmoreMark Brown
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-09-26ARM: S5P: fix incorrect loop iterator usage on gpio-interruptMarek Szyprowski
Loop iterator value after terminating list_for_each_entry() is not NULL. This patch fixes incorrect iterator usage in GPIO interrupt code for SAMSUNG S5P platforms. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-09-26ARM: S3C2443: Fix bit-reset in setrate of clk_armdivHeiko Stuebner
The changed statement should set the old armdiv bits to 0 and not everything else, before setting the new value. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2011-09-25ARM: mach-shmobile: sh7372 sleep warning fixesMagnus Damm
Update the sh7372 sleep code to build parts of the code only when SUSPEND and/or CPU_IDLE are set. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2011-09-25ARM: mach-shmobile: sh7372 A3SM supportMagnus Damm
This patch adds sh7372 A3SM power domain support. The sh7372 A3SM hardware power domain contains the ARM Cortex-A8 CPU Core including L2 cache. This sleep mode can be seen as a one step deeper sleep mode from the already existing Core Standby mode. To wake up from A3SM sleep only a few wakeup sources are supported - so the regular INTC controller will not be able to help us unfortunately. The code in this patch will enter A3SM sleep via the regular Suspend-to-RAM interface in the case of only wakeups supported by A3SM are enabled. If unsupported wakeups are enabled then Core Standby will be used instead. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2011-09-25ARM: mach-shmobile: sh7372 generic suspend/resume supportMagnus Damm
Convert the sh7372 Core Standby code to make use of the new generic ARM cpu suspend/resume code. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2011-09-24OMAP4: Fix the emif and dmm virtual mappingSantosh Shilimkar
Fix the address overlap with Emulation domain (EMU). The previous mapping was entering into EMU mapping and was not as per comments. Fix the mapping accordingly. Signed-off-by: Girish S G <girishsg@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2011-09-24OMAP: Print Initiator name for l3 custom error.sricharan
The initiator id gets logged in the l3 target registers for custom error. So print it to aid debugging. Based on a internal patch by Devaraj Rangasamy <dev@ti.com> Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2011-09-24OMAP: Fix sparse warnings in l3 error handler.sricharan
Fix below sparse warnings from the l3-noc and l3-smx error handlers files. arch/arm/mach-omap2/omap_l3_smx.h:209:22: warning: symbol 'omap3_l3_app_bases' was not declared. Should it be static? arch/arm/mach-omap2/omap_l3_smx.h:308:22: warning: symbol 'omap3_l3_debug_bases' was not declared. Should it be static? arch/arm/mach-omap2/omap_l3_smx.h:325:2: warning: incorrect type in initializer (different address spaces) arch/arm/mach-omap2/omap_l3_smx.h:325:2: expected unsigned int [usertype] * arch/arm/mach-omap2/omap_l3_smx.h:325:2: got unsigned int [noderef] [toplevel] <asn:2>*<noident> arch/arm/mach-omap2/omap_l3_smx.h:326:2: warning: incorrect type in initializer (different address spaces) arch/arm/mach-omap2/omap_l3_smx.h:326:2: expected unsigned int [usertype] * arch/arm/mach-omap2/omap_l3_smx.h:326:2: got unsigned int [noderef] [toplevel] <asn:2>*<noident> arch/arm/mach-omap2/omap_l3_smx.h:324:5: warning: symbol 'omap3_l3_bases' was not declared. Should it be static? CC arch/arm/mach-omap2/omap_l3_smx.o CHECK arch/arm/mach-omap2/omap_l3_noc.c arch/arm/mach-omap2/omap_l3_noc.c:73:13: warning: symbol '__v' shadows an earlier one arch/arm/mach-omap2/omap_l3_noc.c:73:13: originally declared here arch/arm/mach-omap2/omap_l3_noc.c:83:20: warning: symbol '__v' shadows an earlier one arch/arm/mach-omap2/omap_l3_noc.c:83:20: originally declared here arch/arm/mach-omap2/omap_l3_noc.c:90:5: warning: symbol '__v' shadows an earlier one arch/arm/mach-omap2/omap_l3_noc.c:90:5: originally declared here arch/arm/mach-omap2/omap_l3_noc.h:39:5: warning: symbol 'l3_flagmux' was not declared. Should it be static? arch/arm/mach-omap2/omap_l3_noc.h:46:5: warning: symbol 'l3_targ_inst_clk1' was not declared. Should it be static? arch/arm/mach-omap2/omap_l3_noc.h:54:5: warning: symbol 'l3_targ_inst_clk2' was not declared. Should it be static? arch/arm/mach-omap2/omap_l3_noc.h:75:5: warning: symbol 'l3_targ_inst_clk3' was not declared. Should it be static? arch/arm/mach-omap2/omap_l3_noc.h:79:6: warning: symbol 'l3_targ_inst_name' was not declared. Should it be static? arch/arm/mach-omap2/omap_l3_noc.h:112:5: warning: symbol 'l3_targ' was not declared. Should it be static? arch/arm/mach-omap2/omap_l3_noc.c:72:11: warning: cast removes address space of expression arch/arm/mach-omap2/omap_l3_noc.c:73:13: warning: incorrect type in argument 1 (different base types) arch/arm/mach-omap2/omap_l3_noc.c:73:13: expected void const volatile [noderef] <asn:2>*<noident> arch/arm/mach-omap2/omap_l3_noc.c:73:13: got unsigned int arch/arm/mach-omap2/omap_l3_noc.c:83:20: warning: incorrect type in argument 1 (different base types) arch/arm/mach-omap2/omap_l3_noc.c:83:20: expected void const volatile [noderef] <asn:2>*<noident> arch/arm/mach-omap2/omap_l3_noc.c:83:20: got unsigned int arch/arm/mach-omap2/omap_l3_noc.c:90:5: warning: incorrect type in argument 1 (different base types) arch/arm/mach-omap2/omap_l3_noc.c:90:5: expected void const volatile [noderef] <asn:2>*<noident> arch/arm/mach-omap2/omap_l3_noc.c:90:5: got unsigned int arch/arm/mach-omap2/omap_l3_noc.c:96:5: warning: incorrect type in argument 1 (different base types) arch/arm/mach-omap2/omap_l3_noc.c:96:5: expected void const volatile [noderef] <asn:2>*<noident> arch/arm/mach-omap2/omap_l3_noc.c:96:5: got unsigned int arch/arm/mach-omap2/omap_l3_noc.c:108:5: warning: incorrect type in argument 1 (different base types) arch/arm/mach-omap2/omap_l3_noc.c:108:5: expected void const volatile [noderef] <asn:2>*<noident> arch/arm/mach-omap2/omap_l3_noc.c:108:5: got unsigned int Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reported-by: Paul Walmsley <paul@pwsan.com> Reviewed-by: Paul Walmsley <paul@pwsan.com>
2011-09-24OMAP: Fix indentation issues in l3 error handler.sricharan
The indentation problems in the l3 noc and smx error handler files are fixed. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reported-by: Paul Walmsley <paul@pwsan.com>
2011-09-24OMAP: Fix a BUG in l3 error handler.Todd Poynor
With the current sequence of registering the irq and assigning it to the app_irq, debug_irq driver variables, there can be corner cases where the pending irq gets triggered immediately after registering, handler gets called resulting in a crash. So changed this sequence. Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Todd Poynor <toddpoynor@google.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2011-09-24OMAP: Improve register access in L3 Error handler.Todd Poynor
* Changed the way of accessing L3 target registers from standard base rather than relative to STDERRLOG_MAIN. * Use ffs() to find error source from the L3_FLAGMUX_REGERRn register. * Remove extra l3_base[] entry. * Modified L3 custom error message. Signed-off-by: Todd Poynor <toddpoynor@google.com> Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2011-09-23Merge branch 'for_3.2/voltage-cleanup' of ↵Tony Lindgren
git://gitorious.org/khilman/linux-omap-pm into voltage
2011-09-23ARM: mx25: Add the missing IIM base definitionJason Liu
This fix the mx25 building issue of no IIM base definition Signed-off-by: Jason Liu <jason.hui@linaro.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-09-23ARM: mm: Add strongly ordered descriptor support.Santosh Shilimkar
On certain architectures, there might be a need to mark certain addresses with strongly ordered memory attributes to avoid ordering issues at the interconnect level. On OMAP4, the asynchronous bridge buffers can only be drained with strongly ordered accesses and hence the need to mark the memory strongly ordered. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Woodruff Richard <r-woodruff2@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
2011-09-23ARM: vfp: Fix the comment to make it consistent with the code.Santosh Shilimkar
Function vfp_force_reload() clears vfp_current_hw_state, so update the comment accordingly. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
2011-09-23ARM: gic: Allow gic arch extensions to provide irqchip flagsColin Cross
Tegra can benefit from the IRQCHIP_MASK_ON_SUSPEND flag, allow it to be passed to the gic irq chip. Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-and-Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
2011-09-23ARM: vfp: Use cpu pm notifiers to save vfp stateColin Cross
When the cpu is powered down in a low power mode, the vfp registers may be reset. This patch uses CPU_PM_ENTER and CPU_PM_EXIT notifiers to save and restore the cpu's vfp registers. Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-and-Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
2011-09-23ARM: gic: Use cpu pm notifiers to save gic stateColin Cross
When the cpu is powered down in a low power mode, the gic cpu interface may be reset, and when the cpu cluster is powered down, the gic distributor may also be reset. This patch uses CPU_PM_ENTER and CPU_PM_EXIT notifiers to save and restore the gic cpu interface registers, and the CPU_CLUSTER_PM_ENTER and CPU_CLUSTER_PM_EXIT notifiers to save and restore the gic distributor registers. Original-author: Gary King <gking@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-and-Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
2011-09-23ARM: Enable CPU_PM notifiers on ARM machines.Santosh Shilimkar
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-and-Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
2011-09-23ARM i.MX avic: convert to use generic irq chipHui Wang
Convert i.MX avic irq handler to use generic irq chip. This not only provides a cleanup implementation of irq chip handler, but also implements suspend/resume interface with the help of generic irq chip interface. Change mxc_irq_chip to a new structure mxc_extra_irq to handle fiq and priority functions. Signed-off-by: Hui Wang <jason77.wang@gmail.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
2011-09-22Merge branch 'for_3.2/pm-cleanup' of ↵Tony Lindgren
git://gitorious.org/khilman/linux-omap-pm into cleanup
2011-09-22Merge branch 'for_3.2/omap_device' of ↵Tony Lindgren
git://gitorious.org/khilman/linux-omap-pm into cleanup
2011-09-22Merge branch 'pm' into devel-stableRussell King
2011-09-22Merge branch 'tegra/fixes' into next/fixesArnd Bergmann
2011-09-22arm/dt: Tegra: Add support-8bit to SDHCI nodesStephen Warren
For Seaboard's internal eMMC, this makes the difference between a 5.5MB/s and 10.2MB/s transfer rate. On Harmony, there wasn't any measurable difference on my cheap/slow ~2MB/s card. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2011-09-22ARM: mach-nuc93x: deleteNicolas Pitre
This architecture received only generic maintenance since December 2009 when it was originally submitted, and no actual additional support since then. It has no defconfig entry either, meaning that it was never built by the ARM KAutobuild. Incidentally it currently doesn't build either when CONFIG_MACH_NUC932EVB is selected which is the only possible config choice. This is therefore dead code and should be removed. If someone wants to revive this code, it could be retrieved from the Git repository, and ideally be merged in mach-w90x900/ instead. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: Wan ZongShun <mcuos.com@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2011-09-22ARM: ux500: Reprogram timers upon resumeJonas Aaberg
On ux500 the MTU timer blocks are powered off during suspend/resume, so these need some reinitialization when coming back from suspend. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-09-22ARM: plat-nomadik: timer: Export reset functionsJonas Aaberg
We make the reset function from the driver public, then we also move of all register defines from the public header file into driver, where they belong. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-09-22ARM: plat-nomadik: timer: Add support for periodic timersJonas Aaberg
This adds support for a periodic mode in the MTU (Nomadik) timer clockevent driver. It also include changes needed for deeper powerstates where MTU block gets powered off. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-09-22ARM: ux500: Move timer code to separate fileJonas Aaberg
Just split off the timer code to its own file so we have a more fine-grained file tree. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-09-22ARM: ux500: add support for clocksource DBX500 PRCMUMattias Wallin
This patch adds support for the DBX500 PRCMU clocksource to ux500 platforms. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Mattias Wallin <mattias.wallin@stericsson.co> Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-09-22ARM: plat-nomadik: MTU sched_clock as an optionMattias Wallin
This patch makes it possible to configure away the sched_clock part of the MTU timer. Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Mattias Wallin <mattias.wallin@stericsson.com> Signed-off-by: Jonas Aberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-09-22ARM: mach-ux500: unlock I&D l2x0 caches before initLinus Walleij
Apparently U8500 U-Boot versions may leave the l2x0 locked down before executing the kernel. Make sure we unlock it before we initialize the l2x0. This fixes a performance problem reported by Jan Rinze. The l2x0 core has been modified to unlock the l2x0 by default, but it will not touch the locking registers if the l2x0 was already enabled, as on the ux500, so we need this quirk to make sure it is properly turned off. Cc: stable@kernel.org Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Rabin Vincent <rabin.vincent@stericsson.com> Cc: Adrian Bunk <adrian.bunk@movial.com> Reported-by: Jan Rinze <janrinze@gmail.com> Tested-by: Robert Marklund <robert.marklund@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-09-22ARM: mach-ux500: enable fix for ARM errata 754322srinidhi kasagar
This applies ARM errata fix 754322 for all ux500 platforms. Cc: stable@kernel.org Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2011-09-22OMAP4: hwmod: enable mcpdm hwmod device.Peter Ujfalusi
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Jorge Eduardo Candelaria Signed-off-by: Margarita Olaya Cabrera Signed-off-by: Liam Girdwood <lrg@ti.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Benoit Cousson <b-cousson@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
2011-09-22OMAP: McPDM: Convert McPDM device to omap_devicePeter Ujfalusi
McPDM device is converted to omap device. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Jorge Eduardo Candelaria Signed-off-by: Margarita Olaya Cabrera Signed-off-by: Liam Girdwood <lrg@ti.com> Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tony Lindgren <tony@atomide.com>
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