| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2021-08-31 | openrisc/litex: Add ethernet device | Joel Stanley | |
| Add the liteeth ethernet device. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stafford Horne <shorne@gmail.com> | |||
| 2021-08-31 | openrisc/litex: Update uart address | Joel Stanley | |
| Recent litex socs will place the UART at 0xe0006800. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stafford Horne <shorne@gmail.com> | |||
| 2020-11-12 | openrisc: add support for LiteX | Filip Kokosinski | |
| This adds support for a basic LiteX-based SoC with a mor1kx soft CPU. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com> [shorne: Merged in soc-cntl patch, removed CROSS_COMPILE, sort MAINT.] Signed-off-by: Stafford Horne <shorne@gmail.com> | |||
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index : linux.git | |
| Linus' kernel tree | Russell King |
| summaryrefslogtreecommitdiff |