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path: root/drivers/clk/rockchip/clk-rk3588.c
AgeCommit message (Expand)Author
2025-04-10clk: rockchip: rk3588: Add PLL rate for 1500 MHzAlexander Shiyan
2025-01-09clk: rockchip: rk3588: make refclko25m_ethX criticalHeiko Stuebner
2025-01-09clk: rockchip: rk3588: drop RK3588_LINKED_CLKSebastian Reichel
2025-01-09clk: rockchip: implement linked gate clock supportSebastian Reichel
2025-01-09clk: rockchip: rk3588: register GATE_LINK laterSebastian Reichel
2024-08-30clk: rockchip: rk3588: drop unused codeSebastian Reichel
2024-08-29clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_pAlexander Shiyan
2024-02-27clk: rockchip: rk3588: use linked clock ID for GATE_LINKSebastian Reichel
2024-02-27clk: rockchip: rk3588: fix indentSebastian Reichel
2024-02-27clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grfSebastian Reichel
2024-02-27clk: rockchip: rk3588: fix CLK_NR_CLKS usageSebastian Reichel
2023-04-18clk: rockchip: rk3588: make gate linked clocks criticalSebastian Reichel
2022-11-15clk: rockchip: add clock controller for the RK3588Elaine Zhang
generated by cgit (git 2.34.1) at 2025-08-04 13:32:17 +0000