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path: root/drivers/clk
AgeCommit message (Expand)Author
2025-07-16clk: qcom: rpmh: convert from round_rate() to determine_rate()Brian Masney
2025-07-16clk: qcom: rpm: convert from round_rate() to determine_rate()Brian Masney
2025-07-16clk: qcom: gcc-ipq4019: convert from round_rate() to determine_rate()Brian Masney
2025-07-16clk: qcom: videocc-qcs615: Add QCS615 video clock controller driverTaniya Das
2025-07-16clk: qcom: gpucc-qcs615: Add QCS615 graphics clock controller driverTaniya Das
2025-07-16clk: qcom: dispcc-qcs615: Add QCS615 display clock controller driverTaniya Das
2025-07-16clk: qcom: camcc-qcs615: Add QCS615 camera clock controller driverTaniya Das
2025-07-16clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLsTaniya Das
2025-07-16clk: qcom: gcc-ipq5018: fix GE PHY resetGeorge Moussalem
2025-07-16clk: qcom: gcc-qcm2290: Set HW_CTRL_TRIGGER for video GDSCLoic Poulain
2025-07-16clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC supportGeorge Moussalem
2025-07-16clk: qcom: ipq5018: keep XO clock always onGeorge Moussalem
2025-07-14clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate()Brian Masney
2025-07-14clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate()Brian Masney
2025-07-14clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate()Brian Masney
2025-07-14clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate()Brian Masney
2025-07-14clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pllPaul Kocialkowski
2025-07-14clk: sunxi-ng: v3s: Fix de clock definitionPaul Kocialkowski
2025-07-13clk: thead: th1520-ap: Correctly refer the parent of osc_12mYao Zi
2025-07-10clk: rockchip: rk3568: Add PLL rate for 132MHzAndy Yan
2025-07-08clk: renesas: r9a08g045: Add MSTOP for coupled clocks as wellClaudiu Beznea
2025-07-08clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPsJohn Madieu
2025-07-07PM: domains: Add flags to specify power on attach/detachClaudiu Beznea
2025-07-07Merge tag 'spacemit-reset-for-6.17-1' of https://github.com/spacemit-com/linuxYixun Lan
2025-07-04clk: spacemit: mark K1 pll1_d8 as criticalAlex Elder
2025-07-03clk: sunxi-ng: v3s: Fix TCON clock parentsPaul Kocialkowski
2025-07-03clk: sunxi-ng: v3s: Fix CSI1 MCLK clock namePaul Kocialkowski
2025-07-03clk: sunxi-ng: v3s: Fix CSI SCLK clock namePaul Kocialkowski
2025-07-03clk: spacemit: define three reset-only CCUsAlex Elder
2025-07-03clk: spacemit: set up reset auxiliary devicesAlex Elder
2025-07-03soc: spacemit: create a header for clock/reset registersAlex Elder
2025-07-02clk: renesas: r9a09g057: Add XSPI clock/resetLad Prabhakar
2025-07-02clk: renesas: r9a09g056: Add XSPI clock/resetLad Prabhakar
2025-07-02clk: renesas: rzv2h: Add fixed-factor module clocks with status reportingLad Prabhakar
2025-07-02clk: renesas: r9a09g057: Add support for xspi mux and dividerLad Prabhakar
2025-07-02clk: renesas: r9a09g056: Add support for xspi mux and dividerLad Prabhakar
2025-07-02clk: renesas: r9a09g077: Add RIIC module clocksLad Prabhakar
2025-07-02clk: renesas: r9a09g077: Add PLL2 and SDHI clock supportLad Prabhakar
2025-07-02clk: renesas: rzv2h: Drop redundant base pointer from pll_clkLad Prabhakar
2025-07-02clk: renesas: r9a09g057: Add entries for the RSPIsFabrizio Castro
2025-07-02clk: amlogic: s4: remove unused dataJerome Brunet
2025-07-02clk: amlogic: drop clk_regmap tablesJerome Brunet
2025-07-02clk: amlogic: get regmap with clk_regmap_initJerome Brunet
2025-06-30clk: clk-axi-clkgen: fix coding style issuesNuno Sá
2025-06-30clk: clk-axi-clkgen move to min/max()Nuno Sá
2025-06-30clk: clk-axi-clkgen: detect axi_clkgen_limits at runtimeNuno Sá
2025-06-30clk: clk-axi-clkgen: make sure to include mod_devicetable.hNuno Sá
2025-06-30clk: clk-axi-clkgen: fix fpfd_max frequency for zynqNuno Sá
2025-06-30clk: thead: Mark essential bus clocks as CLK_IGNORE_UNUSEDMichal Wilczynski
2025-06-30clk: amlogic: remove unnecessary headersJerome Brunet