summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/display/intel_dpll.c
AgeCommit message (Expand)Author
2021-10-14drm/i915: split out vlv sideband to a separate fileJani Nikula
2021-10-01drm/i915/dpll: move dpll modeset asserts to intel_dpll.cJani Nikula
2021-10-01drm/i915/pps: move pps (panel) modeset asserts to intel_pps.cJani Nikula
2021-09-29drm/i915: constify the dpll clock vtableDave Airlie
2021-09-29drm/i915: split the dpll clock compute out from display vtable.Dave Airlie
2021-09-15drm/i915: s/pipe/transcoder/ when dealing with PIPECONF/TRANSCONFVille Syrjälä
2021-09-15drm/i915: Flatten hsw_crtc_compute_clock()Ville Syrjälä
2021-08-25drm/i915: Fold i9xx_set_pll_dividers() into i9xx_enable_pll()Ville Syrjälä
2021-08-25drm/i915: Reuse ilk_needs_fb_cb_tune() for the reduced clock as wellVille Syrjälä
2021-08-25drm/i915: Call {vlv,chv}_prepare_pll() from {vlv,chv}_enable_pll()Ville Syrjälä
2021-08-25drm/i915: Program DPLL P1 dividers consistentlyVille Syrjälä
2021-08-25drm/i915: Remove the 'reg' local variableVille Syrjälä
2021-08-25drm/i915: Clean up variable names in old dpll functionsVille Syrjälä
2021-08-25drm/i915: Clean dpll calling conventionVille Syrjälä
2021-08-25drm/i915: Constify struct dpll all overVille Syrjälä
2021-08-25drm/i915: Extract ilk_update_pll_dividers()Ville Syrjälä
2021-08-25drm/i915: Set output_types to EDP for vlv/chv DPLL forcingVille Syrjälä
2021-07-29drm/i915/dg2: Add MPLLB programming for SNPS PHYMatt Roper
2021-05-05drm/i915: Don't include intel_de.h from intel_display_types.hVille Syrjälä
2021-04-14drm/i915/display: rename display version macrosLucas De Marchi
2021-04-14drm/i915/display: Eliminate IS_GEN9_{BC,LP}Matt Roper
2021-03-23drm/i915/display: Eliminate most usage of INTEL_GEN()Matt Roper
2021-02-08drm/i915: migrate pll enable/disable code to intel_dpll.[ch]Dave Airlie
2021-01-16drm/i915: refactor pll code out into intel_dpll.cDave Airlie
generated by cgit (git 2.34.1) at 2025-09-15 09:05:37 +0000