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path: root/drivers/pci
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2014-09-30PCI: designware: Setup and clear exactly one MSI at a timeLucas Stach
The setup_irq function is supposed to set up exactly one MSI IRQ. Multiple IRQ setup is handled differently, to respect the choices made by the upper layers. Also only clear one MSI IRQ at a time; the PCI core will call into this function multiple times if it has to tear down more than one MSI IRQ. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pratyush Anand <pratyush.anand@st.com> Acked-by: Jingoo Han <jg1.han@samsung.com>
2014-09-30PCI: Add missing MEM_64 mask in pci_assign_unassigned_bridge_resources()Yinghai Lu
In 5b28541552ef ("PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources"), we added IORESOURCE_MEM_64 to the mask in pci_assign_unassigned_root_bus_resources(), but not to the mask in pci_assign_unassigned_bridge_resources(). Add IORESOURCE_MEM_64 to the pci_assign_unassigned_bridge_resources() type mask. Fixes: 5b28541552ef ("PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources") Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.16+
2014-09-29PCI: Add ACS quirk for Intel 10G NICsAlex Williamson
Intel has verified there is no peer-to-peer between functions for the below selection of 82598, 82599, and X520 10G NICs. These NICs lack an ACS capability, so we're not able to determine this isolation without the help of quirks. Generalize the Solarflare quirk and add these Intel 10G NICs. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: John Ronciak <John.ronciak@intel.com>
2014-09-29Merge branch 'pci/host-designware' into nextBjorn Helgaas
* pci/host-designware: PCI: designware: Add get_msi_data() to pcie_host_ops PCI: designware: Rename get_msi_data() to get_msi_addr() PCI: designware: Fix IO resource end address calculation PCI: designware: Fix configuration base address when using 'reg' PCI: designware: Use NULL instead of false [bhelgaas: Fixup keystone for "PCI: designware: Rename get_msi_data() to get_msi_addr()"]
2014-09-29PCI: Export MSI message relevant functionsGavin Shan
The patch exports 2 MSI message relevant functions, which will be used by VFIO PCI driver. The VFIO PCI driver would be built as a module. Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2014-09-25Merge branches 'pci/enumeration', 'pci/virtualization' and 'pci/cleanup' ↵Bjorn Helgaas
into next * pci/enumeration: PCI: Generate uppercase hex for modalias interface class * pci/virtualization: PCI: Add ACS quirk for Solarflare SFC9120 & SFC9140 PCI: Remove unused pci_get_dma_source() PCI: Remove unused pci_find_upstream_pcie_bridge() * pci/cleanup: PCI: Remove assignment from complicated "if" conditions PCI: Remove assignment from "if" conditions PCI: Remove unnecessary curly braces PCI: Add space before open parenthesis
2014-09-25Merge branches 'pci/host-mvebu' and 'pci/host-spear' into nextBjorn Helgaas
* pci/host-mvebu: PCI: mvebu: Fix uninitialized variable in mvebu_get_tgt_attr() * pci/host-spear: PCI: spear: Pass config resource through reg property
2014-09-25PCI/AER: Add additional PCIe AER error stringsChen, Gong
Add strings for all AER error bits defined in PCIe r3.0. [bhelgaas: changelog, drop designated initializer change] Signed-off-by: Chen, Gong <gong.chen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-24Merge branches 'pci/hotplug', 'pci/initdata' and 'pci/misc' into nextBjorn Helgaas
* pci/hotplug: PCI: pciehp: Stop disabling notifications during init PCI: pciehp: Add more Slot Control debug output PCI: pciehp: Fix wait time in timeout message * pci/initdata: x86/PCI: Mark PCI BIOS initialization code as such x86/PCI: Constify pci_mmcfg_probes[] array x86/PCI: Mark constants of pci_mmcfg_nvidia_mcp55() as __initconst x86/PCI: Move __init annotation to the correct place x86/PCI: Mark DMI tables as initialization data * pci/misc: PCI: Move PCI_VENDOR_ID_VMWARE to pci_ids.h
2014-09-24Merge tag 'pci-v3.17-fixes-3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: "Here are a few fixes that should be in v3.17. - Reverting "Don't scan random busses" covers up a CardBus regression having to do with allocating CardBus bus numbers. - Reverting "Make sure bus numbers stay within parents bounds" covers up an ACPI _CRS bug that makes us reconfigure a bridge, causing a broken device behind it to stop responding. - The pciehp timeout change fixes some code we added in v3.17. Without the fix, we can send a new hotplug command too early, before the timeout has expired. I hope for better fixes for the reverts, but those will have to come after v3.17" * tag 'pci-v3.17-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: PCI: pciehp: Fix pcie_wait_cmd() timeout Revert "PCI: Make sure bus number resources stay within their parents bounds" Revert "PCI: Don't scan random busses in pci_scan_bridge()"
2014-09-24PCI: Remove assignment from complicated "if" conditionsQuentin Lambert
The modifications effectively change the value of len_tmp in the case where the first condition is not met. Signed-off-by: Quentin Lambert <lambert.quentin@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-24PCI: Remove assignment from "if" conditionsQuentin Lambert
The following Coccinelle semantic patch was used to find and correct cases of assignments in "if" conditions: @@ expression var, expr; statement S; @@ + var = expr; if( - (var = expr) + var ) S Signed-off-by: Quentin Lambert <lambert.quentin@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-24PCI: Remove unnecessary curly bracesQuentin Lambert
Remove curly braces in simple "if" cases. No functional change. Signed-off-by: Quentin Lambert <lambert.quentin@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-24PCI: Add space before open parenthesisQuentin Lambert
Add space before open parenthesis as is conventional. No functional change. [bhelgaas: fix a few more in ibmphp, shpchp] Signed-off-by: Quentin Lambert <lambert.quentin@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-24PCI: designware: Add get_msi_data() to pcie_host_opsMinghuan Lian
Add a struct pcie_host_ops .get_msi_data() method for platforms to return their special MSI message data. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mohit KUMAR <mohit.kumar@st.com>
2014-09-24PCI: designware: Rename get_msi_data() to get_msi_addr()Minghuan Lian
The struct pcie_host_ops .get_msi_data() method returns the MSI message address. To accurately express its purpose, rename it to .get_msi_addr(). Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mohit KUMAR <mohit.kumar@st.com>
2014-09-24PCI: designware: Fix IO resource end address calculationMinghuan Lian
End address should be equal to start_addr + size - 1. Fix PCI IO resource end address calculation. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mohit KUMAR <mohit.kumar@st.com>
2014-09-24PCI: designware: Fix configuration base address when using 'reg'Minghuan Lian
The code has calculated cfg0_base and cfg1_base when parsing 'reg' or 'ranges' property of PCI DTS node, so remove duplicate calculation. When using 'reg', resource cfg is not used, so this code computed an incorrect configuration base. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mohit KUMAR <mohit.kumar@st.com>
2014-09-23PCI: pciehp: Stop disabling notifications during initYinghai Lu
During pciehp initialization, we previously wrote two hotplug commands: pciehp_probe pcie_init pcie_disable_notification pcie_write_cmd # command 1 pcie_init_notification pcie_enable_notification pcie_write_cmd # command 2 For controllers with errata like Intel CF118, we previously waited for a timeout before issuing the second hotplug command because the first command only updates interrupt enable bits and is not a "real" hotplug command, so the controller doesn't report Command Completed for it. But there's no need to disable notifications in the first place. If BIOS left them enabled, we could easily take an interrupt before disabling them, so there's no benefit in disabling them for the tiny window before we enable them. Drop the unnecessary pcie_disable_notification() call. [bhelgaas: changelog] Link: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e7-v2-spec-update.html Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-23PCI: pciehp: Add more Slot Control debug outputYinghai Lu
Add more Slot Control debug output and move one print after pcie_write_cmd() to be consistent with other debug output. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-23PCI: pciehp: Fix wait time in timeout messageYinghai Lu
When we warned about a timeout on a hotplug command, we previously printed the time between calls to pcie_write_cmd(), without accounting for any time spent actually waiting. Consider this sequence: pcie_write_cmd write SLTCTL cmd_started = jiffies # T1 pcie_write_cmd pcie_wait_cmd now = jiffies # T2 wait_event_timeout # we may wait here if (timeout) ctrl_info("Timeout on command issued %u msec ago", jiffies_to_msecs(now - cmd_started)) We previously printed (T2 - T1), but that doesn't include the time spent in wait_event_timeout(). Fix this by using the current jiffies value, not the one cached before calling wait_event_timeout(). [bhelgaas: changelog, use current jiffies instead of adding timeout] Fixes: 40b960831cfa ("PCI: pciehp: Compute timeout from hotplug command start time") Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-23Merge branch 'pci/hotplug' into nextBjorn Helgaas
* pci/hotplug: PCI: pciehp: Prevent NULL dereference during probe PCI: pciehp: Reduce PCIe slot_ctrl to 16 bits PCI: Configure *all* devices, not just hot-added ones PCI: Preserve MPS and MRRS when applying _HPX settings PCI: Apply _HPP settings to all hot-added PCI devices PCI: Preserve BIOS PCI_COMMAND_SERR and PCI_COMMAND_PARITY settings PCI: Apply _HPP settings to PCIe devices as well as PCI and PCI-X PCI: Remove unused pci_configure_slot() ACPI / hotplug / PCI: Remove pci_configure_slot() usage PCI: shpchp: Remove pci_configure_slot() usage PCI: pciehp: Remove pci_configure_slot() usage PCI: Add pci_configure_device() during enumeration PCI: Move pci_configure_slot() to drivers/pci/probe.c PCI: Shuffle pci-acpi.c functions to group them logically PCI: Whitespace cleanup in pci-acpi.c PCI: Move pci_get_hp_params() to drivers/pci/pci-acpi.c PCI: pciehp: Configure hot-added display devices PCI: Remove "no hotplug settings from platform" warning
2014-09-22PCI: pciehp: Fix pcie_wait_cmd() timeoutYinghai Lu
pcie_poll_cmd() take msecs instead of jiffies, so convert timeout to msecs. Fixes: 40b960831cfa ("PCI: pciehp: Compute timeout from hotplug command start time") Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-22PCI: Add ACS quirk for Solarflare SFC9120 & SFC9140Alex Williamson
Solarflare confirms that these devices do not allow peer-to-peer between functions. Quirk them to allow IOMMU grouping to expose this isolation. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Robert Stonehouse <rstonehouse@solarflare.com>
2014-09-22PCI: designware: Use NULL instead of falseFabio Estevam
of_get_address() expects pointers in the third and fourth parameters. Pass NULL in order to fix the following sparse warnings: drivers/pci/host/pcie-designware.c:433:51: warning: Using plain integer as NULL pointer drivers/pci/host/pcie-designware.c:433:58: warning: Using plain integer as NULL pointer Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Lucas Stach <l.stach@pengutronix.de> Acked-by: Jingoo Han <jg1.han@samsung.com>
2014-09-22PCI: Remove unused pci_get_dma_source()Alex Williamson
pci_get_dma_source() is unused, so remove it. We now have dma_alias_devfn() to describe this. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-22PCI: Remove unused pci_find_upstream_pcie_bridge()Alex Williamson
pci_find_upstream_pcie_bridge() is unused, so remove it. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-22PCI: mvebu: Fix uninitialized variable in mvebu_get_tgt_attr()Thomas Petazzoni
Geert Uytterhoeven reported a warning when building pci-mvebu: drivers/pci/host/pci-mvebu.c: In function 'mvebu_get_tgt_attr': drivers/pci/host/pci-mvebu.c:887:39: warning: 'rtype' may be used uninitialized in this function [-Wmaybe-uninitialized] if (slot == PCI_SLOT(devfn) && type == rtype) { ^ And indeed, the code of mvebu_get_tgt_attr() may lead to the usage of rtype when being uninitialized, even though it would only happen if we had entries other than I/O space and 32 bits memory space. This commit fixes that by simply skipping the current DT range being considered, if it doesn't match the resource type we're looking for. Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.12+
2014-09-22PCI: spear: Pass config resource through reg propertyPratyush Anand
PCIe configuration space should be passed through reg property, rather than through ranges property. This patch does the correction for SPEAr13XX SOCs. Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mohit Kumar <mohit.kumar@st.com>
2014-09-22PCI: Generate uppercase hex for modalias interface classRicardo Ribalda Delgado
Some implementations of modprobe fail to load the driver for a PCI device automatically because the "interface" part of the modalias from the kernel is lowercase, and the modalias from file2alias is uppercase. The "interface" is the low-order byte of the Class Code, defined in PCI r3.0, Appendix D. Most interface types defined in the spec do not use alpha characters, so they won't be affected. For example, 00h, 01h, 10h, 20h, etc. are unaffected. Print the "interface" byte of the Class Code in uppercase hex, as we already do for the Vendor ID, Device ID, Class, etc. [bhelgaas: changelog] Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> CC: stable@vger.kernel.org
2014-09-22Merge branches 'pci/host-designware', 'pci/host-imx6', 'pci/host-keystone', ↵Bjorn Helgaas
'pci/host-tegra' and 'pci/host-xilinx' into next * pci/host-designware: PCI: designware: Fold struct pcie_port_info into struct pcie_port * pci/host-imx6: PCI: imx6: Delay enabling reference clock for SS until it stabilizes * pci/host-keystone: PCI: keystone: Set device ID based on SoC to support multiple ports PCI: keystone: Assume controller is already in RC mode PCI: keystone: Limit MRSS for all downstream devices * pci/host-tegra: PCI: tegra: Add Tegra124 support PCI: tegra: Make sure the PCIe PLL is really reset PCI: tegra: Fix extended configuration space mapping PCI: tegra: Clear CLKREQ# enable on port disable * pci/host-xilinx: PCI: xilinx: Fix xilinx_pcie_assign_msi() return value test
2014-09-22Merge branches 'pci/enumeration', 'pci/misc' and 'pci/virtualization' into nextBjorn Helgaas
* pci/enumeration: PCI: Enable CRS Software Visibility for root port if it is supported PCI: Check only the Vendor ID to identify Configuration Request Retry * pci/misc: PCI: Parenthesize PCI_DEVID and PCI_VPD_LRDT_ID parameters PCI: Increase IBM ipr SAS Crocodile BARs to at least system page size PCI/AER: Make <linux/aer.h> standalone includable * pci/virtualization: PCI: Use device flag helper functions xen/pciback: Use PCI device flag helper functions KVM: Use PCI device flag helper functions PCI: Add device flag helper functions PCI: Assume all Mellanox devices have broken INTx masking
2014-09-19Merge tag 'pci-v3.17-fixes-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI fixes from Bjorn Helgaas: "These fix: - Boot video device detection on dual-GPU Apple systems - Hotplug fiascos on VGA switcheroo with radeon & nouveau drivers - Boot hang on Freescale i.MX6 systems - Excessive "no hotplug settings from platform" warnings In particular: Enumeration - Don't default exclusively to first video device (Bruno Prémont) PCI device hotplug - Remove "no hotplug settings from platform" warning (Bjorn Helgaas) - Add pci_ignore_hotplug() for VGA switcheroo (Bjorn Helgaas) Freescale i.MX6 - Put LTSSM in "Detect" state before disabling (Lucas Stach)" * tag 'pci-v3.17-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: vgaarb: Drop obsolete #ifndef vgaarb: Don't default exclusively to first video device with mem+io ACPIPHP / radeon / nouveau: Remove acpi_bus_no_hotplug() PCI: Remove "no hotplug settings from platform" warning PCI: Add pci_ignore_hotplug() to ignore hotplug events for a device PCI: imx6: Put LTSSM in "Detect" state before disabling it MAINTAINERS: Add Lucas Stach as co-maintainer for i.MX6 PCI driver
2014-09-19Revert "PCI: Make sure bus number resources stay within their parents bounds"Bjorn Helgaas
This reverts commit 1820ffdccb9b ("PCI: Make sure bus number resources stay within their parents bounds") because it breaks some systems with LSI Logic FC949ES Fibre Channel Adapters, apparently by exposing a defect in those adapters. Dirk tested a Tyan VX50 (B4985) with this device that worked like this prior to 1820ffdccb9b: bus: [bus 00-7f] on node 0 link 1 ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-07]) pci 0000:00:0e.0: PCI bridge to [bus 0a] pci_bus 0000:0a: busn_res: can not insert [bus 0a] under [bus 00-07] (conflicts with (null) [bus 00-07]) pci 0000:0a:00.0: [1000:0646] type 00 class 0x0c0400 (FC adapter) Note that the root bridge [bus 00-07] aperture is wrong; this is a BIOS defect in the PCI0 _CRS method. But prior to 1820ffdccb9b, we didn't enforce that aperture, and the FC adapter worked fine at 0a:00.0. After 1820ffdccb9b, we notice that 00:0e.0's aperture is not contained in the root bridge's aperture, so we reconfigure it so it *is* contained: pci 0000:00:0e.0: bridge configuration invalid ([bus 0a-0a]), reconfiguring pci 0000:00:0e.0: PCI bridge to [bus 06-07] This effectively moves the FC device from 0a:00.0 to 07:00.0, which should be legal. But when we enumerate bus 06, the FC device doesn't respond, so we don't find anything. This is probably a defect in the FC device. Possible fixes (due to Yinghai): 1) Add a quirk to fix the _CRS information based on what amd_bus.c read from the hardware 2) Reset the FC device after we change its bus number 3) Revert 1820ffdccb9b Fix 1 would be relatively easy, but it does sweep the LSI FC issue under the rug. We might want to reconfigure bus numbers in the future for some other reason, e.g., hotplug, and then we could trip over this again. For that reason, I like fix 2, but we don't know whether it actually works, and we don't have a patch for it yet. This revert is fix 3, which also sweeps the LSI FC issue under the rug. Link: https://bugzilla.kernel.org/show_bug.cgi?id=84281 Reported-by: Dirk Gouders <dirk@gouders.net> Tested-by: Dirk Gouders <dirk@gouders.net> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.15+ CC: Yinghai Lu <yinghai@kernel.org>
2014-09-19Revert "PCI: Don't scan random busses in pci_scan_bridge()"Bjorn Helgaas
This reverts commit fc1b253141b3 ("PCI: Don't scan random busses in pci_scan_bridge()") because it breaks CardBus on some machines. David tested a Dell Latitude D505 that worked like this prior to fc1b253141b3: pci 0000:00:1e.0: PCI bridge to [bus 01] pci 0000:01:01.0: CardBus bridge to [bus 02-05] Note that the 01:01.0 CardBus bridge has a bus number aperture of [bus 02-05], but those buses are all outside the 00:1e.0 PCI bridge bus number aperture, so accesses to buses 02-05 never reach CardBus. This is later patched up by yenta_fixup_parent_bridge(), which changes the subordinate bus number of the 00:1e.0 PCI bridge: pci_bus 0000:01: Raising subordinate bus# of parent bus (#01) from #01 to #05 With fc1b253141b3, pci_scan_bridge() fails immediately when it notices that we can't allocate a valid secondary bus number for the CardBus bridge, and CardBus doesn't work at all: pci 0000:01:01.0: can't allocate child bus 01 from [bus 01] I'd prefer to fix this by integrating the yenta_fixup_parent_bridge() logic into pci_scan_bridge() so we fix the bus number apertures up front. But I don't think we can do that before v3.17, so I'm going to revert this to avoid the problem while we're working on the long-term fix. Link: https://bugzilla.kernel.org/show_bug.cgi?id=83441 Link: http://lkml.kernel.org/r/1409303414-5196-1-git-send-email-david.henningsson@canonical.com Reported-by: David Henningsson <david.henningsson@canonical.com> Tested-by: David Henningsson <david.henningsson@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.15+
2014-09-18Merge branch 'pci/vga'; commit '6a73336bde29' into for-linusBjorn Helgaas
* pci/vga: vgaarb: Drop obsolete #ifndef vgaarb: Don't default exclusively to first video device with mem+io * commit '6a73336bde29': PCI: Remove "no hotplug settings from platform" warning
2014-09-16PCI: xilinx: Fix xilinx_pcie_assign_msi() return value testDan Carpenter
We should be testing "hwirq" instead of "irq". "irq" is unsigned so it's never less than zero. Also it's uninitialized. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Srikanth Thokala <sthokal@xilinx.com>
2014-09-16PCI: tegra: Add Tegra124 supportThierry Reding
The PCIe controller on Tegra124 has two root ports that can be used in a x4/x1 or x2/x1 configuration and can run at PCIe 2.0 link speeds (up to 5 GT/s). The PHY programming has been moved into a separate controller, so the driver now needs to request an external PHY referenced using the device tree. Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16PCI: tegra: Make sure the PCIe PLL is really resetEric Yuen
Depending on the prior state of the controller, the PLL reset may not be pulsed. Clear the register bit and set it after a small delay to ensure that the PLL is really reset. Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Eric Yuen <eyuen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16PCI: tegra: Fix extended configuration space mappingPeter Daifuku
The 16 chunks of 64 KiB that need to be stitched together to make up the configuration space for one bus (1 MiB) are located 24 bits (== 16 MiB) apart in physical address space. This is determined by the start of the extended register field (bits 24-27) in the physical mapping. Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16PCI: tegra: Clear CLKREQ# enable on port disableThierry Reding
When a root port is disabled, disable the CLKREQ# signal if available. Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16PCI: Increase IBM ipr SAS Crocodile BARs to at least system page sizeDouglas Lehr
The Crocodile chip occasionally comes up with 4k and 8k BAR sizes. Due to an erratum, setting the SR-IOV page size causes the physical function BARs to expand to the system page size. Since ppc64 uses 64k pages, when Linux tries to assign the smaller resource sizes to the now 64k BARs the address will be truncated and the BARs will overlap. Force Linux to allocate the resource as a full page, which avoids the overlap. [bhelgaas: print expanded resource, too] Signed-off-by: Douglas Lehr <dllehr@us.ibm.com> Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Milton Miller <miltonm@us.ibm.com> CC: stable@vger.kernel.org
2014-09-16PCI: Use device flag helper functionsEthan Zhao
Use PCI device flag helper functions when checking whether a device is assigned. No functional change. Signed-off-by: Ethan Zhao <ethan.zhao@oracle.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16PCI: keystone: Set device ID based on SoC to support multiple portsMurali Karicheri
K2E SoC has two PCI ports. The SATA controller is connected to second PCI port (port 1). To support multiple port handling in Keystone PCI driver, read the PCI device ID dynamically by iomap/read/unmap during probe and save it in driver's private data and update it in host init code. The PCI device ID field in the RC's config space is not filled by default by the hardware and has to be updated by the PCI driver by reading the same from the SoC register indicated by reg index #2 in DT bindings. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16PCI: keystone: Assume controller is already in RC modeMurali Karicheri
Keystone PCI hardware supports both RC and EP modes and devcfg register has bits to boot strap the device to either of these modes. It seems proper to add this functionality to the boot loader rather than in the driver as device will be operating in either mode, not both any time. Currently the driver supports only RC mode and hence register configuration in the driver is not needed and the driver can assume the hardware is in RC mode. Also update the DT documentation accordingly. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-09-16PCI: keystone: Limit MRSS for all downstream devicesMurali Karicheri
Keystone PCIe controller has a limitation that memory read request size must not exceed 256 bytes. This is a hardware limitation. Add a quirk to force this limit on all downstream devices by updating MRRS. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16PCI: pciehp: Prevent NULL dereference during probeAndreas Noever
pciehp assumes that dev->subordinate, the struct pci_bus for a bridge's secondary bus, exists. But we do not create that bus if we run out of bus numbers during enumeration. This leads to a NULL dereference in init_slot() (and other places). Change pciehp_probe() to return -ENODEV when no secondary bus is present. Signed-off-by: Andreas Noever <andreas.noever@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.2+
2014-09-15Merge branch 'pci/hotplug-vga' into for-linusBjorn Helgaas
* pci/hotplug-vga: ACPIPHP / radeon / nouveau: Remove acpi_bus_no_hotplug() PCI: Add pci_ignore_hotplug() to ignore hotplug events for a device
2014-09-12PCI: pciehp: Reduce PCIe slot_ctrl to 16 bitsBjorn Helgaas
4283c70e91dc ("PCI: pciehp: Make pcie_wait_cmd() self-contained") added a cache of the most recent command written to the Slot Control register. This register is only 16 bits wide, but the cache ("slot_ctrl") is 32 bits. Reduce slot_ctrl to a u16 so it matches the register size. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-12PCI: Configure *all* devices, not just hot-added onesBjorn Helgaas
There's not really a good way to determine whether firmware has already configured a device with _HPP/_HPX settings. On legacy systems, the BIOS has probably configured everything, but on UEFI systems it is not required to do so. Per the PCI Firmware Specification, rev 3.1, sec 3.5, if PCI_COMMAND_IO or PCI_COMMAND_MEMORY is set, we can assume firmware has set the corresponding BARs and maybe we can assume it has configured the rest of the device. And if a bridge has PCI_COMMAND_PARITY or PCI_COMMAND_SERR set, we can assume firmware has configured the bridge. But we can't tell much about devices without BARs. I think it should be safe to apply _HPP and _HPX settings anyway, even if firmware has already configured the device, so configure everything we find. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Yinghai Lu <yinghai@kernel.org>
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