summaryrefslogtreecommitdiff
path: root/drivers/phy/cadence/phy-cadence-sierra.c
AgeCommit message (Collapse)Author
2024-11-27Merge tag 'phy-for-6.13' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "New hardware support: - ST STM32MP25 combophy support - Sparx5 support for lan969x serdes and updates to driver to support this - NXP PTN3222 eUSB2 to USB2 redriver - Qualcomm SAR2130P eusb2 support, QCS8300 USB DW3 and QMP USB2 support, X1E80100 QMP PCIe PHY Gen4 support, QCS615 and QCS8300 QMP UFS PHY support and SA8775P eDP PHY support - Rockchip rk3576 usbdp and rk3576 usb2 phy support - Binding for Microchip ATA6561 can phy Updates: - Freescale driver updates from hdmi support - Conversion of rockchip rk3228 hdmi phy binding to yaml - Broadcom usb2-phy deprecated support dropped and USB init array update for BCM4908 - TI USXGMII mode support in J7200 - Switch back to platform_driver::remove() subsystem update" * tag 'phy-for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (59 commits) phy: qcom: qmp: Fix lecacy-legacy typo phy: lan969x-serdes: add support for lan969x serdes driver dt-bindings: phy: sparx5: document lan969x phy: sparx5-serdes: add support for branching on chip type phy: sparx5-serdes: add indirection layer to register macros phy: sparx5-serdes: add function for getting the CMU index phy: sparx5-serdes: add ops to match data phy: sparx5-serdes: add constant for the number of CMU's phy: sparx5-serdes: add constants to match data phy: sparx5-serdes: add support for private match data phy: bcm-ns-usb2: drop support for old binding variant dt-bindings: phy: bcm-ns-usb2-phy: drop deprecated variant dt-bindings: phy: Add QMP UFS PHY compatible for QCS8300 dt-bindings: phy: qcom: snps-eusb2: Add SAR2130P compatible dt-bindings: phy: ti,tcan104x-can: Document Microchip ATA6561 phy: airoha: Fix REG_CSR_2L_RX{0,1}_REV0 definitions phy: airoha: Fix REG_CSR_2L_JCPLL_SDM_HREN config in airoha_pcie_phy_init_ssc_jcpll() phy: airoha: Fix REG_PCIE_PMA_TX_RESET config in airoha_pcie_phy_init_csr_2l() phy: airoha: Fix REG_CSR_2L_PLL_CMN_RESERVE0 config in airoha_pcie_phy_init_clk_out() phy: phy-rockchip-samsung-hdptx: Don't request RST_PHY/RST_ROPLL/RST_LCPLL ...
2024-10-17phy: Switch back to struct platform_driver::remove()Uwe Kleine-König
After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all platform drivers below drivers/phy/ to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. While touching these files, make indention of the struct initializer consistent in several files. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/20241009065307.504930-2-u.kleine-koenig@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-10-07phy: cadence: Sierra: Fix offset of DEQ open eye algorithm control registerBartosz Wawrzyniak
Fix the value of SIERRA_DEQ_OPENEYE_CTRL_PREG and add a definition for SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG. This fixes the SGMII single link register configuration. Fixes: 7a5ad9b4b98c ("phy: cadence: Sierra: Update single link PCIe register configuration") Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com> Link: https://lore.kernel.org/r/20241003123405.1101157-1-bwawrzyn@cisco.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-08-30phy: cadence: sierra: Simplify with scoped for each OF child loopKrzysztof Kozlowski
Use scoped for_each_available_child_of_node_scoped() when iterating over device nodes to make code a bit simpler. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240826-phy-of-node-scope-v1-3-5b4d82582644@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-31phy: cadence: Sierra: Constify a u32[]Christophe JAILLET
'cdns_sierra_pll_mux_table' is not modified in this driver. And it is only used as a "const u32 *". Constifying this structure moves some data to a read-only section, so increase overall security. On a x86_64, with allmodconfig: Before: ====== text data bss dec hex filename 60937 3894 16 64847 fd4f drivers/phy/cadence/phy-cadence-sierra.o After: ===== text data bss dec hex filename 60897 3878 16 64791 fd17 drivers/phy/cadence/phy-cadence-sierra.o Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/43d881d52e3c1632ad197d4c2c18b6c481a13b24.1720723132.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-31phy: cadence: Sierra: Constify struct cdns_sierra_valsChristophe JAILLET
'struct cdns_sierra_vals' is not modified in this driver. Constifying this structure moves some data to a read-only section, so increase overall security. On a x86_64, with allmodconfig: Before: ====== text data bss dec hex filename 60521 4310 16 64847 fd4f drivers/phy/cadence/phy-cadence-sierra.o After: ===== text data bss dec hex filename 60937 3894 16 64847 fd4f drivers/phy/cadence/phy-cadence-sierra.o Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/0ccfd259fdf40475c89cfb22a64c6388e7c646b4.1720723132.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-07-31phy: cadence: Sierra: Constify struct cdns_reg_pairsChristophe JAILLET
'struct cdns_reg_pairs' is not modified in this driver. Constifying this structure moves some data to a read-only section, so increase overall security. On a x86_64, with allmodconfig: Before: ====== text data bss dec hex filename 60489 4342 16 64847 fd4f drivers/phy/cadence/phy-cadence-sierra.o After: ===== text data bss dec hex filename 60521 4310 16 64847 fd4f drivers/phy/cadence/phy-cadence-sierra.o Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/c57ee8206ebba8c222d7d954335654384072b9ac.1720723132.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-07-12phy: cadence: Sierra: Add single link SGMII register configurationMarcin Wierzbicki
Add single link SGMII register configuration for no SSC for cdns,sierra-phy-t0 compatibility string. The configuration is based on Sierra Programmer's Guide and validated in Cisco CrayAR SoC. Co-developed-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com> Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com> Signed-off-by: Marcin Wierzbicki <mawierzb@cisco.com> Link: https://lore.kernel.org/r/20230626105533.2999966-1-mawierzb@cisco.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-06-08phy: cadence: sierra: Add a determine_rate hookMaxime Ripard
The Cadence Sierra PLL clock implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The latter case would be equivalent to setting the flag CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate hook to __clk_mux_determine_rate(). Indeed, if no determine_rate implementation is provided, clk_round_rate() (through clk_core_round_rate_nolock()) will call itself on the parent if CLK_SET_RATE_PARENT is set, and will not change the clock rate otherwise. And if it was an oversight, then we are at least explicit about our behavior now and it can be further refined down the line. Since the CLK_SET_RATE_NO_REPARENT flag was already set though, it seems unlikely. Cc: Kishon Vijay Abraham I <kishon@kernel.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: linux-phy@lists.infradead.org Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20221018-clk-range-checks-fixes-v4-41-971d5077e7d2@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2023-04-12phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configurationSwapnil Jakhade
Add register sequences for PCIe + SGMII PHY multilink configuration. This has been validated on TI J7 platforms. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230403085644.10187-1-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-31phy: cadence: Sierra: Use clk_parent_data to provide parent informationLars-Peter Clausen
Rather than requesting the parent reference clocks for the sierra PHY PLLs and then assigning the parents as a struct clk. Use the clk_parent_data feature for the clock framework and only specify the firmware names of the parent clocks. The clock framework internally will then translate this to the actual clocks. This allows to remove a bit of boilerplate code. It also allows to only specify a single reference clock for both PLLs, which is a valid use case. The clock framework can handle the case where not all inputs for a clock mux are connected, while the custom implementation in the driver could not. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230326011416.363318-2-lars@metafoo.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-31phy: cadence: Sierra: Replace `clk_register(`) with `clk_hw_register()`Lars-Peter Clausen
The `devm_clk_register()` API is deprecated. Switch to `devm_clk_hw_register()`. Since the driver enables its own internal PLLs using the clock API we still need to get a reference to the PLL clocks using the `devm_clk_hw_get_clk()` API. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20230326011416.363318-1-lars@metafoo.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-03-20phy: cadence: phy-cadence-sierra: Convert to platform remove callback ↵Uwe Kleine-König
returning void The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20230307115900.2293120-5-u.kleine-koenig@pengutronix.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-07-08phy: cadence: Sierra: Remove unused `regmap` field from state structLars-Peter Clausen
The driver state struct for the sierra PHY driver has a field named `regmap` that is never referenced. Remove it since it is unused. Not that there are separate fields of type `struct regmap` for the individual sections of the device's register map. These other regmaps are used and not affected by the patch. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20220707071722.44201-1-lars@metafoo.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-04-13phy: cadence: Sierra: Add TI J721E specific PCIe multilink lane configurationSwapnil Jakhade
This patch adds workaround for TI J721E errata i2183 (https://www.ti.com/lit/er/sprz455a/sprz455a.pdf). PCIe fails to link up if SERDES lanes not used by PCIe are assigned to another protocol. For example, link training fails if lanes 2 and 3 are assigned to another protocol while lanes 0 and 1 are used for PCIe to form a two lane link. This failure is due to an incorrect tie-off on an internal status signal indicating electrical idle. Status signals going from SERDES to PCIe Controller are tied-off when a lane is not assigned to PCIe. Signal indicating electrical idle is incorrectly tied-off to a state that indicates non-idle. As a result, PCIe sees unused lanes to be out of electrical idle and this causes LTSSM to exit Detect.Quiet state without waiting for 12ms timeout to occur. If a receiver is not detected on the first receiver detection attempt in Detect.Active state, LTSSM goes back to Detect.Quiet and again moves forward to Detect.Active state without waiting for 12ms as required by PCIe base specification. Since wait time in Detect.Quiet is skipped, multiple receiver detect operations are performed back-to-back without allowing time for capacitance on the transmit lines to discharge. This causes subsequent receiver detection to always fail even if a receiver gets connected eventually. The workaround only works for 1-lane PCIe configuration. This workaround involves enabling receiver detect override by setting TX_RCVDET_OVRD_PREG_j register of the lane running PCIe to 0x2. This causes SERDES to indicate successful receiver detect when LTSSM is in Detect.Active state, whether a receiver is actually present or not. If the receiver is present, LTSSM proceeds to link up as expected. However if receiver is not present, LTSSM will time out in Polling.Configuration substate since the expected training sequence packets will not be received. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20220303055026.24899-1-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-02-07phy: cadence: Sierra: Add support for skipping configurationAswath Govindraju
In some cases, a single SerDes instance can be shared between two different processors, each using a separate link. In these cases, the SerDes configuration is done in an earlier boot stage. Therefore, add support to skip reconfiguring, if it is was already configured beforehand. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20220128072642.29188-1-a-govindraju@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2022-01-24phy: cadence: Sierra: fix error handling bugs in probe()Dan Carpenter
There are two bugs in the error handling: 1: If devm_of_phy_provider_register() fails then there was no cleanup. 2: The error handling called of_node_put(child) improperly leading to a use after free. We are only holding the reference inside the loop so the last two gotos after the loop lead to a use after free bug. Fix this by cleaning up the partial allocations (or partial iterations) in the loop before doing the goto. Fixes: a43f72ae136a ("phy: cadence: Sierra: Change MAX_LANES of Sierra to 16") Fixes: 44d30d622821 ("phy: cadence: Add driver for Sierra PHY") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Link: https://lore.kernel.org/r/20220115115146.GC7552@kili Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Add support for derived reference clock outputSwapnil Jakhade
Sierra has derived differential reference clock output which is sourced after the spread spectrum generation has been added. Add support to drive derived reference clock out of serdes. Model this derived clock as a "clock" so that platforms using this can enable it. Sierra Main LC VCO PLL divider 1 clock is programmed to output 100MHz clock output. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-16-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configurationSwapnil Jakhade
Add register sequences for PCIe + QSGMII PHY multilink configuration. PHY configuration for multi-link operation is done in two steps. e.g. Consider a case for a 4 lane PHY with PCIe using 2 lanes and QSGMII other 2 lanes. Sierra PHY has 2 PLLs, viz. PLLLC and PLLLC1. So in this case, PLLLC is used for PCIe and PLLLC1 is used for QSGMII. PHY is configured in two steps as described below. [1] For first step, the register values are selected as [TYPE_PCIE][TYPE_QSGMII][ssc]. This will configure PHY registers associated for PCIe involving PLLLC registers and registers for first 2 lanes of PHY. [2] In second step, the register values are selected as [TYPE_QSGMII][TYPE_PCIE][ssc]. This will configure PHY registers associated for QSGMII involving PLLLC1 registers and registers for other 2 lanes of PHY. This completes the PHY configuration for multilink operation. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-14-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Add support for PHY multilink configurationsSwapnil Jakhade
Add support for multilink configuration of Sierra PHY. Currently, maximum two links are supported. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-13-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Fix to get correct parent for mux clocksSwapnil Jakhade
Fix get_parent() callback to return the correct index of the parent for PLL_CMNLC1 clock. Add a separate table of register values corresponding to the parent index for PLL_CMNLC1. Update set_parent() callback accordingly. Fixes: 28081b72859f ("phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)") Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-12-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Update single link PCIe register configurationSwapnil Jakhade
Add single link PCIe register configurations for no SSC and internal SSC. Also, add missing PMA lane registers for external SSC. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-11-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operationSwapnil Jakhade
PIPE phy status is used to communicate the completion of several PHY functions. Check if PHY is ready for operation while configured for PIPE mode during startup. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-10-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Check cmn_ready assertion during PHY power onSwapnil Jakhade
Check if PMA cmn_ready is set indicating the startup process is complete. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-9-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Add PHY PCS common register configurationsSwapnil Jakhade
Add PHY PCS common register configuration sequences for single link. Update single link PCIe register sequence accordingly. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-8-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra ↵Swapnil Jakhade
documentation No functional change. Rename some regmap variables as mentioned in Sierra register description documentation. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-7-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Add support to get SSC type from device treeSwapnil Jakhade
Add support to get SSC type from DT. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-6-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Prepare driver to add support for multilink configurationsSwapnil Jakhade
Sierra driver currently supports single link configurations only. Prepare driver to support multilink multiprotocol configurations along with different SSC modes. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-3-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-12-27phy: cadence: Sierra: Use of_device_get_match_data() to get driver dataSwapnil Jakhade
Use of_device_get_match_data() to get driver data instead of boilerplate code. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Link: https://lore.kernel.org/r/20211223060137.9252-2-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-05-31phy: cadence: Sierra: Fix error return code in cdns_sierra_phy_probe()Wang Wensheng
Fix to return a negative error code from the error handling case instead of 0, as done elsewhere in this function. Fixes: a43f72ae136a ("phy: cadence: Sierra: Change MAX_LANES of Sierra to 16") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wang Wensheng <wangwensheng4@huawei.com> Link: https://lore.kernel.org/r/20210517015749.127799-1-wangwensheng4@huawei.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Enable pll_cmnlc and pll_cmnlc1 clocksKishon Vijay Abraham I
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them. This will enable REFRCV/1 in case the pll_cmnlc/1 takes input from REFRCV/1 respectively. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-14-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks)Kishon Vijay Abraham I
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's possible to select one of these two inputs from device tree. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-13-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callbackKishon Vijay Abraham I
commit 44d30d622821 ("phy: cadence: Add driver for Sierra PHY") enabled the clock in probe and failed to disable in remove callback. Add missing clk_disable_unprepare() in cdns_sierra_phy_remove(). Fixes: 44d30d622821 ("phy: cadence: Add driver for Sierra PHY") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Link: https://lore.kernel.org/r/20210319124128.13308-11-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"Kishon Vijay Abraham I
Instead of having separate structure members for each input clock, add an array for the input clocks within "struct cdns_sierra_phy". This is in preparation for adding more input clocks required for supporting additional clock combination. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-10-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Explicitly request exclusive reset controlKishon Vijay Abraham I
No functional change. Since the reset controls obtained in Sierra is exclusively used by the Sierra device, use exclusive reset control request API calls. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20210319124128.13308-8-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Move all reset_control_get*() to a separate functionKishon Vijay Abraham I
No functional change. Group devm_reset_control_get() and devm_reset_control_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20210319124128.13308-7-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Move all clk_get_*() to a separate functionKishon Vijay Abraham I
No functional change. Group all devm_clk_get_optional() to a separate function. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-6-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodesKishon Vijay Abraham I
Cadence Sierra PHY driver registers PHY using devm_phy_create() for all sub-nodes of Sierra device tree node. However Sierra device tree node can have sub-nodes for the various clocks in addtion to the PHY. Use devm_phy_create() only for nodes with name "phy" (or "link" for old device tree) which represent the actual PHY. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Swapnil Jakhade <sjakhade@cadence.com> Link: https://lore.kernel.org/r/20210319124128.13308-4-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2021-03-31phy: cadence: Sierra: Fix PHY power_on sequenceKishon Vijay Abraham I
Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") de-asserts PHY_RESET even before the configurations are loaded in phy_init(). However PHY_RESET should be de-asserted only after all the configurations has been initialized, instead of de-asserting in probe. Fix it here. Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Cc: <stable@vger.kernel.org> # v5.4+ Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://lore.kernel.org/r/20210319124128.13308-2-kishon@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-11-16phy: cadence: convert to devm_platform_ioremap_resourceChunfeng Yun
Use devm_platform_ioremap_resource to simplify code Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Peter Chen <peter.chen@nxp.com> Link: https://lore.kernel.org/r/1604642930-29019-4-git-send-email-chunfeng.yun@mediatek.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-16phy: cadence: Sierra: Constify static structsRikard Falkeborn
The static cdns_reg_pairs and regmap_config structs are not modified and can be made const. This allows the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200912204639.501669-2-rikard.falkeborn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-05-18phy: cadence: sierra: Fix for USB3 U1/U2 stateSanket Parmar
Updated values of USB3 related Sierra PHY registers. This change fixes USB3 device disconnect issue observed while enternig U1/U2 state. Signed-off-by: Sanket Parmar <sparmar@cadence.com> Link: https://lore.kernel.org/r/1589804053-14302-1-git-send-email-sparmar@cadence.com Reviewed-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-14phy: cadence: Sierra: add phy_reset hookRoger Quadros
Some platforms e.g. J721e need lane swap register to be programmed before reset is deasserted. This patch ensures that we propagate the phy_reset back to the reset controller driver. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Reviewed-by: Jyri Sarha <jsarha@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-14phy: cadence: Sierra: remove redundant initialization of pointer regmapColin Ian King
The pointer regmap is being initialized with a value that is never read and it is being updated later with a new value from phy->regmap_common_cdb. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove()Kishon Vijay Abraham I
commit 44d30d622821d3b ("phy: cadence: Add driver for Sierra PHY"), incorrectly used parent device pointer to get driver data. Fix it here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency ↵Kishon Vijay Abraham I
to 25MHz Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz as specified in "Common Module Clock Configurations" of the Cadence Sierra 16FFC Multi-Protocol PHY PMA Specification. It is set to 25MHz since the only user of Cadence Sierra SERDES, TI J721E SoC provides input clock frequency of 100MHz. For other frequencies, cmn_refclk_dig_div/cmn_refclk1_dig_div should be configured based on the "Common Module Clock Configurations". Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: cadence: Sierra: Change MAX_LANES of Sierra to 16Kishon Vijay Abraham I
Sierra SERDES IP supports upto 16 lanes (though not all of it will be enabled in a platform). Allow Sierra driver to support a maximum of upto 16 lanes. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: cadence: Sierra: Check for PLL lock during PHY power onKishon Vijay Abraham I
Check for PLL lock during PHY power on. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: cadence: Sierra: Get reset control "array" for each linkKishon Vijay Abraham I
A link may have multiple lanes each with a separate reset. Get reset control "array" in order to reset all the lanes associated with the link. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2020-01-08phy: cadence: Sierra: Configure both lane cdb and common cdb registers for ↵Anil Varughese
external SSC The existing configuration done in Cadence Sierra driver is only for reference and is not used in any platforms. Remove them and configure both lane cdb and common cdb registers to be used with external SSC configuration. This is validated in TI J721E platform. Signed-off-by: Anil Varughese <aniljoy@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
generated by cgit (git 2.34.1) at 2025-07-31 08:01:42 +0000