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path: root/drivers/spi
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2022-09-22spi: meson-spicc: make symbol 'meson_spicc_pow2_clk_ops' staticWei Yongjun
The sparse tool complains as follows: drivers/spi/spi-meson-spicc.c:570:22: warning: symbol 'meson_spicc_pow2_clk_ops' was not declared. Should it be static? This symbol is not used outside of spi-meson-spicc.c, so marks it static. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20220922040807.1409540-1-weiyongjun@huaweicloud.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-21spi: omap2-mcspi: Fix probe so driver works againDan Carpenter
This condition was accidentally changed from "if (status < 0)" to "if (status)". The platform_get_irq() function returns non-zero positive values on success so, unfortunately, the driver could not be used. Change the condition back to how it was. Fixes: f4ca8c88c2c7 ("spi: omap2-mcspi: Switch to use dev_err_probe() helper") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/Yyq8Q/kd301wVzg8@kili Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-19spi: pxa2xx: Refactor _UID handling to use acpi_dev_uid_to_integer()Andy Shevchenko
ACPI utils provide acpi_dev_uid_to_integer() helper to extract _UID as an integer. Use it instead of custom approach. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Mark Brown <broonie@kernel.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2022-09-19spi: spi-loopback-test: Add test to trigger DMA/PIO mixingVincent Whitchurch
Add a test where a small and a large transfer in a message hit the same cache line. This test currently fails on spi-s3c64xx on in DMA mode since it ends up mixing DMA and PIO without proper cache maintenance. Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Link: https://lore.kernel.org/r/20220916113951.228398-2-vincent.whitchurch@axis.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-19spi: omap2-mcspi: Switch to use dev_err_probe() helperYang Yingliang
In the probe path, dev_err() can be replace with dev_err_probe() which will check if error code is -EPROBE_DEFER and prints the error name. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220917122504.1896302-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-14spi: mpc52xx: Replace of_gpio_count() by gpiod_count()Andy Shevchenko
As a preparation to unexport of_gpio_named_count(), convert the driver to use gpiod_count() instead. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220914153333.37701-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-14spi: fsl_spi: Convert to transfer_oneChristophe Leroy
Let the core handle all the chipselect bakery and replace transfer_one_message() by transfer_one() and prepare_message(). At the time being, there is fsl_spi_cs_control() to handle chipselects. That function handles both GPIO and non-GPIO chipselects. The GPIO chipselects will now be handled by the core directly, so only handle non-GPIO chipselects and hook it to ->set_cs Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/753266abafe81722d86c3ddb8bac8ef1cb00fe8c.1660829841.git.christophe.leroy@csgroup.eu Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-08Merge tag 'spi-fix-v6.0-rc4' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "Several fixes that came in since the merge window, the major one being a fix for the spi-mux driver which was broken by the performance optimisations due to it peering inside the core's data structures more than it should" * tag 'spi-fix-v6.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: spi: Fix queue hang if previous transfer failed spi: mux: Fix mux interaction with fast path optimisations spi: cadence-quadspi: Disable irqs during indirect reads spi: bitbang: Fix lsb-first Rx
2022-09-08spi: meson-spicc: do not rely on busy flag in pow2 clk opsNeil Armstrong
Since [1], controller's busy flag isn't set anymore when the __spi_transfer_message_noqueue() is used instead of the __spi_pump_transfer_message() logic for spi_sync transfers. Since the pow2 clock ops were limited to only be available when a transfer is ongoing (between prepare_transfer_hardware and unprepare_transfer_hardware callbacks), the only way to track this down is to check for the controller cur_msg. [1] ae7d2346dc89 ("spi: Don't use the message queue if possible in spi_sync") Fixes: 09992025dacd ("spi: meson-spicc: add local pow2 clock ops to preserve rate between messages") Fixes: ae7d2346dc89 ("spi: Don't use the message queue if possible in spi_sync") Reported-by: Markus Schneider-Pargmann <msp@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20220908121803.919943-1-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-08spi: lpspi: Remove the unneeded result variableye xingchen
Return the value pm_runtime_force_suspend() directly instead of storing it in another redundant variable. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Link: https://lore.kernel.org/r/20220908010429.342875-1-ye.xingchen@zte.com.cn Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-07spi: Add capability to perform some transfer with chipselect offChristophe Leroy
Some components require a few clock cycles with chipselect off before or/and after the data transfer done with CS on. Typically IDT 801034 QUAD PCM CODEC datasheet states "Note *: CCLK should have one cycle before CS goes low, and two cycles after CS goes high". The cycles "before" are implicitely provided by all previous activity on the SPI bus. But the cycles "after" must be provided in order to terminate the SPI transfer. In order to use that kind of component, add a cs_off flag to spi_transfer struct. When this flag is set, the transfer is performed with chipselect off. This allows consummer to add a dummy transfer at the end of the transfer list which is performed with chipselect OFF, providing the required additional clock cycles. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/434165c46f06d802690208a11e7ea2500e8da4c7.1662558898.git.christophe.leroy@csgroup.eu Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-07spi: nxp-fspi: Do not dereference fwnode in struct deviceAndy Shevchenko
In order to make the underneath API easier to change in the future, prevent users from dereferencing fwnode from struct device. Instead, use the specific dev_fwnode() API for that. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20220906161048.39953-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-05spi: qup: add missing clk_disable_unprepare on error in ↵Xu Qiang
spi_qup_pm_resume_runtime() Add the missing clk_disable_unprepare() before return from spi_qup_pm_resume_runtime() in the error handling case. Fixes: dae1a7700b34 (“spi: qup: Handle clocks in pm_runtime suspend and resume”) Signed-off-by: Xu Qiang <xuqiang36@huawei.com> Link: https://lore.kernel.org/r/20220825065324.68446-2-xuqiang36@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-05spi: qup: add missing clk_disable_unprepare on error in spi_qup_resume()Xu Qiang
Add the missing clk_disable_unprepare() before return from spi_qup_resume() in the error handling case. Fixes: 64ff247a978f (“spi: Add Qualcomm QUP SPI controller support”) Signed-off-by: Xu Qiang <xuqiang36@huawei.com> Link: https://lore.kernel.org/r/20220825065324.68446-1-xuqiang36@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-02spi: spi: Fix queue hang if previous transfer failedDavid Jander
The queue worker always needs to be kicked one final time after a transfer is done in order to transition to idle (ctlr->busy = false). Commit 69fa95905d40 ("spi: Ensure the io_mutex is held until spi_finalize_current_message()") moved this code into __spi_pump_messages(), but it was executed only if the transfer was successful. This condition check causes ctlr-busy to stay true in case of a failed transfer. This in turn causes that no new work is ever scheduled to the work queue. Fixes: 69fa95905d40 ("spi: Ensure the io_mutex is held until spi_finalize_current_message()") Reported-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Signed-off-by: David Jander <david@protonic.nl> Link: https://lore.kernel.org/r/20220901123630.1098433-1-david@protonic.nl Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-02spi: mux: Fix mux interaction with fast path optimisationsMark Brown
The spi-mux driver is rather too clever and attempts to resubmit any message that is submitted to it to the parent controller with some adjusted callbacks. This does not play at all nicely with the fast path which now sets flags on the message indicating that it's being handled through the fast path, we see async messages flagged as being on the fast path. Ideally the spi-mux code would duplicate the message but that's rather invasive and a bit fragile in that it relies on the mux knowing which fields in the message to copy. Instead teach the core that there are controllers which can't cope with the fast path and have the mux flag itself as being such a controller, ensuring that messages going via the mux don't get partially handled via the fast path. This will reduce the performance of any spi-mux connected device since we'll now always use the thread for both the actual controller and the mux controller instead of just the actual controller but given that we were always hitting the slow path anyway it's hopefully not too much of an additional cost and it allows us to keep the fast path. Fixes: ae7d2346dc89 ("spi: Don't use the message queue if possible in spi_sync") Reported-by: Casper Andersson <casper.casan@gmail.com> Tested-by: Casper Andersson <casper.casan@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20220901120732.49245-1-broonie@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-31spi: stm32-qspi: Refactor dual flash mode enable check in ->setup()Andy Shevchenko
gpiod_count() either returns positive number of the CS or negative error code. In the stm32_qspi_setup() we check that configuration has enough CS for the dual flash mode and SPI mode is not changing over the lines of the code. Taking all above into considertion, refactor dual flash mode enable check by dropping unneeded CS check and reusing local mode variable. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220830182821.47919-2-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-31spi: stm32-qspi: Replace of_gpio_named_count() by gpiod_count()Andy Shevchenko
As a preparation to unexport of_gpio_named_count(), convert the driver to use gpiod_count() instead. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220830182821.47919-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-30spi: amd: Fix speed selectionShreeya Patel
If the current speed is equal to the requested speed by the device then return success. This patch fixes a bug introduced by the commit 3fe26121dc3a ("spi: amd: Configure device speed") which checks speed_hz instead of amd_spi->speed_hz. Fixes: 3fe26121dc3a ("spi: amd: Configure device speed") Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20220830093607.45484-1-shreeya.patel@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-29spi: mt7621: Fix an erroneous message + clean-upsMark Brown
Merge series from Christophe JAILLET <christophe.jaillet@wanadoo.fr>: Patch 1 fixes an issue about an error code that is erroneously logged. Patch 2-4 are just clean-ups spotted while fixing it. Additional comments are added below --- in patches 2 and 3.
2022-08-29spi: mt7621: Remove 'clk' from 'struct mt7621_spi'Christophe JAILLET
The 'clk' field in 'struct mt7621_spi' is useless, remove it. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/76ed0ef91479498b9a2d5ef539f80851cffdb4ea.1661599671.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-29spi: mt7621: Use devm_spi_register_controller()Christophe JAILLET
Now that clk_disable_unprepare(clk) is handled with a managed resource, we can use devm_spi_register_controller() and axe the .remove function. The order between spi_unregister_controller() and clk_disable_unprepare() is still the same. (see commit 46b5c4fb87ce ("spi: mt7621: Don't leak SPI master in probe error path") to see why it matters) Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/b7698e198acc998d99e7e7c895a2910f14f89443.1661599671.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-29spi: mt7621: Use the devm_clk_get_enabled() helper to simplify error handlingChristophe JAILLET
The devm_clk_get_enabled() helper: - calls devm_clk_get() - calls clk_prepare_enable() and registers what is needed in order to call clk_disable_unprepare() when needed, as a managed resource. This helper is well suited for cases where the clock would be kept prepared or enabled for the whole lifetime of the driver. This simplifies the error handling a lot. The order between spi_unregister_controller() (in the remove function) and the clk_disable_unprepare() (now handle by a managed resource) is kept the same. (see commit 46b5c4fb87ce ("spi: mt7621: Don't leak SPI master in probe error path") to see why it matters) Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/05a7fd22719008c8a905d6328aa9548ce40f2a7a.1661599671.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-29spi: mt7621: Fix an error message in mt7621_spi_probe()Christophe JAILLET
'status' is known to be 0 at this point. The expected error code is PTR_ERR(clk). Switch to dev_err_probe() in order to display the expected error code (in a human readable way). This also filters -EPROBE_DEFER cases, should it happen. Fixes: 1ab7f2a43558 ("staging: mt7621-spi: add mt7621 support") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Link: https://lore.kernel.org/r/928f3fb507d53ba0774df27cea0bbba4b055993b.1661599671.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-29spi: add generic R-Car Gen4 and specific r8a779f0 supportMark Brown
Merge series from Wolfram Sang <wsa+renesas@sang-engineering.com>: Here are the patches to enable MSIOF on R-Car S4-8. They also introduce generic Gen4 support and move V3U to Gen4 (which it really is).
2022-08-29spi: stm32-qspi: Fix pm_runtime management in stm32_qspi_transfer_one_message()Patrice Chotard
ctrl->auto_runtime_pm was wrongly set to true when adding transfer_one_message() callback. As explained in commit 6e6ccb3d4cdc ("spi: stm32-qspi: Add pm_runtime support") the expected behavior is to prevent runtime suspends between each transfer. Add needed pm_runtime API calls in stm32_qspi_transfer_one_message(). Fixes: a557fca630cc ("spi: stm32_qspi: Add transfer_one_message() spi callback") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220829123250.2170562-1-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-29spi: sh-msiof: add generic Gen4 bindingWolfram Sang
No further changes in this generation discovered yet. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220824094327.33685-3-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-28spi: stm32-qspi: Fix stm32_qspi_transfer_one_message() error pathPatrice Chotard
The patch a557fca630cc: "spi: stm32_qspi: Add transfer_one_message() spi callback" from Aug 23, 2022, leads to the following Smatch static checker warning: drivers/spi/spi-stm32-qspi.c:627 stm32_qspi_transfer_one_message() error: uninitialized symbol 'ret'.Fix the following Smatch static checker warning: Fixes: a557fca630cc ("spi: stm32_qspi: Add transfer_one_message() spi callback") Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220826092031.1393430-1-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-25spi: amd: Configure device speedLucas Tanure
Number of clock frequencies are supported by AMD controller which are mentioned in the amd_spi_freq structure table. Create mechanism to configure device clock frequency such that it is strictly less than the requested frequency. Give priority to the device transfer speed and in case it is not set then use the max clock speed supported by the device. Signed-off-by: Lucas Tanure <tanureal@opensource.cirrus.com> Co-developed-by: Shreeya Patel <shreeya.patel@collabora.com> Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com> Link: https://lore.kernel.org/r/20220825143132.253224-1-shreeya.patel@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-25spi: pxa2xx: Remove the unneeded result variableye xingchen
Return the value clk_prepare_enable() directly instead of storing it in another redundant variable. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Link: https://lore.kernel.org/r/20220825072828.229294-1-ye.xingchen@zte.com.cn Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-24ACPI: Drop parent field from struct acpi_deviceRafael J. Wysocki
The parent field in struct acpi_device is, in fact, redundant, because the dev.parent field in it effectively points to the same object and it is used by the driver core. Accordingly, the parent field can be dropped from struct acpi_device and for this purpose define acpi_dev_parent() to retrieve a parent struct acpi_device pointer from the dev.parent field in struct acpi_device. Next, update all of the users of the parent field in struct acpi_device to use acpi_dev_parent() instead of it and drop it. While at it, drop the ACPI_IS_ROOT_DEVICE() macro that is only used in one place in a confusing way. No intentional functional impact. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Wei Liu <wei.liu@kernel.org> Reviewed-by: Punit Agrawal <punit.agrawal@bytedance.com>
2022-08-23spi: stm32_qspi: use QSPI bus as 8 lines communication channelMark Brown
Merge series from patrice.chotard@foss.st.com <patrice.chotard@foss.st.com>: The goal of this series is to allow to use QSPI bus as a 8 lines communication channel for specific purpose. The QSPI block offers the possibility to communicate with 2 flashes in parrallel using the dual flash mode, 8 data lines are then used. Usage of cs-gpios populated and spi-tx-bus-width / spi-rx-bus-width both set to 8, is needed to enable dual flash mode. The addition of the legacy transfer_one_message() spi callback is also needed as currently the stm32-qspi driver only supports spi_controller_mem_ops API.
2022-08-23spi: dw: Quite logging on deferred controller registrationSerge Semin
It's pretty possible to have the spi_register_controller() method returning -EPROBE_DEFER status in case, for instance, if the GPIOs used for the CS implementation aren't ready to be requested due to the corresponding platform devices still pending to be probed. Let's make sure the DW SSI driver won't print error message in that case by calling the dev_err_probe() function if the SPI-registration procedure exited with a non-zero status. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20220822181853.23063-1-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-23spi: stm32_qspi: Add transfer_one_message() spi callbackPatrice Chotard
Add transfer_one_message() spi callback in order to use the QSPI interface as a communication channel using up to 8 qspi lines (QSPI configured in dual flash mode). To enable this mode, both spi-rx-bus-width and spi-tx-bus-width must be set to 8 and cs-qpios must be populated. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20220823075850.575043-3-patrice.chotard@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-22spi: intel: 64k erase is supported from Canon Lake and beyondMika Westerberg
The hardware sequencer in Intel Canon Lake and beyond supports also 64k erase command. The SPI-NOR core uses SFDP (Serial Flash Discovery Parameter) to figure out what the chip actually supports and only issues 64k erase if it is supported. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20220816125537.89389-1-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-22spi: intel: Add support for second flash chipMika Westerberg
Intel SPI flash controller has been supporting two chip selects long time already even if the most common configuration is to have a single flash chip for the BIOS and related data. This adds support for the second chip select if we find out that there are two flash components (this information is available in the mandatory flash descriptor on the first chip). The second chip is exposed as is without any partition information. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20220816130818.89600-1-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-22spi: cadence-quadspi: Disable irqs during indirect readsNiravkumar L Rabara
On architecture where reading the SRAM is slower than the pace at controller fills it, with interrupt enabled while reading from SRAM FIFO causes unwanted interrupt storm to CPU. The inner "bytes to read" loop never exits and waits for the completion so it is enough to only enable the watermark interrupt when we are out of bytes to read, which only happens when we start the transfer (waiting for the FIFO to fill up initially) if the SRAM is slow. So only using read watermark interrupt, as the current implementation doesn't utilize the SRAM full and indirect complete read interrupt. And disable all the read interrupts while reading from SRAM. Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> Link: https://lore.kernel.org/r/20220813042616.1372110-1-niravkumar.l.rabara@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-19spi: move from strlcpy with unused retval to strscpyWolfram Sang
Follow the advice of the below link and prefer 'strscpy' in this subsystem. Conversion is 1:1 because the return value is not used. Generated by a coccinelle script. Link: https://lore.kernel.org/r/CAHk-=wgfRnXz0W3D37d01q3JFkr_i_uTL=V6A6G1oUZcprmknw@mail.gmail.com/ Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220818210107.7373-1-wsa+renesas@sang-engineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-18spi: amd: Setup all xfers before opcode executionCristian Ciocaltea
The AMD SPI controller hardware seems to expect the FIFO buffer to be fully setup with the details of all transfers in the SPI message before it is able to start processing the data in a reliable way. Furthermore, it imposes a strict ordering restriction, in the sense that all TX transfers must be handled prior any RX transfer. Hence, let's ensure amd_spi_execute_opcode() is called only once, after all TX transfers have been setup, and process any remaining RX transfers afterwards, in a second iteration. Additionally, get rid of the unnecessary AMD_SPI_XFER_TX/RX defines and improve error handling. Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://lore.kernel.org/r/20220818010059.403776-1-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-16Merge tag 'spi-fix-v6.0-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A few fixes that came in since my pull request, the Meson fix is a little large since it's fixing all possible cases of the problem that was observed with the driver and clock API trying to share configuration by integrating the device clocking fully with the clock API rather than spot fixing the one instance that was observed" * tag 'spi-fix-v6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: dt-bindings: Drop Pratyush Yadav spi: meson-spicc: add local pow2 clock ops to preserve rate between messages MAINTAINERS: rectify entry for ARM/HPE GXP ARCHITECTURE spi: spi.c: Add missing __percpu annotations in users of spi_statistics
2022-08-15spi: npcm-pspi: add Arbel NPCM8XX supportMark Brown
Merge series from Tomer Maimon <tmaimon77@gmail.com>: This patch set adds Arbel NPCM8XX Peripheral SPI (PSPI) support to PSPI NPCM driver.
2022-08-15Add support for Microchip QSPI controllerMark Brown
Merge series from Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>: This patch enables the Microchip's FPGA QSPI and Polarfire SoC QSPI controller support. Tested spi-nand (W25N01GV) and spi-nor (MT25QL256A) on Microchip's ICICLE kit. tested using both FPGA QSPI and Polarfie SoC QSPI.
2022-08-15spi: lpspi: Simplify some error messageChristophe JAILLET
dev_err_probe() already prints the error code in a human readable way, so there is no need to duplicate it as a numerical value at the end of the message. Fixes: 12f62a857c83 ("spi: lpspi: Silence error message upon deferred probe") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-By: Alexander Stein <alexander.stein@ew.tq-group.com> Link: https://lore.kernel.org/r/253543c462b765eca40ba54c66f4e3fdf4acdeb7.1659735546.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-15spi: microchip-core: Simplify some error messageChristophe JAILLET
dev_err_probe() already prints the error code in a human readable way, so there is no need to duplicate it as a numerical value at the end of the message. Moreover, in the case of devm_clk_get() it would only display '0' because 'ret' is know to be 0 at this point. Fixes: cdeaf3a99a02 ("spi: microchip-core: switch to use dev_err_probe()") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/fb894ecec68e03fb7fc9353027c8b1a2610833d7.1659735153.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-15spi: s3c64xx: correct dma_chan pointer initializationChanho Park
Use NULL for dma channel pointer initialization instead of plain integer. sparse warnings: (new ones prefixed by >>) >> drivers/spi/spi-s3c64xx.c:387:34: sparse: sparse: Using plain integer as NULL pointer drivers/spi/spi-s3c64xx.c:388:34: sparse: sparse: Using plain integer as NULL pointer Reported-by: kernel test robot <lkp@intel.com> Fixes: 82295bc0d192 ("spi: s3c64xx: move dma_release_channel to unprepare") Fixes: f52b03c70744 ("spi: s3c64xx: requests spi-dma channel only during data transfer") Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Andi Shyti <andi@etezian.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220808004851.25122-1-chanho61.park@samsung.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-15spi: microchip-core-qspi: Add support for microchip fpga qspi controllersNaga Sureshkumar Relli
Add a driver for Microchip FPGA QSPI controllers. This driver also supports "hard" QSPI controllers on Polarfire SoC. Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220808064603.1174906-4-nagasuresh.relli@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-15spi: npcm-pspi: Add NPCM845 peripheral SPI supportTomer Maimon
Add Nuvoton BMC NPCM845 NPCM Peripheral SPI (PSPI) support. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20220722114136.251415-3-tmaimon77@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-15spi: bitbang: Fix lsb-first RxRobin Murphy
Shifting the recieved bit by "bits" inserts it at the top of the *currently remaining* Tx data, so we end up accumulating the whole transfer into bit 0 of the output word. Oops. For the algorithm to work as intended, we need to remember where the top of the *original* word was, and shift Rx to there. Fixes: 1847e3046c52 ("spi: gpio: Implement LSB First bitbang support") Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/28324d8622da80461cce35a82859b003d6f6c4b0.1659538737.git.robin.murphy@arm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-15Merge remote-tracking branch 'spi/for-5.20' into spi-6.0Mark Brown
2022-08-11spi: meson-spicc: add local pow2 clock ops to preserve rate between messagesNeil Armstrong
At the end of a message, the HW gets a reset in meson_spicc_unprepare_transfer(), this resets the SPICC_CONREG register and notably the value set by the Common Clock Framework. This is problematic because: - the register value CCF can be different from the corresponding CCF cached rate - CCF is allowed to change the clock rate whenever the HW state This introduces: - local pow2 clock ops checking the HW state before allowing a clock operation - separation of legacy pow2 clock patch and new enhanced clock path - SPICC_CONREG datarate value is now value kepts across messages It has been checked that: - SPICC_CONREG datarate value is kept across messages - CCF is only allowed to change the SPICC_CONREG datarate value when busy - SPICC_CONREG datarate value is correct for each transfer This didn't appear before commit 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support") because we recalculated and wrote the rate for each xfer. Fixes: 3e0cf4d3fc29 ("spi: meson-spicc: add a linear clock divider support") Reported-by: Da Xue <da@libre.computer> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220811134445.678446-1-narmstrong@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
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