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path: root/drivers/spi
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4 daysspi: spi-pci1xxxx: Drop MSI-X usage as unsupported by DMA engineThangaraj Samynathan
Removes MSI-X from the interrupt request path, as the DMA engine used by the SPI controller does not support MSI-X interrupts. Signed-off-by: Thangaraj Samynathan <thangaraj.s@microchip.com> Link: https://patch.msgid.link/20250612023059.71726-1-thangaraj.s@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
5 daysspi: stm32-ospi: clean up on error in probe()Dan Carpenter
If reset_control_acquire() fails, then we can't return directly. We need to do a little clean up first. Fixes: cf2c3eceb757 ("spi: stm32-ospi: Make usage of reset_control_acquire/release() API") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://patch.msgid.link/aEmAGTUzzKZlLe3K@stanley.mountain Signed-off-by: Mark Brown <broonie@kernel.org>
7 daysSPI: omap2-mcspi: Fix SPI CS behaviour aroundMark Brown
Merge series from Félix Piédallu <felix.piedallu@non.se.com>: These patches fix the behaviour of the SPI Chip Select of the OMAP2 MCSPI driver used on TI SoCs. The omap2-mcspi driver supports the use of multi mode (multichannel in TI documentation). In this mode, the CS is asserted and deasserted by the hardware. The multi mode is disabled for messages when cs_change=0 for all transfers (e.g when CS is kept asserted between transfers of a same message). The multi mode also needs to be disabled for messages when cs_change=1 on the last transfer (e.g when CS is kept asserted after the WHOLE message), and the message right after. Currently, that is not the case and it CS is deasserted by hardware when it shouldn't. This breaks peripheral drivers that send multiple messages with the CS asserted in between. Patch 1 ensures that multi mode is disabled when cs_change=1 on the last transfer of the message. Patch 2 ensures that multi mode is disable on a message following one with cs_change=1 on the last transfer. This is the case for the TPM TIS SPI driver that uses this logic for flow control purposes. Tested on an AM6442 platform with a TPM ST33HTPH2X32AHE4.
7 daysspi: stm32-ospi: Make usage of reset_control_acquire/release() APIPatrice Chotard
As ospi reset is consumed by both OMM and OSPI drivers, use the reset acquire/release mechanism which ensure exclusive reset usage. This avoid to call reset_control_get/put() in OMM driver each time we need to reset OSPI children and guarantee the reset line stays deasserted. During resume, OMM driver takes temporarily control of reset. Fixes: 79b8a705e26c ("spi: stm32: Add OSPI driver") Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://patch.msgid.link/20250609-b4-upstream_ospi_reset_update-v6-1-5b602b567e8a@foss.st.com Signed-off-by: Mark Brown <broonie@kernel.org>
8 daysspi: offload: check offload ops existence before disabling the triggerAndres Urian Florez
Add a safe guard in spi_offload_trigger to check the existence of offload->ops before invoking the trigger_disable callback Signed-off-by: Andres Urian Florez <andres.emb.sys@gmail.com> Link: https://patch.msgid.link/20250608230422.325360-1-andres.emb.sys@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
8 daysspi: spi-pci1xxxx: Fix error code in probeDan Carpenter
Return the error code if pci_alloc_irq_vectors() fails. Don't return success. Fixes: b4608e944177 ("spi: spi-pci1xxxx: Fix Probe failure with Dual SPI instance with INTx interrupts") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Thangaraj Samynathan <thangaraj.s@microchip.com> Link: https://patch.msgid.link/aEKvDrUxD19GWi0u@stanley.mountain Signed-off-by: Mark Brown <broonie@kernel.org>
8 daysspi: loongson: Fix build warnings about export.hHuacai Chen
After commit a934a57a42f64a4 ("scripts/misc-check: check missing #include <linux/export.h> when W=1") and 7d95680d64ac8e836c ("scripts/misc-check: check unnecessary #include <linux/export.h> when W=1"), we get some build warnings with W=1: drivers/spi/spi-loongson-core.c: warning: EXPORT_SYMBOL() is used, but #include <linux/export.h> is missing So fix these build warnings for SPI/Loongson. Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Link: https://patch.msgid.link/20250608142939.172108-1-chenhuacai@loongson.cn Signed-off-by: Mark Brown <broonie@kernel.org>
8 daysspi: omap2-mcspi: Disable multi-mode when the previous message kept CS assertedFélix Piédallu
When the last transfer of a SPI message has the cs_change flag, the CS is kept asserted after the message. The next message can't use multi-mode because the CS will be briefly deasserted before the first transfer. Remove the early exit of the list_for_each_entry because the last transfer actually needs to be always checked. Fixes: d153ff4056cb ("spi: omap2-mcspi: Add support for MULTI-mode") Signed-off-by: Félix Piédallu <felix.piedallu@non.se.com> Link: https://patch.msgid.link/20250606-cs_change_fix-v1-2-27191a98a2e5@non.se.com Signed-off-by: Mark Brown <broonie@kernel.org>
8 daysspi: omap2-mcspi: Disable multi mode when CS should be kept asserted after ↵Félix Piédallu
message When the last transfer of a SPI message has the cs_change flag, the CS is kept asserted after the message. Multi-mode can't respect this as CS is deasserted by the hardware at the end of the message. Disable multi-mode when not applicable to the current message. Fixes: d153ff4056cb ("spi: omap2-mcspi: Add support for MULTI-mode") Signed-off-by: Félix Piédallu <felix.piedallu@non.se.com> Link: https://patch.msgid.link/20250606-cs_change_fix-v1-1-27191a98a2e5@non.se.com Signed-off-by: Mark Brown <broonie@kernel.org>
10 daysMerge tag 'spi-v6.16-merge-window' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull more spi updates from Mark Brown: "A small set of updates that came in during the merge window, we've got: - Some small fixes for the Broadcom and spi-pci1xxxx drivers - A change to the QPIC SNAND driver to flag that the error correction features are less useful than people might be expecting - A new device ID for the SOPHGO SG2042 - The addition of Yang Shen as a Huawei maintainer" * tag 'spi-v6.16-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: spi-qpic-snand: document the limited bit error reporting capability spi: bcm63xx-hsspi: fix shared reset spi: bcm63xx-spi: fix shared reset MAINTAINERS: Update HiSilicon SFC driver maintainer MAINTAINERS: Update HiSilicon SPI Controller driver maintainer spi: dt-bindings: spi-sg2044-nor: Add SOPHGO SG2042 spi: spi-pci1xxxx: Fix Probe failure with Dual SPI instance with INTx interrupts
2025-06-02Merge tag 'mtd/for-6.16' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Miquel Raynal: "A big core MTD change is the introduction of a new class to always register a master device. This is a problem that has been there forever: the "master" device was not always present depending on a number of heuristics such as the presence of fixed partitions and the absence of a Kconfig symbol to force its presence. This was a problem for runtime PM operations which might not have the "master" device available in all situation. The SPI NAND subsystem has seen the introduction of DTR operations (the equivalent of DDR transfers), which involved quite a few preparation patches for clarifying macro names. In the raw NAND subsystem, the brcmnand driver has been "fixed" for old legacy SoCs with an update of the ->exec_op() hook, there has been the introduction of a new controller driver named Loongson-1, and the Qualcomm driver has received quite a few misc fixes as well as a new compatible. Finally, Macornix SPI NOR entries have been cleaned-up and some SFDP table fixups for Macronix MX25L3255E have been merged. Aside from this, there is the usual load of misc improvement, fixes, and yaml conversion" * tag 'mtd/for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (42 commits) mtd: rawnand: brcmnand: legacy exec_op implementation mtd: rawnand: sunxi: Add randomizer configuration in sunxi_nfc_hw_ecc_write_chunk mtd: nand: brcmnand: fix NAND timeout when accessing eMMC mtd: nand: sunxi: Add randomizer configuration before randomizer enable mtd: spinand: esmt: fix id code for F50D1G41LB mtd: rawnand: brcmnand: remove unused parameters mtd: core: always create master device mtd: rawnand: loongson1: Fix inconsistent refcounting in ls1x_nand_chip_init() mtd: rawnand: loongson1: Fix error code in ls1x_nand_dma_transfer() mtd: rawnand: qcom: Fix read len for onfi param page mtd: rawnand: qcom: Fix last codeword read in qcom_param_page_type_exec() mtd: rawnand: qcom: Pass 18 bit offset from NANDc base to BAM base dt-bindings: mtd: qcom,nandc: Document the SDX75 NAND controller mtd: bcm47xxnflash: Add error handling for bcm47xxnflash_ops_bcm4706_ctl_cmd() mtd: rawnand: Use non-hybrid PCI devres API mtd: nand: ecc-mxic: Fix use of uninitialized variable ret mtd: spinand: winbond: Add support for W35N02JW and W35N04JW chips mtd: spinand: winbond: Add octal support mtd: spinand: winbond: Add support for W35N01JW in single mode mtd: spinand: winbond: Rename DTR variants ...
2025-06-02spi: spi-qpic-snand: document the limited bit error reporting capabilityGabor Juhos
The QPIC hardware is not capable of reporting the exact number of the corrected bit errors, it only reports the number of the corrected bytes. Document this behaviour in the code, and also issue a warning message to inform the user about it. No functional changes. Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Link: https://patch.msgid.link/20250527-qpic-snand-limited-biterr-caps-v1-1-61f7cf87be1e@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-30spi: bcm63xx-hsspi: fix shared resetÁlvaro Fernández Rojas
Some bmips SoCs (bcm6362, bcm63268) share the same SPI reset for both SPI and HSSPI controllers, so reset shouldn't be exclusive. Fixes: 0eeadddbf09a ("spi: bcm63xx-hsspi: add reset support") Reported-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://patch.msgid.link/20250529130915.2519590-3-noltari@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-30spi: bcm63xx-spi: fix shared resetÁlvaro Fernández Rojas
Some bmips SoCs (bcm6362, bcm63268) share the same SPI reset for both SPI and HSSPI controllers, so reset shouldn't be exclusive. Fixes: 38807adeaf1e ("spi: bcm63xx-spi: add reset support") Reported-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://patch.msgid.link/20250529130915.2519590-2-noltari@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-27Merge tag 'spi-v6.16' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "The bulk of the changes in this release are driver work, as well as new device support we have some important work on performance over several drivers, and big overhauls for maintainability on a couple too. Highlights include: - Big cleanups of the sh-msiof driver from Geert Uytterhoeven, and of the NXP FSPI driver from Haibo Chen - Performance improvements for the AXI SPI engine - Support for writes to memory mapped flashes on Renesas devices - Integrated DMA support for Tegra210 QSPI, used by the Tegra234 - DMA support for Amlogic SPI controllers - Support for AMD HID2, Qualcomm IPQ5018, Renesas RZ/G3E, Rockchip RK3528 and Samsung Exynos Autov920 An update to fix some issues with the Atmel QSPI driver runtime PM pulled in a new API from the PM core, and the Renesas memory mapped write changes pull in some code that's shared in drivers/memory" * tag 'spi-v6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (90 commits) spi: spi-qpic-snand: return early on error from qcom_spi_io_op() spi: loopback-test: fix up const pointer issue in rx_ranges_cmp() spi: gpio: fix const issue in spi_to_spi_gpio() spi: spi-qpic-snand: remove superfluous parameters of qcom_spi_check_error() dt-bindings: spi: samsung: add exynosautov920-spi compatible spi: spi-qpic-snand: reuse qcom_spi_check_raw_flash_errors() spi: dt-bindings: Add rk3528-spi compatible spi: spi_amd: Update Kconfig dependencies spi: spi_amd: Add HIDDMA basic write support spi: spi_amd: Remove read{q,b} usage on DMA buffer spi: sh-msiof: Move register definitions to <linux/spi/sh_msiof.h> spi: sh-msiof: Document frame start sync pulse mode spi: sh-msiof: Double maximum DMA transfer size using two groups spi: sh-msiof: Simplify BRG's Division Ratio spi: sh-msiof: Increase TX FIFO size for R-Car V4H/V4M spi: sh-msiof: Correct RX FIFO size for R-Car Gen3 spi: sh-msiof: Correct RX FIFO size for R-Car Gen2 spi: sh-msiof: Add core support for dual-group transfers spi: sh-msiof: Correct SIMDR2_GRPMASK spi: sh-msiof: SIFCTR bitfield conversion ...
2025-05-27Merge tag 'sound-6.16-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound Pull sound updates from Takashi Iwai: "We've received a lot of activities in this cycle, mostly about leaf driver codes rather than the core part, but with a good mixture of code cleanups and new driver additions. Below are some highlights: ASoC: - Support for automatically enumerating DAIs from standards conforming SoundWire SDCA devices; not much used as of this writing, rather for future implementations - Conversion of quite a few drivers to newer GPIO APIs - Continued cleanups and helper usages in allover places - Support for a wider range of Intel AVS platforms - Support for AMD ACP 7.x platforms, Cirrus Logic CS35L63 and CS48L32 Everest Semiconductor ES8375 and ES8389, Longsoon-1 AC'97 controllers, nVidia Tegra264, Richtek ALC203 and RT9123 and Rockchip SAI controllers HD-audio: - Lots of cleanups of TAS2781 codec drivers - A new HD-audio control bound via ACPI for Nvidia - Support for Tegra264, Intel WCL, usual new codec quirks USB-audio: - Fix a race at removal of MIDI device - Pioneer DJM-V10 support, Scarlett2 driver cleanups Misc: - Cleanups of deprecated PCI functions - Removal of unused / dead function codes" * tag 'sound-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (364 commits) firmware: cs_dsp: Fix OOB memory read access in KUnit test ASoC: codecs: add support for ES8375 ASoC: dt-bindings: Add Everest ES8375 audio CODEC ALSA: hda: acpi: Make driver's match data const static ALSA: hda: acpi: Use SYSTEM_SLEEP_PM_OPS() ALSA: atmel: Replace deprecated strcpy() with strscpy() ALSA: core: fix up bus match const issues. ASoC: wm_adsp: Make cirrus_dir const ASoC: tegra: Tegra264 support in isomgr_bw ASoC: tegra: AHUB: Add Tegra264 support ASoC: tegra: ADX: Add Tegra264 support ASoC: tegra: AMX: Add Tegra264 support ASoC: tegra: I2S: Add Tegra264 support ASoC: tegra: Update PLL rate for Tegra264 ASoC: tegra: ASRC: Update ARAM address ASoC: tegra: ADMAIF: Add Tegra264 support ASoC: tegra: CIF: Add Tegra264 support dt-bindings: ASoC: Document Tegra264 APE support dt-bindings: ASoC: admaif: Add missing properties ASoC: dt-bindings: audio-graph-card2: reference audio-graph routing property ...
2025-05-27spi: spi-pci1xxxx: Fix Probe failure with Dual SPI instance with INTx interruptsThangaraj Samynathan
Fixes a probe failure that occurs when dual SPI controllers are enabled and INTx interrupts are used. Reduces the minimum required number of interrupt vectors to 1 and registers a shared ISR when the allocated vectors are fewer than the number of controllers. This change ensures that the probe succeeds even with limited vectors, restoring INTx functionality when multiple SPI controllers are present. Signed-off-by: Thangaraj Samynathan <thangaraj.s@microchip.com> Link: https://patch.msgid.link/20250527103244.26861-1-thangaraj.s@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-23spi: spi-qpic-snand: extend bitmasks usageMark Brown
Merge series from Gabor Juhos <j4g8y7@gmail.com>: The two patches in the series are extending the usage of FIELD_PREP() macro and predefined bitmasks usage in the driver.
2025-05-23spi: spi-qpic-snand: return early on error from qcom_spi_io_op()Gabor Juhos
When submitting of the descriptors fails, it is quite likely that the register read buffer contains no valid data. Even if the data is valid the function returns with an error code anyway. Change the code to return early if qcom_submit_descs() fails to avoid superfluously copying possibly invalid data. Also change the return statement at the end of the function to use zero value to indicate success obviusly. Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Link: https://patch.msgid.link/20250515-qpic-snand-early-error-v1-1-681c87611213@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-22spi: spi-fsl-dspi: Reset SR flags before sending a new messageLarisa Grigore
If, in a previous transfer, the controller sends more data than expected by the DSPI target, SR.RFDF (RX FIFO is not empty) will remain asserted. When flushing the FIFOs at the beginning of a new transfer (writing 1 into MCR.CLR_TXF and MCR.CLR_RXF), SR.RFDF should also be cleared. Otherwise, when running in target mode with DMA, if SR.RFDF remains asserted, the DMA callback will be fired before the controller sends any data. Take this opportunity to reset all Status Register fields. Fixes: 5ce3cc567471 ("spi: spi-fsl-dspi: Provide support for DSPI slave mode operation (Vybryd vf610)") Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: James Clark <james.clark@linaro.org> Link: https://patch.msgid.link/20250522-james-nxp-spi-v2-3-bea884630cfb@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-22spi: spi-fsl-dspi: Halt the module after a new message transferBogdan-Gabriel Roman
The XSPI mode implementation in this driver still uses the EOQ flag to signal the last word in a transmission and deassert the PCS signal. However, at speeds lower than ~200kHZ, the PCS signal seems to remain asserted even when SR[EOQF] = 1 indicates the end of a transmission. This is a problem for target devices which require the deassertation of the PCS signal between transfers. Hence, this commit 'forces' the deassertation of the PCS by stopping the module through MCR[HALT] after completing a new transfer. According to the reference manual, the module stops or transitions from the Running state to the Stopped state after the current frame, when any one of the following conditions exist: - The value of SR[EOQF] = 1. - The chip is in Debug mode and the value of MCR[FRZ] = 1. - The value of MCR[HALT] = 1. This shouldn't be done if the last transfer in the message has cs_change set. Fixes: ea93ed4c181b ("spi: spi-fsl-dspi: Use EOQ for last word in buffer even for XSPI mode") Signed-off-by: Bogdan-Gabriel Roman <bogdan-gabriel.roman@nxp.com> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: James Clark <james.clark@linaro.org> Link: https://patch.msgid.link/20250522-james-nxp-spi-v2-2-bea884630cfb@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-22spi: spi-fsl-dspi: restrict register range for regmap accessLarisa Grigore
DSPI registers are NOT continuous, some registers are reserved and accessing them from userspace will trigger external abort, add regmap register access table to avoid below abort. For example on S32G: # cat /sys/kernel/debug/regmap/401d8000.spi/registers Internal error: synchronous external abort: 96000210 1 PREEMPT SMP ... Call trace: regmap_mmio_read32le+0x24/0x48 regmap_mmio_read+0x48/0x70 _regmap_bus_reg_read+0x38/0x48 _regmap_read+0x68/0x1b0 regmap_read+0x50/0x78 regmap_read_debugfs+0x120/0x338 Fixes: 1acbdeb92c87 ("spi/fsl-dspi: Convert to use regmap and add big-endian support") Co-developed-by: Xulin Sun <xulin.sun@windriver.com> Signed-off-by: Xulin Sun <xulin.sun@windriver.com> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: James Clark <james.clark@linaro.org> Link: https://patch.msgid.link/20250522-james-nxp-spi-v2-1-bea884630cfb@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-22spi: loopback-test: fix up const pointer issue in rx_ranges_cmp()Greg Kroah-Hartman
When a list head is a const pointer, the list entry for that head also must remain a const pointer, otherwise we are just "throwing it away" for no good reason. Fix this up by properly marking these structures as const. Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://patch.msgid.link/2025052213-semifinal-sublevel-d631@gregkh Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-22spi: gpio: fix const issue in spi_to_spi_gpio()Greg Kroah-Hartman
While the struct spi_device * passed into spi_to_spi_gpio() is a const one, the struct spi_bitbang * that is retrieved from the controller field in the spi_device is NOT a const pointer, as it is coming from the spi_controller_get_devdata() call, and then passed to container_of() which would strip off the const attribute for no good reason (i.e. if a const pointer is passed to container_of() it still is const coming out). Fix this all up by properly declaring the struct spi_bitbang * as not const. Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Link: https://patch.msgid.link/2025052225-scallion-ritzy-dbbd@gregkh Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-21spi: spi-qpic-snand: remove superfluous parameters of qcom_spi_check_error()Gabor Juhos
The qcom_spi_check_error() function determines the errors of a previous page read operation solely by using the cached register values in the register read buffer. The data pointed by the 'data_buf' and the 'oob_buf' parameters are not used for that at all. Remove the superfluous parameters of the function along with the related local variables to simplify the code. Also, remove the variables from the caller functions which became unused due to the change. Note: Althought the similar parse_read_errors() function in the 'qcom_nand' driver has the same parameters, but that function passes down the pointers to check_for_erased_page() at the end of the function. It is not clear, that a similar call is missing here, or the superfluous parameters are simply leftovers of the development process. Nevertheless, if additional code is needed, the parameters can be added back later. Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Link: https://patch.msgid.link/20250520-qpic-snand-superfluous-params-v1-1-86dd4963e90f@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-21spi: spi-qpic-snand: reuse qcom_spi_check_raw_flash_errors()Gabor Juhos
The qcom_spi_check_raw_flash_errors() function can be used to verify the flash status after raw operations. Move the function slightly up in the code and change the qcom_spi_read_last_cw() function to call it instead of using an open coded implementation of the same check. Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Link: https://patch.msgid.link/20250514-qpic-snand-error-check-v1-1-c0ebd3aae72a@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-20spi: sh-msiof: Transfer size improvements and I2SMark Brown
Merge series from Geert Uytterhoeven <geert+renesas@glider.be>: This patch series (A) improves single transfer sizes in the MSIOF driver, using two methods: - By increasing the assumed FIFO sizes, impacting both PIO and DMA transfers, - By using two groups, impacting DMA transfers, and (B) lets the recently-introduced MSIOF I2S drive reuse the SPI driver's register definitions. All of this is covered with a thick sauce of fixes for (harmless) bugs, cleanups, and refactorings. Note that the driver uses the limitations as specified in the hardware documentation. For discovering the actual FIFO sizes, I wrote some crude test code that can be found at [2]. This is based on spi/for-next and sound-asoc/for-next, and has been tested on a variery of R-Car SoCs. [1] https://lore.kernel.org/cover.1746180072.git.geert+renesas@glider.be [2] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/msiof-fifo
2025-05-20Add sound card support for QCS9100 and QCS9075Mark Brown
Merge series from Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>: This patchset adds support for sound card on Qualcomm QCS9100 and QCS9075 boards.
2025-05-19spi: spi_amd: Update Kconfig dependenciesRaju Rangoju
Add X86 and SPI_MEM as dependencies for the spi_amd driver to ensure it is built only on relevant platforms and with the required SPI memory framework. Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-4-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: spi_amd: Add HIDDMA basic write supportRaju Rangoju
SPI index mode has hardware limitation of transferring only 64 bytes per transaction due to fixed number of FIFO registers. This constraint leads to performance issues when reading/writing data to/from NAND/NOR flash devices, as the controller must issue multiple requests to read/write 64-byte chunks, even if the slave can transfer up to 2 or 4 KB in a single transaction. The AMD HID2 SPI controller supports DMA mode, allowing for reading/writing up to 4 KB of data in a single transaction. The existing spi_amd driver already supports HID2 DMA read operations. This patch introduces changes to implement HID2 DMA single mode basic write support for the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-3-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: spi_amd: Remove read{q,b} usage on DMA bufferRaju Rangoju
Add changes to replace the usage of read{q,b} MMIO accessors with direct memory copy logic for reading data from DMA buffer. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250516100658.585654-2-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Move register definitions to <linux/spi/sh_msiof.h>Geert Uytterhoeven
Move the MSIOF register and register bit definitions from the MSIOF SPI driver to the existing header file <linux/spi/sh_msiof.h>, so they can be shared with the MSIOF I2S driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/066d1086973eb309006258484e9fe8138807e565.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Document frame start sync pulse modeGeert Uytterhoeven
Unused, but nice to have it documented. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/3d3acaab4a4125106a0655d28c09c050341c5eeb.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Double maximum DMA transfer size using two groupsGeert Uytterhoeven
The maximum DMA transfer size is limited by the maximum values that can be written to the word count fields (WDLENx) in the Transmit and Control Data Registers (SITDR2/SIRDR2). As all MSIOF variants support transferring data of multiple (two or four) groups, the maximum size can be doubled by using two groups instead of one, thus reducing setup overhead for very large SPI transfers. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/bad522c76b8d225c195433977b22f95015cf2612.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Simplify BRG's Division RatioGeert Uytterhoeven
As FIELD_PREP() masks the value to be stored in the field, the Baud Rate Generator's Division Ratio handling can be simplified from a look-up table to a single subtraction. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/e736221942b0381fb53dc64109a1389f7ec5f44a.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Increase TX FIFO size for R-Car V4H/V4MGeert Uytterhoeven
The MSIOF transmit FIFOs on R-Car V4H and V4M have 256 stages. Add a new family-specific match entry to handle this. Add quirk match entries for older R-Car Gen4 Socs (R-Car V3U and S4-8) that have transmit FIFOs with only 64 stages, just like on R-Car Gen3. Update the (unused) definition of SIFCTR_TFUA for consistency. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/69cb5fc48f034d37484fa127b9864a1971a83417.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Correct RX FIFO size for R-Car Gen3Geert Uytterhoeven
According to the R-Car Gen3 Hardware Manual Errata for Rev 0.55 of September 28, 2017, the MSIOF receive FIFOs on R-Car Gen3 SoCs have room for 256 words of 32 bits. Note that this change has no actual impact on the behavior of the driver, as SPI_CONTROLLER_MUST_TX is set, and transfer size is currenty limited to the minimum of the transmit and receive FIFO sizes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/6f74508ea4681aa0b7c6bf6810eab026725e75a3.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Correct RX FIFO size for R-Car Gen2Geert Uytterhoeven
According to Renesas Technical Updates TN-RCS-S068A/E, the MSIOF receive FIFOs on R-Car Gen2 SoCs have room for 128 words of 32 bits. Note that this change has no actual impact on the behavior of the driver, as SPI_CONTROLLER_MUST_TX is set, and transfer size is currenty limited to the minimum of the transmit and receive FIFO sizes. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/fd11933f932df81d84f417a21e2179bd4fdcfdc1.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Add core support for dual-group transfersGeert Uytterhoeven
All MSIOF variants support transferring data of multiple (2 or 4) groups. Add definitions for the register bits related to multiple groups, and enhance sh_msiof_spi_set_mode_regs() to accept a second group size. For now the second group is unused. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/be75e20cfcd2a6c0d73ab09e0126f902911adc69.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Correct SIMDR2_GRPMASKGeert Uytterhoeven
The Group Output Mask is not a single bit, but a bit field, containing one bit for each of the four possible groups. Correct the definition. Note that this change has no direct impact, as the driver only uses the first group. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/ad268d67807cb7e544eddaf7a056793482a965d4.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: SIFCTR bitfield conversionGeert Uytterhoeven
Convert MSIOF FIFO Control Register field accesses to use the FIELD_PREP() bitfield access macro. This gets rid of explicit shifts and custom field preparation macros. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/0bf4c366381a8999c9755285272897300852bc18.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: SICTR bitfield conversionGeert Uytterhoeven
Convert MSIOF Control Register field accesses to use the FIELD_PREP() bitfield access macro. This gets rid of explicit shifts. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/4511c678c8fce5969eb50ffa7372d53396ff80ff.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: SITSCR/SIRSCR bitfield conversionGeert Uytterhoeven
Convert MSIOF Transmit and Receive Clock Select Register field accesses to use the FIELD_PREP() bitfield access macro. This gets rid of explicit shifts and custom field preparation macros. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/f2462c99b6ea2e45b995ab4509c2f039043da032.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: SITMDR2 and SIRMDR2 bitfield conversionGeert Uytterhoeven
Convert MSIOF Transmit and Receive Mode Register 2 field accesses to use the FIELD_PREP() bitfield access macro. This gets rid of explicit shifts and custom field preparation macros. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/135b92d010a71e2c224feab3a5792724b4e60ff1.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: SITMDR1/SIRMDR1 bitfield conversionGeert Uytterhoeven
Convert MSIOF Transmit and Receive Mode Register 1 field accesses to use the FIELD_PREP() bitfield access macro. This gets rid of explicit shifts. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/9685c54e752b8ef4256c9b281e9d8292e71d222e.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Make words/fs unsigned in FIFO helpersGeert Uytterhoeven
Make the words and fs parameters of the various FIFO filler and emptier functions unsigned, as they can never be negative. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/a7b13ecb1811148227ec8c883079085ed1ea6eac.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Make words/bits unsigned in sh_msiof_spi_txrx_once()Geert Uytterhoeven
Make the words and bits parameters of sh_msiof_spi_txrx_once() unsigned, as that matches what is passed by the caller. This allows us to replace min_t() by the safer min(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/30eff1052642a4bcb0f1bc4bed7aae25d355a7dc.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Use bool for boolean flagsGeert Uytterhoeven
Use bools instead of integers for boolean flags, which allows us to remove the "!!" idiom from several expressions. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/35cd51bdfb3c810911a5be757e0ce5bb29dcc755.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Complete using dev in sh_msiof_spi_probe()Geert Uytterhoeven
Commit c4887bd4b35b225f ("spi: sh-msiof: use dev in sh_msiof_spi_probe()") forgot to convert one instance. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://patch.msgid.link/88d271b2d16c6ad7f174858894573f91cec1bc90.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Fix maximum DMA transfer sizeGeert Uytterhoeven
The maximum amount of data to transfer in a single DMA request is calculated from the FIFO sizes (which is technically not 100% correct, but a simplification, as it is limited by the maximum word count values in the Transmit and Control Data Registers). However, in case there is both data to transmit and to receive, the transmit limit is overwritten by the receive limit. Fix this by using the minimum applicable FIFO size instead. Move the calculation outside the loop, so it is not repeated for each individual DMA transfer. As currently tx_fifo_size is always equal to rx_fifo_size, this bug had no real impact. Fixes: fe78d0b7691c0274 ("spi: sh-msiof: Fix FIFO size to 64 word from 256 word") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/d9961767a97758b2614f2ee8afe1bd56dc900a60.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit (git 2.34.1) at 2025-06-17 02:26:27 +0000