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path: root/drivers/spi
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2022-10-31spi: mxic: Use devm_platform_ioremap_resource_byname()Yang Yingliang
Use the devm_platform_ioremap_resource_byname() helper instead of calling platform_get_resource_byname() and devm_ioremap_resource() separately. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20221029071720.3041094-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-31spi: npcm-fiu: Use devm_platform_ioremap_resource_byname()Yang Yingliang
Use the devm_platform_ioremap_resource_byname() helper instead of calling platform_get_resource_byname() and devm_ioremap_resource() separately. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20221029071529.3019626-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-31spi: mediatek: Fix package division errorzhichao.liu
Commit 7e963fb2a33ce ("spi: mediatek: add ipm design support for MT7986") makes a mistake on package dividing operation (one change is missing), need to fix it. Background: Ipm design is expanding the HW capability of dma (adjust package length from 1KB to 64KB), and using "dev_comp->ipm_support" flag to indicate it. Issue description: Ipm support patch (said above) is missing to handle remainder at package dividing operation. One case, a transmission length is 65KB, is will divide to 1K (package length) * 65(package loop) in non-ipm desgin case, and will divide to 64K(package length) * 1(package loop) + 1K(remainder) in ipm design case. And the 1K remainder will be lost with the current SW flow, and the transmission will be failure. So, it should be fixed. Solution: Add "ipm_design" flag in function "mtk_spi_get_mult_delta()" to indicate HW capability, and modify the parameters corespondingly. fixes: 7e963fb2a33ce ("spi: mediatek: add ipm design support for MT7986") Signed-off-by: zhichao.liu <zhichao.liu@mediatek.com> Link: https://lore.kernel.org/r/20221021091653.18297-1-zhichao.liu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-28spi: tegra210-quad: Don't initialise DMA if not supportedJon Hunter
The following error messages are observed on boot for Tegra234 ... ERR KERN tegra-qspi 3270000.spi: cannot use DMA: -19 ERR KERN tegra-qspi 3270000.spi: falling back to PIO Tegra234 does not support DMA for the QSPI and so initialising the DMA is expected to fail. The above error messages are misleading for devices that don't support DMA and so fix this by skipping the DMA initialisation for devices that don't support DMA. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20221026155633.141792-1-jonathanh@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-26Merge tag 'spi-fix-v6.1-rc2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A collection of mostly unremarkable fixes for SPI that have built up since the merge window, all driver specific. The change to the qup adding support for GPIO chip selects is fixing a regression due to the removal of legacy GPIO handling, the driver had previously been silently relying on the legacy GPIO support in a slightly broken way which worked well enough on some systems. Fixing it is simply a case of setting a couple of bits of information in the driver description" * tag 'spi-fix-v6.1-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: aspeed: Fix window offset of CE1 spi: qup: support using GPIO as chip select line spi: intel: Fix the offset to get the 64K erase opcode spi: aspeed: Fix typo in mode_bits field for AST2600 platform spi: mpc52xx: Replace NO_IRQ by 0 spi: spi-mem: Fix typo (of -> or) spi: spi-gxp: fix typo in SPDX identifier line spi: tegra210-quad: Fix combined sequence
2022-10-26spi: Remove the obsolte u64_stats_fetch_*_irq() users.Thomas Gleixner
Now that the 32bit UP oddity is gone and 32bit uses always a sequence count, there is no need for the fetch_irq() variants anymore. Convert to the regular interface. Cc: Mark Brown <broonie@kernel.org> Cc: linux-spi@vger.kernel.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lore.kernel.org/r/20221026122951.331638-1-bigeasy@linutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-26spi: meson-spicc: move wait completion in driver to take bursts delay in accountNeil Armstrong
Some delay occurs between each bursts, thus the default delay is wrong and a timeout will occur with big enough transfers. The solution is to handle the timeout management in the driver and add some delay for each bursts in the timeout calculation. Reported-by: Da Xue <da@libre.computer> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20221026-spicc-burst-delay-v1-0-1be5ffb7051a@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-24spi: pxa2xx: Pass the SSP type via device propertyMark Brown
Merge series from Andy Shevchenko <andriy.shevchenko@linux.intel.com>: Currently the SPI PXA2xx devices on Intel platforms can be instantiated via the following paths: 1) as ACPI LPSS device on Haswell, Bay Trail and Cherry Trail; 2) as ACPI LPSS device on the Sky Lake and newer; 3) as PCI LPSS device on Haswell, Bay Trail and Cherry Trail; 4) as PCI LPSS device on the Sky Lake and newer; 5) as PCI device via ID table. Each of these cases provides some platform related data differently, i.e.: 1) via drivers/acpi/acpi_lpss.c and drivers/spi/spi-pxa2xx.c 2) via drivers/mfd/intel-lpss-acpi.c 3) via drivers/spi/spi-pxa2xx-pci.c 4) via drivers/mfd/intel-lpss-pci.c and drivers/spi/spi-pxa2xx.c 5) via drivers/spi/spi-pxa2xx-pci.c This approach has two downsides: a) there is no data propagated in the case #2 because we can't have two or more drivers to match the same ACPI ID and hence some cases are still not supported (Sky Lake and newer ACPI enabled LPSS); b) the data is duplicated over two drivers in the cases #1 & #4 and, besides to be a bloatware, it is error prone (e.g. Lakefield has a wrong data right now due to missed PCI entry in the spi-pxa2xx.c). This series fixes the downsides, and enables previously unsupported cases.
2022-10-24spi: pxa2xx: Move OF and ACPI ID tables closer to their userAndy Shevchenko
There is no code that uses ID tables directly, except the struct device_driver at the end of the file. Hence, move tables closer to its user. It's always possible to access them via pointer to a platform device. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20221021190018.63646-5-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-24spi: pxa2xx: Remove no more needed PCI ID tableAndy Shevchenko
Since the PCI enumerated devices provide a property with SSP type, there is no more necessity to bear the copy of the ID table here. Remove it for good. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20221021190018.63646-4-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-24spi: pxa2xx: Respect Intel SSP type given by a propertyAndy Shevchenko
Allow to set the Intel SSP type by reading the property. Only apply this to the known MFD enumerated LPSS devices. The check is done by the looking for the specifically named IO memory resource provided by upper layer. This won't be an issue in the future because we strictly prioritize the order in which we are looking for the SSP type in the code. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20221021190018.63646-3-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-24spi: pxa2xx: Validate the correctness of the SSP typeAndy Shevchenko
Currently we blindly apply the SSP type value from any source of the information. Increase robustness by validating the value before use. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20221021190018.63646-2-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-24spi: aspeed: Use devm_platform_{get_and_}ioremap_resource()Yang Yingliang
Use the devm_platform_{get_and_}ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20221019092635.1176622-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-24spi: stm32: Print summary 'callbacks suppressed' messageMarek Vasut
The original fix "spi: stm32: Rate-limit the 'Communication suspended' message" still leads to "stm32h7_spi_irq_thread: 1696 callbacks suppressed" spew in the kernel log. Since this 'Communication suspended' message is a debug print, add RATELIMIT_MSG_ON_RELEASE flag to inhibit the "callbacks suspended" part during normal operation and only print summary at the end. Fixes: ea8be08cc9358 ("spi: stm32: Rate-limit the 'Communication suspended' message") Signed-off-by: Marek Vasut <marex@denx.de> Link: https://lore.kernel.org/r/20221018183513.206706-1-marex@denx.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-21spi: amlogic: meson-spicc: Use pinctrl to drive CLK line when idleMark Brown
Merge series from Amjad Ouled-Ameur <aouledameur@baylibre.com>: Between SPI transactions, all SPI pins are in HiZ state. When using the SS signal from the SPICC controller it's not an issue because when the transaction resumes all pins come back to the right state at the same time as SS. The problem is when we use CS as a GPIO. In fact, between the GPIO CS state change and SPI pins state change from idle, you can have a missing or spurious clock transition. Set a bias on the clock depending on the clock polarity requested before CS goes active, by passing a special "idle-low" and "idle-high" pinctrl state and setting the right state at a start of a message.
2022-10-21spi: pxa2xx: Minor cleanupsMark Brown
Merge series from Andy Shevchenko <andriy.shevchenko@linux.intel.com>: This series has a couple of cleanups for the pxa2xx driver.
2022-10-21spi: meson-spicc: Use pinctrl to drive CLK line when idleAmjad Ouled-Ameur
Between SPI transactions, all SPI pins are in HiZ state. When using the SS signal from the SPICC controller it's not an issue because when the transaction resumes all pins come back to the right state at the same time as SS. The problem is when we use CS as a GPIO. In fact, between the GPIO CS state change and SPI pins state change from idle, you can have a missing or spurious clock transition. Set a bias on the clock depending on the clock polarity requested before CS goes active, by passing a special "idle-low" and "idle-high" pinctrl state and setting the right state at a start of a message Reported-by: Da Xue <da@libre.computer> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com> Link: https://lore.kernel.org/r/20221004-up-aml-fix-spi-v4-2-0342d8e10c49@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-21spi: spi-imx: remove unused struct spi_imx_devtype_data::disable_dma callbackMarc Kleine-Budde
In commit 7a908832ace7 ("spi: imx: add fallback feature") the last user of the struct spi_imx_devtype_data::disable_dma callback was removed. However the disable_dma member of struct spi_imx_devtype_data and the callback itself was not removed. Remove struct spi_imx_devtype_data::disable_dma and mx51_disable_dma() as they are unused. Cc: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Link: https://lore.kernel.org/r/20221021131051.1777984-1-mkl@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-21spi: pxa2xx: Switch from PM ifdeffery to pm_ptr()Andy Shevchenko
Cleaning up the driver to use pm_ptr() macro instead of ifdeffery that makes it simpler and allows the compiler to remove those functions if built without CONFIG_PM and CONFIG_PM_SLEEP support. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/20221020194500.10225-6-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-21spi: pxa2xx: Consistently use dev variable in pxa2xx_spi_init_pdata()Andy Shevchenko
We have a temporary variable to keep a pointer to a struct device in the pxa2xx_spi_init_pdata(). Use it consistently there. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20221020194500.10225-5-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-21spi: Introduce spi_get_device_match_data() helperAndy Shevchenko
The proposed spi_get_device_match_data() helper is for retrieving a driver data associated with the ID in an ID table. First, it tries to get driver data of the device enumerated by firmware interface (usually Device Tree or ACPI). If none is found it falls back to the SPI ID table matching. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20221020195421.10482-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-19spi: spi-zyqnmp-gqspi: Add tap delay and Versal platform supportMark Brown
Merge series from Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>: A bunch of improvements to the driver: - Fix kernel-doc warnings in GQSPI driver. - Avoid setting CPOL, CPHA & baud rate multiple times. - Add Versal platform support in GQSPI driver. - Add tap delay support in GQSPI driver.
2022-10-19spi: img-spfi: Use devm_platform_get_and_ioremap_resource()Yang Yingliang
Use the devm_platform_get_and_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20221019093318.1183190-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-19spi: aspeed: Fix window offset of CE1Cédric Le Goater
The offset value of the mapping window in the kernel structure is calculated using the value of the previous window offset. This doesn't reflect how the HW is configured and can lead to erroneous setting of the second flash device (CE1). Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Fixes: e3228ed92893 ("spi: spi-mem: Convert Aspeed SMC driver to spi-mem") Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20221016155722.3520802-1-clg@kaod.org Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-19spi: spi-zynqmp-gqspi: Add tap delay support for GQSPI controller on Versal ↵Amit Kumar Mahapatra
platform Add tap delay support for GQSPI controller on Versal platform. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Link: https://lore.kernel.org/r/20221011062040.12116-8-amit.kumar-mahapatra@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-19spi: spi-zynqmp-gqspi: Add tap delay support for ZynqMP GQSPI ControllerNaga Sureshkumar Relli
GQSPI controller uses the internal clock for loopback mode. The loopback mode is used with the high-speed Quad SPI timing mode, where the memory interface clock needs to be greater than 40 MHz. Based on the tap delay value programmed, the internal clock is delayed and used for capturing the data. Based upon the frequency of operation set the recommended tap delay values in GQSPI driver. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Link: https://lore.kernel.org/r/20221011062040.12116-6-amit.kumar-mahapatra@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-19spi: spi-zynqmp-gqspi: Avoid setting baud rate multiple times for same SPI ↵Amit Kumar Mahapatra
frequency During every transfer the GQSPI driver configures the baud rate value. But when there is no change in the SPI clock frequency the driver should avoid rewriting the same baud rate value to the configuration register. Update GQSPI driver to rewrite the baud rate value if there is any change in SPI clock frequency. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Link: https://lore.kernel.org/r/20221011062040.12116-4-amit.kumar-mahapatra@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-19spi: spi-zynqmp-gqspi: Set CPOL and CPHA during hardware initAmit Kumar Mahapatra
During every transfer GQSPI driver writes the CPOL & CPHA values to the configuration register. But the CPOL & CPHA values do not change in between multiple transfers, so moved the CPOL & CPHA initialization to hardware init so that the values are written only once. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Link: https://lore.kernel.org/r/20221011062040.12116-3-amit.kumar-mahapatra@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-19spi: spi-zynqmp-gqspi: Fix kernel-doc warningsAmit Kumar Mahapatra
Document zynqmp_qspi ctrl and op_lock member description. It also adds return documentation for 'zynqmp_qspi_setuprxdma' and zynqmp_qspi_read_op. Fixes below kernel-doc warnings- spi-zynqmp-gqspi.c:178: warning: Function parameter or member 'ctlr' not described in 'zynqmp_qspi' spi-zynqmp-gqspi.c:178: warning: Function parameter or member 'op_lock' not described in 'zynqmp_qspi' spi-zynqmp-gqspi.c:737: warning: No description found for return value of 'zynqmp_qspi_setuprxdma' spi-zynqmp-gqspi.c:822: warning: No description found for return value of 'zynqmp_qspi_read_op' Signed-off-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> Link: https://lore.kernel.org/r/20221011062040.12116-2-amit.kumar-mahapatra@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-19spi: fsl-cpm: substitute empty_zero_page with helper ZERO_PAGE(0)Giulio Benetti
Not all zero page implementations use empty_zero_page global pointer so let's substitute empty_zero_page occurence with helper ZERO_PAGE(0). Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Link: https://lore.kernel.org/r/20221018215755.33566-2-giulio.benetti@benettiengineering.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-18spi: bcm-qspi: Make bcm_qspi_remove() return voidUwe Kleine-König
The function bcm_qspi_remove() returns zero unconditionally. Make it return void. This is a preparation for making platform remove callbacks return void. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20221017200143.1426528-1-u.kleine-koenig@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-18spi: pxa2xx: Simplify with devm_platform_get_and_ioremap_resource()Andy Shevchenko
Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. No functional changes. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20221017171243.57078-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-17spi: cadence-quadspi: Use devm_platform_{get_and_}ioremap_resource()Yang Yingliang
Use the devm_platform_{get_and}_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220928145852.1882221-2-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-17spi: bcm63xx: Use devm_platform_get_and_ioremap_resource()Yang Yingliang
Use the devm_platform_get_and_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220928145852.1882221-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-17spi: microchip: pci1xxxx: Add driver for SPI controller of PCI1XXXX PCIe switchTharun Kumar P
Microchip pci1xxxx is a PCIe switch with a multi-function endpoint on one of its downstream ports. SPI is one of the functions in the multi-function endpoint. This function has 2 SPI masters, operates at a maximum frequency of 30 MHz and supports 7 client devices per master. This patch adds complete functionality to the SPI function except for suspend and resume. Signed-off-by: Tharun Kumar P <tharunkumar.pasumarthi@microchip.com> Link: https://lore.kernel.org/r/20221006050514.115564-2-tharunkumar.pasumarthi@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-17spi: microchip-core: Remove the unused function mchp_corespi_enable()Jiapeng Chong
The function mchp_corespi_enable() is defined in the spi-microchip-core.c file, but not called elsewhere, so delete this unused function. drivers/spi/spi-microchip-core.c:122:20: warning: unused function 'mchp_corespi_enable'. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2418 Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20221017092141.9789-1-jiapeng.chong@linux.alibaba.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-17Merge existing fixes from spi/for-6.1 into new branchMark Brown
2022-10-17spi: qup: support using GPIO as chip select lineRobert Marko
Most of the device with QUP SPI adapter are actually using GPIO-s for chip select. However, this stopped working after ("spi: Retire legacy GPIO handling") as it introduced a check on ->use_gpio_descriptors flag and since spi-qup driver does not set the flag it meant that all of boards using GPIO-s and with QUP adapter SPI devices stopped working. So, to enable using GPIO-s again set ->use_gpio_descriptors to true and populate ->max_native_cs. Fixes: f48dc6b96649 ("spi: Retire legacy GPIO handling") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: luka.perkov@sartura.hr Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20221006194819.1536932-1-robert.marko@sartura.hr Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-13spi: intel: Fix the offset to get the 64K erase opcodeMauro Lima
According to documentation, the 64K erase opcode is located in VSCC range [16:23] instead of [8:15]. Use the proper value to shift the mask over the correct range. Signed-off-by: Mauro Lima <mauro.lima@eclypsium.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://lore.kernel.org/r/20221012152135.28353-1-mauro.lima@eclypsium.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-10spi: aspeed: Fix typo in mode_bits field for AST2600 platformChin-Ting Kuo
Both quad SPI TX and RX modes can be supported on AST2600. Correct typo in mode_bits field in both ast2600_fmc_data and ast2600_spi_data structs. Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Link: https://lore.kernel.org/r/20221005083209.222272-1-chin-ting_kuo@aspeedtech.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-10spi: mpc52xx: Replace NO_IRQ by 0Christophe Leroy
NO_IRQ is used to check the return of irq_of_parse_and_map(). On some architecture NO_IRQ is 0, on other architectures it is -1. irq_of_parse_and_map() returns 0 on error, independent of NO_IRQ. So use 0 instead of using NO_IRQ. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/f41e09d710879726eacb98daedf16d0847303b9b.1665034444.git.christophe.leroy@csgroup.eu Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-04Merge tag 'spi-v6.1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "With the exception of some refactoring to fix long standing issues where we weren't handling cache syncs properly for messages which had PIO and DMA transfers going to the same page correctly there has been no work on the core this time around, and it's also been quite a quiet release for the drivers too: - Fix cache syncs for cases where we have DMA and PIO transfers in the same message going to the same page - Update the fsl_spi driver to use transfer_one() rather than a custom transfer function - Support for configuring transfer speeds with the AMD SPI controller - Support for a second chip select and 64K erase on Intel SPI - Support for Microchip coreQSPI, Nuvoton NPCM845, NXP i.MX93, and Rockchip RK3128 and RK3588" * tag 'spi-v6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (73 commits) spi: Ensure that sg_table won't be used after being freed spi: spi-gxp: Use devm_platform_ioremap_resource() spi: s3c64xx: Fix large transfers with DMA spi: Split transfers larger than max size spi: Fix cache corruption due to DMA/PIO overlap spi: Save current RX and TX DMA devices spi: mt65xx: Add dma max segment size declaration spi: migrate mt7621 text bindings to YAML spi: renesas,sh-msiof: Add r8a779g0 support spi: spi-fsl-qspi: Use devm_platform_ioremap_resource_byname() spi: spi-fsl-lpspi: Use devm_platform_get_and_ioremap_resource() spi: spi-fsl-dspi: Use devm_platform_get_and_ioremap_resource() spi/omap100k:Fix PM disable depth imbalance in omap1_spi100k_probe spi: dw: Fix PM disable depth imbalance in dw_spi_bt1_probe spi: cadence-quadspi: Fix PM disable depth imbalance in cqspi_probe spi: s3c24xx: Switch to use devm_spi_alloc_master() spi: xilinx: Switch to use devm_spi_alloc_master() spi: img-spfi: using pm_runtime_resume_and_get instead of pm_runtime_get_sync spi: aspeed: Remove redundant dev_err call spi: spi-mpc52xx: switch to using gpiod API ...
2022-10-04spi: spi-gxp: fix typo in SPDX identifier lineBird, Tim
Use '-' instead of '=' in identifier: "GPL-2.0-or-later" Signed-off-by: Tim Bird <tim.bird@sony.com> Link: https://lore.kernel.org/r/BYAPR13MB2503FF6412666D29FEAC8DCDFD5B9@BYAPR13MB2503.namprd13.prod.outlook.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-10-03Merge branch 'acpi-uid'Rafael J. Wysocki
Merge ACPI _UID handling unification changes for 6.1-rc1: - Introduce acpi_dev_uid_to_integer() to convert a _UID string into an integer value (Andy Shevchenko). - Use acpi_dev_uid_to_integer() in several places to unify _UID handling (Andy Shevchenko). * acpi-uid: efi/dev-path-parser: Refactor _UID handling to use acpi_dev_uid_to_integer() spi: pxa2xx: Refactor _UID handling to use acpi_dev_uid_to_integer() perf: qcom_l2_pmu: Refactor _UID handling to use acpi_dev_uid_to_integer() i2c: mlxbf: Refactor _UID handling to use acpi_dev_uid_to_integer() i2c: amd-mp2-plat: Refactor _UID handling to use acpi_dev_uid_to_integer() ACPI: x86: Refactor _UID handling to use acpi_dev_uid_to_integer() ACPI: LPSS: Refactor _UID handling to use acpi_dev_uid_to_integer() ACPI: utils: Add acpi_dev_uid_to_integer() helper to get _UID as integer
2022-10-03spi: tegra210-quad: Fix combined sequenceKrishna Yarlagadda
Return value should be updated to zero in combined sequence routine if transfer is completed successfully. Currently it holds timeout value resulting in errors. Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com> Link: https://lore.kernel.org/r/20221001122148.9158-1-kyarlagadda@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-30Merge branch 'acpi-dev'Rafael J. Wysocki
Merge changes regarding the management of ACPI device objects for 6.1-rc1: - Rename ACPI device object reference counting functions (Rafael Wysocki). - Rearrange ACPI device object initialization code (Rafael Wysocki). - Drop parent field from struct acpi_device (Rafael Wysocki). - Extend the the int3472-tps68470 driver to support multiple consumers of a single TPS68470 along with the requisite framework-level support (Daniel Scally). * acpi-dev: platform/x86: int3472: Add board data for Surface Go2 IR camera platform/x86: int3472: Support multiple gpio lookups in board data platform/x86: int3472: Support multiple clock consumers ACPI: bus: Add iterator for dependent devices ACPI: scan: Add acpi_dev_get_next_consumer_dev() ACPI: property: Use acpi_dev_parent() ACPI: Drop redundant acpi_dev_parent() header ACPI: PM: Fix NULL argument handling in acpi_device_get/set_power() ACPI: Drop parent field from struct acpi_device ACPI: scan: Eliminate __acpi_device_add() ACPI: scan: Rearrange initialization of ACPI device objects ACPI: scan: Rename acpi_bus_get_parent() and rearrange it ACPI: Rename acpi_bus_get/put_acpi_device()
2022-09-30spi: Ensure that sg_table won't be used after being freedMarek Szyprowski
SPI code checks for non-zero sgt->orig_nents to determine if the buffer has been DMA-mapped. Ensure that sg_table is really zeroed after free to avoid potential NULL pointer dereference if the given SPI xfer object is reused again without being DMA-mapped. Fixes: 0c17ba73c08f ("spi: Fix cache corruption due to DMA/PIO overlap") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Link: https://lore.kernel.org/r/20220930113408.19720-1-m.szyprowski@samsung.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-29spi: spi-gxp: Use devm_platform_ioremap_resource()Yang Yingliang
Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220928145256.1879256-1-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-28spi: s3c64xx: Fix large transfers with DMAVincent Whitchurch
The COUNT_VALUE in the PACKET_CNT register is 16-bit so the maximum value is 65535. Asking the driver to transfer a larger size currently leads to the DMA transfer timing out. Implement ->max_transfer_size() and have the core split the transfer as needed. Fixes: 230d42d422e7 ("spi: Add s3c64xx SPI Controller driver") Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Link: https://lore.kernel.org/r/20220927112117.77599-5-vincent.whitchurch@axis.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-09-28spi: Split transfers larger than max sizeVincent Whitchurch
A couple of drivers call spi_split_transfers_maxsize() from their ->prepare_message() callbacks to split transfers which are too big for them to handle. Add support in the core to do this based on ->max_transfer_size() to avoid code duplication. Signed-off-by: Vincent Whitchurch <vincent.whitchurch@axis.com> Link: https://lore.kernel.org/r/20220927112117.77599-4-vincent.whitchurch@axis.com Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-18 11:56:13 +0000