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2021-01-27spi: hisi-sfc-v3xx: add address mode checkYicong Yang
The address mode is either 3 or 4 for the controller, which is configured by the firmware and cannot be modified in the OS driver. Get the firmware configuration and add address mode check in the .supports_op() to block invalid operations. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Acked-by: John Garry <john.garry@huawei.com> Link: https://lore.kernel.org/r/1611740450-47975-3-git-send-email-yangyicong@hisilicon.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-25spidev: Add cisco device compatibleDaniel Walker
Add compatible string for Cisco device present on the Cisco Petra platform. Signed-off-by: Daniel Walker <danielwa@cisco.com> Cc: xe-linux-external@cisco.com Link: https://lore.kernel.org/r/20210121231237.30664-2-danielwa@cisco.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-22spi: spi-au1550: Fix various whitespace warningscorentin
Signed-off-by: corentin <corentin.noel56@gmail.com> Link: https://lore.kernel.org/r/20210122082040.30788-1-corentin.noel.external@stormshield.eu Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-22spi: spi-au1550: quoted string breakcorentin
Signed-off-by: corentin <corentin.noel56@gmail.com> Link: https://lore.kernel.org/r/20210122113052.40429-1-corentin.noel56@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-21spi: remove sirf prima/atlas driverArnd Bergmann
The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Cc: Barry Song <baohua@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Barry Song <baohua@kernel.org> Link: https://lore.kernel.org/r/20210120161658.3820610-1-arnd@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-21spi: atmel: Put allocated master before returnPan Bian
The allocated master is not released. Goto error handling label rather than directly return. Fixes: 5e9af37e46bc ("spi: atmel: introduce probe deferring") Signed-off-by: Pan Bian <bianpan2016@163.com> Fixes: 5e9af37e46bc ("spi: atmel: introduce probe deferring") Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20210120050025.25426-1-bianpan2016@163.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-21spi: spi-mpc52xx: Use new structure for SPI transfer delaysSergiu Cuciurean
In a recent change to the SPI subsystem [1], a new `delay` struct was added to replace the `delay_usecs`. This change replaces the current `delay_usecs` with `delay` for this driver. The `spi_transfer_delay_exec()` function [in the SPI framework] makes sure that both `delay_usecs` & `delay` are used (in this order to preserve backwards compatibility). [1] commit bebcfd272df6 ("spi: introduce `delay` field for `spi_transfer` + spi_transfer_delay_exec()") Signed-off-by: Sergiu Cuciurean <sergiu.cuciurean-OyLXuOCK7orQT0dZR+AlfA@public.gmane.org> Link: https://lore.kernel.org/r/20200227143931.20688-1-sergiu.cuciurean@analog.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-21spi: spi-au1550: Add suffix "int" to all "unsigned"corentin
Signed-off-by: corentin <corentin.noel56@gmail.com> Link: https://lore.kernel.org/r/20210121145236.26460-1-corentin.noel.external@stormshield.eu Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-20spi: altera: Fix memory leak on error pathPan Bian
Release master that have been previously allocated if the number of chipselect is invalid. Fixes: 8e04187c1bc7 ("spi: altera: add SPI core parameters support via platform data.") Signed-off-by: Pan Bian <bianpan2016@163.com> Reviewed-by: Tom Rix <trix@redhat.com> Link: https://lore.kernel.org/r/20210120082635.49304-1-bianpan2016@163.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-20ARM: remove u300 platformArnd Bergmann
The Ericsson U300 platform was one of two ARM929 based SoC platforms for mobile phones in ST-Ericsson after the merger of Ericsson with ST-NXP into ST-Ericsson, the other one being the ST Nomadik. The platform was not widely adopted in Linux based systems and was replaced with the far superior ST-Ericsson U8500 in 2011, but Linus Walleij kept maintaining the code for the whole time. Linus continues to use the Nomadik machine, but decided to drop u300 from the kernel as part of this year's spring cleaning. Thanks for having maintained it all these years. Cc: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/lkml/CACRpkdbJkiHR9FSfJTH_5d_qRU1__dRXHM1TL40iqNRKbGQfrQ@mail.gmail.com/ Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-01-19spi: imx: Don't print error on -EPROBEDEFERGuido Günther
This avoids [ 0.962538] spi_imx 30820000.spi: bitbang start failed with -517 durig driver probe. Fixes: 8197f489f4c4 ("spi: imx: Fix failure path leak on GPIO request error correctly") Signed-off-by: Guido Günther <agx@sigxcpu.org> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/0f51ab42e7c7a3452f2f8652794d81584303ea0d.1610987414.git.agx@sigxcpu.org Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-15Merge series "Remove ARM platform efm32" from Uwe Kleine-König ↵Mark Brown
<u.kleine-koenig@pengutronix.de> Uwe Kleine-König <uwe.kleine-koenig@pengutronix.de>: From: Uwe Kleine-König <uwe.kleine-koenig@pengutronix.de> Hello, there are no known active users of the efm32 platform. Given that the only machine that is supported has only 4 MiB of RAM its use is also quite limited. Back then it served as the platform to develop ARMv7-M support in Linux which was quite fun and still is a blissful memory. Still given that the code serves no purpose and this probably won't change anytime soon, remove all platform support. I'm unsure what to do with the device tree bindings. Should we delete them, too? Best regards Uwe Uwe Kleine-König (7): ARM: drop efm32 platform clk: Drop unused efm32gg driver clocksource: Drop unused efm32 timer code spi: Drop unused efm32 bus driver i2c: Drop unused efm32 bus driver tty: Drop unused efm32 serial driver MAINTAINERS: Remove deleted platform efm32 MAINTAINERS | 7 - arch/arm/Kconfig | 10 +- arch/arm/Kconfig.debug | 17 - arch/arm/Makefile | 1 - arch/arm/boot/dts/Makefile | 2 - arch/arm/boot/dts/efm32gg-dk3750.dts | 88 --- arch/arm/boot/dts/efm32gg.dtsi | 177 ----- arch/arm/configs/efm32_defconfig | 98 --- arch/arm/include/debug/efm32.S | 45 -- arch/arm/mach-efm32/Makefile | 2 - arch/arm/mach-efm32/Makefile.boot | 4 - arch/arm/mach-efm32/dtmachine.c | 16 - arch/arm/mm/Kconfig | 1 - drivers/clk/Makefile | 1 - drivers/clk/clk-efm32gg.c | 84 --- drivers/clocksource/Kconfig | 9 - drivers/clocksource/Makefile | 1 - drivers/clocksource/timer-efm32.c | 278 -------- drivers/i2c/busses/Kconfig | 7 - drivers/i2c/busses/Makefile | 1 - drivers/i2c/busses/i2c-efm32.c | 469 ------------- drivers/spi/Kconfig | 7 - drivers/spi/Makefile | 1 - drivers/spi/spi-efm32.c | 462 ------------ drivers/tty/serial/Kconfig | 13 - drivers/tty/serial/Makefile | 1 - drivers/tty/serial/efm32-uart.c | 852 ----------------------- include/linux/platform_data/efm32-spi.h | 15 - include/linux/platform_data/efm32-uart.h | 19 - include/uapi/linux/serial_core.h | 3 - 30 files changed, 1 insertion(+), 2690 deletions(-) delete mode 100644 arch/arm/boot/dts/efm32gg-dk3750.dts delete mode 100644 arch/arm/boot/dts/efm32gg.dtsi delete mode 100644 arch/arm/configs/efm32_defconfig delete mode 100644 arch/arm/include/debug/efm32.S delete mode 100644 arch/arm/mach-efm32/Makefile delete mode 100644 arch/arm/mach-efm32/Makefile.boot delete mode 100644 arch/arm/mach-efm32/dtmachine.c delete mode 100644 drivers/clk/clk-efm32gg.c delete mode 100644 drivers/clocksource/timer-efm32.c delete mode 100644 drivers/i2c/busses/i2c-efm32.c delete mode 100644 drivers/spi/spi-efm32.c delete mode 100644 drivers/tty/serial/efm32-uart.c delete mode 100644 include/linux/platform_data/efm32-spi.h delete mode 100644 include/linux/platform_data/efm32-uart.h base-commit: 5c8fe583cce542aa0b84adc939ce85293de36e5e -- 2.29.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
2021-01-15spi: Drop unused efm32 bus driverUwe Kleine-König
Support for this machine was just removed, so drop the now unused spi bus driver, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20210114151630.128830-5-u.kleine-koenig@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-15spi: cadence: cache reference clock rate during probeMichael Hennerich
The issue is that using SPI from a callback under the CCF lock will deadlock, since this code uses clk_get_rate(). Fixes: c474b38665463 ("spi: Add driver for Cadence SPI controller") Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Link: https://lore.kernel.org/r/20210114154217.51996-1-alexandru.ardelean@analog.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-14spi: pxa2xx: Add support for Intel Alder Lake PCH-PJarkko Nikula
Add support for LPSS SPI on Intel Alder Lake PCH-P variant. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Link: https://lore.kernel.org/r/20210114144021.1820262-1-jarkko.nikula@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-14spi: bcm2835aux: Call the dedicated transfer completion function.Vincent Pelletier
spi_finalize_current_transfer currently only calls "complete", so no functional change is expected. Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com> Link: https://lore.kernel.org/r/2636096a3b40febf680f9fff33944a5480561df9.1610062884.git.plr.vincent@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-14spi: rockchip: Call the dedicated transfer completion function.Vincent Pelletier
spi_finalize_current_transfer currently only calls "complete", so no functional change is expected. Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com> Link: https://lore.kernel.org/r/f3e1cf19a7dcdd77adc0a719adf46449b84ccadd.1610062884.git.plr.vincent@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-14spi: bcm2835: Call the dedicated transfer completion function.Vincent Pelletier
spi_finalize_current_transfer currently only calls "complete", so no functional change is expected. Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com> Link: https://lore.kernel.org/r/633c3d5c350dde4d14ce2120c32698c25b95d302.1610062884.git.plr.vincent@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-14spi: fsl: Fix driver breakage when SPI_CS_HIGH is not set in spi->modeChristophe Leroy
Commit 766c6b63aa04 ("spi: fix client driver breakages when using GPIO descriptors") broke fsl spi driver. As now we fully rely on gpiolib for handling the polarity of chip selects, the driver shall not alter the GPIO value anymore when SPI_CS_HIGH is not set in spi->mode. Fixes: 766c6b63aa04 ("spi: fix client driver breakages when using GPIO descriptors") Cc: stable@vger.kernel.org Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/6b51cc2bfbca70d3e9b9da7b7aa4c7a9d793ca0e.1610629002.git.christophe.leroy@csgroup.eu Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-13Merge v5.11-rc3Mark Brown
2021-01-13spi: bcm2835: Set controller max_speed_hzRichard Fitzgerald
Set the struct spi_controller max_speed_hz. This is based on the reported source clock frequency during probe. The maximum bus clock is half the source clock (as per the code in bcm2835_spi_transfer_one). Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Link: https://lore.kernel.org/r/20210107164825.21919-1-rf@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-13Merge series "spi: sh-msiof: Advertize bit rate limits and actual speed" ↵Mark Brown
from Geert Uytterhoeven <geert+renesas@glider.be>: Hi Mark, This patch series makes the Renesas MSIOF SPI driver fill in actual transfer speeds and controller limits, so the SPI core can take them into account. This has been tested on R-Car Gen2 and Gen3. Thanks! Geert Uytterhoeven (2): spi: sh-msiof: Fill in spi_transfer.effective_speed_hz spi: sh-msiof: Fill in controller speed limits drivers/spi/spi-sh-msiof.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) -- 2.25.1 Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
2021-01-13Merge series "spi: cadence-quadspi: Add QSPI controller support for Intel ↵Mark Brown
LGM SoC" from "Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com>: Add QSPI controller support for Intel LGM SoC. Patches to move move bindings over to "Documentation/devicetree/bindings/spi/" directory and also added compatible Support for Intel platform. dt-bindings: spi: cadence-qspi: Add support for Intel lgm-qspi (earlier patch mail thread and Ack-by) link: "https://lore.kernel.org/lkml/5d6d1b85.1c69fb81.96938.0315@mx.google.com/" Reference: https://lkml.org/lkml/2020/6/1/50 --- v9: - Vignesh review comments address and update - Retain the patchv4 move the binding documentation from mtd to spi directory. - Add intel's compatible string over the legacy documentation - Remove unused variable, CQSPI_SUPPORTS_MULTI_CHIPSELECT macro and check - YAML convertion patch alone dropped v8: - As Mark suggested to add the dt-bindings documentation patches end of the series , so dropped. v7: - Rob's review comments address and fixed dt-schema warning - Pratyush review comments address and update - DAC bit reset to 0 and 1 (enable/disable) - tested QSI-NOR flash mx25l12805d on LGM soc, it's working after disable DAC - Linus suggested to use 'num-cs' prperty instead of 'num-chipselect' v6: - Rob's review comments update - add compatible string in properly aligned - remove cadence-qspi extra comaptible string in example v5: - Rob's review comments update - const with single compatible string kept v4: - Rob's review comments update - remove '|' no formatting to preserve - child node attributes follows under 'properties' under '@[0-9a-f]+$'. v3: - Pratyush review comments update - CQSPI_SUPPORTS_MULTI_CHIPSELECT macro used instead of cqspi->use_direct_mode - disable DAC support placed in end of controller_init v2: - Rob's review comments update for dt-bindings - add 'oneOf' for compatible selection - drop un-neccessary descriptions - add the cdns,is-decoded-cs and cdns,rclk-en properties as schema - remove 'allOf' in not required place - add AdditionalProperties false - add minItems/maxItems for qspi reset attributes resend-v1: - As per Mark's suggestion , reorder the patch series 1-3 driver support patches, series 4-6 dt-bindings patches. v1: - initial version Ramuthevar Vadivel Murugan (5): spi: cadence-quadspi: Add QSPI support for Intel LGM SoC spi: cadence-quadspi: Disable the DAC for Intel LGM SoC spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoC spi: Move cadence-quadspi.txt to Documentation/devicetree/bindings/spi dt-bindings: spi: cadence-qspi: Add support for Intel lgm-qspi .../bindings/{mtd => spi}/cadence-quadspi.txt | 1 + drivers/spi/Kconfig | 2 +- drivers/spi/spi-cadence-quadspi.c | 24 ++++++++++++++++++---- 3 files changed, 22 insertions(+), 5 deletions(-) rename Documentation/devicetree/bindings/{mtd => spi}/cadence-quadspi.txt (97%) -- 2.11.0 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
2021-01-13spi: stm32: Simplify stm32h7_spi_prepare_fthlv()Marek Vasut
Simplify stm32h7_spi_prepare_fthlv() function implementation, no functional change intended. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Alain Volmat <alain.volmat@st.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: Amelie Delaunay <amelie.delaunay@st.com> Cc: Antonio Borneo <antonio.borneo@st.com> Cc: Mark Brown <broonie@kernel.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Roman Guskov <rguskov@dh-electronics.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-spi@vger.kernel.org Link: https://lore.kernel.org/r/20210104123114.261596-1-marex@denx.de Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-13spi: spi-qcom-qspi: Use irq trigger flags from firmwareStephen Boyd
We don't need to force this to be trigger high here, as the firmware properly configures the irq flags already. Drop it to save a line. Cc: Douglas Anderson <dianders@chromium.org> Cc: Rajendra Nayak <rnayak@codeaurora.org> Cc: Mukesh Kumar Savaliya <msavaliy@codeaurora.org> Cc: Akash Asthana <akashast@codeaurora.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210112001301.687628-1-swboyd@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-13spi: hisi-sfc-v3xx: extend version checking compatibilityYicong Yang
Currently we use concrete version to determine the max_cmd_dword. New entries should be added for compatible hardwares of new version or on new platform, otherwise the device will use 16 dwords instead of 64 even if it supports, which will degrade the performance. This will decrease the compatibility and the maintainability. Drop the switch-case statement of the version checking. Only version less than 0x351 supports maximum 16 command dwords. Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Acked-by: John Garry <john.garry@huawei.com> Link: https://lore.kernel.org/r/1610526716-14882-1-git-send-email-yangyicong@hisilicon.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-13spi: sh-msiof: Fill in controller speed limitsGeert Uytterhoeven
Fill in the controller speed limits, so the SPI core can use them for validating SPI transfers, and adjust or reject transfers when needed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210113101916.1147695-3-geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-13spi: sh-msiof: Fill in spi_transfer.effective_speed_hzGeert Uytterhoeven
Fill in the effective bit rate used for transfers, so the SPI core can calculate instead of estimate delays. Restore "reverse Christmas tree" order of local variables while adding new variables. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210113101916.1147695-2-geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-13spi: cadence-quadspi: Add multi-chipselect support for Intel LGM SoCRamuthevar Vadivel Murugan
Add multiple chipselect support for Intel LGM SoCs, currently QSPI-NOR and QSPI-NAND supported. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Link: https://lore.kernel.org/r/20201124041840.31066-4-vadivel.muruganx.ramuthevar@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-13spi: cadence-quadspi: Disable the DAC for Intel LGM SoCRamuthevar Vadivel Murugan
On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use Direct Access Controller(DAC). This patch adds a quirk to disable the Direct Access Controller for data transfer instead it uses indirect data transfe DAC bit resets to 1 so there is no need to explicitly set it. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Link: https://lore.kernel.org/r/20201124041840.31066-3-vadivel.muruganx.ramuthevar@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-13spi: cadence-quadspi: Add QSPI support for Intel LGM SoCRamuthevar Vadivel Murugan
Add QSPI controller support for Intel LGM SoC. Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> Link: https://lore.kernel.org/r/20201124041840.31066-2-vadivel.muruganx.ramuthevar@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-11spi: rpc-if: Gaurd .pm assignment with CONFIG_PM_SLEEP #ifdef checkLad Prabhakar
With CONFIG_PM_SLEEP disabled the rpcif_spi_pm_ops variable is still referenced and thus increasing the size of kernel. Fix this issue by adding CONFIG_PM_SLEEP #ifdef check around the .pm assignment (image size is critical on RZ/A SoC's where the SRAM sizes range 4~5 MiB). Fixes: 9584fc95cadc0 ("spi: rpc-if: Remove CONFIG_PM_SLEEP ifdefery") Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Suggested-by: Pavel Machek <pavel@denx.de> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20210107145329.27966-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-11spi: cadence-quadspi: Fix build warning on 32-bit platformsPratyush Yadav
The kernel test robot reports the following warning. drivers/spi/spi-cadence-quadspi.c:966:24: warning: comparison of distinct pointer types ('typeof (len) *' (aka 'unsigned int *') and 'typeof (500UL) *' (aka 'unsigned long *')) [-Wcompare-distinct-pointer-types] msecs_to_jiffies(max(len, 500UL)))) { ^~~~~~~~~~~~~~~ include/linux/minmax.h:58:19: note: expanded from macro 'max' #define max(x, y) __careful_cmp(x, y, >) ^~~~~~~~~~~~~~~~~~~~~~ include/linux/minmax.h:42:24: note: expanded from macro '__careful_cmp' __builtin_choose_expr(__safe_cmp(x, y), \ ^~~~~~~~~~~~~~~~ include/linux/minmax.h:32:4: note: expanded from macro '__safe_cmp' (__typecheck(x, y) && __no_side_effects(x, y)) ^~~~~~~~~~~~~~~~~ include/linux/minmax.h:18:28: note: expanded from macro '__typecheck' (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1))) ~~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~ 1 warning generated. This happens because size_t is unsigned long on 64-bit platforms like arm64 but it is unsigned int on 32-bit platforms like arm. Omitting the "UL" would result in a warning on 64-bit platforms. Squash it by type casting the arguments to size_t using max_t(). This way builds on both type of platforms can be satisfied. There is no chance of any truncation since 500 is small enough to fit into both int and long. Fixes: f453f293979f ("spi: cadence-quadspi: Wait at least 500 ms for direct reads") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20210108181457.30291-1-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-11spi: spi-bcm-qspi: style: Simplify bool comparisonYANG LI
Fix the following coccicheck warning: ./drivers/spi/spi-bcm-qspi.c:884:5-34: WARNING: Comparison to bool Signed-off-by: YANG LI <abaci-bugfix@linux.alibaba.com> Reported-by: Abaci Robot<abaci@linux.alibaba.com> Link: https://lore.kernel.org/r/1610357189-60031-1-git-send-email-abaci-bugfix@linux.alibaba.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-08spi: Fix distinct pointer types warning for ARCH=mipsYanteng Si
Fix a new warning report by build for make ARCH=MIPS allmodconfig: drivers/spi/spi-cadence-quadspi.c: In function 'cqspi_direct_read_execute': ./include/linux/minmax.h:18:28: warning: comparison of distinct pointer types lacks a cast 18 | (!!(sizeof((typeof(x) *)1 == (typeof(y) *)1))) | ^~ ./include/linux/minmax.h:32:4: note: in expansion of macro '__typecheck' 32 | (__typecheck(x, y) && __no_side_effects(x, y)) | ^~~~~~~~~~~ ./include/linux/minmax.h:42:24: note: in expansion of macro '__safe_cmp' 42 | __builtin_choose_expr(__safe_cmp(x, y), \ | ^~~~~~~~~~ ./include/linux/minmax.h:58:19: note: in expansion of macro '__careful_cmp' 58 | #define max(x, y) __careful_cmp(x, y, >) | ^~~~~~~~~~~~~ drivers/spi/spi-cadence-quadspi.c:1153:24: note: in expansion of macro 'max' 1153 | msecs_to_jiffies(max(len, 500UL)))) { | ^~~ "len" is unsigned,however,"500" is unsigned long. Signed-off-by: Yanteng Si <siyanteng@loongson.cn> Link: https://lore.kernel.org/r/20210107115704.3835282-1-siyanteng@loongson.cn Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06Merge series "Add Tegra Quad SPI driver" from Sowjanya Komatineni ↵Mark Brown
<skomatineni@nvidia.com>: This series adds Tegra210, Tegra186, and Tegra194 Quad SPI driver and enables Quad SPI on Jetson Nano and Jetson Xavier NX. QSPI controller is available on Tegra210, Tegra186 and Tegra194. Tegra186 and Tegra194 has additional feature of combined sequence mode where command, address and data can all be transferred in a single transfer. Combined sequence mode is useful only when using DMA mode transfer. This series does not have combined sequence mode feature as Tegra186/Tegra194 GPCDMA driver is not upstreamed yet. This series includes - dt-binding document - QSPI driver for Tegra210/Tegra186/Tegra194 - Enables QSPI on Jetson Nano and Jetson Xavier NX. Delta between patch versions: [v5]: Simplified implementation in Patch-0006 [v4]: Updated dummy cycles implementation based on v3 feedback - Added dummy_data bit field int spi_transfer to indicate corresponding transfer is dummy bytes transfer. - Updated Tegra QSPI transfer_one_message to identify dummy transfer and to use HW supported dummy bytes transfer when dummy cycles are with in Tegra QSPI supported max HW dummy cycles otherwise fallsback to transfer dummy bytes from software. - Updated dt-bindings based on v3 feedback. [v3]: v2 has some mixed patches sent out accidentally. v3 sends proper patches with fixes mentioned in v2. [v2]: below v1 feedback - Added SPI_MASTER_USES_HW_DUMMY_CYCLES flag for controllers supporting hardware dummy cycles and skips dummy bytes transfer from software for these controllers. - Updated dt-binding doc with tx/rx tap delay properties. - Added qspi_out clock to dt-binding doc which will be used later with ddr mode support. - All other v1 feedback on some cleanup. Sowjanya Komatineni (9): dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM dt-bindings: spi: Add Tegra Quad SPI device tree binding MAINTAINERS: Add Tegra Quad SPI driver section spi: tegra210-quad: Add support for Tegra210 QSPI controller spi: spi-mem: Mark dummy transfers by setting dummy_data bit spi: tegra210-quad: Add support for hardware dummy cycles transfer arm64: tegra: Enable QSPI on Jetson Nano arm64: tegra: Add QSPI nodes on Tegra194 arm64: tegra: Enable QSPI on Jetson Xavier NX .../bindings/spi/nvidia,tegra210-quad.yaml | 117 ++ MAINTAINERS | 8 + .../dts/nvidia/tegra194-p3509-0000+p3668-0000.dts | 12 + arch/arm64/boot/dts/nvidia/tegra194.dtsi | 28 + arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 12 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +- drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/spi-mem.c | 1 + drivers/spi/spi-tegra210-quad.c | 1410 ++++++++++++++++++++ include/dt-bindings/clock/tegra210-car.h | 2 +- include/linux/spi/spi.h | 2 + 12 files changed, 1604 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml create mode 100644 drivers/spi/spi-tegra210-quad.c -- 2.7.4
2021-01-06spi: tegra210-quad: Add support for hardware dummy cycles transferSowjanya Komatineni
Tegra Quad SPI controller hardware supports sending dummy bytes based on programmed dummy clock cycles after the actual transfer bytes. This patch adds this support of hardware dummy bytes transfer and skips transfer of dummy bytes from the software. For dummy cycles more than Tegra Quad SPI hardware maximum dummy cycles limit, driver transfers dummy bytes from the software. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1608585459-17250-7-git-send-email-skomatineni@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06spi: spi-mem: Mark dummy transfers by setting dummy_data bitSowjanya Komatineni
This patch marks dummy transfer by setting dummy_data bit to 1. Controllers supporting dummy transfer by hardware use this bit field to skip software transfer of dummy bytes and use hardware dummy bytes transfer. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1608585459-17250-6-git-send-email-skomatineni@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06spi: tegra210-quad: Add support for Tegra210 QSPI controllerSowjanya Komatineni
Tegra SoC has a Quad SPI controller starting from Tegra210. This patch adds support for Tegra210 QSPI controller. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Link: https://lore.kernel.org/r/1608585459-17250-5-git-send-email-skomatineni@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06spi: cadence-quadspi: Add DTR supportPratyush Yadav
Double Transfer Rate (DTR) mode transfers data twice per clock cycle. Add support for parsing DTR ops and set up the registers to allow it. Most SPI NOR flashes expect 2 byte commands. Parse the 2-byte opcode from SPI MEM and set it up in the CQSPI_REG_OP_EXT_LOWER register. Increment the delay needed before issuing indirect writes because larger delay is needed for DTR mode. With the current delay some writes end up missing. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20201222184425.7028-8-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06spi: cadence-quadspi: Wait at least 500 ms for direct readsPratyush Yadav
When performing a direct read via DMA the timeout for completion is set equal to the read length. This is fine for larger reads. For a small read like the Read Status Register command, the timeout would be 1 or 2 milliseconds. This is not enough to cover the overhead needed in setting up DMA. Make sure the timeout is at least 500 ms to allow DMA ample time to finish. For reads larger than 500 bytes, the timeout will continue to be equal to the read length. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20201222184425.7028-7-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06spi: cadence-quadspi: Implement a simple supports_op hookPratyush Yadav
The default SPI MEM supports_op hook rejects DTR ops by default. Add a simple supports_op hook that very closely imitates the SPI MEM one. It will be extended in later commits to allow DTR ops. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20201222184425.7028-6-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06spi: cadence-quadspi: Fix dummy cycle calculation when buswidth > 1Pratyush Yadav
SPI MEM deals with dummy bytes but the controller deals with dummy cycles. Multiplying bytes by 8 is correct if the dummy phase uses 1S mode since 1 byte will be sent in 8 cycles. But if the dummy phase uses 4S mode then 1 byte will be sent in 2 cycles. To correctly translate dummy bytes to dummy cycles, the dummy buswidth also needs to be taken into account. Divide 8 by the buswidth to get the correct multiplier for getting the number of cycles. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20201222184425.7028-5-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06spi: cadence-quadspi: Set dummy cycles from STIG commandsPratyush Yadav
If a command does not have an address phase it goes via the STIG path. The dummy cycles are not initialized for the STIG commands. As a result, STIG commands with dummy cycles will not work. Initialize the dummy cycle field before issuing the STIG command to make sure it is sent correctly. Move the code to calculate dummy cycle value to a separate function so it is not repeated twice. DTR support will add some more logic here to it is worth it to extract it out in a function. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20201222184425.7028-4-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06spi: cadence-quadspi: Abort read if dummy cycles required are too manyPratyush Yadav
The controller can only support up to 31 dummy cycles. If the command requires more it falls back to using 31. This command is likely to fail because the correct number of cycles are not waited upon. Rather than silently issuing an incorrect command, fail loudly so the caller can get a chance to find out the command can't be supported by the controller. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller") Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20201222184425.7028-3-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-06spi: cadence-quadspi: Set master max_speed_hzPratyush Yadav
As of commit 9326e4f1e5dd ("spi: Limit the spi device max speed to controller's max speed"), the SPI device max speed is set to the controller's max speed if it is larger. The Cadence QSPI controller does not set the controller's max speed so it is left at its initial value of 0. This means the SPI device max speed is always set to 0. The SPI device max speed is used to calculate the baud rate divider when performing an operation. If this speed is 0, the default divider of 32 is used. No matter what speed is specified by the device tree property 'spi-max-frequency', the device will always operate at ref_clk / 32. Fix this by setting master->max_speed_hz to the ref clock speed so the correct divider can be calculated. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20201222184425.7028-2-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-05spi: txx9: Remove driverThomas Bogendoerfer
CPU support for TX49xx is getting removed, so remove support SPI driver for it. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Link: https://lore.kernel.org/r/20210105140305.141401-5-tsbogend@alpha.franken.de Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-05spi: stm32: update dev_dbg() print format for SPI paramsAlexandru Ardelean
With the introduction of the 'include/uapi/linux/spi/spi.h' header, the type of the macros are enforced to 'unsigned long int' via the _BITUL() macro. This causes some -Wformat warnings in the spi-stm32 driver. This patch adds a double-negation operator to the bit-masks. Essentially, the important values for debugging are 0 or 1, while masking them directly would show 0 or BIT(x) values. This way, the type of the arguments are automatically re-cast. Fixes: f7005142dace ("spi: uapi: unify SPI modes into a single spi.h header") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20210104143103.56510-1-alexandru.ardelean@analog.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-04spi: renesas rpc-if: Update Add RZ/G2 to Kconfig descriptionAdam Ford
The SPI driver for the Renesas RPC-IF is present on the RZ/G2 Series. Add that to the description. Suggested-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210102115412.3402059-3-aford173@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-01-04spi: fix the divide by 0 error when calculating xfer waiting timeXu Yilun
The xfer waiting time is the result of xfer->len / xfer->speed_hz. This patch makes the assumption of 100khz xfer speed if the xfer->speed_hz is not assigned and stays 0. This avoids the divide by 0 issue and ensures a reasonable tolerant waiting time. Signed-off-by: Xu Yilun <yilun.xu@intel.com> Link: https://lore.kernel.org/r/1609723749-3557-1-git-send-email-yilun.xu@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-23 19:10:36 +0000