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2025-05-05spi: loopback-test: Do not split 1024-byte hexdumpsGeert Uytterhoeven
spi_test_print_hex_dump() prints buffers holding less than 1024 bytes in full. Larger buffers are truncated: only the first 512 and the last 512 bytes are printed, separated by a truncation message. The latter is confusing in case the buffer holds exactly 1024 bytes, as all data is printed anyway. Fix this by printing buffers holding up to and including 1024 bytes in full. Fixes: 84e0c4e5e2c4ef42 ("spi: add loopback test driver to allow for spi_master regression tests") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/37ee1bc90c6554c9347040adabf04188c8f704aa.1746184171.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-02Merge tag 'spi-fix-v6.15-rc4' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A fairly small pile of fixes, plus one new compatible string addition to the Synopsis driver for a new platform. The most notable thing is the fix for divide by zeros in spi-mem if an operation has no dummy bytes" * tag 'spi-fix-v6.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: tegra114: Don't fail set_cs_timing when delays are zero spi: spi-qpic-snand: fix NAND_READ_LOCATION_2 register handling spi: spi-mem: Add fix to avoid divide error spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC spi: dt-bindings: snps,dw-apb-ssi: Merge duplicate compatible entry spi: spi-qpic-snand: propagate errors from qcom_spi_block_erase() spi: stm32-ospi: Fix an error handling path in stm32_ospi_probe()
2025-05-03spi: loopback-test: Simplify strange loopback value checkGeert Uytterhoeven
Apply De Morgan's Theorem and drop superfluous parentheses to simplify the check for strange loopback values. While at it, add the missing zero in the related comment. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/da612090f543c8c7cc99fb9dc6ef4abc9560abe4.1746184293.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-02spi: tegra114: Don't fail set_cs_timing when delays are zeroAaron Kling
The original code would skip null delay pointers, but when the pointers were converted to point within the spi_device struct, the check was not updated to skip delays of zero. Hence all spi devices that didn't set delays would fail to probe. Fixes: 04e6bb0d6bb1 ("spi: modify set_cs_timing parameter") Cc: stable@vger.kernel.org Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://patch.msgid.link/20250423-spi-tegra114-v1-1-2d608bcc12f9@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-01ASoC: codec: twl4030: Convert to GPIO descriptorsMark Brown
Merge series from "Peng Fan (OSS)" <peng.fan@oss.nxp.com>: This is separated from [1]. With an update that sorting the headers in a separate patch. No other changes, so I still keep Linus' R-b for Patch 2. [1] https://lore.kernel.org/all/20250408-asoc-gpio-v1-3-c0db9d3fd6e9@nxp.com/
2025-04-30spi: axi-spi-engine: offload instruction optimizationMark Brown
Merge series from David Lechner <dlechner@baylibre.com>: In order to achieve a 4 MSPS rate on a 16-bit ADC with a 80 MHz SCLK using the SPI offload feature of the AXI SPI Engine, we need to shave off some time that is spent executing unnecessary instructions. There are a few one-time setup instructions that can be moved so that they execute only once when the SPI offload trigger is enabled rather than repeating each time the offload is triggered. Additionally, a recent change to the IP block allows dropping the SYNC instruction completely. With these changes, we are left with only the 3 instructions that are needed to to assert CS, transfer the data, and deassert CS. This makes 3 + 16 * 12.5 ns = 237.5 ns < 250 ns which is comfortably within the available time period.
2025-04-30spi: axi-spi-engine: omit SYNC from offload instructionsDavid Lechner
Add optimization to omit SYNC instructions from offload messages. Starting with IP core v1.5.0, the SYNC instruction is no longer required for proper operation when using the offload feature. Omitting the SYNC instruction saves a few clock cycles needed to executed which can e.g. allow achieving higher sample rates on ADCs. Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250428-adi-main-v1-4-4b8a1b88a212@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-30spi: axi-spi-engine: optimize bits_per_word for offloadDavid Lechner
Add an optimization to avoid repeating bits_per_word instructions in each message when using SPI offload. This only applies when all data xfers in a message have the same bits_per_word. In this case, we can execute the instruction that sets bits_per_word when the offload trigger is enabled. This is useful e.g. for obtaining higher sample rates on ADCs since each message takes less time to execute. Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250428-adi-main-v1-3-4b8a1b88a212@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-30spi: axi-spi-engine: don't repeat mode config for offloadDavid Lechner
Add an optimization to avoid repeating the config instruction in each SPI message when using SPI offloading. Instead, the instruction is run once when the SPI offload trigger is enabled. This is done to allow higher sample rates for ADCs using this SPI controller. Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250428-adi-main-v1-2-4b8a1b88a212@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-30spi: axi-spi-engine: wait for completion in setupDavid Lechner
Add a polling wait for SPI instruction execution to complete in the spi_engine_setup() function. In practice, these instructions complete in a few 10s of nanoseconds, so we never ran into any race conditions, but it is good practice to wait for the completion of the SPI engine instructions before returning from the setup function. Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250428-adi-main-v1-1-4b8a1b88a212@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-30spi: spi-qpic-snand: fix NAND_READ_LOCATION_2 register handlingGabor Juhos
The precomputed value for the NAND_READ_LOCATION_2 register should be stored in 'snandc->regs->read_location2'. Fix the qcom_spi_set_read_loc_first() function accordingly. Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://patch.msgid.link/20250428-qpic-snand-readloc2-fix-v1-1-50ce0877ff72@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-29mtd: rawnand: qcom: Pass 18 bit offset from NANDc base to BAM baseMd Sadre Alam
The BAM command descriptor provides only 18 bits to specify the BAM register offset. Additionally, in the BAM command descriptor, the BAM register offset is supposed to be specified as "(NANDc base - BAM base) + reg_off". Since, the BAM controller expecting the value in the form of "NANDc base - BAM base", so that added a new field 'bam_offset' in the NAND properties structure and use it while preparing the command descriptor. Previously, the driver was specifying the NANDc base address in the BAM command descriptor. Cc: stable@vger.kernel.org Fixes: 8d6b6d7e135e ("mtd: nand: qcom: support for command descriptor formation") Tested-by: Lakshmi Sowjanya D <quic_laksd@quicinc.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Acked-by: Mark Brown <broonie@kernel.org> Tested-by: Gabor Juhos <j4g8y7@gmail.com> # on IPQ9574 Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-04-25Configure Clocks, Add Internal DMA supportMark Brown
Merge series from Vishwaroop A <va@nvidia.com>: This series introduces QSPI clock configuration and internal DMA support for Quad SPI controller. The patches have been reorganized for better logical flow and review comments from v2 have been addressed.
2025-04-25ASoC: add Renesas MSIOF sound driverMark Brown
Merge series from Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>: Renesas MSIOF can work as both SPI and I2S. Current Linux supports MSIOF-SPI. This patch-set adds new MSIOF-I2S. Because it is using same HW-IP, we want to share same compatible for both MSIOF-SPI/I2S case. MSIOF-I2S (Sound) will use Audio-Graph-Card/Card2 which uses Of-Graph, but MSIOF-SPI is not use Of-Graph. So, this patch-set assumes it was used as MSIOF-I2S if DT is using Of-Graph, otherwise, it is MSIOF-SPI (This assumption will works if SPI *never* use Of-Graph in the future). One note so far is that it is using "spi@xxx" node name for both MSIOF-SPI/I2S. DTC will automatically checks "spi@xxx" node as SPI device which requests #address-cells/#size-cells. But is not needed for I2S. So we will get warning about it on Sparrow Hawk which uses MSIOF-I2S. We have no solution about it, so far. Link: https://lore.kernel.org/r/87zfgi1a5a.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87h62vh5mj.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/875xjeb0wu.wl-kuninori.morimoto.gx@renesas.com
2025-04-25spi: spi-qpic-snand: remove unused 'wlen' member of 'struct qpic_spi_nand'Gabor Juhos
The 'wlen' member of the qpic_spi_nand structure is never used in the code so remove that. Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Link: https://patch.msgid.link/20250424-qpic-snand-remove-wlen-v1-1-2a7467ce2e3a@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-25spi: spi-mem: Add fix to avoid divide errorRaju Rangoju
For some SPI flash memory operations, dummy bytes are not mandatory. For example, in Winbond SPINAND flash memory devices, the `write_cache` and `update_cache` operation variants have zero dummy bytes. Calculating the duration for SPI memory operations with zero dummy bytes causes a divide error when `ncycles` is calculated in the spi_mem_calc_op_duration(). Add changes to skip the 'ncylcles' calculation for zero dummy bytes. Following divide error is fixed by this change: Oops: divide error: 0000 [#1] PREEMPT SMP NOPTI ... ? do_trap+0xdb/0x100 ? do_error_trap+0x75/0xb0 ? spi_mem_calc_op_duration+0x56/0xb0 ? exc_divide_error+0x3b/0x70 ? spi_mem_calc_op_duration+0x56/0xb0 ? asm_exc_divide_error+0x1b/0x20 ? spi_mem_calc_op_duration+0x56/0xb0 ? spinand_select_op_variant+0xee/0x190 [spinand] spinand_match_and_init+0x13e/0x1a0 [spinand] spinand_manufacturer_match+0x6e/0xa0 [spinand] spinand_probe+0x357/0x7f0 [spinand] ? kernfs_activate+0x87/0xd0 spi_mem_probe+0x7a/0xb0 spi_probe+0x7d/0x130 Fixes: 226d6cb3cb79 ("spi: spi-mem: Estimate the time taken by operations") Suggested-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250424121333.417372-1-Raju.Rangoju@amd.com Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-24spi: meson-spicc: add DMA supportXianwei Zhao
Add DMA support for spicc driver. DMA works if the transfer meets the following conditions: 1. 64 bits per word; 2. The transfer length must be multiples of the dma_burst_len, and the dma_burst_len should be one of 8,7...2, otherwise, it will be split into several SPI bursts. Signed-off-by: Sunny Luo <sunny.luo@amlogic.com> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://patch.msgid.link/20250414-spi-dma-v2-1-84bbd92fa469@amlogic.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-24spi: tegra210-quad: Update dummy sequence configurationVishwaroop A
Adding support for the dummy sequence configuration. The dummy sequence introduces a delay between the command and the data phases of a transfer. This delay, measured in clock cycles, allows the slave device to prepare for data transmission, ensuring data integrity and proper synchronization. Signed-off-by: Vishwaroop A <va@nvidia.com> Link: https://patch.msgid.link/20250416110606.2737315-6-va@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-24spi: tegra210-quad: modify chip select (CS) deactivationVishwaroop A
Modify the chip select (CS) deactivation and inter-transfer delay execution only during the DATA_TRANSFER phase when the cs_change flag is not set. This ensures proper CS handling and timing between transfers while eliminating redundant operations. Fixes: 1b8342cc4a38 ("spi: tegra210-quad: combined sequence mode") Signed-off-by: Vishwaroop A <va@nvidia.com> Link: https://patch.msgid.link/20250416110606.2737315-4-va@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-24spi: tegra210-quad: remove redundant error handling codeVishwaroop A
Remove unnecessary error handling code that terminated transfers and executed delay on errors. This code was redundant as error handling is already done at a higher level in the SPI core. Fixes: 1b8342cc4a38 ("spi: tegra210-quad: combined sequence mode") Signed-off-by: Vishwaroop A <va@nvidia.com> Link: https://patch.msgid.link/20250416110606.2737315-3-va@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-24spi: tegra210-quad: Fix X1_X2_X4 encoding and support x4 transfersVishwaroop A
This patch corrects the QSPI_COMMAND_X1_X2_X4 and QSPI_ADDRESS_X1_X2_X4 macros to properly encode the bus width for x1, x2, and x4 transfers. Although these macros were previously incorrect, they were not being used in the driver, so no functionality was affected. The patch updates tegra_qspi_cmd_config() and tegra_qspi_addr_config() function calls to use the actual bus width from the transfer, instead of hardcoding it to 0 (which implied x1 mode). This change enables proper support for x1, x2, and x4 data transfers by correctly configuring the interface width for commands and addresses. These modifications improve the QSPI driver's flexibility and prepare it for future use cases that may require different bus widths for commands and addresses. Fixes: 1b8342cc4a38 ("spi: tegra210-quad: combined sequence mode") Signed-off-by: Vishwaroop A <va@nvidia.com> Link: https://patch.msgid.link/20250416110606.2737315-2-va@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-24spi: intel: Improve resource mappingHeiner Kallweit
Let's use the pci/platform-specialized functions for mapping a resource, and pass the mapped address to intel_spi_probe. Benefits are: - No separate call needed for getting the resource, and no access to struct pci_dev internals (pdev->resource[]). - More user-friendly output in /proc/iomem. In my case: before 80704000-80704fff : 0000:00:1f.5 80704000-80704fff : 0000:00:1f.5 0000:00:1f.5 after 80704000-80704fff : 0000:00:1f.5 80704000-80704fff : spi_intel_pci Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Link: https://patch.msgid.link/2585fa05-60c4-48c4-a838-e87014665ae2@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-24spi: sh-msiof: ignore driver probing if it was MSIOF SoundKuninori Morimoto
Renesas MSIOF (Clock-Synchronized Serial Interface with FIFO) can work as both SPI and I2S. MSIOF-I2S will use Audio Graph Card/Card2 driver which Of-Graph in DT. MSIOF-SPI/I2S are using same DT compatible properties. MSIOF-I2S uses Of-Graph for Audio-Graph-Card/Card2, MSIOF-SPI doesn't use Of-Graph. Check "port" node when driver probing Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/87wmbi2x0g.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-24spi: sh-msiof: use dev in sh_msiof_spi_probe()Kuninori Morimoto
sh_msiof_spi_probe() is using priv->dev everywhere, but it makes code long. Create struct device *dev and use it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/87y0vy2x0o.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-24spi: spi-qpic-snand: propagate errors from qcom_spi_block_erase()Gabor Juhos
The qcom_spi_block_erase() function returns with error in case of failure. Change the qcom_spi_send_cmdaddr() function to propagate these errors to the callers instead of returning with success. Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://patch.msgid.link/20250423-qpic-snand-propagate-error-v1-1-4b26ed45fdb5@gmail.com Reviewed-by: Md Sadre Alam <quic_mdalam@quicinc.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-22spi: stm32-ospi: Fix an error handling path in stm32_ospi_probe()Christophe JAILLET
If an error occurs after a successful stm32_ospi_dma_setup() call, some dma_release_channel() calls are needed to release some resources, as already done in the remove function. Fixes: 79b8a705e26c ("spi: stm32: Add OSPI driver") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://patch.msgid.link/2674c8df1d05ab312826b69bfe9559f81d125a0b.1744975624.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-21spi: offload: remove unnecessary check on trigger->opsAndres Urian Florez
Considering that trigger->ops = NULL happens only when the trigger is being removed from the list, and at that point the operation is protected with the spi_offload_triggers_lock, it is possible to remove the !trigger->ops check because it will never be true in spi_offload_trigger_get() Signed-off-by: Andres Urian Florez <andres.emb.sys@gmail.com> Reviewed-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250418171426.9868-1-andres.emb.sys@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-21spi: offload: check for match callback when a trigger is being registeredAndres Urian Florez
Make match a required callback when a new trigger is being registered, this allows that other functions like spi_offload_trigger_get() could safely invoke the callback when it is required In v2: - improve readability of the condition Signed-off-by: Andres Urian Florez <andres.emb.sys@gmail.com> Reviewed-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250418224750.46219-1-andres.emb.sys@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-18spi: Introduce and use spi_bpw_to_bytes()Mark Brown
Merge series from Andy Shevchenko <andriy.shevchenko@linux.intel.com>: Recently in the discussion with David the idea of having a common helper popped up. The helper converts the given bits per word to bytes. The result will always be power-of-two (e.g. for 37 bits it returns 8 bytes) or 0 for 0 input. More details are in the respective code comment. This mini-series introduces it and replaces current users under drivers/spi and we expect more (and possibly some lurking in other subsystems).
2025-04-17spi: dw: Use spi_bpw_to_bytes() helperAndy Shevchenko
Use existing helper to get amount of bytes (as power-of-two value) from bits per word. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250417152529.490582-3-andriy.shevchenko@linux.intel.com Acked-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-17spi: Add spi_bpw_to_bytes() helper and use itAndy Shevchenko
This helper converts the given bits per word to bytes. The result will always be power-of-two, e.g., =============== ================= Input (in bits) Output (in bytes) =============== ================= 5 1 9 2 21 4 37 8 =============== ================= It will return 0 for the 0 input. There are a couple of cases in SPI that are using the same approach and at least one more (in IIO) would benefit of it. Add a helper for everyone. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250417152529.490582-2-andriy.shevchenko@linux.intel.com Acked-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-17spi: pci1xxxx: Use non-hybrid PCI devres APIPhilipp Stanner
pci1xxxx enables its PCI device with pcim_enable_device(). This, implicitly, switches the function pci_request_regions() into managed mode, where it becomes a devres function. The PCI subsystem wants to remove this hybrid nature from its interfaces. To do so, users of the aforementioned combination of functions must be ported to non-hybrid functions. Moreover, since both functions are already managed in this driver, the call to pci_release_regions() is unnecessary. Remove the call to pci_release_regions(). Replace the call to sometimes-managed pci_request_regions() with one to the always-managed pcim_request_all_regions(). Signed-off-by: Philipp Stanner <phasta@kernel.org> Link: https://patch.msgid.link/20250417083902.23483-4-phasta@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-17spi: spi-cavium-thunderx: Use non-hybrid PCI devres APIPhilipp Stanner
cavium-thunderx enables its PCI device with pcim_enable_device(). This, implicitly, switches the function pci_request_regions() into managed mode, where it becomes a devres function. The PCI subsystem wants to remove this hybrid nature from its interfaces. To do so, users of the aforementioned combination of functions must be ported to non-hybrid functions. Moreover, since both functions are already managed in this driver, the calls to pci_release_regions() are unnecessary. Remove the calls to pci_release_regions(). Replace the call to sometimes-managed pci_request_regions() with one to the always-managed pcim_request_all_regions(). Signed-off-by: Philipp Stanner <phasta@kernel.org> Link: https://patch.msgid.link/20250417083902.23483-2-phasta@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-17spi: spi-imx: Add check for spi_imx_setupxfer()Tamura Dai
Add check for the return value of spi_imx_setupxfer(). spi_imx->rx and spi_imx->tx function pointer can be NULL when spi_imx_setupxfer() return error, and make NULL pointer dereference. Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 Call trace: 0x0 spi_imx_pio_transfer+0x50/0xd8 spi_imx_transfer_one+0x18c/0x858 spi_transfer_one_message+0x43c/0x790 __spi_pump_transfer_message+0x238/0x5d4 __spi_sync+0x2b0/0x454 spi_write_then_read+0x11c/0x200 Signed-off-by: Tamura Dai <kirinode0@gmail.com> Reviewed-by: Carlos Song <carlos.song@nxp.com> Link: https://patch.msgid.link/20250417011700.14436-1-kirinode0@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-15spi: tegra210-quad: add rate limiting and simplify timeout error messageBreno Leitao
On malfunctioning hardware, timeout error messages can appear thousands of times, creating unnecessary system pressure and log bloat. This patch makes two improvements: 1. Replace dev_err() with dev_err_ratelimited() to prevent log flooding when hardware errors persist 2. Remove the redundant timeout value parameter from the error message, as 'ret' is always zero in this error path These changes reduce logging overhead while maintaining necessary error reporting for debugging purposes. Signed-off-by: Breno Leitao <leitao@debian.org> Link: https://patch.msgid.link/20250401-tegra-v2-2-126c293ec047@debian.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-15spi: tegra210-quad: use WARN_ON_ONCE instead of WARN_ON for timeoutsBreno Leitao
Some machines with tegra_qspi_combined_seq_xfer hardware issues generate excessive kernel warnings, severely polluting the logs: dmesg | grep -i "WARNING:.*tegra_qspi_transfer_one_message" | wc -l 94451 This patch replaces WARN_ON with WARN_ON_ONCE for timeout conditions to reduce log spam. The subsequent error message still prints on each occurrence, providing sufficient information about the failure, while the stack trace is only needed once for debugging purposes. Signed-off-by: Breno Leitao <leitao@debian.org> Link: https://patch.msgid.link/20250401-tegra-v2-1-126c293ec047@debian.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-14spi: sun4i: add support for GPIO chip select linesMans Rullgard
Set use_gpio_descriptors to true so that GPIOs can be used for chip select in accordance with the DT binding. Signed-off-by: Mans Rullgard <mans@mansr.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250410115303.5150-1-mans@mansr.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-13spi: fsl-qspi: Optimize fsl_qspi structKevin Hao
Reorgize the members of the fsl_qspi struct to: - Reduce a hole in the struct. - Group members required by each op (e.g., iobase, ahb_addr, devtype_data and lock) into the same cacheline. Before: struct fsl_qspi { [...] /* size: 176, cachelines: 3, members: 11 */ /* sum members: 168, holes: 1, sum holes: 4 */ /* padding: 4 */ /* member types with holes: 1, total: 1 */ /* last cacheline: 48 bytes */ }; after: struct fsl_qspi { void * iobase; /* 0 8 */ void * ahb_addr; /* 8 8 */ const struct fsl_qspi_devtype_data * devtype_data; /* 16 8 */ struct mutex lock; /* 24 32 */ struct completion c; /* 56 32 */ /* XXX last struct has 1 hole */ /* --- cacheline 1 boundary (64 bytes) was 24 bytes ago --- */ struct clk * clk; /* 88 8 */ struct clk * clk_en; /* 96 8 */ struct pm_qos_request pm_qos_req; /* 104 48 */ /* --- cacheline 2 boundary (128 bytes) was 24 bytes ago --- */ struct device * dev; /* 152 8 */ int selected; /* 160 4 */ u32 memmap_phy; /* 164 4 */ /* size: 168, cachelines: 3, members: 11 */ /* member types with holes: 1, total: 1 */ /* last cacheline: 40 bytes */ }; Reviewed-by: Han Xu <han.xu@nxp.com> Signed-off-by: Kevin Hao <haokexin@gmail.com> Link: https://patch.msgid.link/20250411-spi-v1-1-8d6dfb1a9262@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-13spi: Add support for Double Transfer Rate (DTR) modeMukesh Kumar Savaliya
Introduce support for protocol drivers to specify whether a transfer should use single or dual transfer mode. Currently, the SPI controller cannot determine this information from the user, leading to potential limitations in transfer capabilities. Add a new field `dtr_mode` in the `spi_transfer` structure. The `dtr_mode` field allows protocol drivers to indicate if Double Transfer Rate (DTR) mode is supported for a given transfer. When `dtr_mode` is set to true, the SPI controller will use DTR mode; otherwise, it will default to single transfer mode. Introduce another field `dtr_caps` to indicate if the QSPI controller is capable of supporting DTR mode (SDR and DDR). By default, both `dtr_caps` and `dtr_mode` will be false. These flags manage the QSPI controller's DTR mode capabilities within the SPI framework. The QSPI controller driver uses these flags to configure single or double transfer rates using the controller register. The existing spi-mem driver helps configure the DTR mode but is limited to memory devices. There is no support available to set DTR mode for non-memory devices, e.g., touch or any generic SPI sensor. This change is backward compatible and doesn't break existing SPI or QSPI drivers. Changes include: - Addition of `dtr_mode` and `dtr_caps` fields in the `spi_transfer` structure. - Documentation updates to reflect the new `dtr_mode` and `dtr_caps` fields. Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com> Link: https://patch.msgid.link/20250404135427.313825-1-quic_msavaliy@quicinc.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-10spi: amd: add CONFIG_PCI dependencyArnd Bergmann
Without CONFIG_PCI, the module_pci_driver() macro is not defined: drivers/spi/spi-amd-pci.c:67:1: error: type specifier missing, defaults to 'int'; ISO C99 and later do not support implicit int [-Wimplicit-int] 67 | module_pci_driver(amd_spi_pci_driver); Fixes: b644c2776652 ("spi: spi_amd: Add PCI-based driver for AMD HID2 SPI controller") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://patch.msgid.link/20250410140809.812863-1-arnd@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-10spi: fsl-qspi: Fix double cleanup in probe error pathMark Brown
Merge series from Kevin Hao <haokexin@gmail.com>: This patch series fixes double cleanup issues in the fsl-qspi probe error path and also simplifies the probe error handling using managed APIs.
2025-04-10spi: fsl-qspi: Simplify probe error handling using managed APIKevin Hao
- Switch to devm_spi_alloc_host() to avoid manual spi_controller_put() calls in error paths. - Factor out the hardware disable logic into a dedicated fsl_qspi_disable() helper and register it as a managed cleanup action, removing the need to explicitly disable hardware after fsl_qspi_default_setup() failures. - Move fsl_qspi_cleanup() earlier in the probe sequence to eliminate the need for manual cleanup in the irq failure path. With these changes we can completely eliminate the messy goto labels in probe function. Signed-off-by: Kevin Hao <haokexin@gmail.com> Link: https://patch.msgid.link/20250410-spi-v1-3-56e867cc19cf@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-10spi: fsl-spi: Remove redundant probe error messageKevin Hao
An error message is already emitted by the driver core function call_driver_probe() when the driver probe fails. Therefore, this redundant probe error message is removed. Signed-off-by: Kevin Hao <haokexin@gmail.com> Link: https://patch.msgid.link/20250410-spi-v1-2-56e867cc19cf@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-10spi: fsl-qspi: Fix double cleanup in probe error pathKevin Hao
Commit 40369bfe717e ("spi: fsl-qspi: use devm function instead of driver remove") introduced managed cleanup via fsl_qspi_cleanup(), but incorrectly retain manual cleanup in two scenarios: - On devm_add_action_or_reset() failure, the function automatically call fsl_qspi_cleanup(). However, the current code still jumps to err_destroy_mutex, repeating cleanup. - After the fsl_qspi_cleanup() action is added successfully, there is no need to manually perform the cleanup in the subsequent error path. However, the current code still jumps to err_destroy_mutex on spi controller failure, repeating cleanup. Skip redundant manual cleanup calls to fix these issues. Cc: stable@vger.kernel.org Fixes: 40369bfe717e ("spi: fsl-qspi: use devm function instead of driver remove") Signed-off-by: Kevin Hao <haokexin@gmail.com> Link: https://patch.msgid.link/20250410-spi-v1-1-56e867cc19cf@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-09spi: spi_amd: Fix an IS_ERR() vs NULL check in probeDan Carpenter
The devm_ioremap() function returns NULL on error, it doesn't return error pointers. Update the error checking to match. Fixes: b644c2776652 ("spi: spi_amd: Add PCI-based driver for AMD HID2 SPI controller") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Link: https://patch.msgid.link/0e0f5ede-8993-4fac-967c-51e46b095416@stanley.mountain Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-08spi: spi-stm32-ospi: dt-bindings fixesMark Brown
Merge series from Patrice Chotard <patrice.chotard@foss.st.com>: Make "resets" property mandatory. Update spi-stm32-ospi driver and dt-bindings accordingly.
2025-04-08spi: xcomm: use new GPIO line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://patch.msgid.link/20250408-gpiochip-set-rv-spi-v1-1-597660766654@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-06spi: spi_amd: Add PCI-based driver for AMD HID2 SPI controllerRaju Rangoju
Register a new driver(spi_amd_pci) for the HID2 SPI controller using the PCI ID of the LPC bridge device. Add a new common probe function in spi_amd driver to encapsulate the code required for registering the controller driver. This function will be utilized by both the existing ACPI driver and the newly introduced PCI-based driver for the HID2 SPI controller. The MMIO register base address of the HID2 SPI controller can be obtained from the PCI LPC bridge registers. By implementing these changes, the DMA buffer will be correctly associated with the LPC bridge device, preventing IO_PAGE_FAULT caused by IOMMU when the LPC bridge attempts DMA operations on addresses owned by the HID2 SPI controller. Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250402121514.2941334-1-Raju.Rangoju@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-06spi: spi-qpic-snand: use kmalloc() for OOB buffer allocationGabor Juhos
The qcom_spi_ecc_init_ctx_pipelined() function allocates zeroed memory for the OOB buffer, then it fills the buffer with '0xff' bytes right after the allocation. In this case zeroing the memory during allocation is superfluous, so use kmalloc() instead of kzalloc() to avoid that. Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Link: https://patch.msgid.link/20250320-qpic-snand-kmalloc-v1-1-94e267550675@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-06spi: Simplify conditionals in spi_set_cs()Andy Shevchenko
First of all, the (foo && bar) || (!foo && !bar) when foo and bar are booleans is equivalent to (foo == bar). Second, reuse variable that holds already the calculation of the SPI CS mode to be active-high. No functional changes intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20250331093915.4041600-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit (git 2.34.1) at 2025-08-01 06:10:08 +0000