summaryrefslogtreecommitdiff
path: root/sound/soc/fsl/fsl_sai.h
AgeCommit message (Collapse)Author
2025-04-06ASoC: fsl_sai: separate set_tdm_slot() for tx and rxShengjiu Wang
The transmitter and receiver of SAI can be used for different slot number and slot width configuration, so refine fsl_sai_set_dai_tdm_slot(), add fsl_sai_set_dai_tdm_slot_tx() for tx and fsl_sai_set_dai_tdm_slot_rx() for rx. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://patch.msgid.link/20250328085744.1893434-5-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-06ASoC: fsl_sai: separate 'is_dsp_mode' for tx and rxShengjiu Wang
The transmitter and receiver of SAI can be used for different dsp modes, then 'is_dsp_mode' needs to be separated. Expand 'is_dsp_mode' to array 'is_dsp_mode[]' to support different configuration of tx and rx. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://patch.msgid.link/20250328085744.1893434-4-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-09ASoC: fsl_sai: Add sample rate constraintChancel Liu
Platforms like i.MX93/91 only have one audio PLL. Some sample rates are not supported. If the PLL source is used for 8kHz series rates, then 11kHz series rates can't be supported. Use fsl_asoc_constrain_rates() to constrain rates according to PLL sources. Signed-off-by: Chancel Liu <chancel.liu@nxp.com> Link: https://patch.msgid.link/20241126115440.3929061-5-chancel.liu@nxp.com Acked-by: Shengjiu Wang <shengjiu.wang@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30ASoC: fsl_sai: Enable 'FIFO continue on error' FCONT bitShengjiu Wang
FCONT=1 means On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared. Set FCONT bit in control register to avoid the channel swap issue after SAI xrun. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://patch.msgid.link/1727676508-22830-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-06-26ASoC: fsl_sai: Add separate DAI for transmitter and receiverShengjiu Wang
The transmitter and receiver part of the SAI interface need to be configured with different master/slave mode, especially to work with the audiomix module. +-------+ +-----------+ | SAI1 | --TX--> | | | | <--RX-- | | +-------+ | | | AUDIOMIX | +-------+ | | | SAI2 | --TX--> | | +-------+ +-----------+ The SAI1 TX is in master mode, but SAI1 RX is in slave mode. So add another two DAIs for TX and RX separately. but only defined fsl_sai_set_dai_fmt_tx() and fsl_sai_set_dai_fmt_rx() ops function for current case, in the future, the other ops function for TX and RX can be defined if required. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://patch.msgid.link/1718174452-17596-2-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-07-17ASoC: fsl_sai: Disable bit clock with transmitterMatus Gajdos
Otherwise bit clock remains running writing invalid data to the DAC. Signed-off-by: Matus Gajdos <matuszpd@gmail.com> Acked-by: Shengjiu Wang <shengjiu.wang@gmail.com> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230712124934.32232-1-matuszpd@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-06-16ASoC: Merge fixes due to dependenciesMark Brown
So we can apply the tlv320aic3xxx DT conversion.
2023-06-02ASoC: fsl_sai: Enable BCI bit if SAI works on synchronous mode with BYP assertedChancel Liu
There's an issue on SAI synchronous mode that TX/RX side can't get BCLK from RX/TX it sync with if BYP bit is asserted. It's a workaround to fix it that enable SION of IOMUX pad control and assert BCI. For example if TX sync with RX which means both TX and RX are using clk form RX and BYP=1. TX can get BCLK only if the following two conditions are valid: 1. SION of RX BCLK IOMUX pad is set to 1 2. BCI of TX is set to 1 Signed-off-by: Chancel Liu <chancel.liu@nxp.com> Acked-by: Shengjiu Wang <shengjiu.wang@gmail.com> Link: https://lore.kernel.org/r/20230530103012.3448838-1-chancel.liu@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-05-08ASoC: fsl_sai: MCLK bind with TX/RX enable bitShengjiu Wang
On i.MX8MP, the sai MCLK is bound with TX/RX enable bit, which means the TX/RE enable bit need to be enabled then MCLK can be output on PAD. Some codec (for example: WM8962) needs the MCLK output earlier, otherwise there will be issue for codec configuration. Add new soc data "mclk_with_tere" for this platform and enable the MCLK output in startup stage. As "mclk_with_tere" only applied to i.MX8MP, currently The soc data is shared with i.MX8MN, so need to add an i.MX8MN own soc data with "mclk_with_tere" disabled. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com Link: https://lore.kernel.org/r/1683273322-2525-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org
2022-10-28ASoC: fsl_sai: Specify the maxburst to 8 on i.MX93 platformChancel Liu
There is a limit to eDMA AXI on i.MX93. Only TCD that has NBYTES in a multiple of 8bytes can enable scatter-gather. NBYTES is calculated by bus width times maxburst. On i.MX93 platform the value of maxburst is specified to 8. It makes sure that NBYTES is a multiple of 8bytes. Signed-off-by: Chancel Liu <chancel.liu@nxp.com> Acked-by: Shengjiu Wang <shengjiu.wang@gmail.com> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Link: https://lore.kernel.org/r/20221027060311.2549711-4-chancel.liu@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-08-23ASoC: fsl_sai: Add support multi fifo sdma scriptShengjiu Wang
With disabling combine mode, the multiple successive FIFO registers or non successive FIFO registers of SAI module can work with the sdma multi fifo script. This patch is to configure the necessary information to the SDMA engine driver for support multi fifo script. 'words_per_fifo' is the channels for each dataline 'n_fifos_src' and 'n_fifos_dst' are the fifo number 'stride_fifos_src' and 'stride_fifos_dst' are the stride between enable FIFOs 'maxburst' is the multiply of datalines Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1661218573-2154-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-07-05ASoC: fsl_sai: Add support for PLL switch at runtimeShengjiu Wang
i.MX8MQ/MN/MM/MP platforms typically have 2 AUDIO PLLs being configured to handle 8kHz and 11kHz series audio rates. The patch implements the functionality to select at runtime the appropriate AUDIO PLL as function of sysclk rate. Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1656667961-1799-5-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-27ASoC: fsl_sai: Configure dataline/FIFO information from dts propertyShengjiu Wang
The SAI has multiple successive FIFO registers, but in some use case the required dataline/FIFOs are not successive, so need get such information from dts property "fsl,dataline" fsl,dataline has 3 values for each configuration: first one means the type: I2S(1) or DSD(2), second one is dataline mask for 'rx', third one is dataline mask for 'tx'. Also set dma peripheral address and TRCE bits according to data lane. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Link: https://lore.kernel.org/r/1655451877-16382-8-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-27ASoC: fsl_sai: Make res a member of struct fsl_saiShengjiu Wang
The resource info need to be accessed by hw_params() function for multi fifo case, the start address may be not the FIFO0. So move it to be a member of struct fsl_sai. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1655451877-16382-6-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-27ASoc: fsl_sai: Add pinctrl operation for PDM and DSDShengjiu Wang
With DSD format, the pinctrl is different compare with I2S format, because one dataline only has one channel data, and the codec always mux the LRCLK pin to DSD data line, and on i.MX8MQ the BCLK pin can route to codec on DSD case for the MCLK is too high. Add pinctrl operation that the pinctrl can be switched on runtime according to the I2S format or DSD format Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1655451877-16382-5-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-27ASoC: fsl_sai: Add DSD bit format supportShengjiu Wang
Support DSD_U8, DSD_U16_LE, DSD_U32_LE. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1655451877-16382-3-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-27ASoC: fsl_sai: Add PDM daifmt supportShengjiu Wang
PDM format is used for 1-bit stream, so clear the FBT and SYWD, and the each dataline only has one channel data. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1655451877-16382-2-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-23ASoC: fsl_sai: Fix FSL_SAI_xDR/xFR definitionShengjiu Wang
There are multiple xDR and xFR registers, the index is from 0 to 7. FSL_SAI_xDR and FSL_SAI_xFR is abandoned, replace them with FSL_SAI_xDR0 and FSL_SAI_xFR0. Fixes: 4f7a0728b530 ("ASoC: fsl_sai: Add support for SAI new version") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1653284661-18964-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-05-16ASoC: fsl_sai: Add support for i.MX8MMShengjiu Wang
On i.MX8MM the max register is FSL_SAI_MCTL, which is different with previous platform, so add max_register in soc data to distinguish platforms. And add specific soc data for i.MX8MM Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1652688372-10274-2-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: fsl_sai: store full version instead of major/minorSascha Hauer
The driver tests for the hardware revision being newer than 3.1 with (sai->verid.major >= 3 && sai->verid.minor >= 1). The result is obviously wrong for hardware revision 4.0. Fix this by storing the full version in a single variable and comparing to that one. No practical change at the moment as there is no 4.0 ip version currently. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220302083428.3804687-5-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-03-07ASoC: fsl_sai: Drop unnecessary definesSascha Hauer
The fsl_sai driver has FSL_FMT_TRANSMITTER and FSL_FMT_RECEIVER defines which are used in a single function only then are then only translated into a bool 'tx' variable. Drop the defines and pass the boolean value directly to fsl_sai_set_dai_sysclk_tr(). No functional change. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220302083428.3804687-2-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2022-02-08ASoC: fsl_sai: Enable combine mode softSascha Hauer
The fsl_sai driver calculates the number of pins used and enables multiple channels if necessary. This means the SAI expects data in one FIFO per pin. The SDMA engine only services a single FIFO, so multi pin support doesn't work at all. This patch enables the software combine mode in chips that support it. With this the SAI presents only a single FIFO to the outside and distributes the data into the different FIFOs internally. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Link: https://lore.kernel.org/r/20220111081518.982437-1-s.hauer@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-22ASoC: fsl_sai: Update to modern clocking terminologyMark Brown
As part of moving to remove the old style defines for the bus clocks update the fsl_sai driver to use more modern terminology for clocking. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210921213542.31688-6-broonie@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org>
2021-03-10ASoC: fsl_sai: Add pm qos cpu latency supportShengjiu Wang
On SoCs such as i.MX7ULP, cpuidle has some levels which may disable system/bus clocks, so need to add pm_qos to prevent cpuidle from entering low level idles and make sure system/bus clocks are enabled when sai is active. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1613983220-5373-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-19ASoC: fsl_sai: Correct the clock source for mclk0Shengjiu Wang
On VF610, mclk0 = bus_clk; On i.MX6SX/6UL/6ULL/7D, mclk0 = mclk1; On i.MX7ULP, mclk0 = bus_clk; On i.MX8QM/8QXP, mclk0 = bus_clk; On i.MX8MQ/8MN/8MM/8MP, mclk0 = bus_clk; So add variable mclk0_is_mclk1 in fsl_sai_soc_data to distinguish these platforms. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/1605768038-4582-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-10-09Merge remote-tracking branch 'asoc/for-5.10' into asoc-nextMark Brown
2020-09-25ASoC: fsl_sai: Instantiate snd_soc_dai_driverShengjiu Wang
Instantiate snd_soc_dai_driver for independent symmetric control. Otherwise the symmetric setting may be overwritten by other instance. Fixes: 08fdf65e37d5 ("ASoC: fsl_sai: Add asynchronous mode support") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://lore.kernel.org/r/1600424760-32071-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-09-17ASoC: fsl_sai: Add fsl_sai_check_version functionShengjiu Wang
fsl_sai_check_version can help to parse the version info in VERID and PARAM registers. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1600323079-5317-3-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-09-17ASoC: fsl_sai: Add new added registers and new bit definitionShengjiu Wang
On i.MX8MQ/i.MX8MN/i.MX8MM platform, the sai IP is upgraded. There are some new registers and new bit definition. This patch is to complete the register list. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1600323079-5317-2-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-09-03ASoC: fsl_sai: Set SAI Channel Mode to Output ModeShengjiu Wang
Transmit data pins will output zero when slots are masked or channels are disabled. In CHMOD TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled. When data pins are tri-stated, there is noise on some channels when FS clock value is high and data is read while fsclk is transitioning from high to low. Signed-off-by: Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/1599112427-22038-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-09-03ASoC: fsl_sai: Support multiple data channel enable bitsShengjiu Wang
One data channel is one data line. From imx7ulp, the SAI IP is enhanced to support multiple data channels. If there is only two channels input and slots is 2, then enable one data channel is enough for data transfer. So enable the TCE/RCE and transmit/receive mask register according to the input channels and slots configuration. Move the data channel enablement from startup() to hw_params(). Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/1598958068-10552-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-07-31ASoC: fsl_sai: Fix value of FSL_SAI_CR1_RFW_MASKShengjiu Wang
The fifo_depth is 64 on i.MX8QM/i.MX8QXP, 128 on i.MX8MQ, 16 on i.MX7ULP. Original FSL_SAI_CR1_RFW_MASK value 0x1F is not suitable for these platform, the FIFO watermark mask should be updated according to the fifo_depth. Fixes: a860fac42097 ("ASoC: fsl_sai: Add support for imx7ulp/imx8mq") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/1596176895-28724-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-09-17ASoC: fsl_sai: Fix noise when using EDMAMihai Serban
EDMA requires the period size to be multiple of maxburst. Otherwise the remaining bytes are not transferred and thus noise is produced. We can handle this issue by adding a constraint on SNDRV_PCM_HW_PARAM_PERIOD_SIZE to be multiple of tx/rx maxburst value. Signed-off-by: Mihai Serban <mihai.serban@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190913192807.8423-2-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-09-13ASoC: fsl_sai: Implement set_bclk_ratioViorel Suman
This is to allow machine drivers to set a certain bitclk rate which might not be exactly rate * frame size. Cc: NXP Linux Team <linux-imx@nxp.com> Signed-off-by: Viorel Suman <viorel.suman@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190830215910.31590-1-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-07ASoC: fsl_sai: Add support for SAI new versionDaniel Baluta
New IP version introduces Version ID and Parameter registers and optionally added Timestamp feature. VERID and PARAM registers are placed at the top of registers address space and some registers are shifted according to the following table: Tx/Rx data registers and Tx/Rx FIFO registers keep their addresses, all other registers are shifted by 8. SAI Memory map is described in chapter 13.10.4.1.1 I2S Memory map of the Reference Manual [1]. In order to make as less changes as possible we attach an offset to each register offset to each changed register definition. The offset is read from each board private data. [1]https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMX8MDQLQRM.pdf?__gda__=1563728701_38bea7f0f726472cc675cb141b91bec7&fileExt=.pdf Signed-off-by: Mihai Serban <mihai.serban@nxp.com> [initial coding in the NXP internal tree] Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> [bugfixing and cleanups] Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> [adapted to linux-next] Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190806151214.6783-4-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-07ASoC: fsl_sai: Update Tx/Rx channel enable maskDaniel Baluta
Tx channel enable (TCE) / Rx channel enable (RCE) bits enable corresponding data channel for Tx/Rx operation. Because SAI supports up the 8 channels TCE/RCE occupy up the 8 bits inside TCR3/RCR3 registers we need to extend the mask to reflect this. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190806151214.6783-3-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-07ASoC: fsl_sai: Add registers definition for multiple datalinesDaniel Baluta
SAI IP supports up to 8 data lines. The configuration of supported number of data lines is decided at SoC integration time. This patch adds definitions for all related data TX/RX registers: * TDR0..7, Transmit data register * TFR0..7, Transmit FIFO register * RDR0..7, Receive data register * RFR0..7, Receive FIFO register Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190806151214.6783-2-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-07-22ASoC: fsl_sai: derive TX FIFO watermark from FIFO depthLucas Stach
The DMA request schould be triggered as soon as the FIFO has space for another burst. As different versions of the SAI block have different FIFO sizes, the watrmark level needs to be derived from version specific data. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Angus Ainslie <angus@akkea.ca> Reviewed-by: Angus Ainslie <angus@akkea.ca> Link: https://lore.kernel.org/r/20190717105635.18514-3-l.stach@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2019-07-22ASoC: fsl_sai: add of_match dataLucas Stach
New revisions of the SAI IP block have even more differences that need be taken into account by the driver. To avoid sprinking compatible checks all over the driver move the current differences into of_match_data. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Tested-by: Angus Ainslie <angus@akkea.ca> Reviewed-by: Angus Ainslie <angus@akkea.ca> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Link: https://lore.kernel.org/r/20190717105635.18514-2-l.stach@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2018-05-03ASoC: fsl_sai: Switch to SPDX identifierFabio Estevam
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-11-25ASoC: fsl_sai: add tdm slots operation supportZidan Wang
Add tdm slots operation support. If tdm slots and slot width have been configured in machine driver, we should use these values. Otherwise, using relevant channels and word length to set slots and slot width. SAI will generate BCLK depends on sample rate, slots and slot width. And there may be unused BCLK cycles before each LRCLK transition. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-30Merge remote-tracking branches 'asoc/topic/fsi', 'asoc/topic/fsl', ↵Mark Brown
'asoc/topic/fsl-asrc', 'asoc/topic/fsl-card' and 'asoc/topic/fsl-sai' into asoc-next
2015-08-12ASoC: fsl: fix typos for sound/soc/fsl/*Xiubo Li
There are too much noise about the typos for fsl's drivers. So I fix all the typos here in this patch in almost every file I touched. Signed-off-by: Xiubo Li <lixiubo@cmss.chinamobile.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-11ASoC: fsl-sai: add 32 bit word length supportZidan Wang
Add 32 bit word length support. There are no code changes required in the SAI driver since it has already wirten the word width to the corresponding register. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2015-05-12ASoC: fsl_sai: add sai master mode supportZidan Wang
When sai works on master mode, set its bit clock and frame clock. SAI has 4 MCLK source, bus clock, MCLK1, MCLK2 and MCLK3. fsl_sai_set_bclk will select proper MCLK source, then calculate and set the bit clock divider. After fsl_sai_set_bclk, enable the selected mclk in hw_params(), and add hw_free() to disable the mclk. Signed-off-by: Zidan Wang <zidan.wang@freescale.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-09-01ASoC: fsl-sai: using 'lsb-first' property instead of 'big-endian-data'.Xiubo Li
The 'big-endian-data' property is originally used to indicate whether the LSB firstly or MSB firstly will be transmitted to the CODEC or received from the CODEC, and there has nothing relation to the memory data. Generally, if the audio data in big endian format, which will be using the bytes reversion, Here this can only be used to bits reversion. So using the 'lsb-first' instead of 'big-endian-data' can make the code to be readable easier and more easy to understand what this property is used to do. This property used for configuring whether the LSB or the MSB is transmitted first for the fifo data. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2014-09-01Merge branch 'topic/fsl' of ↵Mark Brown
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into asoc-fsl-sai
2014-08-27ASoC: fsl-sai: Convert to use regmap framework's endianness method.Xiubo Li
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-08-16ASoC: fsl_sai: Add asynchronous mode supportNicolin Chen
SAI supports these operation modes: 1) asynchronous mode Both Tx and Rx are set to be asynchronous. 2) synchronous mode (Rx sync with Tx) Tx is set to be asynchronous, Rx is set to be synchronous. 3) synchronous mode (Tx sync with Rx) Rx is set to be asynchronous, Tx is set to be synchronous. 4) synchronous mode (Tx/Rx sync with another SAI's Tx) 5) synchronous mode (Tx/Rx sync with another SAI's Rx) * 4) and 5) are beyond this patch because they are related with another SAI. As the initial version of this SAI driver, it supported 2) as default while the others were totally missing. So this patch just adds supports for 1) and 3). Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
2014-08-16ASoC: fsl_sai: Initialize with software resetNicolin Chen
This patch adds software reset code in dai_probe() so as to make a true init by clearing SAI's internal logic, including the bit clock generation, status flags, and FIFO pointers. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
generated by cgit (git 2.34.1) at 2025-07-25 19:22:44 +0000