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Define regmap for PHY and PLL registers, the PHY and PLL
registers are accessed by AI interface in controller.
So that driver can use regcache to recover registers
after suspend and resume.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://patch.msgid.link/20241127030035.649219-2-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Below preamble error means wrong preamble of IEC958 received,
the channel order may be wrong at the moment.
FSL_XCVR_IRQ_PREAMBLE_MISMATCH
FSL_XCVR_IRQ_UNEXP_PRE_REC
FSL_XCVR_IRQ_M_W_PRE_MISMATCH
FSL_XCVR_IRQ_B_PRE_MISMATCH
All above errors may cause channel swap, to avoid such issues,
need to reset the DMAC path.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://patch.msgid.link/1728368873-31379-3-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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This enables the interrupt to be asserted when there
is a change in Capabilities data structure / Latency
request of the CMDC Status register.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://patch.msgid.link/1728368873-31379-2-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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On i.MX95, the XCVR uses a new PLL in the PHY, which is
General Purpose (GP) PLL. Add GP PLL configuration support
in the driver and add the 'pll_ver' flag to distinguish
different PLL on different platforms.
The XCVR also use PHY but limited for SPDIF only case
Add 'use_phy' flag to distinguish these platforms.
When there are 'pll8k' and 'pll11k' clock existing, the clock
source of 'phy_clk' can be changed for different sample rate
requirement.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Chancel Liu <chancel.liu@nxp.com>
Link: https://msgid.link/r/1716972002-2315-3-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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Add compatible string and specific soc data to support XCVR on i.MX93
platform. XCVR IP on i.MX93 is cut to SPDIF only by removing external
PHY.
Signed-off-by: Chancel Liu <chancel.liu@nxp.com>
Acked-by: Shengjiu Wang <shengjiu.wang@gmail.com>
Link: https://lore.kernel.org/r/20230104023953.2973362-3-chancel.liu@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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These counter registers are part of register list,
add them to complete the register map
- DMAC counter control registers
- Data path Timestamp counter register
- Data path bit counter register
- Data path bit count timestamp register
- Data path bit read timestamp register
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1666940627-7611-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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XCVR (Audio Transceiver) is a on-chip functional module found
on i.MX8MP. It support HDMI2.1 eARC, HDMI1.4 ARC and SPDIF.
Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
Link: https://lore.kernel.org/r/20201013121733.83684-2-viorel.suman@oss.nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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