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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-sswi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ACLINT Supervisor-level Software Interrupt Device
maintainers:
- Inochi Amaoto <inochiama@outlook.com>
description:
The SSWI device is a part of the ACLINT device. It provides
supervisor-level IPI functionality for a set of HARTs on a supported
platforms. It provides a register to set an IPI (SETSSIP) for each
HART connected to the SSWI device. See draft specification
https://github.com/riscvarchive/riscv-aclint
Following variants of the SSWI ACLINT supported, using dedicated
compatible string
- THEAD C900
- MIPS P8700
properties:
compatible:
oneOf:
- items:
- enum:
- sophgo,sg2044-aclint-sswi
- const: thead,c900-aclint-sswi
- items:
- const: mips,p8700-aclint-sswi
reg:
maxItems: 1
"#interrupt-cells":
const: 0
interrupt-controller: true
interrupts-extended:
minItems: 1
maxItems: 4095
riscv,hart-indexes:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 4095
description:
A list of hart indexes that APLIC should use to address each hart
that is mentioned in the "interrupts-extended"
additionalProperties: false
required:
- compatible
- reg
- "#interrupt-cells"
- interrupt-controller
- interrupts-extended
allOf:
- if:
properties:
compatible:
contains:
const: mips,p8700-aclint-sswi
then:
required:
- riscv,hart-indexes
else:
properties:
riscv,hart-indexes: false
examples:
- |
//Example 1
interrupt-controller@94000000 {
compatible = "sophgo,sg2044-aclint-sswi", "thead,c900-aclint-sswi";
reg = <0x94000000 0x00004000>;
#interrupt-cells = <0>;
interrupt-controller;
interrupts-extended = <&cpu1intc 1>,
<&cpu2intc 1>,
<&cpu3intc 1>,
<&cpu4intc 1>;
};
- |
//Example 2
interrupt-controller@94000000 {
compatible = "mips,p8700-aclint-sswi";
reg = <0x94000000 0x00004000>;
#interrupt-cells = <0>;
interrupt-controller;
interrupts-extended = <&cpu1intc 1>,
<&cpu2intc 1>,
<&cpu3intc 1>,
<&cpu4intc 1>;
riscv,hart-indexes = <0x0 0x1 0x10 0x11>;
};
...
|
