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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/xlnx,intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Interrupt Controller
maintainers:
- Michal Simek <michal.simek@amd.com>
description:
The controller is a soft IP core that is configured at build time for the
number of interrupts and the type of each interrupt. These details cannot
be changed at run time.
properties:
compatible:
const: xlnx,xps-intc-1.00.a
reg:
maxItems: 1
clocks:
maxItems: 1
power-domains:
maxItems: 1
resets:
maxItems: 1
"#interrupt-cells":
const: 2
description:
Specifies the number of cells needed to encode an interrupt source.
The value shall be a minimum of 1. The Xilinx device trees typically
use 2 but the 2nd value is not used.
interrupt-controller: true
interrupts:
maxItems: 1
description:
Specifies the interrupt of the parent controller from which it is chained.
xlnx,kind-of-intr:
$ref: /schemas/types.yaml#/definitions/uint32
description:
A 32 bit value specifying the interrupt type for each possible interrupt
(1 = edge, 0 = level). The interrupt type typically comes in thru
the device tree node of the interrupt generating device, but in this case
the interrupt type is determined by the interrupt controller based on how
it was implemented.
xlnx,num-intr-inputs:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 32
description:
Specifies the number of interrupts supported by the specific
implementation of the controller.
required:
- reg
- "#interrupt-cells"
- interrupt-controller
- xlnx,kind-of-intr
- xlnx,num-intr-inputs
additionalProperties: false
examples:
- |
interrupt-controller@41800000 {
compatible = "xlnx,xps-intc-1.00.a";
reg = <0x41800000 0x10000>;
#interrupt-cells = <2>;
interrupt-controller;
xlnx,kind-of-intr = <0x1>;
xlnx,num-intr-inputs = <1>;
};
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