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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr)
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <riscv/sophgo/cv180x.dtsi>
#include <riscv/sophgo/cv181x.dtsi>
/ {
compatible = "sophgo,sg2000";
interrupt-parent = <&gic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
i-cache-size = <32768>;
d-cache-size = <32768>;
next-level-cache = <&l2>;
};
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x20000>;
};
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>; /* 512MiB */
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
cpu_on = <0xc4000003>;
cpu_off = <0x84000002>;
};
soc {
gic: interrupt-controller@1f01000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x01f01000 0x1000>,
<0x01f02000 0x2000>;
};
pinctrl: pinctrl@3001000 {
compatible = "sophgo,sg2000-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
};
clk: clock-controller@3002000 {
compatible = "sophgo,sg2000-clk";
reg = <0x03002000 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
always-on;
clock-frequency = <25000000>;
};
};
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