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/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (C) 2025 NVIDIA CORPORATION. All rights reserved. */
#ifndef MEMORY_TEGRA_TEGRA264_BWMGR_H
#define MEMORY_TEGRA_TEGRA264_BWMGR_H
#define TEGRA264_BWMGR_ICC_PRIMARY 1
#define TEGRA264_BWMGR_DEBUG 2
#define TEGRA264_BWMGR_CPU_CLUSTER0 3
#define TEGRA264_BWMGR_CPU_CLUSTER1 4
#define TEGRA264_BWMGR_CPU_CLUSTER2 5
#define TEGRA264_BWMGR_CPU_CLUSTER3 6
#define TEGRA264_BWMGR_CPU_CLUSTER4 7
#define TEGRA264_BWMGR_CPU_CLUSTER5 8
#define TEGRA264_BWMGR_CPU_CLUSTER6 9
#define TEGRA264_BWMGR_CACTMON 10
#define TEGRA264_BWMGR_DISPLAY 11
#define TEGRA264_BWMGR_VI 12
#define TEGRA264_BWMGR_APE 13
#define TEGRA264_BWMGR_VIFAL 14
#define TEGRA264_BWMGR_GPU 15
#define TEGRA264_BWMGR_EQOS 16
#define TEGRA264_BWMGR_PCIE_0 17
#define TEGRA264_BWMGR_PCIE_1 18
#define TEGRA264_BWMGR_PCIE_2 19
#define TEGRA264_BWMGR_PCIE_3 20
#define TEGRA264_BWMGR_PCIE_4 21
#define TEGRA264_BWMGR_PCIE_5 22
#define TEGRA264_BWMGR_SDMMC_1 23
#define TEGRA264_BWMGR_SDMMC_2 24
#define TEGRA264_BWMGR_NVDEC 25
#define TEGRA264_BWMGR_NVENC 26
#define TEGRA264_BWMGR_NVJPG_0 27
#define TEGRA264_BWMGR_NVJPG_1 28
#define TEGRA264_BWMGR_OFAA 29
#define TEGRA264_BWMGR_XUSB_HOST 30
#define TEGRA264_BWMGR_XUSB_DEV 31
#define TEGRA264_BWMGR_TSEC 32
#define TEGRA264_BWMGR_VIC 33
#define TEGRA264_BWMGR_APEDMA 34
#define TEGRA264_BWMGR_SE 35
#define TEGRA264_BWMGR_ISP 36
#define TEGRA264_BWMGR_HDA 37
#define TEGRA264_BWMGR_VI2FAL 38
#define TEGRA264_BWMGR_VI2 39
#define TEGRA264_BWMGR_RCE 40
#define TEGRA264_BWMGR_PVA 41
#define TEGRA264_BWMGR_NVPMODEL 42
#endif
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