blob: 172e48caa3a06274f0122d486ec757139772c048 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
|
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
*/
#ifndef VFIO_CDX_PRIVATE_H
#define VFIO_CDX_PRIVATE_H
#define VFIO_CDX_OFFSET_SHIFT 40
static inline u64 vfio_cdx_index_to_offset(u32 index)
{
return ((u64)(index) << VFIO_CDX_OFFSET_SHIFT);
}
struct vfio_cdx_irq {
u32 flags;
u32 count;
int irq_no;
struct eventfd_ctx *trigger;
char *name;
};
struct vfio_cdx_region {
u32 flags;
u32 type;
u64 addr;
resource_size_t size;
};
struct vfio_cdx_device {
struct vfio_device vdev;
struct vfio_cdx_region *regions;
struct vfio_cdx_irq *cdx_irqs;
u32 flags;
#define BME_SUPPORT BIT(0)
u32 msi_count;
u8 config_msi;
};
#ifdef CONFIG_GENERIC_MSI_IRQ
int vfio_cdx_set_irqs_ioctl(struct vfio_cdx_device *vdev,
u32 flags, unsigned int index,
unsigned int start, unsigned int count,
void *data);
void vfio_cdx_irqs_cleanup(struct vfio_cdx_device *vdev);
#else
static int vfio_cdx_set_irqs_ioctl(struct vfio_cdx_device *vdev,
u32 flags, unsigned int index,
unsigned int start, unsigned int count,
void *data)
{
return -EINVAL;
}
static void vfio_cdx_irqs_cleanup(struct vfio_cdx_device *vdev)
{
}
#endif
#endif /* VFIO_CDX_PRIVATE_H */
|
