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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
#ifndef _DT_BINDINGS_MEDIATEK_MT6373_AUXADC_H
#define _DT_BINDINGS_MEDIATEK_MT6373_AUXADC_H
/* ADC Channel Index */
#define MT6373_AUXADC_CHIP_TEMP 0
#define MT6373_AUXADC_VCORE_TEMP 1
#define MT6373_AUXADC_VPROC_TEMP 2
#define MT6373_AUXADC_VGPU_TEMP 3
#define MT6373_AUXADC_VIN1 4
#define MT6373_AUXADC_VIN2 5
#define MT6373_AUXADC_VIN3 6
#define MT6373_AUXADC_VIN4 7
#define MT6373_AUXADC_VIN5 8
#define MT6373_AUXADC_VIN6 9
#define MT6373_AUXADC_VIN7 10
#endif
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