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authorDan Williams <dan.j.williams@intel.com>2021-02-16 20:09:52 -0800
committerDan Williams <dan.j.williams@intel.com>2021-02-16 20:36:38 -0800
commitb39cb1052a5cf41bc12201ec1c0ddae5cb8be868 (patch)
tree13079eddea29561e8e20cd7f388e143ec97494ca /.clang-format
parent8adaf747c9f0b470aea1b0c88583aa0a344e1540 (diff)
cxl/mem: Register CXL memX devices
Create the /sys/bus/cxl hierarchy to enumerate: * Memory Devices (per-endpoint control devices) * Memory Address Space Devices (platform address ranges with interleaving, performance, and persistence attributes) * Memory Regions (active provisioned memory from an address space device that is in use as System RAM or delegated to libnvdimm as Persistent Memory regions). For now, only the per-endpoint control devices are registered on the 'cxl' bus. However, going forward it will provide a mechanism to coordinate cross-device interleave. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> (v2) Link: https://lore.kernel.org/r/20210217040958.1354670-4-ben.widawsky@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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