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authorJoseph Lo <josephl@nvidia.com>2013-07-03 17:50:39 +0800
committerStephen Warren <swarren@nvidia.com>2013-07-19 10:08:05 -0600
commit2f5aaa3d2703256d37ae75818c495783d4ad0543 (patch)
tree8a2a04aae10c5fc208e430e7fa4a457190fcfc03
parentac2527bfc21739b77d687df1bfc4e973103fef7b (diff)
ARM: tegra: set up the correct L2 data RAM latency for Cortex-A15
When there is a cluster power down cycle in suspend, we need to set up the correct L2 RAM data RAM latency to make L2 cache work correctly. This is only needed for cluster 0 and needs to be done in tegra_resume before the cache is enabled. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/reset-handler.S1
-rw-r--r--arch/arm/mach-tegra/sleep.S22
2 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 75285a3b816e..34614bdf3f5b 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -45,6 +45,7 @@
ENTRY(tegra_resume)
check_cpu_part_num 0xc09, r8, r9
bleq v7_invalidate_l1
+ blne tegra_init_l2_for_a15
cpu_id r0
tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 6d6600dcbfe2..8388113419fd 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -69,6 +69,28 @@ ENDPROC(tegra_disable_clean_inv_dcache)
#ifdef CONFIG_PM_SLEEP
/*
+ * tegra_init_l2_for_a15
+ *
+ * set up the correct L2 cache data RAM latency
+ */
+ENTRY(tegra_init_l2_for_a15)
+ mrc p15, 0, r0, c0, c0, 5
+ ubfx r0, r0, #8, #4
+ tst r0, #1 @ only need for cluster 0
+ bne _exit_init_l2_a15
+
+ mrc p15, 0x1, r0, c9, c0, 2
+ and r0, r0, #7
+ cmp r0, #2
+ bicne r0, r0, #7
+ orrne r0, r0, #2
+ mcrne p15, 0x1, r0, c9, c0, 2
+_exit_init_l2_a15:
+
+ mov pc, lr
+ENDPROC(tegra_init_l2_for_a15)
+
+/*
* tegra_sleep_cpu_finish(unsigned long v2p)
*
* enters suspend in LP2 by turning off the mmu and jumping to