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authorMarc Zyngier <marc.zyngier@arm.com>2016-09-23 14:23:43 +0100
committerMarc Zyngier <marc.zyngier@arm.com>2016-09-23 16:34:18 +0100
commit3d9cd95f90b2987ef95182a4340a9150e06c4253 (patch)
tree9bc50aeb7d0293b8c295139d0bb99094c7c9b500
parent6134993789b76d85102d68a286b8b82cb53b52cb (diff)
ARM: gic-v3: Work around definition of gic_write_bpr1
A new accessor for gic_write_bpr1 is added to arch_gicv3.h in 4.9, whilst the CP15 accessors are redifined in a separate branch. This leads to a horrible clash, where the new accessor ends up with a crap "asm volatile" definition. Work around this by carrying our own definition of gic_write_bpr1, creating a small conflict which will be obvious to resolve. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
-rw-r--r--arch/arm/include/asm/arch_gicv3.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h
index 996848efdaa9..1fee657d3827 100644
--- a/arch/arm/include/asm/arch_gicv3.h
+++ b/arch/arm/include/asm/arch_gicv3.h
@@ -216,6 +216,15 @@ static inline void gic_write_sre(u32 val)
isb();
}
+static inline void gic_write_bpr1(u32 val)
+{
+#if defined(__write_sysreg) && defined(ICC_BPR1)
+ write_sysreg(val, ICC_BPR1);
+#else
+ asm volatile("mcr " __stringify(ICC_BPR1) : : "r" (val));
+#endif
+}
+
/*
* Even in 32bit systems that use LPAE, there is no guarantee that the I/O
* interface provides true 64bit atomic accesses, so using strd/ldrd doesn't