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authorDoug Anderson <armlinux@m.disordat.com>2016-04-07 00:26:05 +0100
committerRussell King <rmk+kernel@armlinux.org.uk>2016-07-14 15:32:30 +0100
commit416bcf21591850cd12066b2f11655695118e6908 (patch)
tree2ee82e2bc12a293114b7d07cdb99bc3c51b2ad7e
parent62c0f4a53447bc298c337713d2ede1e6bdec6fdf (diff)
ARM: 8559/1: errata: Workaround erratum A12 821420
This erratum has a very simple workaround (set a bit in a register), so let's apply it. Apparently the workaround's downside is a very slight power impact. Note that applying this errata fixes deadlocks that are easy to reproduce with real world applications. The arguments for why this needs to be in the kernel are similar to the arugments made in the patch "Workaround errata A12 818325/852422 A17 852423". Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--arch/arm/Kconfig10
-rw-r--r--arch/arm/mm/proc-v7.S5
2 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 39cd37f29aaf..ed275aa293e5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1200,6 +1200,16 @@ config ARM_ERRATA_818325_852422
Feature Register. This bit disables an optimisation applied to a
sequence of 2 instructions that use opposing condition codes.
+config ARM_ERRATA_821420
+ bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
+ depends on CPU_V7
+ help
+ This option enables the workaround for the 821420 Cortex-A12
+ (all revs) erratum. In very rare timing conditions, a sequence
+ of VMOV to Core registers instructions, for which the second
+ one is in the shadow of a branch or abort, can lead to a
+ deadlock when the VMOV instructions are issued out-of-order.
+
config ARM_ERRATA_852423
bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
depends on CPU_V7
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b20b02e0b727..eefc10ff8e7e 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -368,6 +368,11 @@ __ca12_errata:
orr r10, r10, #1 << 12 @ set bit #12
mcr p15, 0, r10, c15, c0, 1 @ write diagnostic register
#endif
+#ifdef CONFIG_ARM_ERRATA_821420
+ mrc p15, 0, r10, c15, c0, 2 @ read internal feature reg
+ orr r10, r10, #1 << 1 @ set bit #1
+ mcr p15, 0, r10, c15, c0, 2 @ write internal feature reg
+#endif
b __errata_finish
__ca17_errata: