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authorTudor Ambarus <tudor.ambarus@microchip.com>2019-12-03 14:50:01 +0000
committerMiquel Raynal <miquel.raynal@bootlin.com>2020-01-09 20:11:34 +0100
commit82de6a6fb67e16a30ec2f586b1f6976c2d7b4b62 (patch)
tree43879919e3508cfd3ac274f5eb90040a0d1f7842
parentde08b5ac10420db597cb24c41b4d8d06cce15ffd (diff)
mtd: spi-nor: Fix the writing of the Status Register on micron flashes
Micron flashes do not support 16 bit writes on the Status Register. According to micron datasheets, when using the Write Status Register (01h) command, the chip select should be driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. If CS is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. This fixes the lock operations on micron flashes. Reported-by: John Garry <john.garry@huawei.com> Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: John Garry <john.garry@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-rw-r--r--drivers/mtd/spi-nor/spi-nor.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index f4afe123e9dc..aeb3ad2dbfb8 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -4596,6 +4596,7 @@ static void sst_set_default_init(struct spi_nor *nor)
static void st_micron_set_default_init(struct spi_nor *nor)
{
nor->flags |= SNOR_F_HAS_LOCK;
+ nor->flags &= ~SNOR_F_HAS_16BIT_SR;
nor->params.quad_enable = NULL;
nor->params.set_4byte = st_micron_set_4byte;
}