diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-07-06 11:38:59 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-07-06 11:38:59 -0700 |
| commit | ac7b75966c9c86426b55fe1c50ae148aa4571075 (patch) | |
| tree | cf57426162eb8ccf60f0452fc23a4b7d7c7175d5 | |
| parent | 4f5dfdd29065a0d1d0e61d9744e14d1d852518be (diff) | |
| parent | 3fa53ec2ed885b0aec3f0472e3b4a8a6f1cd748c (diff) | |
Merge tag 'pinctrl-v4.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the big bulk of pin control changes for the v4.13 series:
Core:
- The documentation is moved over to RST.
- We now have agreed bindings for enabling input and output buffers
without actually enabling input and/or output on a pin. We are
chiseling out some details of pin control electronics.
New drivers:
- ZTE ZX
- Renesas RZA1
- MIPS Ingenic JZ47xx: also switch over existing drivers in the tree
to use this pin controller and consolidate earlier spread out code.
- Microschip MCP23S08: this driver is migrated from the GPIO
subsystem and totally rewritten to use proper pin control. All
users are switched over.
New subdrivers:
- Renesas R8A7743 and R8A7745.
- Allwinner Sunxi A83T R_PIO.
- Marvell MVEBU Armada CP110 and AP806.
- Intel Cannon Lake PCH.
- Qualcomm IPQ8074.
Notable improvements:
- IRQ support on the Marvell MVEBU Armada 37xx.
- Meson driver supports HDMI CEC, AO, I2S, SPDIF and PWM.
- Rockchip driver now supports iomux-route switching for RK3228,
RK3328 and RK3399.
- Rockchip A10 and A20 are merged into a single driver.
- STM32 has improved GPIO support.
- Samsung Exynos drivers are split per ARMv7 and ARMv8.
- Marvell MVEBU is converted to use regmap for register access.
Maintenance:
- Several Renesas SH-PFC refactorings and updates.
- Serious code size cut for Mediatek MT7623.
- Misc janitorial and MAINTAINERS fixes"
* tag 'pinctrl-v4.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (137 commits)
pinctrl: samsung: Remove bogus irq_[un]mask from resource management
pinctrl: rza1: make structures rza1_gpiochip_template and rza1_pinmux_ops static
pinctrl: rza1: Remove unneeded wrong check for wrong variable
pinctrl: qcom: Add ipq8074 pinctrl driver
pinctrl: freescale: imx7d: make of_device_ids const.
pinctrl: DT: extend the pinmux property to support integers array
pinctrl: generic: Add output-enable property
pinctrl: armada-37xx: Fix number of pin in sdio_sb
pinctrl: armada-37xx: Fix uart2 group selection register mask
pinctrl: bcm2835: Avoid warning from __irq_do_set_handler
pinctrl: sh-pfc: r8a7795: Add PWM support
MAINTAINERS: Add Qualcomm pinctrl drivers section
arm: dts: dt-bindings: Add Renesas RZ/A1 pinctrl header
dt-bindings: pinctrl: Add RZ/A1 bindings doc
pinctrl: Renesas RZ/A1 pin and gpio controller
pinctrl: sh-pfc: r8a7792: Add SCIF1 and SCIF2 pin groups
pinctrl.txt: move it to the driver-api book
pinctrl: ingenic: checking for NULL instead of IS_ERR()
pinctrl: uniphier: fix WARN_ON() of pingroups dump on LD20
pinctrl: uniphier: fix WARN_ON() of pingroups dump on LD11
...
123 files changed, 14159 insertions, 8629 deletions
diff --git a/Documentation/devicetree/bindings/gpio/ingenic,gpio.txt b/Documentation/devicetree/bindings/gpio/ingenic,gpio.txt new file mode 100644 index 000000000000..7988aeb725f4 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/ingenic,gpio.txt @@ -0,0 +1,46 @@ +Ingenic jz47xx GPIO controller + +That the Ingenic GPIO driver node must be a sub-node of the Ingenic pinctrl +driver node. + +Required properties: +-------------------- + + - compatible: Must contain one of: + - "ingenic,jz4740-gpio" + - "ingenic,jz4770-gpio" + - "ingenic,jz4780-gpio" + - reg: The GPIO bank number. + - interrupt-controller: Marks the device node as an interrupt controller. + - interrupts: Interrupt specifier for the controllers interrupt. + - #interrupt-cells: Should be 2. Refer to + ../interrupt-controller/interrupts.txt for more details. + - gpio-controller: Marks the device node as a GPIO controller. + - #gpio-cells: Should be 2. The first cell is the GPIO number and the second + cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the + GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. + - gpio-ranges: Range of pins managed by the GPIO controller. Refer to + 'gpio.txt' in this directory for more details. + +Example: +-------- + +&pinctrl { + #address-cells = <1>; + #size-cells = <0>; + + gpa: gpio@0 { + compatible = "ingenic,jz4740-gpio"; + reg = <0>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <28>; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt index b53224473672..6f2ec9af0de2 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt @@ -20,8 +20,10 @@ Required properties: "allwinner,sun9i-a80-pinctrl" "allwinner,sun9i-a80-r-pinctrl" "allwinner,sun8i-a83t-pinctrl" + "allwinner,sun8i-a83t-r-pinctrl" "allwinner,sun8i-h3-pinctrl" "allwinner,sun8i-h3-r-pinctrl" + "allwinner,sun8i-r40-pinctrl" "allwinner,sun50i-a64-pinctrl" "allwinner,sun50i-a64-r-pinctrl" "allwinner,sun50i-h5-pinctrl" diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt new file mode 100644 index 000000000000..ca313a7aeaff --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt @@ -0,0 +1,41 @@ +Ingenic jz47xx pin controller + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +For the jz47xx SoCs, pin control is tightly bound with GPIO ports. All pins may +be used as GPIOs, multiplexed device functions are configured within the +GPIO port configuration registers and it is typical to refer to pins using the +naming scheme "PxN" where x is a character identifying the GPIO port with +which the pin is associated and N is an integer from 0 to 31 identifying the +pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and +PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to +PD, for a total of 128 pins. The jz4780 contains 6 GPIO ports, PA to PF, for a +total of 192 pins. + + +Required properties: +-------------------- + + - compatible: One of: + - "ingenic,jz4740-pinctrl" + - "ingenic,jz4770-pinctrl" + - "ingenic,jz4780-pinctrl" + - reg: Address range of the pinctrl registers. + + +GPIO sub-nodes +-------------- + +The pinctrl node can have optional sub-nodes for the Ingenic GPIO driver; +please refer to ../gpio/ingenic,gpio.txt. + + +Example: +-------- + +pinctrl: pin-controller@10010000 { + compatible = "ingenic,jz4740-pinctrl"; + reg = <0x10010000 0x400>; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt index f01d154090da..62d0f33fa65e 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt @@ -204,21 +204,22 @@ each single pin the number of required sub-nodes containing "pin" and maintain. For cases like this, the pin controller driver may use the pinmux helper -property, where the pin identifier is packed with mux configuration settings -in a single integer. +property, where the pin identifier is provided with mux configuration settings +in a pinmux group. A pinmux group consists of the pin identifier and mux +settings represented as a single integer or an array of integers. -The pinmux property accepts an array of integers, each of them describing +The pinmux property accepts an array of pinmux groups, each of them describing a single pin multiplexing configuration. pincontroller { state_0_node_a { - pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ...; + pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...; }; }; Each individual pin controller driver bindings documentation shall specify -how those values (pin IDs and pin multiplexing configuration) are defined and -assembled together. +how pin IDs and pin multiplexing configuration are defined and assembled +together in a pinmux group. == Generic pin configuration node content == @@ -251,14 +252,20 @@ drive-push-pull - drive actively high and low drive-open-drain - drive with open drain drive-open-source - drive with open source drive-strength - sink or source at most X mA -input-enable - enable input on pin (no effect on output) -input-disable - disable input on pin (no effect on output) +input-enable - enable input on pin (no effect on output, such as + enabling an input buffer) +input-disable - disable input on pin (no effect on output, such as + disabling an input buffer) input-schmitt-enable - enable schmitt-trigger mode input-schmitt-disable - disable schmitt-trigger mode input-debounce - debounce mode with debound time X power-source - select between different power supplies low-power-enable - enable low power mode low-power-disable - disable low power mode +output-disable - disable output on a pin (such as disable an output + buffer) +output-enable - enable output on a pin without actively driving it + (such as enabling an output buffer) output-low - set the pin to output mode with low level output-high - set the pin to output mode with high level slew-rate - set the slew rate @@ -300,7 +307,7 @@ arguments are described below. - pinmux takes a list of pin IDs and mux settings as required argument. The specific bindings for the hardware defines: - How pin IDs and mux settings are defined and assembled together in a single - integer. + integer or an array of integers. - bias-pull-up, -down and -pin-default take as optional argument on hardware supporting it the pull strength in Ohm. bias-disable will disable the pull. diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt new file mode 100644 index 000000000000..e219849b21ca --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt @@ -0,0 +1,85 @@ +* ZTE ZX Pin Controller + +The pin controller on ZTE ZX platforms is kinda of hybrid. It consists of +a main controller and an auxiliary one. For example, on ZX296718 SoC, the +main controller is TOP_PMM and the auxiliary one is AON_IOCFG. Both +controllers work together to control pin multiplexing and configuration in +the way illustrated as below. + + + GMII_RXD3 ---+ + | + DVI1_HS ---+----------------------------- GMII_RXD3 (TOP pin) + | + BGPIO16 ---+ ^ + | pinconf + ^ | + | pinmux | + | | + + TOP_PMM (main) AON_IOCFG (aux) + + | | | + | pinmux | | + | pinmux v | + v | pinconf + KEY_ROW2 ---+ v + PORT1_LCD_TE ---+ | + | AGPIO10 ---+------ KEY_ROW2 (AON pin) + I2S0_DOUT3 ---+ | + |-----------------------+ + PWM_OUT3 ---+ + | + VGA_VS1 ---+ + + +For most of pins like GMII_RXD3 in the figure, the pinmux function is +controlled by TOP_PMM block only, and this type of pins are meant by term +'TOP pins'. For pins like KEY_ROW2, the pinmux is controlled by both +TOP_PMM and AON_IOCFG blocks, as the available multiplexing functions for +the pin spread in both controllers. This type of pins are called 'AON pins'. +Though pinmux implementation is quite different, pinconf is same for both +types of pins. Both are controlled by auxiliary controller, i.e. AON_IOCFG +on ZX296718. + +Required properties: +- compatible: should be "zte,zx296718-pmm". +- reg: the register physical address and length. +- zte,auxiliary-controller: phandle to the auxiliary pin controller which + implements pinmux for AON pins and pinconf for all pins. + +The following pin configuration are supported. Please refer to +pinctrl-bindings.txt in this directory for more details of the common +pinctrl bindings used by client devices. + +- bias-pull-up +- bias-pull-down +- drive-strength +- input-enable +- slew-rate + +Examples: + +iocfg: pin-controller@119000 { + compatible = "zte,zx296718-iocfg"; + reg = <0x119000 0x1000>; +}; + +pmm: pin-controller@1462000 { + compatible = "zte,zx296718-pmm"; + reg = <0x1462000 0x1000>; + zte,auxiliary-controller = <&iocfg>; +}; + +&pmm { + vga_pins: vga { + pins = "KEY_COL1", "KEY_COL2", "KEY_ROW1", "KEY_ROW2"; + function = "VGA"; + }; +}; + +&vga { + pinctrl-names = "default"; + pinctrl-0 = <&vga_pins>; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt new file mode 100644 index 000000000000..407b9443629d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt @@ -0,0 +1,172 @@ +Qualcomm Technologies, Inc. IPQ8074 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +IPQ8074 platform. + +- compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,ipq8074-pinctrl" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the base address and size of the TLMM register space. + +- interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: <none> + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/interrupt-controller/irq.h> + +- gpio-controller: + Usage: required + Value type: <none> + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/gpio/gpio.h> + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: <string-array> + Definition: List of gpio pins affected by the properties specified in + this subnode. Valid pins are: + gpio0-gpio69 + +- function: + Usage: required + Value type: <string> + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + atest_char, atest_char0, atest_char1, atest_char2, + atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync, + audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync, + audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c, + blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart, + blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2, + blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0, + blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi, + blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1, + cxc0, cxc1, dbg_out, gcc_plltest, gcc_tlmm, gpio, ldo_en, + ldo_update, led0, led1, led2, mac0_sa0, mac0_sa1, mac1_sa0, + mac1_sa1, mac1_sa2, mac1_sa3, mac2_sa0, mac2_sa1, mdc, + mdio, pcie0_clk, pcie0_rst, pcie0_wake, pcie1_clk, + pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx, pcm_fsync, + pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0, pta1_1, + pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3, + qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, + qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, + qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, + qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, + qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, + qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, + qpic, rx0, rx1, rx2, sd_card, sd_write, tsens_max, wci2a, + wci2b, wci2c, wci2d + +- bias-disable: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as no pull. + +- bias-pull-down: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as pull down. + +- bias-pull-up: + Usage: optional + Value type: <none> + Definition: The specified pins should be configued as pull up. + +- output-high: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + high. + +- output-low: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + low. + +- drive-strength: + Usage: optional + Value type: <u32> + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq8074-pinctrl"; + reg = <0x1000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + uart2: uart2-default { + mux { + pins = "gpio23", "gpio24"; + function = "blsp4_uart1"; + }; + + rx { + pins = "gpio23"; + drive-strength = <4>; + bias-disable; + }; + + tx { + pins = "gpio24"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index 13df9498311a..645082f03259 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -13,6 +13,8 @@ Required Properties: - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller. - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller. - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. + - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller. + - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller. - "renesas,pfc-r8a7778": for R8A7778 (R-Mobile M1) compatible pin-controller. - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt new file mode 100644 index 000000000000..43e21474528a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt @@ -0,0 +1,221 @@ +Renesas RZ/A1 combined Pin and GPIO controller + +The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller, +named "Ports" in the hardware reference manual. +Pin multiplexing and GPIO configuration is performed on a per-pin basis +writing configuration values to per-port register sets. +Each "port" features up to 16 pins, each of them configurable for GPIO +function (port mode) or in alternate function mode. +Up to 8 different alternate function modes exist for each single pin. + +Pin controller node +------------------- + +Required properties: + - compatible + this shall be "renesas,r7s72100-ports". + + - reg + address base and length of the memory area where the pin controller + hardware is mapped to. + +Example: +Pin controller node for RZ/A1H SoC (r7s72100) + +pinctrl: pin-controller@fcfe3000 { + compatible = "renesas,r7s72100-ports"; + + reg = <0xfcfe3000 0x4230>; +}; + +Sub-nodes +--------- + +The child nodes of the pin controller node describe a pin multiplexing +function or a GPIO controller alternatively. + +- Pin multiplexing sub-nodes: + A pin multiplexing sub-node describes how to configure a set of + (or a single) pin in some desired alternate function mode. + A single sub-node may define several pin configurations. + A few alternate function require special pin configuration flags to be + supplied along with the alternate function configuration number. + The hardware reference manual specifies when a pin function requires + "software IO driven" mode to be specified. To do so use the generic + properties from the <include/linux/pinctrl/pinconf_generic.h> header file + to instruct the pin controller to perform the desired pin configuration + operation. + Please refer to pinctrl-bindings.txt to get to know more on generic + pin properties usage. + + The allowed generic formats for a pin multiplexing sub-node are the + following ones: + + node-1 { + pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ; + GENERIC_PINCONFIG; + }; + + node-2 { + sub-node-1 { + pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ; + GENERIC_PINCONFIG; + }; + + sub-node-2 { + pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ; + GENERIC_PINCONFIG; + }; + + ... + + sub-node-n { + pinmux = <PIN_ID_AND_MUX>, <PIN_ID_AND_MUX>, ... ; + GENERIC_PINCONFIG; + }; + }; + + Use the second format when pins part of the same logical group need to have + different generic pin configuration flags applied. + + Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle + of the most external one. + + Eg. + + client-1 { + ... + pinctrl-0 = <&node-1>; + ... + }; + + client-2 { + ... + pinctrl-0 = <&node-2>; + ... + }; + + Required properties: + - pinmux: + integer array representing pin number and pin multiplexing configuration. + When a pin has to be configured in alternate function mode, use this + property to identify the pin by its global index, and provide its + alternate function configuration number along with it. + When multiple pins are required to be configured as part of the same + alternate function they shall be specified as members of the same + argument list of a single "pinmux" property. + Helper macros to ease assembling the pin index from its position + (port where it sits on and pin number) and alternate function identifier + are provided by the pin controller header file at: + <include/dt-bindings/pinctrl/r7s72100-pinctrl.h> + Integers values in "pinmux" argument list are assembled as: + ((PORT * 16 + PIN) | MUX_FUNC << 16) + + Optional generic properties: + - input-enable: + enable input bufer for pins requiring software driven IO input + operations. + - output-high: + enable output buffer for pins requiring software driven IO output + operations. output-low can be used alternatively, as line value is + ignored by the driver. + + The hardware reference manual specifies when a pin has to be configured to + work in bi-directional mode and when the IO direction has to be specified + by software. Bi-directional pins are managed by the pin controller driver + internally, while software driven IO direction has to be explicitly + selected when multiple options are available. + + Example: + A serial communication interface with a TX output pin and an RX input pin. + + &pinctrl { + scif2_pins: serial2 { + pinmux = <RZA1_PINMUX(3, 0, 6)>, <RZA1_PINMUX(3, 2, 4)>; + }; + }; + + Pin #0 on port #3 is configured as alternate function #6. + Pin #2 on port #3 is configured as alternate function #4. + + Example 2: + I2c master: both SDA and SCL pins need bi-directional operations + + &pinctrl { + i2c2_pins: i2c2 { + pinmux = <RZA1_PINMUX(1, 4, 1)>, <RZA1_PINMUX(1, 5, 1)>; + }; + }; + + Pin #4 on port #1 is configured as alternate function #1. + Pin #5 on port #1 is configured as alternate function #1. + Both need to work in bi-directional mode, the driver manages this internally. + + Example 3: + Multi-function timer input and output compare pins. + Configure TIOC0A as software driven input and TIOC0B as software driven + output. + + &pinctrl { + tioc0_pins: tioc0 { + tioc0_input_pins { + pinumx = <RZA1_PINMUX(4, 0, 2)>; + input-enable; + }; + + tioc0_output_pins { + pinmux = <RZA1_PINMUX(4, 1, 1)>; + output-enable; + }; + }; + }; + + &tioc0 { + ... + pinctrl-0 = <&tioc0_pins>; + ... + }; + + Pin #0 on port #4 is configured as alternate function #2 with IO direction + specified by software as input. + Pin #1 on port #4 is configured as alternate function #1 with IO direction + specified by software as output. + +- GPIO controller sub-nodes: + Each port of the r7s72100 pin controller hardware is itself a GPIO controller. + Different SoCs have different numbers of available pins per port, but + generally speaking, each of them can be configured in GPIO ("port") mode + on this hardware. + Describe GPIO controllers using sub-nodes with the following properties. + + Required properties: + - gpio-controller + empty property as defined by the GPIO bindings documentation. + - #gpio-cells + number of cells required to identify and configure a GPIO. + Shall be 2. + - gpio-ranges + Describes a GPIO controller specifying its specific pin base, the pin + base in the global pin numbering space, and the number of controlled + pins, as defined by the GPIO bindings documentation. Refer to + Documentation/devicetree/bindings/gpio/gpio.txt file for a more detailed + description. + + Example: + A GPIO controller node, controlling 16 pins indexed from 0. + The GPIO controller base in the global pin indexing space is pin 48, thus + pins [0 - 15] on this controller map to pins [48 - 63] in the global pin + indexing space. + + port3: gpio-3 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + A device node willing to use pins controlled by this GPIO controller, shall + refer to it as follows: + + led1 { + gpios = <&port3 10 GPIO_ACTIVE_LOW>; + }; diff --git a/Documentation/driver-api/index.rst b/Documentation/driver-api/index.rst index 3cf1acebc4ee..7c94ab50afed 100644 --- a/Documentation/driver-api/index.rst +++ b/Documentation/driver-api/index.rst @@ -43,6 +43,7 @@ available subsections can be seen below. 80211/index uio-howto firmware/index + pinctl misc_devices .. only:: subproject and html diff --git a/Documentation/pinctrl.txt b/Documentation/driver-api/pinctl.rst index f2af35f6d6b2..48f15b4f9d3e 100644 --- a/Documentation/pinctrl.txt +++ b/Documentation/driver-api/pinctl.rst @@ -1,4 +1,7 @@ +=============================== PINCTRL (PIN CONTROL) subsystem +=============================== + This document outlines the pin control subsystem in Linux This subsystem deals with: @@ -33,7 +36,7 @@ When a PIN CONTROLLER is instantiated, it will register a descriptor to the pin control framework, and this descriptor contains an array of pin descriptors describing the pins handled by this specific pin controller. -Here is an example of a PGA (Pin Grid Array) chip seen from underneath: +Here is an example of a PGA (Pin Grid Array) chip seen from underneath:: A B C D E F G H @@ -54,39 +57,40 @@ Here is an example of a PGA (Pin Grid Array) chip seen from underneath: 1 o o o o o o o o To register a pin controller and name all the pins on this package we can do -this in our driver: - -#include <linux/pinctrl/pinctrl.h> - -const struct pinctrl_pin_desc foo_pins[] = { - PINCTRL_PIN(0, "A8"), - PINCTRL_PIN(1, "B8"), - PINCTRL_PIN(2, "C8"), - ... - PINCTRL_PIN(61, "F1"), - PINCTRL_PIN(62, "G1"), - PINCTRL_PIN(63, "H1"), -}; +this in our driver:: -static struct pinctrl_desc foo_desc = { - .name = "foo", - .pins = foo_pins, - .npins = ARRAY_SIZE(foo_pins), - .owner = THIS_MODULE, -}; + #include <linux/pinctrl/pinctrl.h> -int __init foo_probe(void) -{ - int error; + const struct pinctrl_pin_desc foo_pins[] = { + PINCTRL_PIN(0, "A8"), + PINCTRL_PIN(1, "B8"), + PINCTRL_PIN(2, "C8"), + ... + PINCTRL_PIN(61, "F1"), + PINCTRL_PIN(62, "G1"), + PINCTRL_PIN(63, "H1"), + }; + + static struct pinctrl_desc foo_desc = { + .name = "foo", + .pins = foo_pins, + .npins = ARRAY_SIZE(foo_pins), + .owner = THIS_MODULE, + }; + + int __init foo_probe(void) + { + int error; - struct pinctrl_dev *pctl; + struct pinctrl_dev *pctl; - error = pinctrl_register_and_init(&foo_desc, <PARENT>, NULL, &pctl); - if (error) - return error; + error = pinctrl_register_and_init(&foo_desc, <PARENT>, + NULL, &pctl); + if (error) + return error; - return pinctrl_enable(pctl); -} + return pinctrl_enable(pctl); + } To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and selected drivers, you need to select them from your machine's Kconfig entry, @@ -105,7 +109,7 @@ the pin controller. For a padring with 467 pads, as opposed to actual pins, I used an enumeration like this, walking around the edge of the chip, which seems to be industry -standard too (all these pads had names, too): +standard too (all these pads had names, too):: 0 ..... 104 @@ -128,64 +132,64 @@ on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins on { 24, 25 }. These two groups are presented to the pin control subsystem by implementing -some generic pinctrl_ops like this: - -#include <linux/pinctrl/pinctrl.h> - -struct foo_group { - const char *name; - const unsigned int *pins; - const unsigned num_pins; -}; - -static const unsigned int spi0_pins[] = { 0, 8, 16, 24 }; -static const unsigned int i2c0_pins[] = { 24, 25 }; - -static const struct foo_group foo_groups[] = { - { - .name = "spi0_grp", - .pins = spi0_pins, - .num_pins = ARRAY_SIZE(spi0_pins), - }, +some generic pinctrl_ops like this:: + + #include <linux/pinctrl/pinctrl.h> + + struct foo_group { + const char *name; + const unsigned int *pins; + const unsigned num_pins; + }; + + static const unsigned int spi0_pins[] = { 0, 8, 16, 24 }; + static const unsigned int i2c0_pins[] = { 24, 25 }; + + static const struct foo_group foo_groups[] = { + { + .name = "spi0_grp", + .pins = spi0_pins, + .num_pins = ARRAY_SIZE(spi0_pins), + }, + { + .name = "i2c0_grp", + .pins = i2c0_pins, + .num_pins = ARRAY_SIZE(i2c0_pins), + }, + }; + + + static int foo_get_groups_count(struct pinctrl_dev *pctldev) { - .name = "i2c0_grp", - .pins = i2c0_pins, - .num_pins = ARRAY_SIZE(i2c0_pins), - }, -}; - - -static int foo_get_groups_count(struct pinctrl_dev *pctldev) -{ - return ARRAY_SIZE(foo_groups); -} + return ARRAY_SIZE(foo_groups); + } -static const char *foo_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - return foo_groups[selector].name; -} + static const char *foo_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) + { + return foo_groups[selector].name; + } -static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - const unsigned **pins, - unsigned *num_pins) -{ - *pins = (unsigned *) foo_groups[selector].pins; - *num_pins = foo_groups[selector].num_pins; - return 0; -} + static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, + const unsigned **pins, + unsigned *num_pins) + { + *pins = (unsigned *) foo_groups[selector].pins; + *num_pins = foo_groups[selector].num_pins; + return 0; + } -static struct pinctrl_ops foo_pctrl_ops = { - .get_groups_count = foo_get_groups_count, - .get_group_name = foo_get_group_name, - .get_group_pins = foo_get_group_pins, -}; + static struct pinctrl_ops foo_pctrl_ops = { + .get_groups_count = foo_get_groups_count, + .get_group_name = foo_get_group_name, + .get_group_pins = foo_get_group_pins, + }; -static struct pinctrl_desc foo_desc = { - ... - .pctlops = &foo_pctrl_ops, -}; + static struct pinctrl_desc foo_desc = { + ... + .pctlops = &foo_pctrl_ops, + }; The pin control subsystem will call the .get_groups_count() function to determine the total number of legal selectors, then it will call the other functions @@ -213,62 +217,62 @@ The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP above, is entirely defined by the pin controller driver. The pin configuration driver implements callbacks for changing pin -configuration in the pin controller ops like this: +configuration in the pin controller ops like this:: -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinconf.h> -#include "platform_x_pindefs.h" + #include <linux/pinctrl/pinctrl.h> + #include <linux/pinctrl/pinconf.h> + #include "platform_x_pindefs.h" -static int foo_pin_config_get(struct pinctrl_dev *pctldev, - unsigned offset, - unsigned long *config) -{ - struct my_conftype conf; + static int foo_pin_config_get(struct pinctrl_dev *pctldev, + unsigned offset, + unsigned long *config) + { + struct my_conftype conf; - ... Find setting for pin @ offset ... + ... Find setting for pin @ offset ... - *config = (unsigned long) conf; -} + *config = (unsigned long) conf; + } -static int foo_pin_config_set(struct pinctrl_dev *pctldev, - unsigned offset, - unsigned long config) -{ - struct my_conftype *conf = (struct my_conftype *) config; + static int foo_pin_config_set(struct pinctrl_dev *pctldev, + unsigned offset, + unsigned long config) + { + struct my_conftype *conf = (struct my_conftype *) config; - switch (conf) { - case PLATFORM_X_PULL_UP: - ... + switch (conf) { + case PLATFORM_X_PULL_UP: + ... + } } } -} -static int foo_pin_config_group_get (struct pinctrl_dev *pctldev, - unsigned selector, - unsigned long *config) -{ - ... -} + static int foo_pin_config_group_get (struct pinctrl_dev *pctldev, + unsigned selector, + unsigned long *config) + { + ... + } -static int foo_pin_config_group_set (struct pinctrl_dev *pctldev, - unsigned selector, - unsigned long config) -{ - ... -} + static int foo_pin_config_group_set (struct pinctrl_dev *pctldev, + unsigned selector, + unsigned long config) + { + ... + } -static struct pinconf_ops foo_pconf_ops = { - .pin_config_get = foo_pin_config_get, - .pin_config_set = foo_pin_config_set, - .pin_config_group_get = foo_pin_config_group_get, - .pin_config_group_set = foo_pin_config_group_set, -}; + static struct pinconf_ops foo_pconf_ops = { + .pin_config_get = foo_pin_config_get, + .pin_config_set = foo_pin_config_set, + .pin_config_group_get = foo_pin_config_group_get, + .pin_config_group_set = foo_pin_config_group_set, + }; -/* Pin config operations are handled by some pin controller */ -static struct pinctrl_desc foo_desc = { - ... - .confops = &foo_pconf_ops, -}; + /* Pin config operations are handled by some pin controller */ + static struct pinctrl_desc foo_desc = { + ... + .confops = &foo_pconf_ops, + }; Since some controllers have special logic for handling entire groups of pins they can exploit the special whole-group pin control function. The @@ -296,35 +300,35 @@ controller handles control of a certain GPIO pin. Since a single pin controller may be muxing several GPIO ranges (typically SoCs that have one set of pins, but internally several GPIO silicon blocks, each modelled as a struct gpio_chip) any number of GPIO ranges can be added to a pin controller instance -like this: - -struct gpio_chip chip_a; -struct gpio_chip chip_b; - -static struct pinctrl_gpio_range gpio_range_a = { - .name = "chip a", - .id = 0, - .base = 32, - .pin_base = 32, - .npins = 16, - .gc = &chip_a; -}; - -static struct pinctrl_gpio_range gpio_range_b = { - .name = "chip b", - .id = 0, - .base = 48, - .pin_base = 64, - .npins = 8, - .gc = &chip_b; -}; - -{ - struct pinctrl_dev *pctl; - ... - pinctrl_add_gpio_range(pctl, &gpio_range_a); - pinctrl_add_gpio_range(pctl, &gpio_range_b); -} +like this:: + + struct gpio_chip chip_a; + struct gpio_chip chip_b; + + static struct pinctrl_gpio_range gpio_range_a = { + .name = "chip a", + .id = 0, + .base = 32, + .pin_base = 32, + .npins = 16, + .gc = &chip_a; + }; + + static struct pinctrl_gpio_range gpio_range_b = { + .name = "chip b", + .id = 0, + .base = 48, + .pin_base = 64, + .npins = 8, + .gc = &chip_b; + }; + + { + struct pinctrl_dev *pctl; + ... + pinctrl_add_gpio_range(pctl, &gpio_range_a); + pinctrl_add_gpio_range(pctl, &gpio_range_b); + } So this complex system has one pin controller handling two different GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and @@ -348,25 +352,26 @@ chip b: The above examples assume the mapping between the GPIOs and pins is linear. If the mapping is sparse or haphazard, an array of arbitrary pin -numbers can be encoded in the range like this: +numbers can be encoded in the range like this:: -static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 }; + static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 }; -static struct pinctrl_gpio_range gpio_range = { - .name = "chip", - .id = 0, - .base = 32, - .pins = &range_pins, - .npins = ARRAY_SIZE(range_pins), - .gc = &chip; -}; + static struct pinctrl_gpio_range gpio_range = { + .name = "chip", + .id = 0, + .base = 32, + .pins = &range_pins, + .npins = ARRAY_SIZE(range_pins), + .gc = &chip; + }; In this case the pin_base property will be ignored. If the name of a pin group is known, the pins and npins elements of the above structure can be initialised using the function pinctrl_get_group_pins(), e.g. for pin -group "foo": +group "foo":: -pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins); + pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, + &gpio_range.npins); When GPIO-specific functions in the pin control subsystem are called, these ranges will be used to look up the appropriate pin controller by inspecting @@ -405,7 +410,7 @@ we usually mean a way of soldering or wiring the package into an electronic system, even though the framework makes it possible to also change the function at runtime. -Here is an example of a PGA (Pin Grid Array) chip seen from underneath: +Here is an example of a PGA (Pin Grid Array) chip seen from underneath:: A B C D E F G H +---+ @@ -519,12 +524,12 @@ Definitions: In the example case we can define that this particular machine shall use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function fi2c0 group gi2c0, on the primary pin controller, we get mappings - like these: + like these:: - { - {"map-spi0", spi0, pinctrl0, fspi0, gspi0}, - {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0} - } + { + {"map-spi0", spi0, pinctrl0, fspi0, gspi0}, + {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0} + } Every map must be assigned a state name, pin controller, device and function. The group is not compulsory - if it is omitted the first group @@ -578,155 +583,155 @@ some certain registers to activate a certain mux setting for a certain pin. A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4 into some register named MUX to select a certain function with a certain -group of pins would work something like this: - -#include <linux/pinctrl/pinctrl.h> -#include <linux/pinctrl/pinmux.h> - -struct foo_group { - const char *name; - const unsigned int *pins; - const unsigned num_pins; -}; - -static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 }; -static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 }; -static const unsigned i2c0_pins[] = { 24, 25 }; -static const unsigned mmc0_1_pins[] = { 56, 57 }; -static const unsigned mmc0_2_pins[] = { 58, 59 }; -static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 }; - -static const struct foo_group foo_groups[] = { - { - .name = "spi0_0_grp", - .pins = spi0_0_pins, - .num_pins = ARRAY_SIZE(spi0_0_pins), - }, +group of pins would work something like this:: + + #include <linux/pinctrl/pinctrl.h> + #include <linux/pinctrl/pinmux.h> + + struct foo_group { + const char *name; + const unsigned int *pins; + const unsigned num_pins; + }; + + static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 }; + static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 }; + static const unsigned i2c0_pins[] = { 24, 25 }; + static const unsigned mmc0_1_pins[] = { 56, 57 }; + static const unsigned mmc0_2_pins[] = { 58, 59 }; + static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 }; + + static const struct foo_group foo_groups[] = { + { + .name = "spi0_0_grp", + .pins = spi0_0_pins, + .num_pins = ARRAY_SIZE(spi0_0_pins), + }, + { + .name = "spi0_1_grp", + .pins = spi0_1_pins, + .num_pins = ARRAY_SIZE(spi0_1_pins), + }, + { + .name = "i2c0_grp", + .pins = i2c0_pins, + .num_pins = ARRAY_SIZE(i2c0_pins), + }, + { + .name = "mmc0_1_grp", + .pins = mmc0_1_pins, + .num_pins = ARRAY_SIZE(mmc0_1_pins), + }, + { + .name = "mmc0_2_grp", + .pins = mmc0_2_pins, + .num_pins = ARRAY_SIZE(mmc0_2_pins), + }, + { + .name = "mmc0_3_grp", + .pins = mmc0_3_pins, + .num_pins = ARRAY_SIZE(mmc0_3_pins), + }, + }; + + + static int foo_get_groups_count(struct pinctrl_dev *pctldev) { - .name = "spi0_1_grp", - .pins = spi0_1_pins, - .num_pins = ARRAY_SIZE(spi0_1_pins), - }, - { - .name = "i2c0_grp", - .pins = i2c0_pins, - .num_pins = ARRAY_SIZE(i2c0_pins), - }, + return ARRAY_SIZE(foo_groups); + } + + static const char *foo_get_group_name(struct pinctrl_dev *pctldev, + unsigned selector) { - .name = "mmc0_1_grp", - .pins = mmc0_1_pins, - .num_pins = ARRAY_SIZE(mmc0_1_pins), - }, + return foo_groups[selector].name; + } + + static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, + unsigned ** const pins, + unsigned * const num_pins) { - .name = "mmc0_2_grp", - .pins = mmc0_2_pins, - .num_pins = ARRAY_SIZE(mmc0_2_pins), - }, + *pins = (unsigned *) foo_groups[selector].pins; + *num_pins = foo_groups[selector].num_pins; + return 0; + } + + static struct pinctrl_ops foo_pctrl_ops = { + .get_groups_count = foo_get_groups_count, + .get_group_name = foo_get_group_name, + .get_group_pins = foo_get_group_pins, + }; + + struct foo_pmx_func { + const char *name; + const char * const *groups; + const unsigned num_groups; + }; + + static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" }; + static const char * const i2c0_groups[] = { "i2c0_grp" }; + static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp", + "mmc0_3_grp" }; + + static const struct foo_pmx_func foo_functions[] = { + { + .name = "spi0", + .groups = spi0_groups, + .num_groups = ARRAY_SIZE(spi0_groups), + }, + { + .name = "i2c0", + .groups = i2c0_groups, + .num_groups = ARRAY_SIZE(i2c0_groups), + }, + { + .name = "mmc0", + .groups = mmc0_groups, + .num_groups = ARRAY_SIZE(mmc0_groups), + }, + }; + + static int foo_get_functions_count(struct pinctrl_dev *pctldev) { - .name = "mmc0_3_grp", - .pins = mmc0_3_pins, - .num_pins = ARRAY_SIZE(mmc0_3_pins), - }, -}; - - -static int foo_get_groups_count(struct pinctrl_dev *pctldev) -{ - return ARRAY_SIZE(foo_groups); -} - -static const char *foo_get_group_name(struct pinctrl_dev *pctldev, - unsigned selector) -{ - return foo_groups[selector].name; -} - -static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - unsigned ** const pins, - unsigned * const num_pins) -{ - *pins = (unsigned *) foo_groups[selector].pins; - *num_pins = foo_groups[selector].num_pins; - return 0; -} - -static struct pinctrl_ops foo_pctrl_ops = { - .get_groups_count = foo_get_groups_count, - .get_group_name = foo_get_group_name, - .get_group_pins = foo_get_group_pins, -}; - -struct foo_pmx_func { - const char *name; - const char * const *groups; - const unsigned num_groups; -}; - -static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" }; -static const char * const i2c0_groups[] = { "i2c0_grp" }; -static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp", - "mmc0_3_grp" }; - -static const struct foo_pmx_func foo_functions[] = { + return ARRAY_SIZE(foo_functions); + } + + static const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector) { - .name = "spi0", - .groups = spi0_groups, - .num_groups = ARRAY_SIZE(spi0_groups), - }, + return foo_functions[selector].name; + } + + static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector, + const char * const **groups, + unsigned * const num_groups) { - .name = "i2c0", - .groups = i2c0_groups, - .num_groups = ARRAY_SIZE(i2c0_groups), - }, + *groups = foo_functions[selector].groups; + *num_groups = foo_functions[selector].num_groups; + return 0; + } + + static int foo_set_mux(struct pinctrl_dev *pctldev, unsigned selector, + unsigned group) { - .name = "mmc0", - .groups = mmc0_groups, - .num_groups = ARRAY_SIZE(mmc0_groups), - }, -}; - -static int foo_get_functions_count(struct pinctrl_dev *pctldev) -{ - return ARRAY_SIZE(foo_functions); -} - -static const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector) -{ - return foo_functions[selector].name; -} - -static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector, - const char * const **groups, - unsigned * const num_groups) -{ - *groups = foo_functions[selector].groups; - *num_groups = foo_functions[selector].num_groups; - return 0; -} - -static int foo_set_mux(struct pinctrl_dev *pctldev, unsigned selector, - unsigned group) -{ - u8 regbit = (1 << selector + group); - - writeb((readb(MUX)|regbit), MUX) - return 0; -} - -static struct pinmux_ops foo_pmxops = { - .get_functions_count = foo_get_functions_count, - .get_function_name = foo_get_fname, - .get_function_groups = foo_get_groups, - .set_mux = foo_set_mux, - .strict = true, -}; - -/* Pinmux operations are handled by some pin controller */ -static struct pinctrl_desc foo_desc = { - ... - .pctlops = &foo_pctrl_ops, - .pmxops = &foo_pmxops, -}; + u8 regbit = (1 << selector + group); + + writeb((readb(MUX)|regbit), MUX) + return 0; + } + + static struct pinmux_ops foo_pmxops = { + .get_functions_count = foo_get_functions_count, + .get_function_name = foo_get_fname, + .get_function_groups = foo_get_groups, + .set_mux = foo_set_mux, + .strict = true, + }; + + /* Pinmux operations are handled by some pin controller */ + static struct pinctrl_desc foo_desc = { + ... + .pctlops = &foo_pctrl_ops, + .pmxops = &foo_pmxops, + }; In the example activating muxing 0 and 1 at the same time setting bits 0 and 1, uses one pin in common so they would collide. @@ -809,9 +814,9 @@ for a device. The GPIO portions of a pin and its relation to a certain pin controller configuration and muxing logic can be constructed in several ways. Here -are two examples: +are two examples:: -(A) + (A) pin config logic regs | +- SPI @@ -840,7 +845,9 @@ simultaneous access to the same pin from GPIO and pin multiplexing consumers on hardware of this type. The pinctrl driver should set this flag accordingly. -(B) +:: + + (B) pin config logic regs @@ -911,52 +918,55 @@ has to be handled by the <linux/gpio.h> interface. Instead view this as a certain pin config setting. Look in e.g. <linux/pinctrl/pinconf-generic.h> and you find this in the documentation: - PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument + PIN_CONFIG_OUTPUT: + this will configure the pin in output, use argument 1 to indicate high level, argument 0 to indicate low level. So it is perfectly possible to push a pin into "GPIO mode" and drive the line low as part of the usual pin control map. So for example your UART -driver may look like this: +driver may look like this:: -#include <linux/pinctrl/consumer.h> + #include <linux/pinctrl/consumer.h> -struct pinctrl *pinctrl; -struct pinctrl_state *pins_default; -struct pinctrl_state *pins_sleep; + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_sleep; -pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT); -pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP); + pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT); + pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP); -/* Normal mode */ -retval = pinctrl_select_state(pinctrl, pins_default); -/* Sleep mode */ -retval = pinctrl_select_state(pinctrl, pins_sleep); + /* Normal mode */ + retval = pinctrl_select_state(pinctrl, pins_default); + /* Sleep mode */ + retval = pinctrl_select_state(pinctrl, pins_sleep); And your machine configuration may look like this: -------------------------------------------------- -static unsigned long uart_default_mode[] = { - PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0), -}; - -static unsigned long uart_sleep_mode[] = { - PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0), -}; - -static struct pinctrl_map pinmap[] __initdata = { - PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo", - "u0_group", "u0"), - PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo", - "UART_TX_PIN", uart_default_mode), - PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo", - "u0_group", "gpio-mode"), - PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo", - "UART_TX_PIN", uart_sleep_mode), -}; - -foo_init(void) { - pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap)); -} +:: + + static unsigned long uart_default_mode[] = { + PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0), + }; + + static unsigned long uart_sleep_mode[] = { + PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0), + }; + + static struct pinctrl_map pinmap[] __initdata = { + PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo", + "u0_group", "u0"), + PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo", + "UART_TX_PIN", uart_default_mode), + PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo", + "u0_group", "gpio-mode"), + PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo", + "UART_TX_PIN", uart_sleep_mode), + }; + + foo_init(void) { + pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap)); + } Here the pins we want to control are in the "u0_group" and there is some function called "u0" that can be enabled on this group of pins, and then @@ -985,7 +995,7 @@ API. Board/machine configuration -================================== +=========================== Boards and machines define how a certain complete running system is put together, including how GPIOs and devices are muxed, how regulators are @@ -994,33 +1004,33 @@ part of this. A pin controller configuration for a machine looks pretty much like a simple regulator configuration, so for the example array above we want to enable i2c -and spi on the second function mapping: - -#include <linux/pinctrl/machine.h> - -static const struct pinctrl_map mapping[] __initconst = { - { - .dev_name = "foo-spi.0", - .name = PINCTRL_STATE_DEFAULT, - .type = PIN_MAP_TYPE_MUX_GROUP, - .ctrl_dev_name = "pinctrl-foo", - .data.mux.function = "spi0", - }, - { - .dev_name = "foo-i2c.0", - .name = PINCTRL_STATE_DEFAULT, - .type = PIN_MAP_TYPE_MUX_GROUP, - .ctrl_dev_name = "pinctrl-foo", - .data.mux.function = "i2c0", - }, - { - .dev_name = "foo-mmc.0", - .name = PINCTRL_STATE_DEFAULT, - .type = PIN_MAP_TYPE_MUX_GROUP, - .ctrl_dev_name = "pinctrl-foo", - .data.mux.function = "mmc0", - }, -}; +and spi on the second function mapping:: + + #include <linux/pinctrl/machine.h> + + static const struct pinctrl_map mapping[] __initconst = { + { + .dev_name = "foo-spi.0", + .name = PINCTRL_STATE_DEFAULT, + .type = PIN_MAP_TYPE_MUX_GROUP, + .ctrl_dev_name = "pinctrl-foo", + .data.mux.function = "spi0", + }, + { + .dev_name = "foo-i2c.0", + .name = PINCTRL_STATE_DEFAULT, + .type = PIN_MAP_TYPE_MUX_GROUP, + .ctrl_dev_name = "pinctrl-foo", + .data.mux.function = "i2c0", + }, + { + .dev_name = "foo-mmc.0", + .name = PINCTRL_STATE_DEFAULT, + .type = PIN_MAP_TYPE_MUX_GROUP, + .ctrl_dev_name = "pinctrl-foo", + .data.mux.function = "mmc0", + }, + }; The dev_name here matches to the unique device name that can be used to look up the device struct (just like with clockdev or regulators). The function name @@ -1029,76 +1039,81 @@ must match a function provided by the pinmux driver handling this pin range. As you can see we may have several pin controllers on the system and thus we need to specify which one of them contains the functions we wish to map. -You register this pinmux mapping to the pinmux subsystem by simply: +You register this pinmux mapping to the pinmux subsystem by simply:: ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping)); Since the above construct is pretty common there is a helper macro to make it even more compact which assumes you want to use pinctrl-foo and position -0 for mapping, for example: +0 for mapping, for example:: -static struct pinctrl_map mapping[] __initdata = { - PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"), -}; + static struct pinctrl_map mapping[] __initdata = { + PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, + "pinctrl-foo", NULL, "i2c0"), + }; The mapping table may also contain pin configuration entries. It's common for each pin/group to have a number of configuration entries that affect it, so the table entries for configuration reference an array of config parameters -and values. An example using the convenience macros is shown below: - -static unsigned long i2c_grp_configs[] = { - FOO_PIN_DRIVEN, - FOO_PIN_PULLUP, -}; - -static unsigned long i2c_pin_configs[] = { - FOO_OPEN_COLLECTOR, - FOO_SLEW_RATE_SLOW, -}; - -static struct pinctrl_map mapping[] __initdata = { - PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"), - PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs), - PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs), - PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs), -}; +and values. An example using the convenience macros is shown below:: + + static unsigned long i2c_grp_configs[] = { + FOO_PIN_DRIVEN, + FOO_PIN_PULLUP, + }; + + static unsigned long i2c_pin_configs[] = { + FOO_OPEN_COLLECTOR, + FOO_SLEW_RATE_SLOW, + }; + + static struct pinctrl_map mapping[] __initdata = { + PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, + "pinctrl-foo", "i2c0", "i2c0"), + PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, + "pinctrl-foo", "i2c0", i2c_grp_configs), + PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, + "pinctrl-foo", "i2c0scl", i2c_pin_configs), + PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, + "pinctrl-foo", "i2c0sda", i2c_pin_configs), + }; Finally, some devices expect the mapping table to contain certain specific named states. When running on hardware that doesn't need any pin controller configuration, the mapping table must still contain those named states, in order to explicitly indicate that the states were provided and intended to be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining -a named state without causing any pin controller to be programmed: +a named state without causing any pin controller to be programmed:: -static struct pinctrl_map mapping[] __initdata = { - PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT), -}; + static struct pinctrl_map mapping[] __initdata = { + PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT), + }; Complex mappings ================ As it is possible to map a function to different groups of pins an optional -.group can be specified like this: - -... -{ - .dev_name = "foo-spi.0", - .name = "spi0-pos-A", - .type = PIN_MAP_TYPE_MUX_GROUP, - .ctrl_dev_name = "pinctrl-foo", - .function = "spi0", - .group = "spi0_0_grp", -}, -{ - .dev_name = "foo-spi.0", - .name = "spi0-pos-B", - .type = PIN_MAP_TYPE_MUX_GROUP, - .ctrl_dev_name = "pinctrl-foo", - .function = "spi0", - .group = "spi0_1_grp", -}, -... +.group can be specified like this:: + + ... + { + .dev_name = "foo-spi.0", + .name = "spi0-pos-A", + .type = PIN_MAP_TYPE_MUX_GROUP, + .ctrl_dev_name = "pinctrl-foo", + .function = "spi0", + .group = "spi0_0_grp", + }, + { + .dev_name = "foo-spi.0", + .name = "spi0-pos-B", + .type = PIN_MAP_TYPE_MUX_GROUP, + .ctrl_dev_name = "pinctrl-foo", + .function = "spi0", + .group = "spi0_1_grp", + }, + ... This example mapping is used to switch between two positions for spi0 at runtime, as described further below under the heading "Runtime pinmuxing". @@ -1107,67 +1122,67 @@ Further it is possible for one named state to affect the muxing of several groups of pins, say for example in the mmc0 example above, where you can additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the -case), we define a mapping like this: - -... -{ - .dev_name = "foo-mmc.0", - .name = "2bit" - .type = PIN_MAP_TYPE_MUX_GROUP, - .ctrl_dev_name = "pinctrl-foo", - .function = "mmc0", - .group = "mmc0_1_grp", -}, -{ - .dev_name = "foo-mmc.0", - .name = "4bit" - .type = PIN_MAP_TYPE_MUX_GROUP, - .ctrl_dev_name = "pinctrl-foo", - .function = "mmc0", - .group = "mmc0_1_grp", -}, -{ - .dev_name = "foo-mmc.0", - .name = "4bit" - .type = PIN_MAP_TYPE_MUX_GROUP, - .ctrl_dev_name = "pinctrl-foo", - .function = "mmc0", - .group = "mmc0_2_grp", -}, -{ - .dev_name = "foo-mmc.0", - .name = "8bit" - .type = PIN_MAP_TYPE_MUX_GROUP, - .ctrl_dev_name = "pinctrl-foo", - .function = "mmc0", - .group = "mmc0_1_grp", -}, -{ - .dev_name = "foo-mmc.0", - .name = "8bit" - .type = PIN_MAP_TYPE_MUX_GROUP, - .ctrl_dev_name = "pinctrl-foo", - .function = "mmc0", - .group = "mmc0_2_grp", -}, -{ - .dev_name = "foo-mmc.0", - .name = "8bit" - .type = PIN_MAP_TYPE_MUX_GROUP, - .ctrl_dev_name = "pinctrl-foo", - .function = "mmc0", - .group = "mmc0_3_grp", -}, -... +case), we define a mapping like this:: + + ... + { + .dev_name = "foo-mmc.0", + .name = "2bit" + .type = PIN_MAP_TYPE_MUX_GROUP, + .ctrl_dev_name = "pinctrl-foo", + .function = "mmc0", + .group = "mmc0_1_grp", + }, + { + .dev_name = "foo-mmc.0", + .name = "4bit" + .type = PIN_MAP_TYPE_MUX_GROUP, + .ctrl_dev_name = "pinctrl-foo", + .function = "mmc0", + .group = "mmc0_1_grp", + }, + { + .dev_name = "foo-mmc.0", + .name = "4bit" + .type = PIN_MAP_TYPE_MUX_GROUP, + .ctrl_dev_name = "pinctrl-foo", + .function = "mmc0", + .group = "mmc0_2_grp", + }, + { + .dev_name = "foo-mmc.0", + .name = "8bit" + .type = PIN_MAP_TYPE_MUX_GROUP, + .ctrl_dev_name = "pinctrl-foo", + .function = "mmc0", + .group = "mmc0_1_grp", + }, + { + .dev_name = "foo-mmc.0", + .name = "8bit" + .type = PIN_MAP_TYPE_MUX_GROUP, + .ctrl_dev_name = "pinctrl-foo", + .function = "mmc0", + .group = "mmc0_2_grp", + }, + { + .dev_name = "foo-mmc.0", + .name = "8bit" + .type = PIN_MAP_TYPE_MUX_GROUP, + .ctrl_dev_name = "pinctrl-foo", + .function = "mmc0", + .group = "mmc0_3_grp", + }, + ... The result of grabbing this mapping from the device with something like -this (see next paragraph): +this (see next paragraph):: p = devm_pinctrl_get(dev); s = pinctrl_lookup_state(p, "8bit"); ret = pinctrl_select_state(p, s); -or more simply: +or more simply:: p = devm_pinctrl_get_select(dev, "8bit"); @@ -1205,39 +1220,39 @@ PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save current in sleep mode. A driver may request a certain control state to be activated, usually just the -default state like this: +default state like this:: -#include <linux/pinctrl/consumer.h> + #include <linux/pinctrl/consumer.h> -struct foo_state { - struct pinctrl *p; - struct pinctrl_state *s; - ... -}; + struct foo_state { + struct pinctrl *p; + struct pinctrl_state *s; + ... + }; -foo_probe() -{ - /* Allocate a state holder named "foo" etc */ - struct foo_state *foo = ...; + foo_probe() + { + /* Allocate a state holder named "foo" etc */ + struct foo_state *foo = ...; - foo->p = devm_pinctrl_get(&device); - if (IS_ERR(foo->p)) { - /* FIXME: clean up "foo" here */ - return PTR_ERR(foo->p); - } + foo->p = devm_pinctrl_get(&device); + if (IS_ERR(foo->p)) { + /* FIXME: clean up "foo" here */ + return PTR_ERR(foo->p); + } - foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT); - if (IS_ERR(foo->s)) { - /* FIXME: clean up "foo" here */ - return PTR_ERR(s); - } + foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT); + if (IS_ERR(foo->s)) { + /* FIXME: clean up "foo" here */ + return PTR_ERR(s); + } - ret = pinctrl_select_state(foo->s); - if (ret < 0) { - /* FIXME: clean up "foo" here */ - return ret; + ret = pinctrl_select_state(foo->s); + if (ret < 0) { + /* FIXME: clean up "foo" here */ + return ret; + } } -} This get/lookup/select/put sequence can just as well be handled by bus drivers if you don't want each and every driver to handle it and you know the @@ -1299,16 +1314,16 @@ Drivers needing both pin control and GPIOs Again, it is discouraged to let drivers lookup and select pin control states themselves, but again sometimes this is unavoidable. -So say that your driver is fetching its resources like this: +So say that your driver is fetching its resources like this:: -#include <linux/pinctrl/consumer.h> -#include <linux/gpio.h> + #include <linux/pinctrl/consumer.h> + #include <linux/gpio.h> -struct pinctrl *pinctrl; -int gpio; + struct pinctrl *pinctrl; + int gpio; -pinctrl = devm_pinctrl_get_select_default(&dev); -gpio = devm_gpio_request(&dev, 14, "foo"); + pinctrl = devm_pinctrl_get_select_default(&dev); + gpio = devm_gpio_request(&dev, 14, "foo"); Here we first request a certain pin state and then request GPIO 14 to be used. If you're using the subsystems orthogonally like this, you should @@ -1347,21 +1362,22 @@ lookup_state() and select_state() on it immediately after the pin control device has been registered. This occurs for mapping table entries where the client device name is equal -to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT. +to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT:: -{ - .dev_name = "pinctrl-foo", - .name = PINCTRL_STATE_DEFAULT, - .type = PIN_MAP_TYPE_MUX_GROUP, - .ctrl_dev_name = "pinctrl-foo", - .function = "power_func", -}, + { + .dev_name = "pinctrl-foo", + .name = PINCTRL_STATE_DEFAULT, + .type = PIN_MAP_TYPE_MUX_GROUP, + .ctrl_dev_name = "pinctrl-foo", + .function = "power_func", + }, Since it may be common to request the core to hog a few always-applicable mux settings on the primary pin controller, there is a convenience macro for -this: +this:: -PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func") + PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, + "power_func") This gives the exact same result as the above construction. @@ -1378,45 +1394,45 @@ function, but with different named in the mapping as described under This snippet first initializes a state object for both groups (in foo_probe()), then muxes the function in the pins defined by group A, and finally muxes it in -on the pins defined by group B: +on the pins defined by group B:: -#include <linux/pinctrl/consumer.h> + #include <linux/pinctrl/consumer.h> -struct pinctrl *p; -struct pinctrl_state *s1, *s2; + struct pinctrl *p; + struct pinctrl_state *s1, *s2; -foo_probe() -{ - /* Setup */ - p = devm_pinctrl_get(&device); - if (IS_ERR(p)) - ... + foo_probe() + { + /* Setup */ + p = devm_pinctrl_get(&device); + if (IS_ERR(p)) + ... + + s1 = pinctrl_lookup_state(foo->p, "pos-A"); + if (IS_ERR(s1)) + ... + + s2 = pinctrl_lookup_state(foo->p, "pos-B"); + if (IS_ERR(s2)) + ... + } - s1 = pinctrl_lookup_state(foo->p, "pos-A"); - if (IS_ERR(s1)) + foo_switch() + { + /* Enable on position A */ + ret = pinctrl_select_state(s1); + if (ret < 0) ... - s2 = pinctrl_lookup_state(foo->p, "pos-B"); - if (IS_ERR(s2)) ... -} - -foo_switch() -{ - /* Enable on position A */ - ret = pinctrl_select_state(s1); - if (ret < 0) - ... - - ... - /* Enable on position B */ - ret = pinctrl_select_state(s2); - if (ret < 0) - ... + /* Enable on position B */ + ret = pinctrl_select_state(s2); + if (ret < 0) + ... - ... -} + ... + } The above has to be done from process context. The reservation of the pins will be done when the state is activated, so in effect one specific pin diff --git a/MAINTAINERS b/MAINTAINERS index d93d4dec16f2..75ac9dc85804 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1515,6 +1515,7 @@ F: arch/arm64/boot/dts/marvell/armada* F: drivers/cpufreq/mvebu-cpufreq.c F: drivers/irqchip/irq-armada-370-xp.c F: drivers/irqchip/irq-mvebu-* +F: drivers/pinctrl/mvebu/ F: drivers/rtc/rtc-armada38x.c ARM/Marvell Berlin SoC support @@ -1681,7 +1682,6 @@ F: arch/arm/mach-qcom/ F: arch/arm64/boot/dts/qcom/* F: drivers/i2c/busses/i2c-qup.c F: drivers/clk/qcom/ -F: drivers/pinctrl/qcom/ F: drivers/dma/qcom/ F: drivers/soc/qcom/ F: drivers/spi/spi-qup.c @@ -10267,6 +10267,13 @@ M: Heikki Krogerus <heikki.krogerus@linux.intel.com> S: Maintained F: drivers/pinctrl/intel/ +PIN CONTROLLER - QUALCOMM +M: Bjorn Andersson <bjorn.andersson@linaro.org> +S: Maintained +L: linux-arm-msm@vger.kernel.org +F: Documentation/devicetree/bindings/pinctrl/qcom,*.txt +F: drivers/pinctrl/qcom/ + PIN CONTROLLER - RENESAS M: Laurent Pinchart <laurent.pinchart@ideasonboard.com> M: Geert Uytterhoeven <geert+renesas@glider.be> diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig index 6ba430d2b5b2..e15fa5f168bb 100644 --- a/arch/arm/configs/lpc32xx_defconfig +++ b/arch/arm/configs/lpc32xx_defconfig @@ -112,7 +112,7 @@ CONFIG_GPIO_SX150X=y CONFIG_GPIO_74X164=y CONFIG_GPIO_MAX7301=y CONFIG_GPIO_MC33880=y -CONFIG_GPIO_MCP23S08=y +CONFIG_PINCTRL_MCP23S08=y CONFIG_SENSORS_DS620=y CONFIG_SENSORS_MAX6639=y CONFIG_WATCHDOG=y diff --git a/arch/blackfin/configs/BF609-EZKIT_defconfig b/arch/blackfin/configs/BF609-EZKIT_defconfig index ba4267f658af..3ce77f07208a 100644 --- a/arch/blackfin/configs/BF609-EZKIT_defconfig +++ b/arch/blackfin/configs/BF609-EZKIT_defconfig @@ -105,7 +105,7 @@ CONFIG_SPI=y CONFIG_SPI_ADI_V3=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_MCP23S08=y +CONFIG_PINCTRL_MCP23S08=y # CONFIG_HWMON is not set CONFIG_WATCHDOG=y CONFIG_BFIN_WDT=y diff --git a/arch/blackfin/mach-bf527/boards/tll6527m.c b/arch/blackfin/mach-bf527/boards/tll6527m.c index c1acce4c2e45..ce5488e8226b 100644 --- a/arch/blackfin/mach-bf527/boards/tll6527m.c +++ b/arch/blackfin/mach-bf527/boards/tll6527m.c @@ -348,14 +348,14 @@ static struct platform_device bfin_i2s = { }; #endif -#if IS_ENABLED(CONFIG_GPIO_MCP23S08) +#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08) #include <linux/spi/mcp23s08.h> static const struct mcp23s08_platform_data bfin_mcp23s08_sys_gpio_info = { - .chip[0].is_present = true, + .spi_present_mask = BIT(0), .base = 0x30, }; static const struct mcp23s08_platform_data bfin_mcp23s08_usr_gpio_info = { - .chip[2].is_present = true, + .spi_present_mask = BIT(2), .base = 0x38, }; #endif @@ -423,7 +423,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { .mode = SPI_CPHA | SPI_CPOL, }, #endif -#if IS_ENABLED(CONFIG_GPIO_MCP23S08) +#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08) { .modalias = "mcp23s08", .platform_data = &bfin_mcp23s08_sys_gpio_info, diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c index 9231e5a72b93..51157a255824 100644 --- a/arch/blackfin/mach-bf609/boards/ezkit.c +++ b/arch/blackfin/mach-bf609/boards/ezkit.c @@ -1887,7 +1887,7 @@ static struct platform_device i2c_bfin_twi1_device = { }; #endif -#if IS_ENABLED(CONFIG_GPIO_MCP23S08) +#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08) #include <linux/spi/mcp23s08.h> static const struct mcp23s08_platform_data bfin_mcp23s08_soft_switch0 = { .base = 120, @@ -1929,7 +1929,7 @@ static struct i2c_board_info __initdata bfin_i2c_board_info0[] = { I2C_BOARD_INFO("ssm2602", 0x1b), }, #endif -#if IS_ENABLED(CONFIG_GPIO_MCP23S08) +#if IS_ENABLED(CONFIG_PINCTRL_MCP23S08) { I2C_BOARD_INFO("mcp23017", 0x21), .platform_data = (void *)&bfin_mcp23s08_soft_switch0 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2828ecde133d..45bcd1cfcec0 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -364,6 +364,7 @@ config MACH_INGENIC select SYS_SUPPORTS_ZBOOT_UART16550 select DMA_NONCOHERENT select IRQ_MIPS_CPU + select PINCTRL select GPIOLIB select COMMON_CLK select GENERIC_IRQ_CHIP diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts index 1652d8d60b1e..fd138d9978c1 100644 --- a/arch/mips/boot/dts/ingenic/ci20.dts +++ b/arch/mips/boot/dts/ingenic/ci20.dts @@ -29,18 +29,30 @@ &uart0 { status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_uart0>; }; &uart1 { status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_uart1>; }; &uart3 { status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_uart2>; }; &uart4 { status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pins_uart4>; }; &nemc { @@ -61,6 +73,13 @@ ingenic,nemc-tAW = <15>; ingenic,nemc-tSTRV = <100>; + /* + * Only CLE/ALE are needed for the devices that are connected, rather + * than the full address line set. + */ + pinctrl-names = "default"; + pinctrl-0 = <&pins_nemc>; + nand@1 { reg = <1>; @@ -69,6 +88,9 @@ nand-ecc-mode = "hw"; nand-on-flash-bbt; + pinctrl-names = "default"; + pinctrl-0 = <&pins_nemc_cs1>; + partitions { compatible = "fixed-partitions"; #address-cells = <2>; @@ -106,3 +128,41 @@ &bch { status = "okay"; }; + +&pinctrl { + pins_uart0: uart0 { + function = "uart0"; + groups = "uart0-data"; + bias-disable; + }; + + pins_uart1: uart1 { + function = "uart1"; + groups = "uart1-data"; + bias-disable; + }; + + pins_uart2: uart2 { + function = "uart2"; + groups = "uart2-data", "uart2-hwflow"; + bias-disable; + }; + + pins_uart4: uart4 { + function = "uart4"; + groups = "uart4-data"; + bias-disable; + }; + + pins_nemc: nemc { + function = "nemc"; + groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we", "nemc-frd-fwe"; + bias-disable; + }; + + pins_nemc_cs1: nemc-cs1 { + function = "nemc-cs1"; + groups = "nemc-cs1"; + bias-disable; + }; +}; diff --git a/arch/mips/boot/dts/ingenic/jz4740.dtsi b/arch/mips/boot/dts/ingenic/jz4740.dtsi index 3e1587f1f77a..2ca7ce7481f1 100644 --- a/arch/mips/boot/dts/ingenic/jz4740.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4740.dtsi @@ -55,6 +55,74 @@ clock-names = "rtc"; }; + pinctrl: pin-controller@10010000 { + compatible = "ingenic,jz4740-pinctrl"; + reg = <0x10010000 0x400>; + + #address-cells = <1>; + #size-cells = <0>; + + gpa: gpio@0 { + compatible = "ingenic,jz4740-gpio"; + reg = <0>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <28>; + }; + + gpb: gpio@1 { + compatible = "ingenic,jz4740-gpio"; + reg = <1>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 32 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <27>; + }; + + gpc: gpio@2 { + compatible = "ingenic,jz4740-gpio"; + reg = <2>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 64 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <26>; + }; + + gpd: gpio@3 { + compatible = "ingenic,jz4740-gpio"; + reg = <3>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 96 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <25>; + }; + }; + uart0: serial@10030000 { compatible = "ingenic,jz4740-uart"; reg = <0x10030000 0x100>; diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi b/arch/mips/boot/dts/ingenic/jz4780.dtsi index b868b429add2..4853ef67b3ab 100644 --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi @@ -44,6 +44,104 @@ #clock-cells = <1>; }; + pinctrl: pin-controller@10010000 { + compatible = "ingenic,jz4780-pinctrl"; + reg = <0x10010000 0x600>; + + #address-cells = <1>; + #size-cells = <0>; + + gpa: gpio@0 { + compatible = "ingenic,jz4780-gpio"; + reg = <0>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <17>; + }; + + gpb: gpio@1 { + compatible = "ingenic,jz4780-gpio"; + reg = <1>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 32 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <16>; + }; + + gpc: gpio@2 { + compatible = "ingenic,jz4780-gpio"; + reg = <2>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 64 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <15>; + }; + + gpd: gpio@3 { + compatible = "ingenic,jz4780-gpio"; + reg = <3>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 96 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <14>; + }; + + gpe: gpio@4 { + compatible = "ingenic,jz4780-gpio"; + reg = <4>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 128 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <13>; + }; + + gpf: gpio@5 { + compatible = "ingenic,jz4780-gpio"; + reg = <5>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 160 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <12>; + }; + }; + uart0: serial@10030000 { compatible = "ingenic,jz4780-uart"; reg = <0x10030000 0x100>; diff --git a/arch/mips/boot/dts/ingenic/qi_lb60.dts b/arch/mips/boot/dts/ingenic/qi_lb60.dts index be1a7d3a3e1b..b715ee2ac2ee 100644 --- a/arch/mips/boot/dts/ingenic/qi_lb60.dts +++ b/arch/mips/boot/dts/ingenic/qi_lb60.dts @@ -17,3 +17,16 @@ &rtc_dev { system-power-controller; }; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pins_uart0>; +}; + +&pinctrl { + pins_uart0: uart0 { + function = "uart0"; + groups = "uart0-data"; + bias-disable; + }; +}; diff --git a/arch/mips/include/asm/mach-jz4740/gpio.h b/arch/mips/include/asm/mach-jz4740/gpio.h index 7c7708a23baa..fd847c984701 100644 --- a/arch/mips/include/asm/mach-jz4740/gpio.h +++ b/arch/mips/include/asm/mach-jz4740/gpio.h @@ -16,380 +16,9 @@ #ifndef _JZ_GPIO_H #define _JZ_GPIO_H -#include <linux/types.h> - -enum jz_gpio_function { - JZ_GPIO_FUNC_NONE, - JZ_GPIO_FUNC1, - JZ_GPIO_FUNC2, - JZ_GPIO_FUNC3, -}; - -/* - Usually a driver for a SoC component has to request several gpio pins and - configure them as function pins. - jz_gpio_bulk_request can be used to ease this process. - Usually one would do something like: - - static const struct jz_gpio_bulk_request i2c_pins[] = { - JZ_GPIO_BULK_PIN(I2C_SDA), - JZ_GPIO_BULK_PIN(I2C_SCK), - }; - - inside the probe function: - - ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins)); - if (ret) { - ... - - inside the remove function: - - jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins)); - -*/ - -struct jz_gpio_bulk_request { - int gpio; - const char *name; - enum jz_gpio_function function; -}; - -#define JZ_GPIO_BULK_PIN(pin) { \ - .gpio = JZ_GPIO_ ## pin, \ - .name = #pin, \ - .function = JZ_GPIO_FUNC_ ## pin \ -} - -int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num); -void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num); -void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num); -void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num); -void jz_gpio_enable_pullup(unsigned gpio); -void jz_gpio_disable_pullup(unsigned gpio); -int jz_gpio_set_function(int gpio, enum jz_gpio_function function); - -int jz_gpio_port_direction_input(int port, uint32_t mask); -int jz_gpio_port_direction_output(int port, uint32_t mask); -void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask); -uint32_t jz_gpio_port_get_value(int port, uint32_t mask); - #define JZ_GPIO_PORTA(x) ((x) + 32 * 0) #define JZ_GPIO_PORTB(x) ((x) + 32 * 1) #define JZ_GPIO_PORTC(x) ((x) + 32 * 2) #define JZ_GPIO_PORTD(x) ((x) + 32 * 3) -/* Port A function pins */ -#define JZ_GPIO_MEM_DATA0 JZ_GPIO_PORTA(0) -#define JZ_GPIO_MEM_DATA1 JZ_GPIO_PORTA(1) -#define JZ_GPIO_MEM_DATA2 JZ_GPIO_PORTA(2) -#define JZ_GPIO_MEM_DATA3 JZ_GPIO_PORTA(3) -#define JZ_GPIO_MEM_DATA4 JZ_GPIO_PORTA(4) -#define JZ_GPIO_MEM_DATA5 JZ_GPIO_PORTA(5) -#define JZ_GPIO_MEM_DATA6 JZ_GPIO_PORTA(6) -#define JZ_GPIO_MEM_DATA7 JZ_GPIO_PORTA(7) -#define JZ_GPIO_MEM_DATA8 JZ_GPIO_PORTA(8) -#define JZ_GPIO_MEM_DATA9 JZ_GPIO_PORTA(9) -#define JZ_GPIO_MEM_DATA10 JZ_GPIO_PORTA(10) -#define JZ_GPIO_MEM_DATA11 JZ_GPIO_PORTA(11) -#define JZ_GPIO_MEM_DATA12 JZ_GPIO_PORTA(12) -#define JZ_GPIO_MEM_DATA13 JZ_GPIO_PORTA(13) -#define JZ_GPIO_MEM_DATA14 JZ_GPIO_PORTA(14) -#define JZ_GPIO_MEM_DATA15 JZ_GPIO_PORTA(15) -#define JZ_GPIO_MEM_DATA16 JZ_GPIO_PORTA(16) -#define JZ_GPIO_MEM_DATA17 JZ_GPIO_PORTA(17) -#define JZ_GPIO_MEM_DATA18 JZ_GPIO_PORTA(18) -#define JZ_GPIO_MEM_DATA19 JZ_GPIO_PORTA(19) -#define JZ_GPIO_MEM_DATA20 JZ_GPIO_PORTA(20) -#define JZ_GPIO_MEM_DATA21 JZ_GPIO_PORTA(21) -#define JZ_GPIO_MEM_DATA22 JZ_GPIO_PORTA(22) -#define JZ_GPIO_MEM_DATA23 JZ_GPIO_PORTA(23) -#define JZ_GPIO_MEM_DATA24 JZ_GPIO_PORTA(24) -#define JZ_GPIO_MEM_DATA25 JZ_GPIO_PORTA(25) -#define JZ_GPIO_MEM_DATA26 JZ_GPIO_PORTA(26) -#define JZ_GPIO_MEM_DATA27 JZ_GPIO_PORTA(27) -#define JZ_GPIO_MEM_DATA28 JZ_GPIO_PORTA(28) -#define JZ_GPIO_MEM_DATA29 JZ_GPIO_PORTA(29) -#define JZ_GPIO_MEM_DATA30 JZ_GPIO_PORTA(30) -#define JZ_GPIO_MEM_DATA31 JZ_GPIO_PORTA(31) - -#define JZ_GPIO_FUNC_MEM_DATA0 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA1 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA2 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA3 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA4 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA5 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA6 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA7 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA8 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA9 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA10 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA11 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA12 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA13 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA14 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA15 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA16 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA17 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA18 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA19 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA20 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA21 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA22 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA23 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA24 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA25 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA26 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA27 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA28 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA29 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA30 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DATA31 JZ_GPIO_FUNC1 - -/* Port B function pins */ -#define JZ_GPIO_MEM_ADDR0 JZ_GPIO_PORTB(0) -#define JZ_GPIO_MEM_ADDR1 JZ_GPIO_PORTB(1) -#define JZ_GPIO_MEM_ADDR2 JZ_GPIO_PORTB(2) -#define JZ_GPIO_MEM_ADDR3 JZ_GPIO_PORTB(3) -#define JZ_GPIO_MEM_ADDR4 JZ_GPIO_PORTB(4) -#define JZ_GPIO_MEM_ADDR5 JZ_GPIO_PORTB(5) -#define JZ_GPIO_MEM_ADDR6 JZ_GPIO_PORTB(6) -#define JZ_GPIO_MEM_ADDR7 JZ_GPIO_PORTB(7) -#define JZ_GPIO_MEM_ADDR8 JZ_GPIO_PORTB(8) -#define JZ_GPIO_MEM_ADDR9 JZ_GPIO_PORTB(9) -#define JZ_GPIO_MEM_ADDR10 JZ_GPIO_PORTB(10) -#define JZ_GPIO_MEM_ADDR11 JZ_GPIO_PORTB(11) -#define JZ_GPIO_MEM_ADDR12 JZ_GPIO_PORTB(12) -#define JZ_GPIO_MEM_ADDR13 JZ_GPIO_PORTB(13) -#define JZ_GPIO_MEM_ADDR14 JZ_GPIO_PORTB(14) -#define JZ_GPIO_MEM_ADDR15 JZ_GPIO_PORTB(15) -#define JZ_GPIO_MEM_ADDR16 JZ_GPIO_PORTB(16) -#define JZ_GPIO_LCD_CLS JZ_GPIO_PORTB(17) -#define JZ_GPIO_LCD_SPL JZ_GPIO_PORTB(18) -#define JZ_GPIO_MEM_DCS JZ_GPIO_PORTB(19) -#define JZ_GPIO_MEM_RAS JZ_GPIO_PORTB(20) -#define JZ_GPIO_MEM_CAS JZ_GPIO_PORTB(21) -#define JZ_GPIO_MEM_SDWE JZ_GPIO_PORTB(22) -#define JZ_GPIO_MEM_CKE JZ_GPIO_PORTB(23) -#define JZ_GPIO_MEM_CKO JZ_GPIO_PORTB(24) -#define JZ_GPIO_MEM_CS0 JZ_GPIO_PORTB(25) -#define JZ_GPIO_MEM_CS1 JZ_GPIO_PORTB(26) -#define JZ_GPIO_MEM_CS2 JZ_GPIO_PORTB(27) -#define JZ_GPIO_MEM_CS3 JZ_GPIO_PORTB(28) -#define JZ_GPIO_MEM_RD JZ_GPIO_PORTB(29) -#define JZ_GPIO_MEM_WR JZ_GPIO_PORTB(30) -#define JZ_GPIO_MEM_WE0 JZ_GPIO_PORTB(31) - -#define JZ_GPIO_FUNC_MEM_ADDR0 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR1 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR2 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR3 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR4 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR5 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR6 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR7 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR8 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR9 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR10 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR11 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR12 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR13 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR14 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR15 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_ADDR16 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_CLS JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_SPL JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_DCS JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_RAS JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_CAS JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_SDWE JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_CKE JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_CKO JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_CS0 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_CS1 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_CS2 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_CS3 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_RD JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_WR JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_WE0 JZ_GPIO_FUNC1 - - -#define JZ_GPIO_MEM_ADDR21 JZ_GPIO_PORTB(17) -#define JZ_GPIO_MEM_ADDR22 JZ_GPIO_PORTB(18) - -#define JZ_GPIO_FUNC_MEM_ADDR21 JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_MEM_ADDR22 JZ_GPIO_FUNC2 - -/* Port C function pins */ -#define JZ_GPIO_LCD_DATA0 JZ_GPIO_PORTC(0) -#define JZ_GPIO_LCD_DATA1 JZ_GPIO_PORTC(1) -#define JZ_GPIO_LCD_DATA2 JZ_GPIO_PORTC(2) -#define JZ_GPIO_LCD_DATA3 JZ_GPIO_PORTC(3) -#define JZ_GPIO_LCD_DATA4 JZ_GPIO_PORTC(4) -#define JZ_GPIO_LCD_DATA5 JZ_GPIO_PORTC(5) -#define JZ_GPIO_LCD_DATA6 JZ_GPIO_PORTC(6) -#define JZ_GPIO_LCD_DATA7 JZ_GPIO_PORTC(7) -#define JZ_GPIO_LCD_DATA8 JZ_GPIO_PORTC(8) -#define JZ_GPIO_LCD_DATA9 JZ_GPIO_PORTC(9) -#define JZ_GPIO_LCD_DATA10 JZ_GPIO_PORTC(10) -#define JZ_GPIO_LCD_DATA11 JZ_GPIO_PORTC(11) -#define JZ_GPIO_LCD_DATA12 JZ_GPIO_PORTC(12) -#define JZ_GPIO_LCD_DATA13 JZ_GPIO_PORTC(13) -#define JZ_GPIO_LCD_DATA14 JZ_GPIO_PORTC(14) -#define JZ_GPIO_LCD_DATA15 JZ_GPIO_PORTC(15) -#define JZ_GPIO_LCD_DATA16 JZ_GPIO_PORTC(16) -#define JZ_GPIO_LCD_DATA17 JZ_GPIO_PORTC(17) -#define JZ_GPIO_LCD_PCLK JZ_GPIO_PORTC(18) -#define JZ_GPIO_LCD_HSYNC JZ_GPIO_PORTC(19) -#define JZ_GPIO_LCD_VSYNC JZ_GPIO_PORTC(20) -#define JZ_GPIO_LCD_DE JZ_GPIO_PORTC(21) -#define JZ_GPIO_LCD_PS JZ_GPIO_PORTC(22) -#define JZ_GPIO_LCD_REV JZ_GPIO_PORTC(23) -#define JZ_GPIO_MEM_WE1 JZ_GPIO_PORTC(24) -#define JZ_GPIO_MEM_WE2 JZ_GPIO_PORTC(25) -#define JZ_GPIO_MEM_WE3 JZ_GPIO_PORTC(26) -#define JZ_GPIO_MEM_WAIT JZ_GPIO_PORTC(27) -#define JZ_GPIO_MEM_FRE JZ_GPIO_PORTC(28) -#define JZ_GPIO_MEM_FWE JZ_GPIO_PORTC(29) - -#define JZ_GPIO_FUNC_LCD_DATA0 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA1 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA2 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA3 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA4 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA5 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA6 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA7 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA8 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA9 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA10 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA11 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA12 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA13 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA14 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA15 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA16 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DATA17 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_PCLK JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_VSYNC JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_HSYNC JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_DE JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_PS JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_LCD_REV JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_WE1 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_WE2 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_WE3 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_WAIT JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_FRE JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MEM_FWE JZ_GPIO_FUNC1 - - -#define JZ_GPIO_MEM_ADDR19 JZ_GPIO_PORTB(22) -#define JZ_GPIO_MEM_ADDR20 JZ_GPIO_PORTB(23) - -#define JZ_GPIO_FUNC_MEM_ADDR19 JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_MEM_ADDR20 JZ_GPIO_FUNC2 - -/* Port D function pins */ -#define JZ_GPIO_CIM_DATA0 JZ_GPIO_PORTD(0) -#define JZ_GPIO_CIM_DATA1 JZ_GPIO_PORTD(1) -#define JZ_GPIO_CIM_DATA2 JZ_GPIO_PORTD(2) -#define JZ_GPIO_CIM_DATA3 JZ_GPIO_PORTD(3) -#define JZ_GPIO_CIM_DATA4 JZ_GPIO_PORTD(4) -#define JZ_GPIO_CIM_DATA5 JZ_GPIO_PORTD(5) -#define JZ_GPIO_CIM_DATA6 JZ_GPIO_PORTD(6) -#define JZ_GPIO_CIM_DATA7 JZ_GPIO_PORTD(7) -#define JZ_GPIO_MSC_CMD JZ_GPIO_PORTD(8) -#define JZ_GPIO_MSC_CLK JZ_GPIO_PORTD(9) -#define JZ_GPIO_MSC_DATA0 JZ_GPIO_PORTD(10) -#define JZ_GPIO_MSC_DATA1 JZ_GPIO_PORTD(11) -#define JZ_GPIO_MSC_DATA2 JZ_GPIO_PORTD(12) -#define JZ_GPIO_MSC_DATA3 JZ_GPIO_PORTD(13) -#define JZ_GPIO_CIM_MCLK JZ_GPIO_PORTD(14) -#define JZ_GPIO_CIM_PCLK JZ_GPIO_PORTD(15) -#define JZ_GPIO_CIM_VSYNC JZ_GPIO_PORTD(16) -#define JZ_GPIO_CIM_HSYNC JZ_GPIO_PORTD(17) -#define JZ_GPIO_SPI_CLK JZ_GPIO_PORTD(18) -#define JZ_GPIO_SPI_CE0 JZ_GPIO_PORTD(19) -#define JZ_GPIO_SPI_DT JZ_GPIO_PORTD(20) -#define JZ_GPIO_SPI_DR JZ_GPIO_PORTD(21) -#define JZ_GPIO_SPI_CE1 JZ_GPIO_PORTD(22) -#define JZ_GPIO_PWM0 JZ_GPIO_PORTD(23) -#define JZ_GPIO_PWM1 JZ_GPIO_PORTD(24) -#define JZ_GPIO_PWM2 JZ_GPIO_PORTD(25) -#define JZ_GPIO_PWM3 JZ_GPIO_PORTD(26) -#define JZ_GPIO_PWM4 JZ_GPIO_PORTD(27) -#define JZ_GPIO_PWM5 JZ_GPIO_PORTD(28) -#define JZ_GPIO_PWM6 JZ_GPIO_PORTD(30) -#define JZ_GPIO_PWM7 JZ_GPIO_PORTD(31) - -#define JZ_GPIO_FUNC_CIM_DATA JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_CIM_DATA0 JZ_GPIO_FUNC_CIM_DATA -#define JZ_GPIO_FUNC_CIM_DATA1 JZ_GPIO_FUNC_CIM_DATA -#define JZ_GPIO_FUNC_CIM_DATA2 JZ_GPIO_FUNC_CIM_DATA -#define JZ_GPIO_FUNC_CIM_DATA3 JZ_GPIO_FUNC_CIM_DATA -#define JZ_GPIO_FUNC_CIM_DATA4 JZ_GPIO_FUNC_CIM_DATA -#define JZ_GPIO_FUNC_CIM_DATA5 JZ_GPIO_FUNC_CIM_DATA -#define JZ_GPIO_FUNC_CIM_DATA6 JZ_GPIO_FUNC_CIM_DATA -#define JZ_GPIO_FUNC_CIM_DATA7 JZ_GPIO_FUNC_CIM_DATA -#define JZ_GPIO_FUNC_MSC_CMD JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MSC_CLK JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MSC_DATA JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_MSC_DATA0 JZ_GPIO_FUNC_MSC_DATA -#define JZ_GPIO_FUNC_MSC_DATA1 JZ_GPIO_FUNC_MSC_DATA -#define JZ_GPIO_FUNC_MSC_DATA2 JZ_GPIO_FUNC_MSC_DATA -#define JZ_GPIO_FUNC_MSC_DATA3 JZ_GPIO_FUNC_MSC_DATA -#define JZ_GPIO_FUNC_CIM_MCLK JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_CIM_PCLK JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_CIM_VSYNC JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_CIM_HSYNC JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_SPI_CLK JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_SPI_CE0 JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_SPI_DT JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_SPI_DR JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_SPI_CE1 JZ_GPIO_FUNC1 - -#define JZ_GPIO_FUNC_PWM JZ_GPIO_FUNC1 -#define JZ_GPIO_FUNC_PWM0 JZ_GPIO_FUNC_PWM -#define JZ_GPIO_FUNC_PWM1 JZ_GPIO_FUNC_PWM -#define JZ_GPIO_FUNC_PWM2 JZ_GPIO_FUNC_PWM -#define JZ_GPIO_FUNC_PWM3 JZ_GPIO_FUNC_PWM -#define JZ_GPIO_FUNC_PWM4 JZ_GPIO_FUNC_PWM -#define JZ_GPIO_FUNC_PWM5 JZ_GPIO_FUNC_PWM -#define JZ_GPIO_FUNC_PWM6 JZ_GPIO_FUNC_PWM -#define JZ_GPIO_FUNC_PWM7 JZ_GPIO_FUNC_PWM - -#define JZ_GPIO_MEM_SCLK_RSTN JZ_GPIO_PORTD(18) -#define JZ_GPIO_MEM_BCLK JZ_GPIO_PORTD(19) -#define JZ_GPIO_MEM_SDATO JZ_GPIO_PORTD(20) -#define JZ_GPIO_MEM_SDATI JZ_GPIO_PORTD(21) -#define JZ_GPIO_MEM_SYNC JZ_GPIO_PORTD(22) -#define JZ_GPIO_I2C_SDA JZ_GPIO_PORTD(23) -#define JZ_GPIO_I2C_SCK JZ_GPIO_PORTD(24) -#define JZ_GPIO_UART0_TXD JZ_GPIO_PORTD(25) -#define JZ_GPIO_UART0_RXD JZ_GPIO_PORTD(26) -#define JZ_GPIO_MEM_ADDR17 JZ_GPIO_PORTD(27) -#define JZ_GPIO_MEM_ADDR18 JZ_GPIO_PORTD(28) -#define JZ_GPIO_UART0_CTS JZ_GPIO_PORTD(30) -#define JZ_GPIO_UART0_RTS JZ_GPIO_PORTD(31) - -#define JZ_GPIO_FUNC_MEM_SCLK_RSTN JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_MEM_BCLK JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_MEM_SDATO JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_MEM_SDATI JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_MEM_SYNC JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_I2C_SDA JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_I2C_SCK JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_UART0_TXD JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_UART0_RXD JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_MEM_ADDR17 JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_MEM_ADDR18 JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_UART0_CTS JZ_GPIO_FUNC2 -#define JZ_GPIO_FUNC_UART0_RTS JZ_GPIO_FUNC2 - -#define JZ_GPIO_UART1_RXD JZ_GPIO_PORTD(30) -#define JZ_GPIO_UART1_TXD JZ_GPIO_PORTD(31) - -#define JZ_GPIO_FUNC_UART1_RXD JZ_GPIO_FUNC3 -#define JZ_GPIO_FUNC_UART1_TXD JZ_GPIO_FUNC3 - #endif diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile index 39d70bde8cfe..6b9c1f7c31c9 100644 --- a/arch/mips/jz4740/Makefile +++ b/arch/mips/jz4740/Makefile @@ -7,8 +7,6 @@ obj-y += prom.o time.o reset.o setup.o \ platform.o timer.o -obj-$(CONFIG_MACH_JZ4740) += gpio.o - CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt # board specific support diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c index a5bd94b95263..6d7f97552200 100644 --- a/arch/mips/jz4740/board-qi_lb60.c +++ b/arch/mips/jz4740/board-qi_lb60.c @@ -22,6 +22,8 @@ #include <linux/input/matrix_keypad.h> #include <linux/spi/spi.h> #include <linux/spi/spi_gpio.h> +#include <linux/pinctrl/machine.h> +#include <linux/pinctrl/pinconf-generic.h> #include <linux/power_supply.h> #include <linux/power/jz4740-battery.h> #include <linux/power/gpio-charger.h> @@ -159,7 +161,7 @@ static struct jz_nand_platform_data qi_lb60_nand_pdata = { static struct gpiod_lookup_table qi_lb60_nand_gpio_table = { .dev_id = "jz4740-nand.0", .table = { - GPIO_LOOKUP("Bank C", 30, "busy", 0), + GPIO_LOOKUP("GPIOC", 30, "busy", 0), { }, }, }; @@ -421,8 +423,8 @@ static struct platform_device qi_lb60_audio_device = { static struct gpiod_lookup_table qi_lb60_audio_gpio_table = { .dev_id = "qi-lb60-audio", .table = { - GPIO_LOOKUP("Bank B", 29, "snd", 0), - GPIO_LOOKUP("Bank D", 4, "amp", 0), + GPIO_LOOKUP("GPIOB", 29, "snd", 0), + GPIO_LOOKUP("GPIOD", 4, "amp", 0), { }, }, }; @@ -447,13 +449,36 @@ static struct platform_device *jz_platform_devices[] __initdata = { &qi_lb60_audio_device, }; -static void __init board_gpio_setup(void) -{ - /* We only need to enable/disable pullup here for pins used in generic - * drivers. Everything else is done by the drivers themselves. */ - jz_gpio_disable_pullup(QI_LB60_GPIO_SD_VCC_EN_N); - jz_gpio_disable_pullup(QI_LB60_GPIO_SD_CD); -} +static unsigned long pin_cfg_bias_disable[] = { + PIN_CONFIG_BIAS_DISABLE, +}; + +static struct pinctrl_map pin_map[] __initdata = { + /* NAND pin configuration */ + PIN_MAP_MUX_GROUP_DEFAULT("jz4740-nand", + "10010000.jz4740-pinctrl", "nand", "nand-cs1"), + + /* fbdev pin configuration */ + PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_DEFAULT, + "10010000.jz4740-pinctrl", "lcd", "lcd-8bit"), + PIN_MAP_MUX_GROUP("jz4740-fb", PINCTRL_STATE_SLEEP, + "10010000.jz4740-pinctrl", "lcd", "lcd-no-pins"), + + /* MMC pin configuration */ + PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0", + "10010000.jz4740-pinctrl", "mmc", "mmc-1bit"), + PIN_MAP_MUX_GROUP_DEFAULT("jz4740-mmc.0", + "10010000.jz4740-pinctrl", "mmc", "mmc-4bit"), + PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0", + "10010000.jz4740-pinctrl", "PD0", pin_cfg_bias_disable), + PIN_MAP_CONFIGS_PIN_DEFAULT("jz4740-mmc.0", + "10010000.jz4740-pinctrl", "PD2", pin_cfg_bias_disable), + + /* PWM pin configuration */ + PIN_MAP_MUX_GROUP_DEFAULT("jz4740-pwm", + "10010000.jz4740-pinctrl", "pwm4", "pwm4"), +}; + static int __init qi_lb60_init_platform_devices(void) { @@ -469,6 +494,7 @@ static int __init qi_lb60_init_platform_devices(void) ARRAY_SIZE(qi_lb60_spi_board_info)); pwm_add_table(qi_lb60_pwm_lookup, ARRAY_SIZE(qi_lb60_pwm_lookup)); + pinctrl_register_mappings(pin_map, ARRAY_SIZE(pin_map)); return platform_add_devices(jz_platform_devices, ARRAY_SIZE(jz_platform_devices)); @@ -479,8 +505,6 @@ static int __init qi_lb60_board_setup(void) { printk(KERN_INFO "Qi Hardware JZ4740 QI LB60 setup\n"); - board_gpio_setup(); - if (qi_lb60_init_platform_devices()) panic("Failed to initialize platform devices"); diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c deleted file mode 100644 index cac1ccde2214..000000000000 --- a/arch/mips/jz4740/gpio.c +++ /dev/null @@ -1,519 +0,0 @@ -/* - * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> - * JZ4740 platform GPIO support - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#include <linux/kernel.h> -#include <linux/export.h> -#include <linux/init.h> - -#include <linux/io.h> -#include <linux/gpio/driver.h> -/* FIXME: needed for gpio_request(), try to remove consumer API from driver */ -#include <linux/gpio.h> -#include <linux/delay.h> -#include <linux/interrupt.h> -#include <linux/irqchip/ingenic.h> -#include <linux/bitops.h> - -#include <linux/debugfs.h> -#include <linux/seq_file.h> - -#include <asm/mach-jz4740/base.h> -#include <asm/mach-jz4740/gpio.h> - -#define JZ4740_GPIO_BASE_A (32*0) -#define JZ4740_GPIO_BASE_B (32*1) -#define JZ4740_GPIO_BASE_C (32*2) -#define JZ4740_GPIO_BASE_D (32*3) - -#define JZ4740_GPIO_NUM_A 32 -#define JZ4740_GPIO_NUM_B 32 -#define JZ4740_GPIO_NUM_C 31 -#define JZ4740_GPIO_NUM_D 32 - -#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A) -#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B) -#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C) -#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D) - -#define JZ_REG_GPIO_PIN 0x00 -#define JZ_REG_GPIO_DATA 0x10 -#define JZ_REG_GPIO_DATA_SET 0x14 -#define JZ_REG_GPIO_DATA_CLEAR 0x18 -#define JZ_REG_GPIO_MASK 0x20 -#define JZ_REG_GPIO_MASK_SET 0x24 -#define JZ_REG_GPIO_MASK_CLEAR 0x28 -#define JZ_REG_GPIO_PULL 0x30 -#define JZ_REG_GPIO_PULL_SET 0x34 -#define JZ_REG_GPIO_PULL_CLEAR 0x38 -#define JZ_REG_GPIO_FUNC 0x40 -#define JZ_REG_GPIO_FUNC_SET 0x44 -#define JZ_REG_GPIO_FUNC_CLEAR 0x48 -#define JZ_REG_GPIO_SELECT 0x50 -#define JZ_REG_GPIO_SELECT_SET 0x54 -#define JZ_REG_GPIO_SELECT_CLEAR 0x58 -#define JZ_REG_GPIO_DIRECTION 0x60 -#define JZ_REG_GPIO_DIRECTION_SET 0x64 -#define JZ_REG_GPIO_DIRECTION_CLEAR 0x68 -#define JZ_REG_GPIO_TRIGGER 0x70 -#define JZ_REG_GPIO_TRIGGER_SET 0x74 -#define JZ_REG_GPIO_TRIGGER_CLEAR 0x78 -#define JZ_REG_GPIO_FLAG 0x80 -#define JZ_REG_GPIO_FLAG_CLEAR 0x14 - -#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f) -#define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg)) -#define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg)) - -struct jz_gpio_chip { - unsigned int irq; - unsigned int irq_base; - uint32_t edge_trigger_both; - - void __iomem *base; - - struct gpio_chip gpio_chip; -}; - -static struct jz_gpio_chip jz4740_gpio_chips[]; - -static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio) -{ - return &jz4740_gpio_chips[gpio >> 5]; -} - -static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gc) -{ - return gpiochip_get_data(gc); -} - -static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(struct irq_data *data) -{ - struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); - return gc->private; -} - -static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg) -{ - writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg)); -} - -int jz_gpio_set_function(int gpio, enum jz_gpio_function function) -{ - if (function == JZ_GPIO_FUNC_NONE) { - jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR); - jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR); - jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR); - } else { - jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET); - jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR); - switch (function) { - case JZ_GPIO_FUNC1: - jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR); - break; - case JZ_GPIO_FUNC3: - jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET); - case JZ_GPIO_FUNC2: /* Falltrough */ - jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET); - break; - default: - BUG(); - break; - } - } - - return 0; -} -EXPORT_SYMBOL_GPL(jz_gpio_set_function); - -int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num) -{ - size_t i; - int ret; - - for (i = 0; i < num; ++i, ++request) { - ret = gpio_request(request->gpio, request->name); - if (ret) - goto err; - jz_gpio_set_function(request->gpio, request->function); - } - - return 0; - -err: - for (--request; i > 0; --i, --request) { - gpio_free(request->gpio); - jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE); - } - - return ret; -} -EXPORT_SYMBOL_GPL(jz_gpio_bulk_request); - -void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num) -{ - size_t i; - - for (i = 0; i < num; ++i, ++request) { - gpio_free(request->gpio); - jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE); - } - -} -EXPORT_SYMBOL_GPL(jz_gpio_bulk_free); - -void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num) -{ - size_t i; - - for (i = 0; i < num; ++i, ++request) { - jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE); - jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR); - jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET); - } -} -EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend); - -void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num) -{ - size_t i; - - for (i = 0; i < num; ++i, ++request) - jz_gpio_set_function(request->gpio, request->function); -} -EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume); - -void jz_gpio_enable_pullup(unsigned gpio) -{ - jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR); -} -EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup); - -void jz_gpio_disable_pullup(unsigned gpio) -{ - jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET); -} -EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup); - -static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio) -{ - return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio)); -} - -static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value) -{ - uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET); - reg += !value; - writel(BIT(gpio), reg); -} - -static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, - int value) -{ - writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET)); - jz_gpio_set_value(chip, gpio, value); - - return 0; -} - -static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) -{ - writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR)); - - return 0; -} - -static int jz_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) -{ - struct jz_gpio_chip *jz_gpio = gpiochip_get_data(chip); - - return jz_gpio->irq_base + gpio; -} - -int jz_gpio_port_direction_input(int port, uint32_t mask) -{ - writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR)); - - return 0; -} -EXPORT_SYMBOL(jz_gpio_port_direction_input); - -int jz_gpio_port_direction_output(int port, uint32_t mask) -{ - writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET)); - - return 0; -} -EXPORT_SYMBOL(jz_gpio_port_direction_output); - -void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask) -{ - writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR)); - writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET)); -} -EXPORT_SYMBOL(jz_gpio_port_set_value); - -uint32_t jz_gpio_port_get_value(int port, uint32_t mask) -{ - uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN)); - - return value & mask; -} -EXPORT_SYMBOL(jz_gpio_port_get_value); - -#define IRQ_TO_BIT(irq) BIT((irq - JZ4740_IRQ_GPIO(0)) & 0x1f) - -static void jz_gpio_check_trigger_both(struct jz_gpio_chip *chip, unsigned int irq) -{ - uint32_t value; - void __iomem *reg; - uint32_t mask = IRQ_TO_BIT(irq); - - if (!(chip->edge_trigger_both & mask)) - return; - - reg = chip->base; - - value = readl(chip->base + JZ_REG_GPIO_PIN); - if (value & mask) - reg += JZ_REG_GPIO_DIRECTION_CLEAR; - else - reg += JZ_REG_GPIO_DIRECTION_SET; - - writel(mask, reg); -} - -static void jz_gpio_irq_demux_handler(struct irq_desc *desc) -{ - uint32_t flag; - unsigned int gpio_irq; - struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc); - - flag = readl(chip->base + JZ_REG_GPIO_FLAG); - if (!flag) - return; - - gpio_irq = chip->irq_base + __fls(flag); - - jz_gpio_check_trigger_both(chip, gpio_irq); - - generic_handle_irq(gpio_irq); -}; - -static inline void jz_gpio_set_irq_bit(struct irq_data *data, unsigned int reg) -{ - struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); - writel(IRQ_TO_BIT(data->irq), chip->base + reg); -} - -static void jz_gpio_irq_unmask(struct irq_data *data) -{ - struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); - - jz_gpio_check_trigger_both(chip, data->irq); - irq_gc_unmask_enable_reg(data); -}; - -/* TODO: Check if function is gpio */ -static unsigned int jz_gpio_irq_startup(struct irq_data *data) -{ - jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_SET); - jz_gpio_irq_unmask(data); - return 0; -} - -static void jz_gpio_irq_shutdown(struct irq_data *data) -{ - irq_gc_mask_disable_reg(data); - - /* Set direction to input */ - jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); - jz_gpio_set_irq_bit(data, JZ_REG_GPIO_SELECT_CLEAR); -} - -static int jz_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type) -{ - struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); - unsigned int irq = data->irq; - - if (flow_type == IRQ_TYPE_EDGE_BOTH) { - uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN); - if (value & IRQ_TO_BIT(irq)) - flow_type = IRQ_TYPE_EDGE_FALLING; - else - flow_type = IRQ_TYPE_EDGE_RISING; - chip->edge_trigger_both |= IRQ_TO_BIT(irq); - } else { - chip->edge_trigger_both &= ~IRQ_TO_BIT(irq); - } - - switch (flow_type) { - case IRQ_TYPE_EDGE_RISING: - jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET); - jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET); - break; - case IRQ_TYPE_EDGE_FALLING: - jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); - jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_SET); - break; - case IRQ_TYPE_LEVEL_HIGH: - jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_SET); - jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR); - break; - case IRQ_TYPE_LEVEL_LOW: - jz_gpio_set_irq_bit(data, JZ_REG_GPIO_DIRECTION_CLEAR); - jz_gpio_set_irq_bit(data, JZ_REG_GPIO_TRIGGER_CLEAR); - break; - default: - return -EINVAL; - } - - return 0; -} - -static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on) -{ - struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(data); - - irq_gc_set_wake(data, on); - irq_set_irq_wake(chip->irq, on); - - return 0; -} - -#define JZ4740_GPIO_CHIP(_bank) { \ - .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \ - .gpio_chip = { \ - .label = "Bank " # _bank, \ - .owner = THIS_MODULE, \ - .set = jz_gpio_set_value, \ - .get = jz_gpio_get_value, \ - .direction_output = jz_gpio_direction_output, \ - .direction_input = jz_gpio_direction_input, \ - .to_irq = jz_gpio_to_irq, \ - .base = JZ4740_GPIO_BASE_ ## _bank, \ - .ngpio = JZ4740_GPIO_NUM_ ## _bank, \ - }, \ -} - -static struct jz_gpio_chip jz4740_gpio_chips[] = { - JZ4740_GPIO_CHIP(A), - JZ4740_GPIO_CHIP(B), - JZ4740_GPIO_CHIP(C), - JZ4740_GPIO_CHIP(D), -}; - -static void jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id) -{ - struct irq_chip_generic *gc; - struct irq_chip_type *ct; - - chip->base = ioremap(JZ4740_GPIO_BASE_ADDR + (id * 0x100), 0x100); - - chip->irq = JZ4740_IRQ_INTC_GPIO(id); - irq_set_chained_handler_and_data(chip->irq, - jz_gpio_irq_demux_handler, chip); - - gc = irq_alloc_generic_chip(chip->gpio_chip.label, 1, chip->irq_base, - chip->base, handle_level_irq); - - gc->wake_enabled = IRQ_MSK(chip->gpio_chip.ngpio); - gc->private = chip; - - ct = gc->chip_types; - ct->regs.enable = JZ_REG_GPIO_MASK_CLEAR; - ct->regs.disable = JZ_REG_GPIO_MASK_SET; - ct->regs.ack = JZ_REG_GPIO_FLAG_CLEAR; - - ct->chip.name = "GPIO"; - ct->chip.irq_mask = irq_gc_mask_disable_reg; - ct->chip.irq_unmask = jz_gpio_irq_unmask; - ct->chip.irq_ack = irq_gc_ack_set_bit; - ct->chip.irq_suspend = ingenic_intc_irq_suspend; - ct->chip.irq_resume = ingenic_intc_irq_resume; - ct->chip.irq_startup = jz_gpio_irq_startup; - ct->chip.irq_shutdown = jz_gpio_irq_shutdown; - ct->chip.irq_set_type = jz_gpio_irq_set_type; - ct->chip.irq_set_wake = jz_gpio_irq_set_wake; - ct->chip.flags = IRQCHIP_SET_TYPE_MASKED; - - irq_setup_generic_chip(gc, IRQ_MSK(chip->gpio_chip.ngpio), - IRQ_GC_INIT_NESTED_LOCK, 0, IRQ_NOPROBE | IRQ_LEVEL); - - gpiochip_add_data(&chip->gpio_chip, chip); -} - -static int __init jz4740_gpio_init(void) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i) - jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i); - - printk(KERN_INFO "JZ4740 GPIO initialized\n"); - - return 0; -} -arch_initcall(jz4740_gpio_init); - -#ifdef CONFIG_DEBUG_FS - -static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip, - const char *name, unsigned int reg) -{ - seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg)); -} - -static int gpio_regs_show(struct seq_file *s, void *unused) -{ - struct jz_gpio_chip *chip = jz4740_gpio_chips; - int i; - - for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) { - seq_printf(s, "==GPIO %d==\n", i); - gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN); - gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA); - gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK); - gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL); - gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC); - gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT); - gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION); - gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER); - gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG); - } - - return 0; -} - -static int gpio_regs_open(struct inode *inode, struct file *file) -{ - return single_open(file, gpio_regs_show, NULL); -} - -static const struct file_operations gpio_regs_operations = { - .open = gpio_regs_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -static int __init gpio_debugfs_init(void) -{ - (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO, - NULL, NULL, &gpio_regs_operations); - return 0; -} -subsys_initcall(gpio_debugfs_init); - -#endif diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 23ca51ee6b28..395c85df48fd 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -242,6 +242,17 @@ config GPIO_ICH If unsure, say N. +config GPIO_INGENIC + tristate "Ingenic JZ47xx SoCs GPIO support" + depends on OF + depends on MACH_INGENIC || COMPILE_TEST + select GPIOLIB_IRQCHIP + help + Say yes here to support the GPIO functionality present on the + JZ4740 and JZ4780 SoCs from Ingenic. + + If unsure, say N. + config GPIO_IOP tristate "Intel IOP GPIO" depends on ARCH_IOP32X || ARCH_IOP33X || COMPILE_TEST @@ -1227,23 +1238,6 @@ config GPIO_PISOSR endmenu -menu "SPI or I2C GPIO expanders" - depends on (SPI_MASTER && !I2C) || I2C - -config GPIO_MCP23S08 - tristate "Microchip MCP23xxx I/O expander" - depends on OF_GPIO - select GPIOLIB_IRQCHIP - select REGMAP_I2C if I2C - select REGMAP if SPI_MASTER - help - SPI/I2C driver for Microchip MCP23S08/MCP23S17/MCP23008/MCP23017 - I/O expanders. - This provides a GPIO interface supporting inputs and outputs. - The I2C versions of the chips can be used as interrupt-controller. - -endmenu - menu "USB GPIO expanders" depends on USB diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 68b96277d9fa..845f990fc987 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -55,6 +55,7 @@ obj-$(CONFIG_GPIO_GPIO_MM) += gpio-gpio-mm.o obj-$(CONFIG_GPIO_GRGPIO) += gpio-grgpio.o obj-$(CONFIG_HTC_EGPIO) += gpio-htc-egpio.o obj-$(CONFIG_GPIO_ICH) += gpio-ich.o +obj-$(CONFIG_GPIO_INGENIC) += gpio-ingenic.o obj-$(CONFIG_GPIO_IOP) += gpio-iop.o obj-$(CONFIG_GPIO_IT87) += gpio-it87.o obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o @@ -77,7 +78,6 @@ obj-$(CONFIG_GPIO_MENZ127) += gpio-menz127.o obj-$(CONFIG_GPIO_MERRIFIELD) += gpio-merrifield.o obj-$(CONFIG_GPIO_MC33880) += gpio-mc33880.o obj-$(CONFIG_GPIO_MC9S08DZ60) += gpio-mc9s08dz60.o -obj-$(CONFIG_GPIO_MCP23S08) += gpio-mcp23s08.o obj-$(CONFIG_GPIO_ML_IOH) += gpio-ml-ioh.o obj-$(CONFIG_GPIO_MM_LANTIQ) += gpio-mm-lantiq.o obj-$(CONFIG_GPIO_MOCKUP) += gpio-mockup.o diff --git a/drivers/gpio/gpio-ingenic.c b/drivers/gpio/gpio-ingenic.c new file mode 100644 index 000000000000..254780730b95 --- /dev/null +++ b/drivers/gpio/gpio-ingenic.c @@ -0,0 +1,394 @@ +/* + * Ingenic JZ47xx GPIO driver + * + * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <linux/gpio/driver.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/of_irq.h> +#include <linux/pinctrl/consumer.h> +#include <linux/regmap.h> + +#define GPIO_PIN 0x00 +#define GPIO_MSK 0x20 + +#define JZ4740_GPIO_DATA 0x10 +#define JZ4740_GPIO_SELECT 0x50 +#define JZ4740_GPIO_DIR 0x60 +#define JZ4740_GPIO_TRIG 0x70 +#define JZ4740_GPIO_FLAG 0x80 + +#define JZ4770_GPIO_INT 0x10 +#define JZ4770_GPIO_PAT1 0x30 +#define JZ4770_GPIO_PAT0 0x40 +#define JZ4770_GPIO_FLAG 0x50 + +#define REG_SET(x) ((x) + 0x4) +#define REG_CLEAR(x) ((x) + 0x8) + +enum jz_version { + ID_JZ4740, + ID_JZ4770, + ID_JZ4780, +}; + +struct ingenic_gpio_chip { + struct regmap *map; + struct gpio_chip gc; + struct irq_chip irq_chip; + unsigned int irq, reg_base; + enum jz_version version; +}; + +static u32 gpio_ingenic_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) +{ + unsigned int val; + + regmap_read(jzgc->map, jzgc->reg_base + reg, &val); + + return (u32) val; +} + +static void gpio_ingenic_set_bit(struct ingenic_gpio_chip *jzgc, + u8 reg, u8 offset, bool set) +{ + if (set) + reg = REG_SET(reg); + else + reg = REG_CLEAR(reg); + + regmap_write(jzgc->map, jzgc->reg_base + reg, BIT(offset)); +} + +static inline bool gpio_get_value(struct ingenic_gpio_chip *jzgc, u8 offset) +{ + unsigned int val = gpio_ingenic_read_reg(jzgc, GPIO_PIN); + + return !!(val & BIT(offset)); +} + +static void gpio_set_value(struct ingenic_gpio_chip *jzgc, u8 offset, int value) +{ + if (jzgc->version >= ID_JZ4770) + gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value); + else + gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); +} + +static void irq_set_type(struct ingenic_gpio_chip *jzgc, + u8 offset, unsigned int type) +{ + u8 reg1, reg2; + + if (jzgc->version >= ID_JZ4770) { + reg1 = JZ4770_GPIO_PAT1; + reg2 = JZ4770_GPIO_PAT0; + } else { + reg1 = JZ4740_GPIO_TRIG; + reg2 = JZ4740_GPIO_DIR; + } + + switch (type) { + case IRQ_TYPE_EDGE_RISING: + gpio_ingenic_set_bit(jzgc, reg2, offset, true); + gpio_ingenic_set_bit(jzgc, reg1, offset, true); + break; + case IRQ_TYPE_EDGE_FALLING: + gpio_ingenic_set_bit(jzgc, reg2, offset, false); + gpio_ingenic_set_bit(jzgc, reg1, offset, true); + break; + case IRQ_TYPE_LEVEL_HIGH: + gpio_ingenic_set_bit(jzgc, reg2, offset, true); + gpio_ingenic_set_bit(jzgc, reg1, offset, false); + break; + case IRQ_TYPE_LEVEL_LOW: + default: + gpio_ingenic_set_bit(jzgc, reg2, offset, false); + gpio_ingenic_set_bit(jzgc, reg1, offset, false); + break; + } +} + +static void ingenic_gpio_irq_mask(struct irq_data *irqd) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); + + gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true); +} + +static void ingenic_gpio_irq_unmask(struct irq_data *irqd) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); + + gpio_ingenic_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false); +} + +static void ingenic_gpio_irq_enable(struct irq_data *irqd) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); + int irq = irqd->hwirq; + + if (jzgc->version >= ID_JZ4770) + gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, true); + else + gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); + + ingenic_gpio_irq_unmask(irqd); +} + +static void ingenic_gpio_irq_disable(struct irq_data *irqd) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); + int irq = irqd->hwirq; + + ingenic_gpio_irq_mask(irqd); + + if (jzgc->version >= ID_JZ4770) + gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_INT, irq, false); + else + gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); +} + +static void ingenic_gpio_irq_ack(struct irq_data *irqd) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); + int irq = irqd->hwirq; + bool high; + + if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) { + /* + * Switch to an interrupt for the opposite edge to the one that + * triggered the interrupt being ACKed. + */ + high = gpio_get_value(jzgc, irq); + if (high) + irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_FALLING); + else + irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING); + } + + if (jzgc->version >= ID_JZ4770) + gpio_ingenic_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false); + else + gpio_ingenic_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); +} + +static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); + + switch (type) { + case IRQ_TYPE_EDGE_BOTH: + case IRQ_TYPE_EDGE_RISING: + case IRQ_TYPE_EDGE_FALLING: + irq_set_handler_locked(irqd, handle_edge_irq); + break; + case IRQ_TYPE_LEVEL_HIGH: + case IRQ_TYPE_LEVEL_LOW: + irq_set_handler_locked(irqd, handle_level_irq); + break; + default: + irq_set_handler_locked(irqd, handle_bad_irq); + } + + if (type == IRQ_TYPE_EDGE_BOTH) { + /* + * The hardware does not support interrupts on both edges. The + * best we can do is to set up a single-edge interrupt and then + * switch to the opposing edge when ACKing the interrupt. + */ + bool high = gpio_get_value(jzgc, irqd->hwirq); + + type = high ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING; + } + + irq_set_type(jzgc, irqd->hwirq, type); + return 0; +} + +static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on) +{ + struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); + struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); + + return irq_set_irq_wake(jzgc->irq, on); +} + +static void ingenic_gpio_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); + struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); + unsigned long flag, i; + + chained_irq_enter(irq_chip, desc); + + if (jzgc->version >= ID_JZ4770) + flag = gpio_ingenic_read_reg(jzgc, JZ4770_GPIO_FLAG); + else + flag = gpio_ingenic_read_reg(jzgc, JZ4740_GPIO_FLAG); + + for_each_set_bit(i, &flag, 32) + generic_handle_irq(irq_linear_revmap(gc->irqdomain, i)); + chained_irq_exit(irq_chip, desc); +} + +static void ingenic_gpio_set(struct gpio_chip *gc, + unsigned int offset, int value) +{ + struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); + + gpio_set_value(jzgc, offset, value); +} + +static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset) +{ + struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); + + return (int) gpio_get_value(jzgc, offset); +} + +static int ingenic_gpio_direction_input(struct gpio_chip *gc, + unsigned int offset) +{ + return pinctrl_gpio_direction_input(gc->base + offset); +} + +static int ingenic_gpio_direction_output(struct gpio_chip *gc, + unsigned int offset, int value) +{ + ingenic_gpio_set(gc, offset, value); + return pinctrl_gpio_direction_output(gc->base + offset); +} + +static const struct of_device_id ingenic_gpio_of_match[] = { + { .compatible = "ingenic,jz4740-gpio", .data = (void *)ID_JZ4740 }, + { .compatible = "ingenic,jz4770-gpio", .data = (void *)ID_JZ4770 }, + { .compatible = "ingenic,jz4780-gpio", .data = (void *)ID_JZ4780 }, + {}, +}; +MODULE_DEVICE_TABLE(of, ingenic_gpio_of_match); + +static int ingenic_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + const struct of_device_id *of_id = of_match_device( + ingenic_gpio_of_match, dev); + struct ingenic_gpio_chip *jzgc; + u32 bank; + int err; + + jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL); + if (!jzgc) + return -ENOMEM; + + jzgc->map = dev_get_drvdata(dev->parent); + if (!jzgc->map) { + dev_err(dev, "Cannot get parent regmap\n"); + return -ENXIO; + } + + err = of_property_read_u32(dev->of_node, "reg", &bank); + if (err) { + dev_err(dev, "Cannot read \"reg\" property: %i\n", err); + return err; + } + + jzgc->reg_base = bank * 0x100; + + jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); + if (!jzgc->gc.label) + return -ENOMEM; + + /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY + * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN + * <linux/gpio/consumer.h> INSTEAD. + */ + jzgc->gc.base = bank * 32; + + jzgc->gc.ngpio = 32; + jzgc->gc.parent = dev; + jzgc->gc.of_node = dev->of_node; + jzgc->gc.owner = THIS_MODULE; + jzgc->version = (enum jz_version)of_id->data; + + jzgc->gc.set = ingenic_gpio_set; + jzgc->gc.get = ingenic_gpio_get; + jzgc->gc.direction_input = ingenic_gpio_direction_input; + jzgc->gc.direction_output = ingenic_gpio_direction_output; + + if (of_property_read_bool(dev->of_node, "gpio-ranges")) { + jzgc->gc.request = gpiochip_generic_request; + jzgc->gc.free = gpiochip_generic_free; + } + + err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); + if (err) + return err; + + jzgc->irq = irq_of_parse_and_map(dev->of_node, 0); + if (!jzgc->irq) + return -EINVAL; + + jzgc->irq_chip.name = jzgc->gc.label; + jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable; + jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable; + jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask; + jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask; + jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack; + jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type; + jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake; + jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; + + err = gpiochip_irqchip_add(&jzgc->gc, &jzgc->irq_chip, 0, + handle_level_irq, IRQ_TYPE_NONE); + if (err) + return err; + + gpiochip_set_chained_irqchip(&jzgc->gc, &jzgc->irq_chip, + jzgc->irq, ingenic_gpio_irq_handler); + return 0; +} + +static int ingenic_gpio_remove(struct platform_device *pdev) +{ + return 0; +} + +static struct platform_driver ingenic_gpio_driver = { + .driver = { + .name = "gpio-ingenic", + .of_match_table = of_match_ptr(ingenic_gpio_of_match), + }, + .probe = ingenic_gpio_probe, + .remove = ingenic_gpio_remove, +}; + +static int __init ingenic_gpio_drv_register(void) +{ + return platform_driver_register(&ingenic_gpio_driver); +} +subsys_initcall(ingenic_gpio_drv_register); + +static void __exit ingenic_gpio_drv_unregister(void) +{ + platform_driver_unregister(&ingenic_gpio_driver); +} +module_exit(ingenic_gpio_drv_unregister); + +MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>"); +MODULE_DESCRIPTION("Ingenic JZ47xx GPIO driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c index 57e254aac48d..7db8c7a8d38d 100644 --- a/drivers/mmc/host/jz4740_mmc.c +++ b/drivers/mmc/host/jz4740_mmc.c @@ -20,6 +20,7 @@ #include <linux/irq.h> #include <linux/interrupt.h> #include <linux/module.h> +#include <linux/pinctrl/consumer.h> #include <linux/platform_device.h> #include <linux/delay.h> #include <linux/scatterlist.h> @@ -27,7 +28,6 @@ #include <linux/bitops.h> #include <linux/gpio.h> -#include <asm/mach-jz4740/gpio.h> #include <asm/cacheflush.h> #include <linux/dma-mapping.h> #include <linux/dmaengine.h> @@ -901,15 +901,6 @@ static const struct mmc_host_ops jz4740_mmc_ops = { .enable_sdio_irq = jz4740_mmc_enable_sdio_irq, }; -static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = { - JZ_GPIO_BULK_PIN(MSC_CMD), - JZ_GPIO_BULK_PIN(MSC_CLK), - JZ_GPIO_BULK_PIN(MSC_DATA0), - JZ_GPIO_BULK_PIN(MSC_DATA1), - JZ_GPIO_BULK_PIN(MSC_DATA2), - JZ_GPIO_BULK_PIN(MSC_DATA3), -}; - static int jz4740_mmc_request_gpio(struct device *dev, int gpio, const char *name, bool output, int value) { @@ -973,15 +964,6 @@ static void jz4740_mmc_free_gpios(struct platform_device *pdev) gpio_free(pdata->gpio_power); } -static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host) -{ - size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins); - if (host->pdata && host->pdata->data_1bit) - num_pins -= 3; - - return num_pins; -} - static int jz4740_mmc_probe(struct platform_device* pdev) { int ret; @@ -1022,15 +1004,9 @@ static int jz4740_mmc_probe(struct platform_device* pdev) goto err_free_host; } - ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); - if (ret) { - dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret); - goto err_free_host; - } - ret = jz4740_mmc_request_gpios(mmc, pdev); if (ret) - goto err_gpio_bulk_free; + goto err_release_dma; mmc->ops = &jz4740_mmc_ops; mmc->f_min = JZ_MMC_CLK_RATE / 128; @@ -1086,10 +1062,9 @@ err_free_irq: free_irq(host->irq, host); err_free_gpios: jz4740_mmc_free_gpios(pdev); -err_gpio_bulk_free: +err_release_dma: if (host->use_dma) jz4740_mmc_release_dma_channels(host); - jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); err_free_host: mmc_free_host(mmc); @@ -1109,7 +1084,6 @@ static int jz4740_mmc_remove(struct platform_device *pdev) free_irq(host->irq, host); jz4740_mmc_free_gpios(pdev); - jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); if (host->use_dma) jz4740_mmc_release_dma_channels(host); @@ -1123,20 +1097,12 @@ static int jz4740_mmc_remove(struct platform_device *pdev) static int jz4740_mmc_suspend(struct device *dev) { - struct jz4740_mmc_host *host = dev_get_drvdata(dev); - - jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); - - return 0; + return pinctrl_pm_select_sleep_state(dev); } static int jz4740_mmc_resume(struct device *dev) { - struct jz4740_mmc_host *host = dev_get_drvdata(dev); - - jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); - - return 0; + return pinctrl_pm_select_default_state(dev); } static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend, diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c index 5551c36adbdf..0d06a1f07d82 100644 --- a/drivers/mtd/nand/jz4740_nand.c +++ b/drivers/mtd/nand/jz4740_nand.c @@ -25,7 +25,6 @@ #include <linux/gpio.h> -#include <asm/mach-jz4740/gpio.h> #include <asm/mach-jz4740/jz4740_nand.h> #define JZ_REG_NAND_CTRL 0x50 @@ -310,34 +309,20 @@ static int jz_nand_detect_bank(struct platform_device *pdev, uint8_t *nand_dev_id) { int ret; - int gpio; - char gpio_name[9]; char res_name[6]; uint32_t ctrl; struct nand_chip *chip = &nand->chip; struct mtd_info *mtd = nand_to_mtd(chip); - /* Request GPIO port. */ - gpio = JZ_GPIO_MEM_CS0 + bank - 1; - sprintf(gpio_name, "NAND CS%d", bank); - ret = gpio_request(gpio, gpio_name); - if (ret) { - dev_warn(&pdev->dev, - "Failed to request %s gpio %d: %d\n", - gpio_name, gpio, ret); - goto notfound_gpio; - } - /* Request I/O resource. */ sprintf(res_name, "bank%d", bank); ret = jz_nand_ioremap_resource(pdev, res_name, &nand->bank_mem[bank - 1], &nand->bank_base[bank - 1]); if (ret) - goto notfound_resource; + return ret; /* Enable chip in bank. */ - jz_gpio_set_function(gpio, JZ_GPIO_FUNC_MEM_CS0); ctrl = readl(nand->base + JZ_REG_NAND_CTRL); ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1); writel(ctrl, nand->base + JZ_REG_NAND_CTRL); @@ -377,12 +362,8 @@ notfound_id: dev_info(&pdev->dev, "No chip found on bank %i\n", bank); ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1)); writel(ctrl, nand->base + JZ_REG_NAND_CTRL); - jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE); jz_nand_iounmap_resource(nand->bank_mem[bank - 1], nand->bank_base[bank - 1]); -notfound_resource: - gpio_free(gpio); -notfound_gpio: return ret; } @@ -503,7 +484,6 @@ err_nand_release: err_unclaim_banks: while (chipnr--) { unsigned char bank = nand->banks[chipnr]; - gpio_free(JZ_GPIO_MEM_CS0 + bank - 1); jz_nand_iounmap_resource(nand->bank_mem[bank - 1], nand->bank_base[bank - 1]); } @@ -530,7 +510,6 @@ static int jz_nand_remove(struct platform_device *pdev) if (bank != 0) { jz_nand_iounmap_resource(nand->bank_mem[bank - 1], nand->bank_base[bank - 1]); - gpio_free(JZ_GPIO_MEM_CS0 + bank - 1); } } diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 37af5e3029d5..e14b46c7b37f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -146,6 +146,20 @@ config PINCTRL_FALCON depends on SOC_FALCON depends on PINCTRL_LANTIQ +config PINCTRL_MCP23S08 + tristate "Microchip MCP23xxx I/O expander" + depends on SPI_MASTER || I2C + depends on I2C || I2C=n + select GPIOLIB_IRQCHIP + select REGMAP_I2C if I2C + select REGMAP_SPI if SPI_MASTER + select GENERIC_PINCONF + help + SPI/I2C driver for Microchip MCP23S08/MCP23S17/MCP23008/MCP23017 + I/O expanders. + This provides a GPIO interface supporting inputs and outputs. + The I2C versions of the chips can be used as interrupt-controller. + config PINCTRL_MESON bool depends on OF @@ -174,6 +188,17 @@ config PINCTRL_ROCKCHIP select GENERIC_IRQ_CHIP select MFD_SYSCON +config PINCTRL_RZA1 + bool "Renesas RZ/A1 gpio and pinctrl driver" + depends on OF + depends on ARCH_R7S72100 || COMPILE_TEST + select GPIOLIB + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + help + This selects pinctrl driver for Renesas RZ/A1 platforms. + config PINCTRL_SINGLE tristate "One-register-per-pin type device tree based pinctrl driver" depends on OF @@ -296,6 +321,16 @@ config PINCTRL_ZYNQ help This selects the pinctrl driver for Xilinx Zynq. +config PINCTRL_INGENIC + bool "Pinctrl driver for the Ingenic JZ47xx SoCs" + default y + depends on OF + depends on MACH_INGENIC || COMPILE_TEST + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select REGMAP_MMIO + source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig" source "drivers/pinctrl/berlin/Kconfig" @@ -315,6 +350,7 @@ source "drivers/pinctrl/ti/Kconfig" source "drivers/pinctrl/uniphier/Kconfig" source "drivers/pinctrl/vt8500/Kconfig" source "drivers/pinctrl/mediatek/Kconfig" +source "drivers/pinctrl/zte/Kconfig" config PINCTRL_XWAY bool diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 0e9b2226a7c2..2bc641d62400 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -19,12 +19,14 @@ obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o +obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o obj-$(CONFIG_PINCTRL_MESON) += meson/ obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o +obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_SIRF) += sirf/ obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o @@ -39,6 +41,7 @@ obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o +obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o obj-$(CONFIG_ARCH_ASPEED) += aspeed/ obj-y += bcm/ @@ -58,3 +61,4 @@ obj-y += ti/ obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_ARCH_VT8500) += vt8500/ obj-$(CONFIG_PINCTRL_MTK) += mediatek/ +obj-$(CONFIG_PINCTRL_ZX) += zte/ diff --git a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c index 810a81786f62..a7cceffcedfa 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2013 Broadcom Corporation + * Copyright (C) 2013-2017 Broadcom * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -10,9 +10,10 @@ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + #include <linux/err.h> #include <linux/io.h> -#include <linux/module.h> +#include <linux/init.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> @@ -1444,10 +1445,4 @@ static struct platform_driver bcm281xx_pinctrl_driver = { .of_match_table = bcm281xx_pinctrl_of_match, }, }; - -module_platform_driver_probe(bcm281xx_pinctrl_driver, bcm281xx_pinctrl_probe); - -MODULE_AUTHOR("Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>"); -MODULE_AUTHOR("Sherman Yin <syin@broadcom.com>"); -MODULE_DESCRIPTION("Broadcom BCM281xx pinctrl driver"); -MODULE_LICENSE("GPL v2"); +builtin_platform_driver_probe(bcm281xx_pinctrl_driver, bcm281xx_pinctrl_probe); diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index 85d009112864..230883168e99 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -27,7 +27,7 @@ #include <linux/io.h> #include <linux/irq.h> #include <linux/irqdesc.h> -#include <linux/module.h> +#include <linux/init.h> #include <linux/of_address.h> #include <linux/of.h> #include <linux/of_irq.h> @@ -1048,6 +1048,10 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) for (i = 0; i < BCM2835_NUM_IRQS; i++) { pc->irq[i] = irq_of_parse_and_map(np, i); pc->irq_group[i] = i; + + if (pc->irq[i] == 0) + continue; + /* * Use the same handler for all groups: this is necessary * since we use one gpiochip to cover all lines - the @@ -1075,31 +1079,17 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) return 0; } -static int bcm2835_pinctrl_remove(struct platform_device *pdev) -{ - struct bcm2835_pinctrl *pc = platform_get_drvdata(pdev); - - gpiochip_remove(&pc->gpio_chip); - - return 0; -} - static const struct of_device_id bcm2835_pinctrl_match[] = { { .compatible = "brcm,bcm2835-gpio" }, {} }; -MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match); static struct platform_driver bcm2835_pinctrl_driver = { .probe = bcm2835_pinctrl_probe, - .remove = bcm2835_pinctrl_remove, .driver = { .name = MODULE_NAME, .of_match_table = bcm2835_pinctrl_match, + .suppress_bind_attrs = true, }, }; -module_platform_driver(bcm2835_pinctrl_driver); - -MODULE_AUTHOR("Chris Boot, Simon Arlott, Stephen Warren"); -MODULE_DESCRIPTION("BCM2835 Pin control driver"); -MODULE_LICENSE("GPL"); +builtin_platform_driver(bcm2835_pinctrl_driver); diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c b/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c index d31c95701a92..44df35942a43 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c @@ -1,4 +1,5 @@ -/* Copyright (C) 2014-2015 Broadcom Corporation +/* + * Copyright (C) 2014-2017 Broadcom * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -8,6 +9,10 @@ * kind, whether express or implied; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. + */ + +/* + * Broadcom Cygnus IOMUX driver * * This file contains the Cygnus IOMUX driver that supports group based PINMUX * configuration. Although PINMUX configuration is mainly group based, the @@ -17,7 +22,6 @@ #include <linux/err.h> #include <linux/io.h> -#include <linux/module.h> #include <linux/of.h> #include <linux/slab.h> #include <linux/platform_device.h> @@ -1016,7 +1020,3 @@ static int __init cygnus_pinmux_init(void) return platform_driver_register(&cygnus_pinmux_driver); } arch_initcall(cygnus_pinmux_init); - -MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>"); -MODULE_DESCRIPTION("Broadcom Cygnus IOMUX driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index af5e904d4a1e..85a8c97d9dfe 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014-2015 Broadcom Corporation + * Copyright (C) 2014-2017 Broadcom * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -9,7 +9,9 @@ * kind, whether express or implied; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ + +/* * This file contains the Broadcom Iproc GPIO driver that supports 3 * GPIO controllers on Iproc including the ASIU GPIO controller, the * chipCommonG GPIO controller, and the always-on GPIO controller. Basic diff --git a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c index 22442438275a..1cfe45fd391f 100644 --- a/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-nsp-gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Broadcom Corporation + * Copyright (C) 2014-2017 Broadcom * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -9,7 +9,9 @@ * kind, whether express or implied; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * + */ + +/* * This file contains the Broadcom Northstar Plus (NSP) GPIO driver that * supports the chipCommonA GPIO controller. Basic PINCONF such as bias, * pull up/down, slew and drive strength are also supported in this driver. diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index bd459a93b0e7..c5e2c5705058 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -170,7 +170,7 @@ const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin) const struct pin_desc *desc; desc = pin_desc_get(pctldev, pin); - if (desc == NULL) { + if (!desc) { dev_err(pctldev->dev, "failed to get pin(%d) name\n", pin); return NULL; @@ -214,7 +214,7 @@ static void pinctrl_free_pindescs(struct pinctrl_dev *pctldev, pindesc = radix_tree_lookup(&pctldev->pin_desc_tree, pins[i].number); - if (pindesc != NULL) { + if (pindesc) { radix_tree_delete(&pctldev->pin_desc_tree, pins[i].number); if (pindesc->dynamic_name) @@ -230,7 +230,7 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev, struct pin_desc *pindesc; pindesc = pin_desc_get(pctldev, pin->number); - if (pindesc != NULL) { + if (pindesc) { dev_err(pctldev->dev, "pin %d already registered\n", pin->number); return -EINVAL; @@ -248,7 +248,7 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev, pindesc->name = pin->name; } else { pindesc->name = kasprintf(GFP_KERNEL, "PIN%u", pin->number); - if (pindesc->name == NULL) { + if (!pindesc->name) { kfree(pindesc); return -ENOMEM; } @@ -402,7 +402,7 @@ static int pinctrl_get_device_gpio_range(unsigned gpio, struct pinctrl_gpio_range *range; range = pinctrl_match_gpio_range(pctldev, gpio); - if (range != NULL) { + if (range) { *outdev = pctldev; *outrange = range; mutex_unlock(&pinctrldev_list_mutex); @@ -933,7 +933,7 @@ static int add_setting(struct pinctrl *p, struct pinctrl_dev *pctldev, else setting->pctldev = get_pinctrl_dev_from_devname(map->ctrl_dev_name); - if (setting->pctldev == NULL) { + if (!setting->pctldev) { kfree(setting); /* Do not defer probing of hogs (circular loop) */ if (!strcmp(map->ctrl_dev_name, map->dev_name)) @@ -1024,6 +1024,16 @@ static struct pinctrl *create_pinctrl(struct device *dev, /* Map must be for this device */ if (strcmp(map->dev_name, devname)) continue; + /* + * If pctldev is not null, we are claiming hog for it, + * that means, setting that is served by pctldev by itself. + * + * Thus we must skip map that is for this device but is served + * by other device. + */ + if (pctldev && + strcmp(dev_name(pctldev->dev), map->ctrl_dev_name)) + continue; ret = add_setting(p, pctldev, map); /* @@ -1080,7 +1090,7 @@ struct pinctrl *pinctrl_get(struct device *dev) * return another pointer to it. */ p = find_pinctrl(dev); - if (p != NULL) { + if (p) { dev_dbg(dev, "obtain a copy of previously claimed pinctrl\n"); kref_get(&p->users); return p; @@ -1551,7 +1561,7 @@ static int pinctrl_pins_show(struct seq_file *s, void *what) pin = pctldev->desc->pins[i].number; desc = pin_desc_get(pctldev, pin); /* Pin space may be sparse */ - if (desc == NULL) + if (!desc) continue; seq_printf(s, "pin %d (%s) ", pin, desc->name); @@ -1718,7 +1728,7 @@ static int pinctrl_maps_show(struct seq_file *s, void *what) break; } - seq_printf(s, "\n"); + seq_putc(s, '\n'); } mutex_unlock(&pinctrl_maps_mutex); @@ -2131,7 +2141,7 @@ void pinctrl_unregister(struct pinctrl_dev *pctldev) { struct pinctrl_gpio_range *range, *n; - if (pctldev == NULL) + if (!pctldev) return; mutex_lock(&pctldev->mutex); diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index cae05e76c111..0b266b2aecd4 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -2,7 +2,7 @@ config PINCTRL_IMX bool select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS - select PINCONF + select GENERIC_PINCONF select REGMAP config PINCTRL_IMX1_CORE diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 74bd90dfd7b1..72aca758f4c6 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -27,6 +27,7 @@ #include <linux/regmap.h> #include "../core.h" +#include "../pinconf.h" #include "../pinmux.h" #include "pinctrl-imx.h" @@ -196,14 +197,16 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, if (info->flags & SHARE_MUX_CONF_REG) { u32 reg; reg = readl(ipctl->base + pin_reg->mux_reg); - reg &= ~(0x7 << 20); - reg |= (pin->mux_mode << 20); + reg &= ~info->mux_mask; + reg |= (pin->mux_mode << info->mux_shift); writel(reg, ipctl->base + pin_reg->mux_reg); + dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", + pin_reg->mux_reg, reg); } else { writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); + dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", + pin_reg->mux_reg, pin->mux_mode); } - dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", - pin_reg->mux_reg, pin->mux_mode); /* * If the select input value begins with 0xff, it's a quirky @@ -287,7 +290,7 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, mux_pin: reg = readl(ipctl->base + pin_reg->mux_reg); - reg &= ~(0x7 << 20); + reg &= ~info->mux_mask; reg |= imx_pin->config; writel(reg, ipctl->base + pin_reg->mux_reg); @@ -359,6 +362,62 @@ static const struct pinmux_ops imx_pmx_ops = { .gpio_set_direction = imx_pmx_gpio_set_direction, }; +/* decode generic config into raw register values */ +static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl, + unsigned long *configs, + unsigned int num_configs) +{ + struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_cfg_params_decode *decode; + enum pin_config_param param; + u32 raw_config = 0; + u32 param_val; + int i, j; + + WARN_ON(num_configs > info->num_decodes); + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + param_val = pinconf_to_config_argument(configs[i]); + decode = info->decodes; + for (j = 0; j < info->num_decodes; j++) { + if (param == decode->param) { + if (decode->invert) + param_val = !param_val; + raw_config |= (param_val << decode->shift) + & decode->mask; + break; + } + decode++; + } + } + + if (info->fixup) + info->fixup(configs, num_configs, &raw_config); + + return raw_config; +} + +static u32 imx_pinconf_parse_generic_config(struct device_node *np, + struct imx_pinctrl *ipctl) +{ + struct imx_pinctrl_soc_info *info = ipctl->info; + struct pinctrl_dev *pctl = ipctl->pctl; + unsigned int num_configs; + unsigned long *configs; + int ret; + + if (!info->generic_pinconf) + return 0; + + ret = pinconf_generic_parse_dt_config(np, pctl, &configs, + &num_configs); + if (ret) + return 0; + + return imx_pinconf_decode_generic_config(ipctl, configs, num_configs); +} + static int imx_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin_id, unsigned long *config) { @@ -375,7 +434,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, *config = readl(ipctl->base + pin_reg->conf_reg); if (info->flags & SHARE_MUX_CONF_REG) - *config &= 0xffff; + *config &= ~info->mux_mask; return 0; } @@ -402,14 +461,16 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev, if (info->flags & SHARE_MUX_CONF_REG) { u32 reg; reg = readl(ipctl->base + pin_reg->conf_reg); - reg &= ~0xffff; + reg &= info->mux_mask; reg |= configs[i]; writel(reg, ipctl->base + pin_reg->conf_reg); + dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", + pin_reg->conf_reg, reg); } else { writel(configs[i], ipctl->base + pin_reg->conf_reg); + dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", + pin_reg->conf_reg, configs[i]); } - dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", - pin_reg->conf_reg, configs[i]); } /* for each config */ return 0; @@ -475,9 +536,10 @@ static const struct pinconf_ops imx_pinconf_ops = { static int imx_pinctrl_parse_groups(struct device_node *np, struct group_desc *grp, - struct imx_pinctrl_soc_info *info, + struct imx_pinctrl *ipctl, u32 index) { + struct imx_pinctrl_soc_info *info = ipctl->info; int size, pin_size; const __be32 *list; int i; @@ -489,25 +551,44 @@ static int imx_pinctrl_parse_groups(struct device_node *np, pin_size = SHARE_FSL_PIN_SIZE; else pin_size = FSL_PIN_SIZE; + + if (info->generic_pinconf) + pin_size -= 4; + /* Initialise group */ grp->name = np->name; /* * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>, * do sanity check and calculate pins number + * + * First try legacy 'fsl,pins' property, then fall back to the + * generic 'pins'. + * + * Note: for generic 'pins' case, there's no CONFIG part in + * the binding format. */ list = of_get_property(np, "fsl,pins", &size); if (!list) { - dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name); - return -EINVAL; + list = of_get_property(np, "pins", &size); + if (!list) { + dev_err(info->dev, + "no fsl,pins and pins property in node %s\n", + np->full_name); + return -EINVAL; + } } /* we do not check return since it's safe node passed down */ if (!size || size % pin_size) { - dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name); + dev_err(info->dev, "Invalid fsl,pins or pins property in node %s\n", + np->full_name); return -EINVAL; } + /* first try to parse the generic pin config */ + config = imx_pinconf_parse_generic_config(np, ipctl); + grp->num_pins = size / pin_size; grp->data = devm_kzalloc(info->dev, grp->num_pins * sizeof(struct imx_pin), GFP_KERNEL); @@ -544,11 +625,18 @@ static int imx_pinctrl_parse_groups(struct device_node *np, pin->mux_mode = be32_to_cpu(*list++); pin->input_val = be32_to_cpu(*list++); - /* SION bit is in mux register */ - config = be32_to_cpu(*list++); - if (config & IMX_PAD_SION) - pin->mux_mode |= IOMUXC_CONFIG_SION; - pin->config = config & ~IMX_PAD_SION; + if (info->generic_pinconf) { + /* generic pin config decoded */ + pin->config = config; + } else { + /* legacy pin config read from devicetree */ + config = be32_to_cpu(*list++); + + /* SION bit is in mux register */ + if (config & IMX_PAD_SION) + pin->mux_mode |= IOMUXC_CONFIG_SION; + pin->config = config & ~IMX_PAD_SION; + } dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, pin->mux_mode, pin->config); @@ -581,9 +669,10 @@ static int imx_pinctrl_parse_functions(struct device_node *np, dev_err(info->dev, "no groups defined in %s\n", np->full_name); return -EINVAL; } - func->group_names = devm_kzalloc(info->dev, - func->num_group_names * + func->group_names = devm_kcalloc(info->dev, func->num_group_names, sizeof(char *), GFP_KERNEL); + if (!func->group_names) + return -ENOMEM; for_each_child_of_node(np, child) { func->group_names[i] = child->name; @@ -598,7 +687,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np, info->group_index++, grp); mutex_unlock(&info->mutex); - imx_pinctrl_parse_groups(child, grp, info, i++); + imx_pinctrl_parse_groups(child, grp, ipctl, i++); } return 0; @@ -769,6 +858,10 @@ int imx_pinctrl_probe(struct platform_device *pdev, imx_pinctrl_desc->confops = &imx_pinconf_ops; imx_pinctrl_desc->owner = THIS_MODULE; + /* for generic pinconf */ + imx_pinctrl_desc->custom_params = info->custom_params; + imx_pinctrl_desc->num_custom_params = info->num_custom_params; + mutex_init(&info->mutex); ipctl->info = info; diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index ff2d3e56b7c5..880bba7fd1ab 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -15,6 +15,8 @@ #ifndef __DRIVERS_PINCTRL_IMX_H #define __DRIVERS_PINCTRL_IMX_H +#include <linux/pinctrl/pinconf-generic.h> + struct platform_device; /** @@ -44,6 +46,14 @@ struct imx_pin_reg { s16 conf_reg; }; +/* decode a generic config into raw register value */ +struct imx_cfg_params_decode { + enum pin_config_param param; + u32 mask; + u8 shift; + bool invert; +}; + struct imx_pinctrl_soc_info { struct device *dev; const struct pinctrl_pin_desc *pins; @@ -53,8 +63,27 @@ struct imx_pinctrl_soc_info { unsigned int flags; const char *gpr_compatible; struct mutex mutex; + + /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */ + unsigned int mux_mask; + u8 mux_shift; + + /* generic pinconf */ + bool generic_pinconf; + const struct pinconf_generic_params *custom_params; + unsigned int num_custom_params; + struct imx_cfg_params_decode *decodes; + unsigned int num_decodes; + void (*fixup)(unsigned long *configs, unsigned int num_configs, + u32 *raw_config); }; +#define IMX_CFG_PARAMS_DECODE(p, m, o) \ + { .param = p, .mask = m, .shift = o, .invert = false, } + +#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \ + { .param = p, .mask = m, .shift = o, .invert = true, } + #define SHARE_MUX_CONF_REG 0x1 #define ZERO_OFFSET_VALID 0x2 diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c index a465a66c3ef4..754159ee7b1e 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx7d.c +++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c @@ -358,19 +358,19 @@ static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = { IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07), }; -static struct imx_pinctrl_soc_info imx7d_pinctrl_info = { +static const struct imx_pinctrl_soc_info imx7d_pinctrl_info = { .pins = imx7d_pinctrl_pads, .npins = ARRAY_SIZE(imx7d_pinctrl_pads), .gpr_compatible = "fsl,imx7d-iomuxc-gpr", }; -static struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = { +static const struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = { .pins = imx7d_lpsr_pinctrl_pads, .npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads), .flags = ZERO_OFFSET_VALID, }; -static struct of_device_id imx7d_pinctrl_of_match[] = { +static const struct of_device_id imx7d_pinctrl_of_match[] = { { .compatible = "fsl,imx7d-iomuxc", .data = &imx7d_pinctrl_info, }, { .compatible = "fsl,imx7d-iomuxc-lpsr", .data = &imx7d_lpsr_pinctrl_info }, { /* sentinel */ } diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c index 2b1e198e3092..3bd85564d1e4 100644 --- a/drivers/pinctrl/freescale/pinctrl-vf610.c +++ b/drivers/pinctrl/freescale/pinctrl-vf610.c @@ -299,6 +299,8 @@ static struct imx_pinctrl_soc_info vf610_pinctrl_info = { .pins = vf610_pinctrl_pads, .npins = ARRAY_SIZE(vf610_pinctrl_pads), .flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID, + .mux_mask = 0x700000, + .mux_shift = 20, }; static const struct of_device_id vf610_pinctrl_of_match[] = { diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index 396830a41127..b82d6ff3116f 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -56,6 +56,14 @@ config PINCTRL_BROXTON Broxton pinctrl driver provides an interface that allows configuring of SoC pins and using them as GPIOs. +config PINCTRL_CANNONLAKE + tristate "Intel Cannon Lake PCH pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Cannon Lake PCH pins and using them as GPIOs. + config PINCTRL_GEMINILAKE tristate "Intel Gemini Lake SoC pinctrl and GPIO driver" depends on ACPI diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index 12f3af5b2ca5..81df3cf408e3 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -5,5 +5,6 @@ obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o +obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c new file mode 100644 index 000000000000..3bc609b67dc2 --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c @@ -0,0 +1,442 @@ +/* + * Intel Cannon Lake PCH pinctrl/GPIO driver + * + * Copyright (C) 2017, Intel Corporation + * Author: Mika Westerberg <mika.westerberg@linux.intel.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/acpi.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-intel.h" + +#define CNL_PAD_OWN 0x020 +#define CNL_PADCFGLOCK 0x080 +#define CNL_HOSTSW_OWN 0x0b0 +#define CNL_GPI_IE 0x120 + +#define CNL_GPP(r, s, e) \ + { \ + .reg_num = (r), \ + .base = (s), \ + .size = ((e) - (s) + 1), \ + } + +#define CNL_COMMUNITY(b, s, e, g) \ + { \ + .barno = (b), \ + .padown_offset = CNL_PAD_OWN, \ + .padcfglock_offset = CNL_PADCFGLOCK, \ + .hostown_offset = CNL_HOSTSW_OWN, \ + .ie_offset = CNL_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = ARRAY_SIZE(g), \ + } + +/* Cannon Lake-LP */ +static const struct pinctrl_pin_desc cnllp_pins[] = { + /* GPP_A */ + PINCTRL_PIN(0, "RCINB"), + PINCTRL_PIN(1, "LAD_0"), + PINCTRL_PIN(2, "LAD_1"), + PINCTRL_PIN(3, "LAD_2"), + PINCTRL_PIN(4, "LAD_3"), + PINCTRL_PIN(5, "LFRAMEB"), + PINCTRL_PIN(6, "SERIRQ"), + PINCTRL_PIN(7, "PIRQAB"), + PINCTRL_PIN(8, "CLKRUNB"), + PINCTRL_PIN(9, "CLKOUT_LPC_0"), + PINCTRL_PIN(10, "CLKOUT_LPC_1"), + PINCTRL_PIN(11, "PMEB"), + PINCTRL_PIN(12, "BM_BUSYB"), + PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"), + PINCTRL_PIN(14, "SUS_STATB"), + PINCTRL_PIN(15, "SUSACKB"), + PINCTRL_PIN(16, "SD_1P8_SEL"), + PINCTRL_PIN(17, "SD_PWR_EN_B"), + PINCTRL_PIN(18, "ISH_GP_0"), + PINCTRL_PIN(19, "ISH_GP_1"), + PINCTRL_PIN(20, "ISH_GP_2"), + PINCTRL_PIN(21, "ISH_GP_3"), + PINCTRL_PIN(22, "ISH_GP_4"), + PINCTRL_PIN(23, "ISH_GP_5"), + PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"), + /* GPP_B */ + PINCTRL_PIN(25, "CORE_VID_0"), + PINCTRL_PIN(26, "CORE_VID_1"), + PINCTRL_PIN(27, "VRALERTB"), + PINCTRL_PIN(28, "CPU_GP_2"), + PINCTRL_PIN(29, "CPU_GP_3"), + PINCTRL_PIN(30, "SRCCLKREQB_0"), + PINCTRL_PIN(31, "SRCCLKREQB_1"), + PINCTRL_PIN(32, "SRCCLKREQB_2"), + PINCTRL_PIN(33, "SRCCLKREQB_3"), + PINCTRL_PIN(34, "SRCCLKREQB_4"), + PINCTRL_PIN(35, "SRCCLKREQB_5"), + PINCTRL_PIN(36, "EXT_PWR_GATEB"), + PINCTRL_PIN(37, "SLP_S0B"), + PINCTRL_PIN(38, "PLTRSTB"), + PINCTRL_PIN(39, "SPKR"), + PINCTRL_PIN(40, "GSPI0_CS0B"), + PINCTRL_PIN(41, "GSPI0_CLK"), + PINCTRL_PIN(42, "GSPI0_MISO"), + PINCTRL_PIN(43, "GSPI0_MOSI"), + PINCTRL_PIN(44, "GSPI1_CS0B"), + PINCTRL_PIN(45, "GSPI1_CLK"), + PINCTRL_PIN(46, "GSPI1_MISO"), + PINCTRL_PIN(47, "GSPI1_MOSI"), + PINCTRL_PIN(48, "SML1ALERTB"), + PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"), + PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"), + /* GPP_G */ + PINCTRL_PIN(51, "SD3_CMD"), + PINCTRL_PIN(52, "SD3_D0_SD4_RCLK_P"), + PINCTRL_PIN(53, "SD3_D1_SD4_RCLK_N"), + PINCTRL_PIN(54, "SD3_D2"), + PINCTRL_PIN(55, "SD3_D3"), + PINCTRL_PIN(56, "SD3_CDB"), + PINCTRL_PIN(57, "SD3_CLK"), + PINCTRL_PIN(58, "SD3_WP"), + /* SPI */ + PINCTRL_PIN(59, "SPI0_IO_2"), + PINCTRL_PIN(60, "SPI0_IO_3"), + PINCTRL_PIN(61, "SPI0_MOSI_IO_0"), + PINCTRL_PIN(62, "SPI0_MISO_IO_1"), + PINCTRL_PIN(63, "SPI0_TPM_CSB"), + PINCTRL_PIN(64, "SPI0_FLASH_0_CSB"), + PINCTRL_PIN(65, "SPI0_FLASH_1_CSB"), + PINCTRL_PIN(66, "SPI0_CLK"), + PINCTRL_PIN(67, "SPI0_CLK_LOOPBK"), + /* GPP_D */ + PINCTRL_PIN(68, "SPI1_CSB"), + PINCTRL_PIN(69, "SPI1_CLK"), + PINCTRL_PIN(70, "SPI1_MISO_IO_1"), + PINCTRL_PIN(71, "SPI1_MOSI_IO_0"), + PINCTRL_PIN(72, "IMGCLKOUT_0"), + PINCTRL_PIN(73, "ISH_I2C0_SDA"), + PINCTRL_PIN(74, "ISH_I2C0_SCL"), + PINCTRL_PIN(75, "ISH_I2C1_SDA"), + PINCTRL_PIN(76, "ISH_I2C1_SCL"), + PINCTRL_PIN(77, "ISH_SPI_CSB"), + PINCTRL_PIN(78, "ISH_SPI_CLK"), + PINCTRL_PIN(79, "ISH_SPI_MISO"), + PINCTRL_PIN(80, "ISH_SPI_MOSI"), + PINCTRL_PIN(81, "ISH_UART0_RXD"), + PINCTRL_PIN(82, "ISH_UART0_TXD"), + PINCTRL_PIN(83, "ISH_UART0_RTSB"), + PINCTRL_PIN(84, "ISH_UART0_CTSB"), + PINCTRL_PIN(85, "DMIC_CLK_1"), + PINCTRL_PIN(86, "DMIC_DATA_1"), + PINCTRL_PIN(87, "DMIC_CLK_0"), + PINCTRL_PIN(88, "DMIC_DATA_0"), + PINCTRL_PIN(89, "SPI1_IO_2"), + PINCTRL_PIN(90, "SPI1_IO_3"), + PINCTRL_PIN(91, "SSP_MCLK"), + PINCTRL_PIN(92, "GSPI2_CLK_LOOPBK"), + /* GPP_F */ + PINCTRL_PIN(93, "CNV_GNSS_PA_BLANKING"), + PINCTRL_PIN(94, "CNV_GNSS_FTA"), + PINCTRL_PIN(95, "CNV_GNSS_SYSCK"), + PINCTRL_PIN(96, "EMMC_HIP_MON"), + PINCTRL_PIN(97, "CNV_BRI_DT"), + PINCTRL_PIN(98, "CNV_BRI_RSP"), + PINCTRL_PIN(99, "CNV_RGI_DT"), + PINCTRL_PIN(100, "CNV_RGI_RSP"), + PINCTRL_PIN(101, "CNV_MFUART2_RXD"), + PINCTRL_PIN(102, "CNV_MFUART2_TXD"), + PINCTRL_PIN(103, "GPP_F_10"), + PINCTRL_PIN(104, "EMMC_CMD"), + PINCTRL_PIN(105, "EMMC_DATA_0"), + PINCTRL_PIN(106, "EMMC_DATA_1"), + PINCTRL_PIN(107, "EMMC_DATA_2"), + PINCTRL_PIN(108, "EMMC_DATA_3"), + PINCTRL_PIN(109, "EMMC_DATA_4"), + PINCTRL_PIN(110, "EMMC_DATA_5"), + PINCTRL_PIN(111, "EMMC_DATA_6"), + PINCTRL_PIN(112, "EMMC_DATA_7"), + PINCTRL_PIN(113, "EMMC_RCLK"), + PINCTRL_PIN(114, "EMMC_CLK"), + PINCTRL_PIN(115, "EMMC_RESETB"), + PINCTRL_PIN(116, "A4WP_PRESENT"), + /* GPP_H */ + PINCTRL_PIN(117, "SSP2_SCLK"), + PINCTRL_PIN(118, "SSP2_SFRM"), + PINCTRL_PIN(119, "SSP2_TXD"), + PINCTRL_PIN(120, "SSP2_RXD"), + PINCTRL_PIN(121, "I2C2_SDA"), + PINCTRL_PIN(122, "I2C2_SCL"), + PINCTRL_PIN(123, "I2C3_SDA"), + PINCTRL_PIN(124, "I2C3_SCL"), + PINCTRL_PIN(125, "I2C4_SDA"), + PINCTRL_PIN(126, "I2C4_SCL"), + PINCTRL_PIN(127, "I2C5_SDA"), + PINCTRL_PIN(128, "I2C5_SCL"), + PINCTRL_PIN(129, "M2_SKT2_CFG_0"), + PINCTRL_PIN(130, "M2_SKT2_CFG_1"), + PINCTRL_PIN(131, "M2_SKT2_CFG_2"), + PINCTRL_PIN(132, "M2_SKT2_CFG_3"), + PINCTRL_PIN(133, "DDPF_CTRLCLK"), + PINCTRL_PIN(134, "DDPF_CTRLDATA"), + PINCTRL_PIN(135, "CPU_VCCIO_PWR_GATEB"), + PINCTRL_PIN(136, "TIMESYNC_0"), + PINCTRL_PIN(137, "IMGCLKOUT_1"), + PINCTRL_PIN(138, "GPPC_H_21"), + PINCTRL_PIN(139, "GPPC_H_22"), + PINCTRL_PIN(140, "GPPC_H_23"), + /* vGPIO */ + PINCTRL_PIN(141, "CNV_BTEN"), + PINCTRL_PIN(142, "CNV_GNEN"), + PINCTRL_PIN(143, "CNV_WFEN"), + PINCTRL_PIN(144, "CNV_WCEN"), + PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(146, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(147, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(148, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(151, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(152, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(155, "vCNV_GNSS_UART_TXD"), + PINCTRL_PIN(156, "vCNV_GNSS_UART_RXD"), + PINCTRL_PIN(157, "vCNV_GNSS_UART_CTS_B"), + PINCTRL_PIN(158, "vCNV_GNSS_UART_RTS_B"), + PINCTRL_PIN(159, "vUART0_TXD"), + PINCTRL_PIN(160, "vUART0_RXD"), + PINCTRL_PIN(161, "vUART0_CTS_B"), + PINCTRL_PIN(162, "vUART0_RTS_B"), + PINCTRL_PIN(163, "vISH_UART0_TXD"), + PINCTRL_PIN(164, "vISH_UART0_RXD"), + PINCTRL_PIN(165, "vISH_UART0_CTS_B"), + PINCTRL_PIN(166, "vISH_UART0_RTS_B"), + PINCTRL_PIN(167, "vISH_UART1_TXD"), + PINCTRL_PIN(168, "vISH_UART1_RXD"), + PINCTRL_PIN(169, "vISH_UART1_CTS_B"), + PINCTRL_PIN(170, "vISH_UART1_RTS_B"), + PINCTRL_PIN(171, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(172, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(173, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(174, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(175, "vSSP2_SCLK"), + PINCTRL_PIN(176, "vSSP2_SFRM"), + PINCTRL_PIN(177, "vSSP2_TXD"), + PINCTRL_PIN(178, "vSSP2_RXD"), + PINCTRL_PIN(179, "vCNV_GNSS_HOST_WAKEB"), + PINCTRL_PIN(180, "vSD3_CD_B"), + /* GPP_C */ + PINCTRL_PIN(181, "SMBCLK"), + PINCTRL_PIN(182, "SMBDATA"), + PINCTRL_PIN(183, "SMBALERTB"), + PINCTRL_PIN(184, "SML0CLK"), + PINCTRL_PIN(185, "SML0DATA"), + PINCTRL_PIN(186, "SML0ALERTB"), + PINCTRL_PIN(187, "SML1CLK"), + PINCTRL_PIN(188, "SML1DATA"), + PINCTRL_PIN(189, "UART0_RXD"), + PINCTRL_PIN(190, "UART0_TXD"), + PINCTRL_PIN(191, "UART0_RTSB"), + PINCTRL_PIN(192, "UART0_CTSB"), + PINCTRL_PIN(193, "UART1_RXD"), + PINCTRL_PIN(194, "UART1_TXD"), + PINCTRL_PIN(195, "UART1_RTSB"), + PINCTRL_PIN(196, "UART1_CTSB"), + PINCTRL_PIN(197, "I2C0_SDA"), + PINCTRL_PIN(198, "I2C0_SCL"), + PINCTRL_PIN(199, "I2C1_SDA"), + PINCTRL_PIN(200, "I2C1_SCL"), + PINCTRL_PIN(201, "UART2_RXD"), + PINCTRL_PIN(202, "UART2_TXD"), + PINCTRL_PIN(203, "UART2_RTSB"), + PINCTRL_PIN(204, "UART2_CTSB"), + /* GPP_E */ + PINCTRL_PIN(205, "SATAXPCIE_0"), + PINCTRL_PIN(206, "SATAXPCIE_1"), + PINCTRL_PIN(207, "SATAXPCIE_2"), + PINCTRL_PIN(208, "CPU_GP_0"), + PINCTRL_PIN(209, "SATA_DEVSLP_0"), + PINCTRL_PIN(210, "SATA_DEVSLP_1"), + PINCTRL_PIN(211, "SATA_DEVSLP_2"), + PINCTRL_PIN(212, "CPU_GP_1"), + PINCTRL_PIN(213, "SATA_LEDB"), + PINCTRL_PIN(214, "USB2_OCB_0"), + PINCTRL_PIN(215, "USB2_OCB_1"), + PINCTRL_PIN(216, "USB2_OCB_2"), + PINCTRL_PIN(217, "USB2_OCB_3"), + PINCTRL_PIN(218, "DDSP_HPD_0"), + PINCTRL_PIN(219, "DDSP_HPD_1"), + PINCTRL_PIN(220, "DDSP_HPD_2"), + PINCTRL_PIN(221, "DDSP_HPD_3"), + PINCTRL_PIN(222, "EDP_HPD"), + PINCTRL_PIN(223, "DDPB_CTRLCLK"), + PINCTRL_PIN(224, "DDPB_CTRLDATA"), + PINCTRL_PIN(225, "DDPC_CTRLCLK"), + PINCTRL_PIN(226, "DDPC_CTRLDATA"), + PINCTRL_PIN(227, "DDPD_CTRLCLK"), + PINCTRL_PIN(228, "DDPD_CTRLDATA"), + /* JTAG */ + PINCTRL_PIN(229, "JTAG_TDO"), + PINCTRL_PIN(230, "JTAGX"), + PINCTRL_PIN(231, "PRDYB"), + PINCTRL_PIN(232, "PREQB"), + PINCTRL_PIN(233, "CPU_TRSTB"), + PINCTRL_PIN(234, "JTAG_TDI"), + PINCTRL_PIN(235, "JTAG_TMS"), + PINCTRL_PIN(236, "JTAG_TCK"), + PINCTRL_PIN(237, "ITP_PMODE"), + /* HVCMOS */ + PINCTRL_PIN(238, "L_BKLTEN"), + PINCTRL_PIN(239, "L_BKLTCTL"), + PINCTRL_PIN(240, "L_VDDEN"), + PINCTRL_PIN(241, "SYS_PWROK"), + PINCTRL_PIN(242, "SYS_RESETB"), + PINCTRL_PIN(243, "MLK_RSTB"), +}; + +static const unsigned int cnllp_spi0_pins[] = { 40, 41, 42, 43, 7 }; +static const unsigned int cnllp_spi0_modes[] = { 1, 1, 1, 1, 2 }; +static const unsigned int cnllp_spi1_pins[] = { 44, 45, 46, 47, 11 }; +static const unsigned int cnllp_spi1_modes[] = { 1, 1, 1, 1, 2 }; +static const unsigned int cnllp_spi2_pins[] = { 77, 78, 79, 80, 83 }; +static const unsigned int cnllp_spi2_modes[] = { 3, 3, 3, 3, 2 }; + +static const unsigned int cnllp_i2c0_pins[] = { 197, 198 }; +static const unsigned int cnllp_i2c1_pins[] = { 199, 200 }; +static const unsigned int cnllp_i2c2_pins[] = { 121, 122 }; +static const unsigned int cnllp_i2c3_pins[] = { 123, 124 }; +static const unsigned int cnllp_i2c4_pins[] = { 125, 126 }; +static const unsigned int cnllp_i2c5_pins[] = { 127, 128 }; + +static const unsigned int cnllp_uart0_pins[] = { 189, 190, 191, 192 }; +static const unsigned int cnllp_uart1_pins[] = { 193, 194, 195, 196 }; +static const unsigned int cnllp_uart2_pins[] = { 201, 202, 203, 204 }; + +static const struct intel_pingroup cnllp_groups[] = { + PIN_GROUP("spi0_grp", cnllp_spi0_pins, cnllp_spi0_modes), + PIN_GROUP("spi1_grp", cnllp_spi1_pins, cnllp_spi1_modes), + PIN_GROUP("spi2_grp", cnllp_spi2_pins, cnllp_spi2_modes), + PIN_GROUP("i2c0_grp", cnllp_i2c0_pins, 1), + PIN_GROUP("i2c1_grp", cnllp_i2c1_pins, 1), + PIN_GROUP("i2c2_grp", cnllp_i2c2_pins, 1), + PIN_GROUP("i2c3_grp", cnllp_i2c3_pins, 1), + PIN_GROUP("i2c4_grp", cnllp_i2c4_pins, 1), + PIN_GROUP("i2c5_grp", cnllp_i2c5_pins, 1), + PIN_GROUP("uart0_grp", cnllp_uart0_pins, 1), + PIN_GROUP("uart1_grp", cnllp_uart1_pins, 1), + PIN_GROUP("uart2_grp", cnllp_uart2_pins, 1), +}; + +static const char * const cnllp_spi0_groups[] = { "spi0_grp" }; +static const char * const cnllp_spi1_groups[] = { "spi1_grp" }; +static const char * const cnllp_spi2_groups[] = { "spi2_grp" }; +static const char * const cnllp_i2c0_groups[] = { "i2c0_grp" }; +static const char * const cnllp_i2c1_groups[] = { "i2c1_grp" }; +static const char * const cnllp_i2c2_groups[] = { "i2c2_grp" }; +static const char * const cnllp_i2c3_groups[] = { "i2c3_grp" }; +static const char * const cnllp_i2c4_groups[] = { "i2c4_grp" }; +static const char * const cnllp_i2c5_groups[] = { "i2c5_grp" }; +static const char * const cnllp_uart0_groups[] = { "uart0_grp" }; +static const char * const cnllp_uart1_groups[] = { "uart1_grp" }; +static const char * const cnllp_uart2_groups[] = { "uart2_grp" }; + +static const struct intel_function cnllp_functions[] = { + FUNCTION("spi0", cnllp_spi0_groups), + FUNCTION("spi1", cnllp_spi1_groups), + FUNCTION("spi2", cnllp_spi2_groups), + FUNCTION("i2c0", cnllp_i2c0_groups), + FUNCTION("i2c1", cnllp_i2c1_groups), + FUNCTION("i2c2", cnllp_i2c2_groups), + FUNCTION("i2c3", cnllp_i2c3_groups), + FUNCTION("i2c4", cnllp_i2c4_groups), + FUNCTION("i2c5", cnllp_i2c5_groups), + FUNCTION("uart0", cnllp_uart0_groups), + FUNCTION("uart1", cnllp_uart1_groups), + FUNCTION("uart2", cnllp_uart2_groups), +}; + +static const struct intel_padgroup cnllp_community0_gpps[] = { + CNL_GPP(0, 0, 24), /* GPP_A */ + CNL_GPP(1, 25, 50), /* GPP_B */ + CNL_GPP(2, 51, 58), /* GPP_G */ + CNL_GPP(3, 59, 67), /* SPI */ +}; + +static const struct intel_padgroup cnllp_community1_gpps[] = { + CNL_GPP(0, 68, 92), /* GPP_D */ + CNL_GPP(1, 93, 116), /* GPP_F */ + CNL_GPP(2, 117, 140), /* GPP_H */ + CNL_GPP(3, 141, 172), /* vGPIO */ + CNL_GPP(4, 173, 180), /* vGPIO */ +}; + +static const struct intel_padgroup cnllp_community4_gpps[] = { + CNL_GPP(0, 181, 204), /* GPP_C */ + CNL_GPP(1, 205, 228), /* GPP_E */ + CNL_GPP(2, 229, 237), /* JTAG */ + CNL_GPP(3, 238, 243), /* HVCMOS */ +}; + +static const struct intel_community cnllp_communities[] = { + CNL_COMMUNITY(0, 0, 67, cnllp_community0_gpps), + CNL_COMMUNITY(1, 68, 180, cnllp_community1_gpps), + CNL_COMMUNITY(2, 181, 243, cnllp_community4_gpps), +}; + +static const struct intel_pinctrl_soc_data cnllp_soc_data = { + .pins = cnllp_pins, + .npins = ARRAY_SIZE(cnllp_pins), + .groups = cnllp_groups, + .ngroups = ARRAY_SIZE(cnllp_groups), + .functions = cnllp_functions, + .nfunctions = ARRAY_SIZE(cnllp_functions), + .communities = cnllp_communities, + .ncommunities = ARRAY_SIZE(cnllp_communities), +}; + +static const struct acpi_device_id cnl_pinctrl_acpi_match[] = { + { "INT34BB", (kernel_ulong_t)&cnllp_soc_data }, + { }, +}; +MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match); + +static int cnl_pinctrl_probe(struct platform_device *pdev) +{ + const struct intel_pinctrl_soc_data *soc_data; + const struct acpi_device_id *id; + + id = acpi_match_device(cnl_pinctrl_acpi_match, &pdev->dev); + if (!id || !id->driver_data) + return -ENODEV; + + soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data; + return intel_pinctrl_probe(pdev, soc_data); +} + +static const struct dev_pm_ops cnl_pinctrl_pm_ops = { + SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend, + intel_pinctrl_resume) +}; + +static struct platform_driver cnl_pinctrl_driver = { + .probe = cnl_pinctrl_probe, + .driver = { + .name = "cannonlake-pinctrl", + .acpi_match_table = cnl_pinctrl_acpi_match, + .pm = &cnl_pinctrl_pm_ops, + }, +}; + +module_platform_driver(cnl_pinctrl_driver); + +MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); +MODULE_DESCRIPTION("Intel Cannon Lake PCH pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 592b465e981e..6dc1096d3d34 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -117,6 +117,7 @@ struct intel_pinctrl { }; #define pin_to_padno(c, p) ((p) - (c)->pin_base) +#define padgroup_offset(g, p) ((p) - (g)->base) static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, unsigned pin) @@ -135,6 +136,22 @@ static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl, return NULL; } +static const struct intel_padgroup * +intel_community_get_padgroup(const struct intel_community *community, + unsigned pin) +{ + int i; + + for (i = 0; i < community->ngpps; i++) { + const struct intel_padgroup *padgrp = &community->gpps[i]; + + if (pin >= padgrp->base && pin < padgrp->base + padgrp->size) + return padgrp; + } + + return NULL; +} + static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, unsigned reg) { @@ -158,7 +175,8 @@ static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin, static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) { const struct intel_community *community; - unsigned padno, gpp, offset, group; + const struct intel_padgroup *padgrp; + unsigned gpp, offset, gpp_offset; void __iomem *padown; community = intel_get_community(pctrl, pin); @@ -167,19 +185,23 @@ static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin) if (!community->padown_offset) return true; - padno = pin_to_padno(community, pin); - group = padno / community->gpp_size; - gpp = PADOWN_GPP(padno % community->gpp_size); - offset = community->padown_offset + 0x10 * group + gpp * 4; + padgrp = intel_community_get_padgroup(community, pin); + if (!padgrp) + return false; + + gpp_offset = padgroup_offset(padgrp, pin); + gpp = PADOWN_GPP(gpp_offset); + offset = community->padown_offset + padgrp->padown_num * 4 + gpp * 4; padown = community->regs + offset; - return !(readl(padown) & PADOWN_MASK(padno)); + return !(readl(padown) & PADOWN_MASK(gpp_offset)); } static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) { const struct intel_community *community; - unsigned padno, gpp, offset; + const struct intel_padgroup *padgrp; + unsigned offset, gpp_offset; void __iomem *hostown; community = intel_get_community(pctrl, pin); @@ -188,18 +210,22 @@ static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin) if (!community->hostown_offset) return false; - padno = pin_to_padno(community, pin); - gpp = padno / community->gpp_size; - offset = community->hostown_offset + gpp * 4; + padgrp = intel_community_get_padgroup(community, pin); + if (!padgrp) + return true; + + gpp_offset = padgroup_offset(padgrp, pin); + offset = community->hostown_offset + padgrp->reg_num * 4; hostown = community->regs + offset; - return !(readl(hostown) & BIT(padno % community->gpp_size)); + return !(readl(hostown) & BIT(gpp_offset)); } static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) { struct intel_community *community; - unsigned padno, gpp, offset; + const struct intel_padgroup *padgrp; + unsigned offset, gpp_offset; u32 value; community = intel_get_community(pctrl, pin); @@ -208,22 +234,25 @@ static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin) if (!community->padcfglock_offset) return false; - padno = pin_to_padno(community, pin); - gpp = padno / community->gpp_size; + padgrp = intel_community_get_padgroup(community, pin); + if (!padgrp) + return true; + + gpp_offset = padgroup_offset(padgrp, pin); /* * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, * the pad is considered unlocked. Any other case means that it is * either fully or partially locked and we don't touch it. */ - offset = community->padcfglock_offset + gpp * 8; + offset = community->padcfglock_offset + padgrp->reg_num * 8; value = readl(community->regs + offset); - if (value & BIT(pin % community->gpp_size)) + if (value & BIT(gpp_offset)) return true; - offset = community->padcfglock_offset + 4 + gpp * 8; + offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; value = readl(community->regs + offset); - if (value & BIT(pin % community->gpp_size)) + if (value & BIT(gpp_offset)) return true; return false; @@ -369,7 +398,11 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function, value = readl(padcfg0); value &= ~PADCFG0_PMODE_MASK; - value |= grp->mode << PADCFG0_PMODE_SHIFT; + + if (grp->modes) + value |= grp->modes[i] << PADCFG0_PMODE_SHIFT; + else + value |= grp->mode << PADCFG0_PMODE_SHIFT; writel(value, padcfg0); } @@ -777,18 +810,22 @@ static void intel_gpio_irq_ack(struct irq_data *d) const struct intel_community *community; unsigned pin = irqd_to_hwirq(d); - raw_spin_lock(&pctrl->lock); - community = intel_get_community(pctrl, pin); if (community) { - unsigned padno = pin_to_padno(community, pin); - unsigned gpp_offset = padno % community->gpp_size; - unsigned gpp = padno / community->gpp_size; + const struct intel_padgroup *padgrp; + unsigned gpp, gpp_offset; + + padgrp = intel_community_get_padgroup(community, pin); + if (!padgrp) + return; + gpp = padgrp->reg_num; + gpp_offset = padgroup_offset(padgrp, pin); + + raw_spin_lock(&pctrl->lock); writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); + raw_spin_unlock(&pctrl->lock); } - - raw_spin_unlock(&pctrl->lock); } static void intel_gpio_irq_enable(struct irq_data *d) @@ -797,27 +834,30 @@ static void intel_gpio_irq_enable(struct irq_data *d) struct intel_pinctrl *pctrl = gpiochip_get_data(gc); const struct intel_community *community; unsigned pin = irqd_to_hwirq(d); - unsigned long flags; - - raw_spin_lock_irqsave(&pctrl->lock, flags); community = intel_get_community(pctrl, pin); if (community) { - unsigned padno = pin_to_padno(community, pin); - unsigned gpp_size = community->gpp_size; - unsigned gpp_offset = padno % gpp_size; - unsigned gpp = padno / gpp_size; + const struct intel_padgroup *padgrp; + unsigned gpp, gpp_offset; + unsigned long flags; u32 value; + padgrp = intel_community_get_padgroup(community, pin); + if (!padgrp) + return; + + gpp = padgrp->reg_num; + gpp_offset = padgroup_offset(padgrp, pin); + + raw_spin_lock_irqsave(&pctrl->lock, flags); /* Clear interrupt status first to avoid unexpected interrupt */ writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4); value = readl(community->regs + community->ie_offset + gpp * 4); value |= BIT(gpp_offset); writel(value, community->regs + community->ie_offset + gpp * 4); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); } - - raw_spin_unlock_irqrestore(&pctrl->lock, flags); } static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) @@ -826,28 +866,33 @@ static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask) struct intel_pinctrl *pctrl = gpiochip_get_data(gc); const struct intel_community *community; unsigned pin = irqd_to_hwirq(d); - unsigned long flags; - - raw_spin_lock_irqsave(&pctrl->lock, flags); community = intel_get_community(pctrl, pin); if (community) { - unsigned padno = pin_to_padno(community, pin); - unsigned gpp_offset = padno % community->gpp_size; - unsigned gpp = padno / community->gpp_size; + const struct intel_padgroup *padgrp; + unsigned gpp, gpp_offset; + unsigned long flags; void __iomem *reg; u32 value; + padgrp = intel_community_get_padgroup(community, pin); + if (!padgrp) + return; + + gpp = padgrp->reg_num; + gpp_offset = padgroup_offset(padgrp, pin); + reg = community->regs + community->ie_offset + gpp * 4; + + raw_spin_lock_irqsave(&pctrl->lock, flags); value = readl(reg); if (mask) value &= ~BIT(gpp_offset); else value |= BIT(gpp_offset); writel(value, reg); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); } - - raw_spin_unlock_irqrestore(&pctrl->lock, flags); } static void intel_gpio_irq_mask(struct irq_data *d) @@ -938,23 +983,20 @@ static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl, int gpp; for (gpp = 0; gpp < community->ngpps; gpp++) { + const struct intel_padgroup *padgrp = &community->gpps[gpp]; unsigned long pending, enabled, gpp_offset; - pending = readl(community->regs + GPI_IS + gpp * 4); + pending = readl(community->regs + GPI_IS + padgrp->reg_num * 4); enabled = readl(community->regs + community->ie_offset + - gpp * 4); + padgrp->reg_num * 4); /* Only interrupts that are enabled */ pending &= enabled; - for_each_set_bit(gpp_offset, &pending, community->gpp_size) { + for_each_set_bit(gpp_offset, &pending, padgrp->size) { unsigned padno, irq; - /* - * The last group in community can have less pins - * than NPADS_IN_GPP. - */ - padno = gpp_offset + gpp * community->gpp_size; + padno = padgrp->base - community->pin_base + gpp_offset; if (padno >= community->npins) break; @@ -1045,6 +1087,56 @@ static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq) return 0; } +static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl, + struct intel_community *community) +{ + struct intel_padgroup *gpps; + unsigned npins = community->npins; + unsigned padown_num = 0; + size_t ngpps, i; + + if (community->gpps) + ngpps = community->ngpps; + else + ngpps = DIV_ROUND_UP(community->npins, community->gpp_size); + + gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL); + if (!gpps) + return -ENOMEM; + + for (i = 0; i < ngpps; i++) { + if (community->gpps) { + gpps[i] = community->gpps[i]; + } else { + unsigned gpp_size = community->gpp_size; + + gpps[i].reg_num = i; + gpps[i].base = community->pin_base + i * gpp_size; + gpps[i].size = min(gpp_size, npins); + npins -= gpps[i].size; + } + + if (gpps[i].size > 32) + return -EINVAL; + + gpps[i].padown_num = padown_num; + + /* + * In older hardware the number of padown registers per + * group is fixed regardless of the group size. + */ + if (community->gpp_num_padown_regs) + padown_num += community->gpp_num_padown_regs; + else + padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32); + } + + community->ngpps = ngpps; + community->gpps = gpps; + + return 0; +} + static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) { #ifdef CONFIG_PM_SLEEP @@ -1142,8 +1234,10 @@ int intel_pinctrl_probe(struct platform_device *pdev, community->regs = regs; community->pad_regs = regs + padbar; - community->ngpps = DIV_ROUND_UP(community->npins, - community->gpp_size); + + ret = intel_pinctrl_add_padgroups(pctrl, community); + if (ret) + return ret; } irq = platform_get_irq(pdev, 0); diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index fe9521f345b5..7fdb07753c2d 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -22,13 +22,16 @@ struct device; * @name: Name of the groups * @pins: All pins in this group * @npins: Number of pins in this groups - * @mode: Native mode in which the group is muxed out @pins + * @mode: Native mode in which the group is muxed out @pins. Used if @modes + * is %NULL. + * @modes: If not %NULL this will hold mode for each pin in @pins */ struct intel_pingroup { const char *name; const unsigned *pins; size_t npins; unsigned short mode; + const unsigned *modes; }; /** @@ -44,6 +47,23 @@ struct intel_function { }; /** + * struct intel_padgroup - Hardware pad group information + * @reg_num: GPI_IS register number + * @base: Starting pin of this group + * @size: Size of this group (maximum is 32). + * @padown_num: PAD_OWN register number (assigned by the core driver) + * + * If pad groups of a community are not the same size, use this structure + * to specify them. + */ +struct intel_padgroup { + unsigned reg_num; + unsigned base; + unsigned size; + unsigned padown_num; +}; + +/** * struct intel_community - Intel pin community description * @barno: MMIO BAR number where registers for this community reside * @padown_offset: Register offset of PAD_OWN register from @regs. If %0 @@ -56,13 +76,22 @@ struct intel_function { * @ie_offset: Register offset of GPI_IE from @regs. * @pin_base: Starting pin of pins in this community * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, - * HOSTSW_OWN, GPI_IS, GPI_IE, etc. + * HOSTSW_OWN, GPI_IS, GPI_IE, etc. Used when @gpps is %NULL. + * @gpp_num_padown_regs: Number of pad registers each pad group consumes at + * minimum. Use %0 if the number of registers can be + * determined by the size of the group. * @npins: Number of pins in this community * @features: Additional features supported by the hardware + * @gpps: Pad groups if the controller has variable size pad groups + * @ngpps: Number of pad groups in this community * @regs: Community specific common registers (reserved for core driver) * @pad_regs: Community specific pad registers (reserved for core driver) - * @ngpps: Number of groups (hw groups) in this community (reserved for - * core driver) + * + * Most Intel GPIO host controllers this driver supports each pad group is + * of equal size (except the last one). In that case the driver can just + * fill in @gpp_size field and let the core driver to handle the rest. If + * the controller has pad groups of variable size the client driver can + * pass custom @gpps and @ngpps instead. */ struct intel_community { unsigned barno; @@ -72,23 +101,37 @@ struct intel_community { unsigned ie_offset; unsigned pin_base; unsigned gpp_size; + unsigned gpp_num_padown_regs; size_t npins; unsigned features; + const struct intel_padgroup *gpps; + size_t ngpps; + /* Reserved for the core driver */ void __iomem *regs; void __iomem *pad_regs; - size_t ngpps; }; /* Additional features supported by the hardware */ #define PINCTRL_FEATURE_DEBOUNCE BIT(0) #define PINCTRL_FEATURE_1K_PD BIT(1) -#define PIN_GROUP(n, p, m) \ - { \ - .name = (n), \ - .pins = (p), \ - .npins = ARRAY_SIZE((p)), \ - .mode = (m), \ +/** + * PIN_GROUP - Declare a pin group + * @n: Name of the group + * @p: An array of pins this group consists + * @m: Mode which the pins are put when this group is active. Can be either + * a single integer or an array of integers in which case mode is per + * pin. + */ +#define PIN_GROUP(n, p, m) \ + { \ + .name = (n), \ + .pins = (p), \ + .npins = ARRAY_SIZE((p)), \ + .mode = __builtin_choose_expr( \ + __builtin_constant_p((m)), (m), 0), \ + .modes = __builtin_choose_expr( \ + __builtin_constant_p((m)), NULL, (m)), \ } #define FUNCTION(n, g) \ diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c index 9877526c0807..8870a4100164 100644 --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -31,6 +31,7 @@ .hostown_offset = SPT_HOSTSW_OWN, \ .ie_offset = SPT_GPI_IE, \ .gpp_size = 24, \ + .gpp_num_padown_regs = 4, \ .pin_base = (s), \ .npins = ((e) - (s) + 1), \ } diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 80fe3b48796c..fac9866311f3 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -11,18 +11,11 @@ config PINCTRL_MTK # For ARMv7 SoCs config PINCTRL_MT2701 bool "Mediatek MT2701 pin control" - depends on MACH_MT2701 || COMPILE_TEST + depends on MACH_MT7623 || MACH_MT2701 || COMPILE_TEST depends on OF default MACH_MT2701 select PINCTRL_MTK -config PINCTRL_MT7623 - bool "Mediatek MT7623 pin control" - depends on MACH_MT7623 || COMPILE_TEST - depends on OF - default MACH_MT7623 - select PINCTRL_MTK_COMMON - config PINCTRL_MT8135 bool "Mediatek MT8135 pin control" depends on MACH_MT8135 || COMPILE_TEST diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 3e3390a14716..e59c613d4ddd 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -3,7 +3,6 @@ obj-y += pinctrl-mtk-common.o # SoC Drivers obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o -obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c index 8d802fa7decd..f86f3b379607 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c @@ -565,6 +565,7 @@ static int mt2701_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id mt2701_pctrl_match[] = { { .compatible = "mediatek,mt2701-pinctrl", }, + { .compatible = "mediatek,mt7623-pinctrl", }, {} }; MODULE_DEVICE_TABLE(of, mt2701_pctrl_match); diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c deleted file mode 100644 index fa28dd6b871b..000000000000 --- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c +++ /dev/null @@ -1,379 +0,0 @@ -/* - * Copyright (c) 2016 John Crispin <john@phrozen.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <dt-bindings/pinctrl/mt65xx.h> -#include <linux/module.h> -#include <linux/of.h> -#include <linux/of_device.h> -#include <linux/platform_device.h> -#include <linux/pinctrl/pinctrl.h> -#include <linux/regmap.h> - -#include "pinctrl-mtk-common.h" -#include "pinctrl-mtk-mt7623.h" - -static const struct mtk_drv_group_desc mt7623_drv_grp[] = { - /* 0E4E8SR 4/8/12/16 */ - MTK_DRV_GRP(4, 16, 1, 2, 4), - /* 0E2E4SR 2/4/6/8 */ - MTK_DRV_GRP(2, 8, 1, 2, 2), - /* E8E4E2 2/4/6/8/10/12/14/16 */ - MTK_DRV_GRP(2, 16, 0, 2, 2) -}; - -#define DRV_SEL0 0xf50 -#define DRV_SEL1 0xf60 -#define DRV_SEL2 0xf70 -#define DRV_SEL3 0xf80 -#define DRV_SEL4 0xf90 -#define DRV_SEL5 0xfa0 -#define DRV_SEL6 0xfb0 -#define DRV_SEL7 0xfe0 -#define DRV_SEL8 0xfd0 -#define DRV_SEL9 0xff0 -#define DRV_SEL10 0xf00 - -#define MSDC0_CTRL0 0xcc0 -#define MSDC0_CTRL1 0xcd0 -#define MSDC0_CTRL2 0xce0 -#define MSDC0_CTRL3 0xcf0 -#define MSDC0_CTRL4 0xd00 -#define MSDC0_CTRL5 0xd10 -#define MSDC0_CTRL6 0xd20 -#define MSDC1_CTRL0 0xd30 -#define MSDC1_CTRL1 0xd40 -#define MSDC1_CTRL2 0xd50 -#define MSDC1_CTRL3 0xd60 -#define MSDC1_CTRL4 0xd70 -#define MSDC1_CTRL5 0xd80 -#define MSDC1_CTRL6 0xd90 - -#define IES_EN0 0xb20 -#define IES_EN1 0xb30 -#define IES_EN2 0xb40 - -#define SMT_EN0 0xb50 -#define SMT_EN1 0xb60 -#define SMT_EN2 0xb70 - -static const struct mtk_pin_drv_grp mt7623_pin_drv[] = { - MTK_PIN_DRV_GRP(0, DRV_SEL0, 0, 1), - MTK_PIN_DRV_GRP(1, DRV_SEL0, 0, 1), - MTK_PIN_DRV_GRP(2, DRV_SEL0, 0, 1), - MTK_PIN_DRV_GRP(3, DRV_SEL0, 0, 1), - MTK_PIN_DRV_GRP(4, DRV_SEL0, 0, 1), - MTK_PIN_DRV_GRP(5, DRV_SEL0, 0, 1), - MTK_PIN_DRV_GRP(6, DRV_SEL0, 0, 1), - MTK_PIN_DRV_GRP(7, DRV_SEL0, 4, 1), - MTK_PIN_DRV_GRP(8, DRV_SEL0, 4, 1), - MTK_PIN_DRV_GRP(9, DRV_SEL0, 4, 1), - MTK_PIN_DRV_GRP(10, DRV_SEL0, 8, 1), - MTK_PIN_DRV_GRP(11, DRV_SEL0, 8, 1), - MTK_PIN_DRV_GRP(12, DRV_SEL0, 8, 1), - MTK_PIN_DRV_GRP(13, DRV_SEL0, 8, 1), - MTK_PIN_DRV_GRP(14, DRV_SEL0, 12, 0), - MTK_PIN_DRV_GRP(15, DRV_SEL0, 12, 0), - MTK_PIN_DRV_GRP(18, DRV_SEL1, 4, 0), - MTK_PIN_DRV_GRP(19, DRV_SEL1, 4, 0), - MTK_PIN_DRV_GRP(20, DRV_SEL1, 4, 0), - MTK_PIN_DRV_GRP(21, DRV_SEL1, 4, 0), - MTK_PIN_DRV_GRP(22, DRV_SEL1, 8, 0), - MTK_PIN_DRV_GRP(23, DRV_SEL1, 8, 0), - MTK_PIN_DRV_GRP(24, DRV_SEL1, 8, 0), - MTK_PIN_DRV_GRP(25, DRV_SEL1, 8, 0), - MTK_PIN_DRV_GRP(26, DRV_SEL1, 8, 0), - MTK_PIN_DRV_GRP(27, DRV_SEL1, 12, 0), - MTK_PIN_DRV_GRP(28, DRV_SEL1, 12, 0), - MTK_PIN_DRV_GRP(29, DRV_SEL1, 12, 0), - MTK_PIN_DRV_GRP(33, DRV_SEL2, 0, 0), - MTK_PIN_DRV_GRP(34, DRV_SEL2, 0, 0), - MTK_PIN_DRV_GRP(35, DRV_SEL2, 0, 0), - MTK_PIN_DRV_GRP(36, DRV_SEL2, 0, 0), - MTK_PIN_DRV_GRP(37, DRV_SEL2, 0, 0), - MTK_PIN_DRV_GRP(39, DRV_SEL2, 8, 1), - MTK_PIN_DRV_GRP(40, DRV_SEL2, 8, 1), - MTK_PIN_DRV_GRP(41, DRV_SEL2, 8, 1), - MTK_PIN_DRV_GRP(42, DRV_SEL2, 8, 1), - MTK_PIN_DRV_GRP(43, DRV_SEL2, 12, 0), - MTK_PIN_DRV_GRP(44, DRV_SEL2, 12, 0), - MTK_PIN_DRV_GRP(45, DRV_SEL2, 12, 0), - MTK_PIN_DRV_GRP(47, DRV_SEL3, 0, 0), - MTK_PIN_DRV_GRP(48, DRV_SEL3, 0, 0), - MTK_PIN_DRV_GRP(49, DRV_SEL3, 4, 0), - MTK_PIN_DRV_GRP(53, DRV_SEL3, 12, 0), - MTK_PIN_DRV_GRP(54, DRV_SEL3, 12, 0), - MTK_PIN_DRV_GRP(55, DRV_SEL3, 12, 0), - MTK_PIN_DRV_GRP(56, DRV_SEL3, 12, 0), - MTK_PIN_DRV_GRP(60, DRV_SEL4, 8, 1), - MTK_PIN_DRV_GRP(61, DRV_SEL4, 8, 1), - MTK_PIN_DRV_GRP(62, DRV_SEL4, 8, 1), - MTK_PIN_DRV_GRP(63, DRV_SEL4, 12, 1), - MTK_PIN_DRV_GRP(64, DRV_SEL4, 12, 1), - MTK_PIN_DRV_GRP(65, DRV_SEL4, 12, 1), - MTK_PIN_DRV_GRP(66, DRV_SEL5, 0, 1), - MTK_PIN_DRV_GRP(67, DRV_SEL5, 0, 1), - MTK_PIN_DRV_GRP(68, DRV_SEL5, 0, 1), - MTK_PIN_DRV_GRP(69, DRV_SEL5, 0, 1), - MTK_PIN_DRV_GRP(70, DRV_SEL5, 0, 1), - MTK_PIN_DRV_GRP(71, DRV_SEL5, 0, 1), - MTK_PIN_DRV_GRP(72, DRV_SEL3, 4, 0), - MTK_PIN_DRV_GRP(73, DRV_SEL3, 4, 0), - MTK_PIN_DRV_GRP(74, DRV_SEL3, 4, 0), - MTK_PIN_DRV_GRP(83, DRV_SEL5, 0, 1), - MTK_PIN_DRV_GRP(84, DRV_SEL5, 0, 1), - MTK_PIN_DRV_GRP(105, MSDC1_CTRL1, 0, 1), - MTK_PIN_DRV_GRP(106, MSDC1_CTRL0, 0, 1), - MTK_PIN_DRV_GRP(107, MSDC1_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(108, MSDC1_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(109, MSDC1_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(110, MSDC1_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(111, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(112, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(113, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(114, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(115, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(116, MSDC0_CTRL1, 0, 1), - MTK_PIN_DRV_GRP(117, MSDC0_CTRL0, 0, 1), - MTK_PIN_DRV_GRP(118, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(119, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(120, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(121, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(126, DRV_SEL3, 4, 0), - MTK_PIN_DRV_GRP(199, DRV_SEL0, 4, 1), - MTK_PIN_DRV_GRP(200, DRV_SEL8, 0, 0), - MTK_PIN_DRV_GRP(201, DRV_SEL8, 0, 0), - MTK_PIN_DRV_GRP(203, DRV_SEL8, 4, 0), - MTK_PIN_DRV_GRP(204, DRV_SEL8, 4, 0), - MTK_PIN_DRV_GRP(205, DRV_SEL8, 4, 0), - MTK_PIN_DRV_GRP(206, DRV_SEL8, 4, 0), - MTK_PIN_DRV_GRP(207, DRV_SEL8, 4, 0), - MTK_PIN_DRV_GRP(208, DRV_SEL8, 8, 0), - MTK_PIN_DRV_GRP(209, DRV_SEL8, 8, 0), - MTK_PIN_DRV_GRP(236, DRV_SEL9, 4, 0), - MTK_PIN_DRV_GRP(237, DRV_SEL9, 4, 0), - MTK_PIN_DRV_GRP(238, DRV_SEL9, 4, 0), - MTK_PIN_DRV_GRP(239, DRV_SEL9, 4, 0), - MTK_PIN_DRV_GRP(240, DRV_SEL9, 4, 0), - MTK_PIN_DRV_GRP(241, DRV_SEL9, 4, 0), - MTK_PIN_DRV_GRP(242, DRV_SEL9, 8, 0), - MTK_PIN_DRV_GRP(243, DRV_SEL9, 8, 0), - MTK_PIN_DRV_GRP(257, MSDC0_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(261, MSDC1_CTRL2, 0, 1), - MTK_PIN_DRV_GRP(262, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(263, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(264, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(265, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(266, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(267, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(268, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(269, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(270, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(271, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(272, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(274, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(275, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(276, DRV_SEL10, 8, 0), - MTK_PIN_DRV_GRP(278, DRV_SEL2, 8, 1), -}; - -static const struct mtk_pin_spec_pupd_set_samereg mt7623_spec_pupd[] = { - MTK_PIN_PUPD_SPEC_SR(105, MSDC1_CTRL1, 8, 9, 10), - MTK_PIN_PUPD_SPEC_SR(106, MSDC1_CTRL0, 8, 9, 10), - MTK_PIN_PUPD_SPEC_SR(107, MSDC1_CTRL3, 0, 1, 2), - MTK_PIN_PUPD_SPEC_SR(108, MSDC1_CTRL3, 4, 5, 6), - MTK_PIN_PUPD_SPEC_SR(109, MSDC1_CTRL3, 8, 9, 10), - MTK_PIN_PUPD_SPEC_SR(110, MSDC1_CTRL3, 12, 13, 14), - MTK_PIN_PUPD_SPEC_SR(111, MSDC0_CTRL4, 12, 13, 14), - MTK_PIN_PUPD_SPEC_SR(112, MSDC0_CTRL4, 8, 9, 10), - MTK_PIN_PUPD_SPEC_SR(113, MSDC0_CTRL4, 4, 5, 6), - MTK_PIN_PUPD_SPEC_SR(114, MSDC0_CTRL4, 0, 1, 2), - MTK_PIN_PUPD_SPEC_SR(115, MSDC0_CTRL5, 0, 1, 2), - MTK_PIN_PUPD_SPEC_SR(116, MSDC0_CTRL1, 8, 9, 10), - MTK_PIN_PUPD_SPEC_SR(117, MSDC0_CTRL0, 8, 9, 10), - MTK_PIN_PUPD_SPEC_SR(118, MSDC0_CTRL3, 12, 13, 14), - MTK_PIN_PUPD_SPEC_SR(119, MSDC0_CTRL3, 8, 9, 10), - MTK_PIN_PUPD_SPEC_SR(120, MSDC0_CTRL3, 4, 5, 6), - MTK_PIN_PUPD_SPEC_SR(121, MSDC0_CTRL3, 0, 1, 2), -}; - -static int mt7623_spec_pull_set(struct regmap *regmap, unsigned int pin, - unsigned char align, bool isup, unsigned int r1r0) -{ - return mtk_pctrl_spec_pull_set_samereg(regmap, mt7623_spec_pupd, - ARRAY_SIZE(mt7623_spec_pupd), pin, align, isup, r1r0); -} - -static const struct mtk_pin_ies_smt_set mt7623_ies_set[] = { - MTK_PIN_IES_SMT_SPEC(0, 6, IES_EN0, 0), - MTK_PIN_IES_SMT_SPEC(7, 9, IES_EN0, 1), - MTK_PIN_IES_SMT_SPEC(10, 13, IES_EN0, 2), - MTK_PIN_IES_SMT_SPEC(14, 15, IES_EN0, 3), - MTK_PIN_IES_SMT_SPEC(18, 21, IES_EN0, 5), - MTK_PIN_IES_SMT_SPEC(22, 26, IES_EN0, 6), - MTK_PIN_IES_SMT_SPEC(27, 29, IES_EN0, 7), - MTK_PIN_IES_SMT_SPEC(33, 37, IES_EN0, 8), - MTK_PIN_IES_SMT_SPEC(39, 42, IES_EN0, 9), - MTK_PIN_IES_SMT_SPEC(43, 45, IES_EN0, 10), - MTK_PIN_IES_SMT_SPEC(47, 48, IES_EN0, 11), - MTK_PIN_IES_SMT_SPEC(49, 49, IES_EN0, 12), - MTK_PIN_IES_SMT_SPEC(53, 56, IES_EN0, 14), - MTK_PIN_IES_SMT_SPEC(60, 62, IES_EN1, 0), - MTK_PIN_IES_SMT_SPEC(63, 65, IES_EN1, 1), - MTK_PIN_IES_SMT_SPEC(66, 71, IES_EN1, 2), - MTK_PIN_IES_SMT_SPEC(72, 74, IES_EN0, 12), - MTK_PIN_IES_SMT_SPEC(75, 76, IES_EN1, 3), - MTK_PIN_IES_SMT_SPEC(83, 84, IES_EN1, 2), - MTK_PIN_IES_SMT_SPEC(105, 121, MSDC1_CTRL1, 4), - MTK_PIN_IES_SMT_SPEC(122, 125, IES_EN1, 7), - MTK_PIN_IES_SMT_SPEC(126, 126, IES_EN0, 12), - MTK_PIN_IES_SMT_SPEC(199, 201, IES_EN0, 1), - MTK_PIN_IES_SMT_SPEC(203, 207, IES_EN2, 2), - MTK_PIN_IES_SMT_SPEC(208, 209, IES_EN2, 3), - MTK_PIN_IES_SMT_SPEC(236, 241, IES_EN2, 6), - MTK_PIN_IES_SMT_SPEC(242, 243, IES_EN2, 7), - MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL2, 4), - MTK_PIN_IES_SMT_SPEC(262, 272, IES_EN2, 12), - MTK_PIN_IES_SMT_SPEC(274, 276, IES_EN2, 12), - MTK_PIN_IES_SMT_SPEC(278, 278, IES_EN2, 13), -}; - -static const struct mtk_pin_ies_smt_set mt7623_smt_set[] = { - MTK_PIN_IES_SMT_SPEC(0, 6, SMT_EN0, 0), - MTK_PIN_IES_SMT_SPEC(7, 9, SMT_EN0, 1), - MTK_PIN_IES_SMT_SPEC(10, 13, SMT_EN0, 2), - MTK_PIN_IES_SMT_SPEC(14, 15, SMT_EN0, 3), - MTK_PIN_IES_SMT_SPEC(18, 21, SMT_EN0, 5), - MTK_PIN_IES_SMT_SPEC(22, 26, SMT_EN0, 6), - MTK_PIN_IES_SMT_SPEC(27, 29, SMT_EN0, 7), - MTK_PIN_IES_SMT_SPEC(33, 37, SMT_EN0, 8), - MTK_PIN_IES_SMT_SPEC(39, 42, SMT_EN0, 9), - MTK_PIN_IES_SMT_SPEC(43, 45, SMT_EN0, 10), - MTK_PIN_IES_SMT_SPEC(47, 48, SMT_EN0, 11), - MTK_PIN_IES_SMT_SPEC(49, 49, SMT_EN0, 12), - MTK_PIN_IES_SMT_SPEC(53, 56, SMT_EN0, 14), - MTK_PIN_IES_SMT_SPEC(60, 62, SMT_EN1, 0), - MTK_PIN_IES_SMT_SPEC(63, 65, SMT_EN1, 1), - MTK_PIN_IES_SMT_SPEC(66, 71, SMT_EN1, 2), - MTK_PIN_IES_SMT_SPEC(72, 74, SMT_EN0, 12), - MTK_PIN_IES_SMT_SPEC(75, 76, SMT_EN1, 3), - MTK_PIN_IES_SMT_SPEC(83, 84, SMT_EN1, 2), - MTK_PIN_IES_SMT_SPEC(105, 106, MSDC1_CTRL1, 11), - MTK_PIN_IES_SMT_SPEC(107, 107, MSDC1_CTRL3, 3), - MTK_PIN_IES_SMT_SPEC(108, 108, MSDC1_CTRL3, 7), - MTK_PIN_IES_SMT_SPEC(109, 109, MSDC1_CTRL3, 11), - MTK_PIN_IES_SMT_SPEC(110, 111, MSDC1_CTRL3, 15), - MTK_PIN_IES_SMT_SPEC(112, 112, MSDC0_CTRL4, 11), - MTK_PIN_IES_SMT_SPEC(113, 113, MSDC0_CTRL4, 7), - MTK_PIN_IES_SMT_SPEC(114, 115, MSDC0_CTRL4, 3), - MTK_PIN_IES_SMT_SPEC(116, 117, MSDC0_CTRL1, 11), - MTK_PIN_IES_SMT_SPEC(118, 118, MSDC0_CTRL3, 15), - MTK_PIN_IES_SMT_SPEC(119, 119, MSDC0_CTRL3, 11), - MTK_PIN_IES_SMT_SPEC(120, 120, MSDC0_CTRL3, 7), - MTK_PIN_IES_SMT_SPEC(121, 121, MSDC0_CTRL3, 3), - MTK_PIN_IES_SMT_SPEC(122, 125, SMT_EN1, 7), - MTK_PIN_IES_SMT_SPEC(126, 126, SMT_EN0, 12), - MTK_PIN_IES_SMT_SPEC(199, 201, SMT_EN0, 1), - MTK_PIN_IES_SMT_SPEC(203, 207, SMT_EN2, 2), - MTK_PIN_IES_SMT_SPEC(208, 209, SMT_EN2, 3), - MTK_PIN_IES_SMT_SPEC(236, 241, SMT_EN2, 6), - MTK_PIN_IES_SMT_SPEC(242, 243, SMT_EN2, 7), - MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL6, 3), - MTK_PIN_IES_SMT_SPEC(262, 272, SMT_EN2, 12), - MTK_PIN_IES_SMT_SPEC(274, 276, SMT_EN2, 12), - MTK_PIN_IES_SMT_SPEC(278, 278, SMT_EN2, 13), -}; - -static int mt7623_ies_smt_set(struct regmap *regmap, unsigned int pin, - unsigned char align, int value, enum pin_config_param arg) -{ - if (arg == PIN_CONFIG_INPUT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_ies_set, - ARRAY_SIZE(mt7623_ies_set), pin, align, value); - else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) - return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_smt_set, - ARRAY_SIZE(mt7623_smt_set), pin, align, value); - return -EINVAL; -} - -static const struct mtk_pinctrl_devdata mt7623_pinctrl_data = { - .pins = mtk_pins_mt7623, - .npins = ARRAY_SIZE(mtk_pins_mt7623), - .grp_desc = mt7623_drv_grp, - .n_grp_cls = ARRAY_SIZE(mt7623_drv_grp), - .pin_drv_grp = mt7623_pin_drv, - .n_pin_drv_grps = ARRAY_SIZE(mt7623_pin_drv), - .spec_pull_set = mt7623_spec_pull_set, - .spec_ies_smt_set = mt7623_ies_smt_set, - .dir_offset = 0x0000, - .pullen_offset = 0x0150, - .pullsel_offset = 0x0280, - .dout_offset = 0x0500, - .din_offset = 0x0630, - .pinmux_offset = 0x0760, - .type1_start = 280, - .type1_end = 280, - .port_shf = 4, - .port_mask = 0x1f, - .port_align = 4, - .eint_offsets = { - .name = "mt7623_eint", - .stat = 0x000, - .ack = 0x040, - .mask = 0x080, - .mask_set = 0x0c0, - .mask_clr = 0x100, - .sens = 0x140, - .sens_set = 0x180, - .sens_clr = 0x1c0, - .soft = 0x200, - .soft_set = 0x240, - .soft_clr = 0x280, - .pol = 0x300, - .pol_set = 0x340, - .pol_clr = 0x380, - .dom_en = 0x400, - .dbnc_ctrl = 0x500, - .dbnc_set = 0x600, - .dbnc_clr = 0x700, - .port_mask = 6, - .ports = 6, - }, - .ap_num = 169, - .db_cnt = 16, -}; - -static int mt7623_pinctrl_probe(struct platform_device *pdev) -{ - return mtk_pctrl_init(pdev, &mt7623_pinctrl_data, NULL); -} - -static const struct of_device_id mt7623_pctrl_match[] = { - { .compatible = "mediatek,mt7623-pinctrl", }, - {} -}; -MODULE_DEVICE_TABLE(of, mt7623_pctrl_match); - -static struct platform_driver mtk_pinctrl_driver = { - .probe = mt7623_pinctrl_probe, - .driver = { - .name = "mediatek-mt7623-pinctrl", - .of_match_table = mt7623_pctrl_match, - }, -}; - -static int __init mtk_pinctrl_init(void) -{ - return platform_driver_register(&mtk_pinctrl_driver); -} - -arch_initcall(mtk_pinctrl_init); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h deleted file mode 100644 index e06cfc40da0f..000000000000 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h +++ /dev/null @@ -1,1936 +0,0 @@ -/* - * Copyright (c) 2016 John Crispin <john@phrozen.org> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __PINCTRL_MTK_MT7623_H -#define __PINCTRL_MTK_MT7623_H - -#include <linux/pinctrl/pinctrl.h> -#include "pinctrl-mtk-common.h" - -static const struct mtk_desc_pin mtk_pins_mt7623[] = { - MTK_PIN( - PINCTRL_PIN(0, "PWRAP_SPI0_MI"), - "J20", "mt7623", - MTK_EINT_FUNCTION(0, 148), - MTK_FUNCTION(0, "GPIO0"), - MTK_FUNCTION(1, "PWRAP_SPIDO"), - MTK_FUNCTION(2, "PWRAP_SPIDI") - ), - MTK_PIN( - PINCTRL_PIN(1, "PWRAP_SPI0_MO"), - "D10", "mt7623", - MTK_EINT_FUNCTION(0, 149), - MTK_FUNCTION(0, "GPIO1"), - MTK_FUNCTION(1, "PWRAP_SPIDI"), - MTK_FUNCTION(2, "PWRAP_SPIDO") - ), - MTK_PIN( - PINCTRL_PIN(2, "PWRAP_INT"), - "E11", "mt7623", - MTK_EINT_FUNCTION(0, 150), - MTK_FUNCTION(0, "GPIO2"), - MTK_FUNCTION(1, "PWRAP_INT") - ), - MTK_PIN( - PINCTRL_PIN(3, "PWRAP_SPI0_CK"), - "H12", "mt7623", - MTK_EINT_FUNCTION(0, 151), - MTK_FUNCTION(0, "GPIO3"), - MTK_FUNCTION(1, "PWRAP_SPICK_I") - ), - MTK_PIN( - PINCTRL_PIN(4, "PWRAP_SPI0_CSN"), - "E12", "mt7623", - MTK_EINT_FUNCTION(0, 152), - MTK_FUNCTION(0, "GPIO4"), - MTK_FUNCTION(1, "PWRAP_SPICS_B_I") - ), - MTK_PIN( - PINCTRL_PIN(5, "PWRAP_SPI0_CK2"), - "H11", "mt7623", - MTK_EINT_FUNCTION(0, 155), - MTK_FUNCTION(0, "GPIO5"), - MTK_FUNCTION(1, "PWRAP_SPICK2_I") - ), - MTK_PIN( - PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"), - "G11", "mt7623", - MTK_EINT_FUNCTION(0, 156), - MTK_FUNCTION(0, "GPIO6"), - MTK_FUNCTION(1, "PWRAP_SPICS2_B_I") - ), - MTK_PIN( - PINCTRL_PIN(7, "SPI1_CSN"), - "G19", "mt7623", - MTK_EINT_FUNCTION(0, 153), - MTK_FUNCTION(0, "GPIO7"), - MTK_FUNCTION(1, "SPI1_CS") - ), - MTK_PIN( - PINCTRL_PIN(8, "SPI1_MI"), - "F19", "mt7623", - MTK_EINT_FUNCTION(0, 154), - MTK_FUNCTION(0, "GPIO8"), - MTK_FUNCTION(1, "SPI1_MI"), - MTK_FUNCTION(2, "SPI1_MO") - ), - MTK_PIN( - PINCTRL_PIN(9, "SPI1_MO"), - "G20", "mt7623", - MTK_EINT_FUNCTION(0, 157), - MTK_FUNCTION(0, "GPIO9"), - MTK_FUNCTION(1, "SPI1_MO"), - MTK_FUNCTION(2, "SPI1_MI") - ), - MTK_PIN( - PINCTRL_PIN(10, "RTC32K_CK"), - "A13", "mt7623", - MTK_EINT_FUNCTION(0, 158), - MTK_FUNCTION(0, "GPIO10"), - MTK_FUNCTION(1, "RTC32K_CK") - ), - MTK_PIN( - PINCTRL_PIN(11, "WATCHDOG"), - "D14", "mt7623", - MTK_EINT_FUNCTION(0, 159), - MTK_FUNCTION(0, "GPIO11"), - MTK_FUNCTION(1, "WATCHDOG") - ), - MTK_PIN( - PINCTRL_PIN(12, "SRCLKENA"), - "C13", "mt7623", - MTK_EINT_FUNCTION(0, 169), - MTK_FUNCTION(0, "GPIO12"), - MTK_FUNCTION(1, "SRCLKENA") - ), - MTK_PIN( - PINCTRL_PIN(13, "SRCLKENAI"), - "B13", "mt7623", - MTK_EINT_FUNCTION(0, 161), - MTK_FUNCTION(0, "GPIO13"), - MTK_FUNCTION(1, "SRCLKENAI") - ), - MTK_PIN( - PINCTRL_PIN(14, "GPIO14"), - "E18", "mt7623", - MTK_EINT_FUNCTION(0, 162), - MTK_FUNCTION(0, "GPIO14"), - MTK_FUNCTION(1, "URXD2"), - MTK_FUNCTION(2, "UTXD2") - ), - MTK_PIN( - PINCTRL_PIN(15, "GPIO15"), - "E17", "mt7623", - MTK_EINT_FUNCTION(0, 163), - MTK_FUNCTION(0, "GPIO15"), - MTK_FUNCTION(1, "UTXD2"), - MTK_FUNCTION(2, "URXD2") - ), - MTK_PIN( - PINCTRL_PIN(16, "GPIO16"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO16") - ), - MTK_PIN( - PINCTRL_PIN(17, "GPIO17"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO17") - ), - MTK_PIN( - PINCTRL_PIN(18, "PCM_CLK"), - "C19", "mt7623", - MTK_EINT_FUNCTION(0, 166), - MTK_FUNCTION(0, "GPIO18"), - MTK_FUNCTION(1, "PCM_CLK0"), - MTK_FUNCTION(6, "AP_PCM_CLKO") - ), - MTK_PIN( - PINCTRL_PIN(19, "PCM_SYNC"), - "D19", "mt7623", - MTK_EINT_FUNCTION(0, 167), - MTK_FUNCTION(0, "GPIO19"), - MTK_FUNCTION(1, "PCM_SYNC"), - MTK_FUNCTION(6, "AP_PCM_SYNC") - ), - MTK_PIN( - PINCTRL_PIN(20, "PCM_RX"), - "D18", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO20"), - MTK_FUNCTION(1, "PCM_RX"), - MTK_FUNCTION(4, "PCM_TX"), - MTK_FUNCTION(6, "AP_PCM_RX") - ), - MTK_PIN( - PINCTRL_PIN(21, "PCM_TX"), - "C18", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO21"), - MTK_FUNCTION(1, "PCM_TX"), - MTK_FUNCTION(4, "PCM_RX"), - MTK_FUNCTION(6, "AP_PCM_TX") - ), - MTK_PIN( - PINCTRL_PIN(22, "EINT0"), - "H15", "mt7623", - MTK_EINT_FUNCTION(0, 0), - MTK_FUNCTION(0, "GPIO22"), - MTK_FUNCTION(1, "UCTS0"), - MTK_FUNCTION(2, "PCIE0_PERST_N") - ), - MTK_PIN( - PINCTRL_PIN(23, "EINT1"), - "J16", "mt7623", - MTK_EINT_FUNCTION(0, 1), - MTK_FUNCTION(0, "GPIO23"), - MTK_FUNCTION(1, "URTS0"), - MTK_FUNCTION(2, "PCIE1_PERST_N") - ), - MTK_PIN( - PINCTRL_PIN(24, "EINT2"), - "H16", "mt7623", - MTK_EINT_FUNCTION(0, 2), - MTK_FUNCTION(0, "GPIO24"), - MTK_FUNCTION(1, "UCTS1"), - MTK_FUNCTION(2, "PCIE2_PERST_N") - ), - MTK_PIN( - PINCTRL_PIN(25, "EINT3"), - "K15", "mt7623", - MTK_EINT_FUNCTION(0, 3), - MTK_FUNCTION(0, "GPIO25"), - MTK_FUNCTION(1, "URTS1") - ), - MTK_PIN( - PINCTRL_PIN(26, "EINT4"), - "G15", "mt7623", - MTK_EINT_FUNCTION(0, 4), - MTK_FUNCTION(0, "GPIO26"), - MTK_FUNCTION(1, "UCTS3"), - MTK_FUNCTION(6, "PCIE2_WAKE_N") - ), - MTK_PIN( - PINCTRL_PIN(27, "EINT5"), - "F15", "mt7623", - MTK_EINT_FUNCTION(0, 5), - MTK_FUNCTION(0, "GPIO27"), - MTK_FUNCTION(1, "URTS3"), - MTK_FUNCTION(6, "PCIE1_WAKE_N") - ), - MTK_PIN( - PINCTRL_PIN(28, "EINT6"), - "J15", "mt7623", - MTK_EINT_FUNCTION(0, 6), - MTK_FUNCTION(0, "GPIO28"), - MTK_FUNCTION(1, "DRV_VBUS"), - MTK_FUNCTION(6, "PCIE0_WAKE_N") - ), - MTK_PIN( - PINCTRL_PIN(29, "EINT7"), - "E15", "mt7623", - MTK_EINT_FUNCTION(0, 7), - MTK_FUNCTION(0, "GPIO29"), - MTK_FUNCTION(1, "IDDIG"), - MTK_FUNCTION(2, "MSDC1_WP"), - MTK_FUNCTION(6, "PCIE2_PERST_N") - ), - MTK_PIN( - PINCTRL_PIN(30, "GPIO30"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO30") - ), - MTK_PIN( - PINCTRL_PIN(31, "GPIO31"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO31") - ), - MTK_PIN( - PINCTRL_PIN(32, "GPIO32"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO32") - ), - MTK_PIN( - PINCTRL_PIN(33, "I2S1_DATA"), - "Y18", "mt7623", - MTK_EINT_FUNCTION(0, 15), - MTK_FUNCTION(0, "GPIO33"), - MTK_FUNCTION(1, "I2S1_DATA"), - MTK_FUNCTION(3, "PCM_TX"), - MTK_FUNCTION(6, "AP_PCM_TX") - ), - MTK_PIN( - PINCTRL_PIN(34, "I2S1_DATA_IN"), - "Y17", "mt7623", - MTK_EINT_FUNCTION(0, 16), - MTK_FUNCTION(0, "GPIO34"), - MTK_FUNCTION(1, "I2S1_DATA_IN"), - MTK_FUNCTION(3, "PCM_RX"), - MTK_FUNCTION(6, "AP_PCM_RX") - ), - MTK_PIN( - PINCTRL_PIN(35, "I2S1_BCK"), - "V17", "mt7623", - MTK_EINT_FUNCTION(0, 17), - MTK_FUNCTION(0, "GPIO35"), - MTK_FUNCTION(1, "I2S1_BCK"), - MTK_FUNCTION(3, "PCM_CLK0"), - MTK_FUNCTION(6, "AP_PCM_CLKO") - ), - MTK_PIN( - PINCTRL_PIN(36, "I2S1_LRCK"), - "W17", "mt7623", - MTK_EINT_FUNCTION(0, 18), - MTK_FUNCTION(0, "GPIO36"), - MTK_FUNCTION(1, "I2S1_LRCK"), - MTK_FUNCTION(3, "PCM_SYNC"), - MTK_FUNCTION(6, "AP_PCM_SYNC") - ), - MTK_PIN( - PINCTRL_PIN(37, "I2S1_MCLK"), - "AA18", "mt7623", - MTK_EINT_FUNCTION(0, 19), - MTK_FUNCTION(0, "GPIO37"), - MTK_FUNCTION(1, "I2S1_MCLK") - ), - MTK_PIN( - PINCTRL_PIN(38, "GPIO38"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO38") - ), - MTK_PIN( - PINCTRL_PIN(39, "JTMS"), - "G21", "mt7623", - MTK_EINT_FUNCTION(0, 21), - MTK_FUNCTION(0, "GPIO39"), - MTK_FUNCTION(1, "JTMS") - ), - MTK_PIN( - PINCTRL_PIN(40, "GPIO40"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO40") - ), - MTK_PIN( - PINCTRL_PIN(41, "JTDI"), - "H22", "mt7623", - MTK_EINT_FUNCTION(0, 23), - MTK_FUNCTION(0, "GPIO41"), - MTK_FUNCTION(1, "JTDI") - ), - MTK_PIN( - PINCTRL_PIN(42, "JTDO"), - "H21", "mt7623", - MTK_EINT_FUNCTION(0, 24), - MTK_FUNCTION(0, "GPIO42"), - MTK_FUNCTION(1, "JTDO") - ), - MTK_PIN( - PINCTRL_PIN(43, "NCLE"), - "C7", "mt7623", - MTK_EINT_FUNCTION(0, 25), - MTK_FUNCTION(0, "GPIO43"), - MTK_FUNCTION(1, "NCLE"), - MTK_FUNCTION(2, "EXT_XCS2") - ), - MTK_PIN( - PINCTRL_PIN(44, "NCEB1"), - "C6", "mt7623", - MTK_EINT_FUNCTION(0, 26), - MTK_FUNCTION(0, "GPIO44"), - MTK_FUNCTION(1, "NCEB1"), - MTK_FUNCTION(2, "IDDIG") - ), - MTK_PIN( - PINCTRL_PIN(45, "NCEB0"), - "D7", "mt7623", - MTK_EINT_FUNCTION(0, 27), - MTK_FUNCTION(0, "GPIO45"), - MTK_FUNCTION(1, "NCEB0"), - MTK_FUNCTION(2, "DRV_VBUS") - ), - MTK_PIN( - PINCTRL_PIN(46, "IR"), - "D15", "mt7623", - MTK_EINT_FUNCTION(0, 28), - MTK_FUNCTION(0, "GPIO46"), - MTK_FUNCTION(1, "IR") - ), - MTK_PIN( - PINCTRL_PIN(47, "NREB"), - "A6", "mt7623", - MTK_EINT_FUNCTION(0, 29), - MTK_FUNCTION(0, "GPIO47"), - MTK_FUNCTION(1, "NREB") - ), - MTK_PIN( - PINCTRL_PIN(48, "NRNB"), - "B6", "mt7623", - MTK_EINT_FUNCTION(0, 30), - MTK_FUNCTION(0, "GPIO48"), - MTK_FUNCTION(1, "NRNB") - ), - MTK_PIN( - PINCTRL_PIN(49, "I2S0_DATA"), - "AB18", "mt7623", - MTK_EINT_FUNCTION(0, 31), - MTK_FUNCTION(0, "GPIO49"), - MTK_FUNCTION(1, "I2S0_DATA"), - MTK_FUNCTION(3, "PCM_TX"), - MTK_FUNCTION(6, "AP_I2S_DO") - ), - MTK_PIN( - PINCTRL_PIN(50, "GPIO50"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO50") - ), - MTK_PIN( - PINCTRL_PIN(51, "GPIO51"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO51") - ), - MTK_PIN( - PINCTRL_PIN(52, "GPIO52"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO52") - ), - MTK_PIN( - PINCTRL_PIN(53, "SPI0_CSN"), - "E7", "mt7623", - MTK_EINT_FUNCTION(0, 35), - MTK_FUNCTION(0, "GPIO53"), - MTK_FUNCTION(1, "SPI0_CS"), - MTK_FUNCTION(5, "PWM1") - ), - MTK_PIN( - PINCTRL_PIN(54, "SPI0_CK"), - "F7", "mt7623", - MTK_EINT_FUNCTION(0, 36), - MTK_FUNCTION(0, "GPIO54"), - MTK_FUNCTION(1, "SPI0_CK") - ), - MTK_PIN( - PINCTRL_PIN(55, "SPI0_MI"), - "E6", "mt7623", - MTK_EINT_FUNCTION(0, 37), - MTK_FUNCTION(0, "GPIO55"), - MTK_FUNCTION(1, "SPI0_MI"), - MTK_FUNCTION(2, "SPI0_MO"), - MTK_FUNCTION(3, "MSDC1_WP"), - MTK_FUNCTION(5, "PWM2") - ), - MTK_PIN( - PINCTRL_PIN(56, "SPI0_MO"), - "G7", "mt7623", - MTK_EINT_FUNCTION(0, 38), - MTK_FUNCTION(0, "GPIO56"), - MTK_FUNCTION(1, "SPI0_MO"), - MTK_FUNCTION(2, "SPI0_MI") - ), - MTK_PIN( - PINCTRL_PIN(57, "GPIO57"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO57") - ), - MTK_PIN( - PINCTRL_PIN(58, "GPIO58"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO58") - ), - MTK_PIN( - PINCTRL_PIN(59, "GPIO59"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO59") - ), - MTK_PIN( - PINCTRL_PIN(60, "WB_RSTB"), - "Y21", "mt7623", - MTK_EINT_FUNCTION(0, 41), - MTK_FUNCTION(0, "GPIO60"), - MTK_FUNCTION(1, "WB_RSTB") - ), - MTK_PIN( - PINCTRL_PIN(61, "GPIO61"), - "AA21", "mt7623", - MTK_EINT_FUNCTION(0, 42), - MTK_FUNCTION(0, "GPIO61"), - MTK_FUNCTION(1, "TEST_FD") - ), - MTK_PIN( - PINCTRL_PIN(62, "GPIO62"), - "AB22", "mt7623", - MTK_EINT_FUNCTION(0, 43), - MTK_FUNCTION(0, "GPIO62"), - MTK_FUNCTION(1, "TEST_FC") - ), - MTK_PIN( - PINCTRL_PIN(63, "WB_SCLK"), - "AC23", "mt7623", - MTK_EINT_FUNCTION(0, 44), - MTK_FUNCTION(0, "GPIO63"), - MTK_FUNCTION(1, "WB_SCLK") - ), - MTK_PIN( - PINCTRL_PIN(64, "WB_SDATA"), - "AB21", "mt7623", - MTK_EINT_FUNCTION(0, 45), - MTK_FUNCTION(0, "GPIO64"), - MTK_FUNCTION(1, "WB_SDATA") - ), - MTK_PIN( - PINCTRL_PIN(65, "WB_SEN"), - "AB24", "mt7623", - MTK_EINT_FUNCTION(0, 46), - MTK_FUNCTION(0, "GPIO65"), - MTK_FUNCTION(1, "WB_SEN") - ), - MTK_PIN( - PINCTRL_PIN(66, "WB_CRTL0"), - "AB20", "mt7623", - MTK_EINT_FUNCTION(0, 47), - MTK_FUNCTION(0, "GPIO66"), - MTK_FUNCTION(1, "WB_CRTL0") - ), - MTK_PIN( - PINCTRL_PIN(67, "WB_CRTL1"), - "AC20", "mt7623", - MTK_EINT_FUNCTION(0, 48), - MTK_FUNCTION(0, "GPIO67"), - MTK_FUNCTION(1, "WB_CRTL1") - ), - MTK_PIN( - PINCTRL_PIN(68, "WB_CRTL2"), - "AB19", "mt7623", - MTK_EINT_FUNCTION(0, 49), - MTK_FUNCTION(0, "GPIO68"), - MTK_FUNCTION(1, "WB_CRTL2") - ), - MTK_PIN( - PINCTRL_PIN(69, "WB_CRTL3"), - "AC19", "mt7623", - MTK_EINT_FUNCTION(0, 50), - MTK_FUNCTION(0, "GPIO69"), - MTK_FUNCTION(1, "WB_CRTL3") - ), - MTK_PIN( - PINCTRL_PIN(70, "WB_CRTL4"), - "AD19", "mt7623", - MTK_EINT_FUNCTION(0, 51), - MTK_FUNCTION(0, "GPIO70"), - MTK_FUNCTION(1, "WB_CRTL4") - ), - MTK_PIN( - PINCTRL_PIN(71, "WB_CRTL5"), - "AE19", "mt7623", - MTK_EINT_FUNCTION(0, 52), - MTK_FUNCTION(0, "GPIO71"), - MTK_FUNCTION(1, "WB_CRTL5") - ), - MTK_PIN( - PINCTRL_PIN(72, "I2S0_DATA_IN"), - "AA20", "mt7623", - MTK_EINT_FUNCTION(0, 53), - MTK_FUNCTION(0, "GPIO72"), - MTK_FUNCTION(1, "I2S0_DATA_IN"), - MTK_FUNCTION(3, "PCM_RX"), - MTK_FUNCTION(4, "PWM0"), - MTK_FUNCTION(5, "DISP_PWM"), - MTK_FUNCTION(6, "AP_I2S_DI") - ), - MTK_PIN( - PINCTRL_PIN(73, "I2S0_LRCK"), - "Y20", "mt7623", - MTK_EINT_FUNCTION(0, 54), - MTK_FUNCTION(0, "GPIO73"), - MTK_FUNCTION(1, "I2S0_LRCK"), - MTK_FUNCTION(3, "PCM_SYNC"), - MTK_FUNCTION(6, "AP_I2S_LRCK") - ), - MTK_PIN( - PINCTRL_PIN(74, "I2S0_BCK"), - "Y19", "mt7623", - MTK_EINT_FUNCTION(0, 55), - MTK_FUNCTION(0, "GPIO74"), - MTK_FUNCTION(1, "I2S0_BCK"), - MTK_FUNCTION(3, "PCM_CLK0"), - MTK_FUNCTION(6, "AP_I2S_BCK") - ), - MTK_PIN( - PINCTRL_PIN(75, "SDA0"), - "K19", "mt7623", - MTK_EINT_FUNCTION(0, 56), - MTK_FUNCTION(0, "GPIO75"), - MTK_FUNCTION(1, "SDA0") - ), - MTK_PIN( - PINCTRL_PIN(76, "SCL0"), - "K20", "mt7623", - MTK_EINT_FUNCTION(0, 57), - MTK_FUNCTION(0, "GPIO76"), - MTK_FUNCTION(1, "SCL0") - ), - MTK_PIN( - PINCTRL_PIN(77, "GPIO77"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO77") - ), - MTK_PIN( - PINCTRL_PIN(78, "GPIO78"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO78") - ), - MTK_PIN( - PINCTRL_PIN(79, "GPIO79"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO79") - ), - MTK_PIN( - PINCTRL_PIN(80, "GPIO80"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO80") - ), - MTK_PIN( - PINCTRL_PIN(81, "GPIO81"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO81") - ), - MTK_PIN( - PINCTRL_PIN(82, "GPIO82"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO82") - ), - MTK_PIN( - PINCTRL_PIN(83, "LCM_RST"), - "V16", "mt7623", - MTK_EINT_FUNCTION(0, 64), - MTK_FUNCTION(0, "GPIO83"), - MTK_FUNCTION(1, "LCM_RST") - ), - MTK_PIN( - PINCTRL_PIN(84, "DSI_TE"), - "V14", "mt7623", - MTK_EINT_FUNCTION(0, 65), - MTK_FUNCTION(0, "GPIO84"), - MTK_FUNCTION(1, "DSI_TE") - ), - MTK_PIN( - PINCTRL_PIN(85, "GPIO85"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO85") - ), - MTK_PIN( - PINCTRL_PIN(86, "GPIO86"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO86") - ), - MTK_PIN( - PINCTRL_PIN(87, "GPIO87"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO87") - ), - MTK_PIN( - PINCTRL_PIN(88, "GPIO88"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO88") - ), - MTK_PIN( - PINCTRL_PIN(89, "GPIO89"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO89") - ), - MTK_PIN( - PINCTRL_PIN(90, "GPIO90"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO90") - ), - MTK_PIN( - PINCTRL_PIN(91, "GPIO91"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO91") - ), - MTK_PIN( - PINCTRL_PIN(92, "GPIO92"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO92") - ), - MTK_PIN( - PINCTRL_PIN(93, "GPIO93"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO93") - ), - MTK_PIN( - PINCTRL_PIN(94, "GPIO94"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO94") - ), - MTK_PIN( - PINCTRL_PIN(95, "MIPI_TCN"), - "AB14", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO95"), - MTK_FUNCTION(1, "TCN") - ), - MTK_PIN( - PINCTRL_PIN(96, "MIPI_TCP"), - "AC14", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO96"), - MTK_FUNCTION(1, "TCP") - ), - MTK_PIN( - PINCTRL_PIN(97, "MIPI_TDN1"), - "AE15", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO97"), - MTK_FUNCTION(1, "TDN1") - ), - MTK_PIN( - PINCTRL_PIN(98, "MIPI_TDP1"), - "AD15", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO98"), - MTK_FUNCTION(1, "TDP1") - ), - MTK_PIN( - PINCTRL_PIN(99, "MIPI_TDN0"), - "AB15", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO99"), - MTK_FUNCTION(1, "TDN0") - ), - MTK_PIN( - PINCTRL_PIN(100, "MIPI_TDP0"), - "AC15", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO100"), - MTK_FUNCTION(1, "TDP0") - ), - MTK_PIN( - PINCTRL_PIN(101, "GPIO101"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO101") - ), - MTK_PIN( - PINCTRL_PIN(102, "GPIO102"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO102") - ), - MTK_PIN( - PINCTRL_PIN(103, "GPIO103"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO103") - ), - MTK_PIN( - PINCTRL_PIN(104, "GPIO104"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO104") - ), - MTK_PIN( - PINCTRL_PIN(105, "MSDC1_CMD"), - "AD2", "mt7623", - MTK_EINT_FUNCTION(0, 78), - MTK_FUNCTION(0, "GPIO105"), - MTK_FUNCTION(1, "MSDC1_CMD"), - MTK_FUNCTION(3, "SDA1"), - MTK_FUNCTION(6, "I2SOUT_BCK") - ), - MTK_PIN( - PINCTRL_PIN(106, "MSDC1_CLK"), - "AD3", "mt7623", - MTK_EINT_FUNCTION(0, 79), - MTK_FUNCTION(0, "GPIO106"), - MTK_FUNCTION(1, "MSDC1_CLK"), - MTK_FUNCTION(3, "SCL1"), - MTK_FUNCTION(6, "I2SOUT_LRCK") - ), - MTK_PIN( - PINCTRL_PIN(107, "MSDC1_DAT0"), - "AE2", "mt7623", - MTK_EINT_FUNCTION(0, 80), - MTK_FUNCTION(0, "GPIO107"), - MTK_FUNCTION(1, "MSDC1_DAT0"), - MTK_FUNCTION(5, "UTXD0"), - MTK_FUNCTION(6, "I2SOUT_DATA_OUT") - ), - MTK_PIN( - PINCTRL_PIN(108, "MSDC1_DAT1"), - "AC1", "mt7623", - MTK_EINT_FUNCTION(0, 81), - MTK_FUNCTION(0, "GPIO108"), - MTK_FUNCTION(1, "MSDC1_DAT1"), - MTK_FUNCTION(3, "PWM0"), - MTK_FUNCTION(5, "URXD0"), - MTK_FUNCTION(6, "PWM1") - ), - MTK_PIN( - PINCTRL_PIN(109, "MSDC1_DAT2"), - "AC3", "mt7623", - MTK_EINT_FUNCTION(0, 82), - MTK_FUNCTION(0, "GPIO109"), - MTK_FUNCTION(1, "MSDC1_DAT2"), - MTK_FUNCTION(3, "SDA2"), - MTK_FUNCTION(5, "UTXD1"), - MTK_FUNCTION(6, "PWM2") - ), - MTK_PIN( - PINCTRL_PIN(110, "MSDC1_DAT3"), - "AC4", "mt7623", - MTK_EINT_FUNCTION(0, 83), - MTK_FUNCTION(0, "GPIO110"), - MTK_FUNCTION(1, "MSDC1_DAT3"), - MTK_FUNCTION(3, "SCL2"), - MTK_FUNCTION(5, "URXD1"), - MTK_FUNCTION(6, "PWM3") - ), - MTK_PIN( - PINCTRL_PIN(111, "MSDC0_DAT7"), - "A2", "mt7623", - MTK_EINT_FUNCTION(0, 84), - MTK_FUNCTION(0, "GPIO111"), - MTK_FUNCTION(1, "MSDC0_DAT7"), - MTK_FUNCTION(4, "NLD7") - ), - MTK_PIN( - PINCTRL_PIN(112, "MSDC0_DAT6"), - "B3", "mt7623", - MTK_EINT_FUNCTION(0, 85), - MTK_FUNCTION(0, "GPIO112"), - MTK_FUNCTION(1, "MSDC0_DAT6"), - MTK_FUNCTION(4, "NLD6") - ), - MTK_PIN( - PINCTRL_PIN(113, "MSDC0_DAT5"), - "C4", "mt7623", - MTK_EINT_FUNCTION(0, 86), - MTK_FUNCTION(0, "GPIO113"), - MTK_FUNCTION(1, "MSDC0_DAT5"), - MTK_FUNCTION(4, "NLD5") - ), - MTK_PIN( - PINCTRL_PIN(114, "MSDC0_DAT4"), - "A4", "mt7623", - MTK_EINT_FUNCTION(0, 87), - MTK_FUNCTION(0, "GPIO114"), - MTK_FUNCTION(1, "MSDC0_DAT4"), - MTK_FUNCTION(4, "NLD4") - ), - MTK_PIN( - PINCTRL_PIN(115, "MSDC0_RSTB"), - "C5", "mt7623", - MTK_EINT_FUNCTION(0, 88), - MTK_FUNCTION(0, "GPIO115"), - MTK_FUNCTION(1, "MSDC0_RSTB"), - MTK_FUNCTION(4, "NLD8") - ), - MTK_PIN( - PINCTRL_PIN(116, "MSDC0_CMD"), - "D5", "mt7623", - MTK_EINT_FUNCTION(0, 89), - MTK_FUNCTION(0, "GPIO116"), - MTK_FUNCTION(1, "MSDC0_CMD"), - MTK_FUNCTION(4, "NALE") - ), - MTK_PIN( - PINCTRL_PIN(117, "MSDC0_CLK"), - "B1", "mt7623", - MTK_EINT_FUNCTION(0, 90), - MTK_FUNCTION(0, "GPIO117"), - MTK_FUNCTION(1, "MSDC0_CLK"), - MTK_FUNCTION(4, "NWEB") - ), - MTK_PIN( - PINCTRL_PIN(118, "MSDC0_DAT3"), - "D6", "mt7623", - MTK_EINT_FUNCTION(0, 91), - MTK_FUNCTION(0, "GPIO118"), - MTK_FUNCTION(1, "MSDC0_DAT3"), - MTK_FUNCTION(4, "NLD3") - ), - MTK_PIN( - PINCTRL_PIN(119, "MSDC0_DAT2"), - "B2", "mt7623", - MTK_EINT_FUNCTION(0, 92), - MTK_FUNCTION(0, "GPIO119"), - MTK_FUNCTION(1, "MSDC0_DAT2"), - MTK_FUNCTION(4, "NLD2") - ), - MTK_PIN( - PINCTRL_PIN(120, "MSDC0_DAT1"), - "A3", "mt7623", - MTK_EINT_FUNCTION(0, 93), - MTK_FUNCTION(0, "GPIO120"), - MTK_FUNCTION(1, "MSDC0_DAT1"), - MTK_FUNCTION(4, "NLD1") - ), - MTK_PIN( - PINCTRL_PIN(121, "MSDC0_DAT0"), - "B4", "mt7623", - MTK_EINT_FUNCTION(0, 94), - MTK_FUNCTION(0, "GPIO121"), - MTK_FUNCTION(1, "MSDC0_DAT0"), - MTK_FUNCTION(4, "NLD0"), - MTK_FUNCTION(5, "WATCHDOG") - ), - MTK_PIN( - PINCTRL_PIN(122, "GPIO122"), - "H17", "mt7623", - MTK_EINT_FUNCTION(0, 95), - MTK_FUNCTION(0, "GPIO122"), - MTK_FUNCTION(1, "TEST"), - MTK_FUNCTION(4, "SDA2"), - MTK_FUNCTION(5, "URXD0") - ), - MTK_PIN( - PINCTRL_PIN(123, "GPIO123"), - "F17", "mt7623", - MTK_EINT_FUNCTION(0, 96), - MTK_FUNCTION(0, "GPIO123"), - MTK_FUNCTION(1, "TEST"), - MTK_FUNCTION(4, "SCL2"), - MTK_FUNCTION(5, "UTXD0") - ), - MTK_PIN( - PINCTRL_PIN(124, "GPIO124"), - "H18", "mt7623", - MTK_EINT_FUNCTION(0, 97), - MTK_FUNCTION(0, "GPIO124"), - MTK_FUNCTION(1, "TEST"), - MTK_FUNCTION(4, "SDA1"), - MTK_FUNCTION(5, "PWM3") - ), - MTK_PIN( - PINCTRL_PIN(125, "GPIO125"), - "G17", "mt7623", - MTK_EINT_FUNCTION(0, 98), - MTK_FUNCTION(0, "GPIO125"), - MTK_FUNCTION(1, "TEST"), - MTK_FUNCTION(4, "SCL1"), - MTK_FUNCTION(5, "PWM4") - ), - MTK_PIN( - PINCTRL_PIN(126, "I2S0_MCLK"), - "AA19", "mt7623", - MTK_EINT_FUNCTION(0, 99), - MTK_FUNCTION(0, "GPIO126"), - MTK_FUNCTION(1, "I2S0_MCLK"), - MTK_FUNCTION(6, "AP_I2S_MCLK") - ), - MTK_PIN( - PINCTRL_PIN(127, "GPIO127"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO127") - ), - MTK_PIN( - PINCTRL_PIN(128, "GPIO128"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO128") - ), - MTK_PIN( - PINCTRL_PIN(129, "GPIO129"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO129") - ), - MTK_PIN( - PINCTRL_PIN(130, "GPIO130"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO130") - ), - MTK_PIN( - PINCTRL_PIN(131, "GPIO131"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO131") - ), - MTK_PIN( - PINCTRL_PIN(132, "GPIO132"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO132") - ), - MTK_PIN( - PINCTRL_PIN(133, "GPIO133"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO133") - ), - MTK_PIN( - PINCTRL_PIN(134, "GPIO134"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO134") - ), - MTK_PIN( - PINCTRL_PIN(135, "GPIO135"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO135") - ), - MTK_PIN( - PINCTRL_PIN(136, "GPIO136"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO136") - ), - MTK_PIN( - PINCTRL_PIN(137, "GPIO137"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO137") - ), - MTK_PIN( - PINCTRL_PIN(138, "GPIO138"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO138") - ), - MTK_PIN( - PINCTRL_PIN(139, "GPIO139"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO139") - ), - MTK_PIN( - PINCTRL_PIN(140, "GPIO140"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO140") - ), - MTK_PIN( - PINCTRL_PIN(141, "GPIO141"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO141") - ), - MTK_PIN( - PINCTRL_PIN(142, "GPIO142"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO142") - ), - MTK_PIN( - PINCTRL_PIN(143, "GPIO143"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO143") - ), - MTK_PIN( - PINCTRL_PIN(144, "GPIO144"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO144") - ), - MTK_PIN( - PINCTRL_PIN(145, "GPIO145"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO145") - ), - MTK_PIN( - PINCTRL_PIN(146, "GPIO146"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO146") - ), - MTK_PIN( - PINCTRL_PIN(147, "GPIO147"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO147") - ), - MTK_PIN( - PINCTRL_PIN(148, "GPIO148"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO148") - ), - MTK_PIN( - PINCTRL_PIN(149, "GPIO149"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO149") - ), - MTK_PIN( - PINCTRL_PIN(150, "GPIO150"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO150") - ), - MTK_PIN( - PINCTRL_PIN(151, "GPIO151"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO151") - ), - MTK_PIN( - PINCTRL_PIN(152, "GPIO152"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO152") - ), - MTK_PIN( - PINCTRL_PIN(153, "GPIO153"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO153") - ), - MTK_PIN( - PINCTRL_PIN(154, "GPIO154"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO154") - ), - MTK_PIN( - PINCTRL_PIN(155, "GPIO155"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO155") - ), - MTK_PIN( - PINCTRL_PIN(156, "GPIO156"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO156") - ), - MTK_PIN( - PINCTRL_PIN(157, "GPIO157"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO157") - ), - MTK_PIN( - PINCTRL_PIN(158, "GPIO158"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO158") - ), - MTK_PIN( - PINCTRL_PIN(159, "GPIO159"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO159") - ), - MTK_PIN( - PINCTRL_PIN(160, "GPIO160"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO160") - ), - MTK_PIN( - PINCTRL_PIN(161, "GPIO161"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO161") - ), - MTK_PIN( - PINCTRL_PIN(162, "GPIO162"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO162") - ), - MTK_PIN( - PINCTRL_PIN(163, "GPIO163"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO163") - ), - MTK_PIN( - PINCTRL_PIN(164, "GPIO164"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO164") - ), - MTK_PIN( - PINCTRL_PIN(165, "GPIO165"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO165") - ), - MTK_PIN( - PINCTRL_PIN(166, "GPIO166"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO166") - ), - MTK_PIN( - PINCTRL_PIN(167, "GPIO167"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO167") - ), - MTK_PIN( - PINCTRL_PIN(168, "GPIO168"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO168") - ), - MTK_PIN( - PINCTRL_PIN(169, "GPIO169"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO169") - ), - MTK_PIN( - PINCTRL_PIN(170, "GPIO170"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO170") - ), - MTK_PIN( - PINCTRL_PIN(171, "GPIO171"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO171") - ), - MTK_PIN( - PINCTRL_PIN(172, "GPIO172"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO172") - ), - MTK_PIN( - PINCTRL_PIN(173, "GPIO173"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO173") - ), - MTK_PIN( - PINCTRL_PIN(174, "GPIO174"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO174") - ), - MTK_PIN( - PINCTRL_PIN(175, "GPIO175"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO175") - ), - MTK_PIN( - PINCTRL_PIN(176, "GPIO176"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO176") - ), - MTK_PIN( - PINCTRL_PIN(177, "GPIO177"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO177") - ), - MTK_PIN( - PINCTRL_PIN(178, "GPIO178"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO178") - ), - MTK_PIN( - PINCTRL_PIN(179, "GPIO179"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO179") - ), - MTK_PIN( - PINCTRL_PIN(180, "GPIO180"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO180") - ), - MTK_PIN( - PINCTRL_PIN(181, "GPIO181"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO181") - ), - MTK_PIN( - PINCTRL_PIN(182, "GPIO182"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO182") - ), - MTK_PIN( - PINCTRL_PIN(183, "GPIO183"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO183") - ), - MTK_PIN( - PINCTRL_PIN(184, "GPIO184"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO184") - ), - MTK_PIN( - PINCTRL_PIN(185, "GPIO185"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO185") - ), - MTK_PIN( - PINCTRL_PIN(186, "GPIO186"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO186") - ), - MTK_PIN( - PINCTRL_PIN(187, "GPIO187"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO187") - ), - MTK_PIN( - PINCTRL_PIN(188, "GPIO188"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO188") - ), - MTK_PIN( - PINCTRL_PIN(189, "GPIO189"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO189") - ), - MTK_PIN( - PINCTRL_PIN(190, "GPIO190"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO190") - ), - MTK_PIN( - PINCTRL_PIN(191, "GPIO191"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO191") - ), - MTK_PIN( - PINCTRL_PIN(192, "GPIO192"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO192") - ), - MTK_PIN( - PINCTRL_PIN(193, "GPIO193"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO193") - ), - MTK_PIN( - PINCTRL_PIN(194, "GPIO194"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO194") - ), - MTK_PIN( - PINCTRL_PIN(195, "GPIO195"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO195") - ), - MTK_PIN( - PINCTRL_PIN(196, "GPIO196"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO196") - ), - MTK_PIN( - PINCTRL_PIN(197, "GPIO197"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO197") - ), - MTK_PIN( - PINCTRL_PIN(198, "GPIO198"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO198") - ), - MTK_PIN( - PINCTRL_PIN(199, "SPI1_CK"), - "E19", "mt7623", - MTK_EINT_FUNCTION(0, 111), - MTK_FUNCTION(0, "GPIO199"), - MTK_FUNCTION(1, "SPI1_CK") - ), - MTK_PIN( - PINCTRL_PIN(200, "URXD2"), - "K18", "mt7623", - MTK_EINT_FUNCTION(0, 112), - MTK_FUNCTION(0, "GPIO200"), - MTK_FUNCTION(6, "URXD2") - ), - MTK_PIN( - PINCTRL_PIN(201, "UTXD2"), - "L18", "mt7623", - MTK_EINT_FUNCTION(0, 113), - MTK_FUNCTION(0, "GPIO201"), - MTK_FUNCTION(6, "UTXD2") - ), - MTK_PIN( - PINCTRL_PIN(202, "GPIO202"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO202") - ), - MTK_PIN( - PINCTRL_PIN(203, "PWM0"), - "AA16", "mt7623", - MTK_EINT_FUNCTION(0, 115), - MTK_FUNCTION(0, "GPIO203"), - MTK_FUNCTION(1, "PWM0"), - MTK_FUNCTION(2, "DISP_PWM") - ), - MTK_PIN( - PINCTRL_PIN(204, "PWM1"), - "Y16", "mt7623", - MTK_EINT_FUNCTION(0, 116), - MTK_FUNCTION(0, "GPIO204"), - MTK_FUNCTION(1, "PWM1") - ), - MTK_PIN( - PINCTRL_PIN(205, "PWM2"), - "AA15", "mt7623", - MTK_EINT_FUNCTION(0, 117), - MTK_FUNCTION(0, "GPIO205"), - MTK_FUNCTION(1, "PWM2") - ), - MTK_PIN( - PINCTRL_PIN(206, "PWM3"), - "AA17", "mt7623", - MTK_EINT_FUNCTION(0, 118), - MTK_FUNCTION(0, "GPIO206"), - MTK_FUNCTION(1, "PWM3") - ), - MTK_PIN( - PINCTRL_PIN(207, "PWM4"), - "Y15", "mt7623", - MTK_EINT_FUNCTION(0, 119), - MTK_FUNCTION(0, "GPIO207"), - MTK_FUNCTION(1, "PWM4") - ), - MTK_PIN( - PINCTRL_PIN(208, "AUD_EXT_CK1"), - "W14", "mt7623", - MTK_EINT_FUNCTION(0, 120), - MTK_FUNCTION(0, "GPIO208"), - MTK_FUNCTION(1, "AUD_EXT_CK1"), - MTK_FUNCTION(2, "PWM0"), - MTK_FUNCTION(3, "PCIE0_PERST_N"), - MTK_FUNCTION(5, "DISP_PWM") - ), - MTK_PIN( - PINCTRL_PIN(209, "AUD_EXT_CK2"), - "V15", "mt7623", - MTK_EINT_FUNCTION(0, 121), - MTK_FUNCTION(0, "GPIO209"), - MTK_FUNCTION(1, "AUD_EXT_CK2"), - MTK_FUNCTION(2, "MSDC1_WP"), - MTK_FUNCTION(3, "PCIE1_PERST_N"), - MTK_FUNCTION(5, "PWM1") - ), - MTK_PIN( - PINCTRL_PIN(210, "GPIO210"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO210") - ), - MTK_PIN( - PINCTRL_PIN(211, "GPIO211"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO211") - ), - MTK_PIN( - PINCTRL_PIN(212, "GPIO212"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO212") - ), - MTK_PIN( - PINCTRL_PIN(213, "GPIO213"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO213") - ), - MTK_PIN( - PINCTRL_PIN(214, "GPIO214"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO214") - ), - MTK_PIN( - PINCTRL_PIN(215, "GPIO215"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO215") - ), - MTK_PIN( - PINCTRL_PIN(216, "GPIO216"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO216") - ), - MTK_PIN( - PINCTRL_PIN(217, "GPIO217"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO217") - ), - MTK_PIN( - PINCTRL_PIN(218, "GPIO218"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO218") - ), - MTK_PIN( - PINCTRL_PIN(219, "GPIO219"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO219") - ), - MTK_PIN( - PINCTRL_PIN(220, "GPIO220"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO220") - ), - MTK_PIN( - PINCTRL_PIN(221, "GPIO221"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO221") - ), - MTK_PIN( - PINCTRL_PIN(222, "GPIO222"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO222") - ), - MTK_PIN( - PINCTRL_PIN(223, "GPIO223"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO223") - ), - MTK_PIN( - PINCTRL_PIN(224, "GPIO224"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO224") - ), - MTK_PIN( - PINCTRL_PIN(225, "GPIO225"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO225") - ), - MTK_PIN( - PINCTRL_PIN(226, "GPIO226"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO226") - ), - MTK_PIN( - PINCTRL_PIN(227, "GPIO227"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO227") - ), - MTK_PIN( - PINCTRL_PIN(228, "GPIO228"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO228") - ), - MTK_PIN( - PINCTRL_PIN(229, "GPIO229"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO229") - ), - MTK_PIN( - PINCTRL_PIN(230, "GPIO230"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO230") - ), - MTK_PIN( - PINCTRL_PIN(231, "GPIO231"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO231") - ), - MTK_PIN( - PINCTRL_PIN(232, "GPIO232"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO232") - ), - MTK_PIN( - PINCTRL_PIN(233, "GPIO233"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO233") - ), - MTK_PIN( - PINCTRL_PIN(234, "GPIO234"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO234") - ), - MTK_PIN( - PINCTRL_PIN(235, "GPIO235"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO235") - ), - MTK_PIN( - PINCTRL_PIN(236, "EXT_SDIO3"), - "A8", "mt7623", - MTK_EINT_FUNCTION(0, 122), - MTK_FUNCTION(0, "GPIO236"), - MTK_FUNCTION(1, "EXT_SDIO3"), - MTK_FUNCTION(2, "IDDIG") - ), - MTK_PIN( - PINCTRL_PIN(237, "EXT_SDIO2"), - "D8", "mt7623", - MTK_EINT_FUNCTION(0, 123), - MTK_FUNCTION(0, "GPIO237"), - MTK_FUNCTION(1, "EXT_SDIO2"), - MTK_FUNCTION(2, "DRV_VBUS") - ), - MTK_PIN( - PINCTRL_PIN(238, "EXT_SDIO1"), - "D9", "mt7623", - MTK_EINT_FUNCTION(0, 124), - MTK_FUNCTION(0, "GPIO238"), - MTK_FUNCTION(1, "EXT_SDIO1") - ), - MTK_PIN( - PINCTRL_PIN(239, "EXT_SDIO0"), - "B8", "mt7623", - MTK_EINT_FUNCTION(0, 125), - MTK_FUNCTION(0, "GPIO239"), - MTK_FUNCTION(1, "EXT_SDIO0") - ), - MTK_PIN( - PINCTRL_PIN(240, "EXT_XCS"), - "C9", "mt7623", - MTK_EINT_FUNCTION(0, 126), - MTK_FUNCTION(0, "GPIO240"), - MTK_FUNCTION(1, "EXT_XCS") - ), - MTK_PIN( - PINCTRL_PIN(241, "EXT_SCK"), - "C8", "mt7623", - MTK_EINT_FUNCTION(0, 127), - MTK_FUNCTION(0, "GPIO241"), - MTK_FUNCTION(1, "EXT_SCK") - ), - MTK_PIN( - PINCTRL_PIN(242, "URTS2"), - "G18", "mt7623", - MTK_EINT_FUNCTION(0, 128), - MTK_FUNCTION(0, "GPIO242"), - MTK_FUNCTION(1, "URTS2"), - MTK_FUNCTION(2, "UTXD3"), - MTK_FUNCTION(3, "URXD3"), - MTK_FUNCTION(4, "SCL1") - ), - MTK_PIN( - PINCTRL_PIN(243, "UCTS2"), - "H19", "mt7623", - MTK_EINT_FUNCTION(0, 129), - MTK_FUNCTION(0, "GPIO243"), - MTK_FUNCTION(1, "UCTS2"), - MTK_FUNCTION(2, "URXD3"), - MTK_FUNCTION(3, "UTXD3"), - MTK_FUNCTION(4, "SDA1") - ), - MTK_PIN( - PINCTRL_PIN(244, "GPIO244"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO244") - ), - MTK_PIN( - PINCTRL_PIN(245, "GPIO245"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO245") - ), - MTK_PIN( - PINCTRL_PIN(246, "GPIO246"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO246") - ), - MTK_PIN( - PINCTRL_PIN(247, "GPIO247"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO247") - ), - MTK_PIN( - PINCTRL_PIN(248, "GPIO248"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO248") - ), - MTK_PIN( - PINCTRL_PIN(249, "GPIO249"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO249") - ), - MTK_PIN( - PINCTRL_PIN(250, "GPIO250"), - "A15", "mt7623", - MTK_EINT_FUNCTION(0, 135), - MTK_FUNCTION(0, "GPIO250"), - MTK_FUNCTION(1, "TEST_MD7"), - MTK_FUNCTION(6, "PCIE0_CLKREQ_N") - ), - MTK_PIN( - PINCTRL_PIN(251, "GPIO251"), - "B15", "mt7623", - MTK_EINT_FUNCTION(0, 136), - MTK_FUNCTION(0, "GPIO251"), - MTK_FUNCTION(1, "TEST_MD6"), - MTK_FUNCTION(6, "PCIE0_WAKE_N") - ), - MTK_PIN( - PINCTRL_PIN(252, "GPIO252"), - "C16", "mt7623", - MTK_EINT_FUNCTION(0, 137), - MTK_FUNCTION(0, "GPIO252"), - MTK_FUNCTION(1, "TEST_MD5"), - MTK_FUNCTION(6, "PCIE1_CLKREQ_N") - ), - MTK_PIN( - PINCTRL_PIN(253, "GPIO253"), - "D17", "mt7623", - MTK_EINT_FUNCTION(0, 138), - MTK_FUNCTION(0, "GPIO253"), - MTK_FUNCTION(1, "TEST_MD4"), - MTK_FUNCTION(6, "PCIE1_WAKE_N") - ), - MTK_PIN( - PINCTRL_PIN(254, "GPIO254"), - "D16", "mt7623", - MTK_EINT_FUNCTION(0, 139), - MTK_FUNCTION(0, "GPIO254"), - MTK_FUNCTION(1, "TEST_MD3"), - MTK_FUNCTION(6, "PCIE2_CLKREQ_N") - ), - MTK_PIN( - PINCTRL_PIN(255, "GPIO255"), - "C17", "mt7623", - MTK_EINT_FUNCTION(0, 140), - MTK_FUNCTION(0, "GPIO255"), - MTK_FUNCTION(1, "TEST_MD2"), - MTK_FUNCTION(6, "PCIE2_WAKE_N") - ), - MTK_PIN( - PINCTRL_PIN(256, "GPIO256"), - "B17", "mt7623", - MTK_EINT_FUNCTION(0, 141), - MTK_FUNCTION(0, "GPIO256"), - MTK_FUNCTION(1, "TEST_MD1") - ), - MTK_PIN( - PINCTRL_PIN(257, "GPIO257"), - "C15", "mt7623", - MTK_EINT_FUNCTION(0, 142), - MTK_FUNCTION(0, "GPIO257"), - MTK_FUNCTION(1, "TEST_MD0") - ), - MTK_PIN( - PINCTRL_PIN(258, "GPIO258"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO258") - ), - MTK_PIN( - PINCTRL_PIN(259, "GPIO259"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO259") - ), - MTK_PIN( - PINCTRL_PIN(260, "GPIO260"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO260") - ), - MTK_PIN( - PINCTRL_PIN(261, "MSDC1_INS"), - "AD1", "mt7623", - MTK_EINT_FUNCTION(0, 146), - MTK_FUNCTION(0, "GPIO261"), - MTK_FUNCTION(1, "MSDC1_INS") - ), - MTK_PIN( - PINCTRL_PIN(262, "G2_TXEN"), - "A23", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO262"), - MTK_FUNCTION(1, "G2_TXEN") - ), - MTK_PIN( - PINCTRL_PIN(263, "G2_TXD3"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO263"), - MTK_FUNCTION(1, "G2_TXD3") - ), - MTK_PIN( - PINCTRL_PIN(264, "G2_TXD2"), - "C24", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO264"), - MTK_FUNCTION(1, "G2_TXD2") - ), - MTK_PIN( - PINCTRL_PIN(265, "G2_TXD1"), - "B25", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO265"), - MTK_FUNCTION(1, "G2_TXD1") - ), - MTK_PIN( - PINCTRL_PIN(266, "G2_TXD0"), - "A24", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO266"), - MTK_FUNCTION(1, "G2_TXD0") - ), - MTK_PIN( - PINCTRL_PIN(267, "G2_TXCLK"), - "C23", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO267"), - MTK_FUNCTION(1, "G2_TXC") - ), - MTK_PIN( - PINCTRL_PIN(268, "G2_RXCLK"), - "B23", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO268"), - MTK_FUNCTION(1, "G2_RXC") - ), - MTK_PIN( - PINCTRL_PIN(269, "G2_RXD0"), - "D21", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO269"), - MTK_FUNCTION(1, "G2_RXD0") - ), - MTK_PIN( - PINCTRL_PIN(270, "G2_RXD1"), - "B22", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO270"), - MTK_FUNCTION(1, "G2_RXD1") - ), - MTK_PIN( - PINCTRL_PIN(271, "G2_RXD2"), - "A22", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO271"), - MTK_FUNCTION(1, "G2_RXD2") - ), - MTK_PIN( - PINCTRL_PIN(272, "G2_RXD3"), - "C22", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO272"), - MTK_FUNCTION(1, "G2_RXD3") - ), - MTK_PIN( - PINCTRL_PIN(273, "GPIO273"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO273") - ), - MTK_PIN( - PINCTRL_PIN(274, "G2_RXDV"), - "C21", "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO274"), - MTK_FUNCTION(1, "G2_RXDV") - ), - MTK_PIN( - PINCTRL_PIN(275, "G2_MDC"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO275"), - MTK_FUNCTION(1, "MDC") - ), - MTK_PIN( - PINCTRL_PIN(276, "G2_MDIO"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO276"), - MTK_FUNCTION(1, "MDIO") - ), - MTK_PIN( - PINCTRL_PIN(277, "GPIO277"), - NULL, "mt7623", - MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), - MTK_FUNCTION(0, "GPIO277") - ), - MTK_PIN( - PINCTRL_PIN(278, "JTAG_RESET"), - "H20", "mt7623", - MTK_EINT_FUNCTION(0, 147), - MTK_FUNCTION(0, "GPIO278"), - MTK_FUNCTION(1, "JTAG_RESET") - ), -}; - -#endif /* __PINCTRL_MTK_MT7623_H */ diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index 9b00be15d258..7bbc0d3cddcf 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -85,6 +85,7 @@ static const struct pinctrl_pin_desc meson_gxbb_periphs_pins[] = { MESON_PIN(GPIODV_15, EE_OFF), MESON_PIN(GPIODV_16, EE_OFF), MESON_PIN(GPIODV_17, EE_OFF), + MESON_PIN(GPIODV_18, EE_OFF), MESON_PIN(GPIODV_19, EE_OFF), MESON_PIN(GPIODV_20, EE_OFF), MESON_PIN(GPIODV_21, EE_OFF), @@ -137,7 +138,6 @@ static const struct pinctrl_pin_desc meson_gxbb_periphs_pins[] = { MESON_PIN(GPIOX_19, EE_OFF), MESON_PIN(GPIOX_20, EE_OFF), MESON_PIN(GPIOX_21, EE_OFF), - MESON_PIN(GPIOX_22, EE_OFF), MESON_PIN(GPIOCLK_0, EE_OFF), MESON_PIN(GPIOCLK_1, EE_OFF), @@ -161,6 +161,11 @@ static const unsigned int nor_q_pins[] = { PIN(BOOT_12, EE_OFF) }; static const unsigned int nor_c_pins[] = { PIN(BOOT_13, EE_OFF) }; static const unsigned int nor_cs_pins[] = { PIN(BOOT_15, EE_OFF) }; +static const unsigned int spi_sclk_pins[] = { PIN(GPIOZ_6, EE_OFF) }; +static const unsigned int spi_ss0_pins[] = { PIN(GPIOZ_7, EE_OFF) }; +static const unsigned int spi_miso_pins[] = { PIN(GPIOZ_12, EE_OFF) }; +static const unsigned int spi_mosi_pins[] = { PIN(GPIOZ_13, EE_OFF) }; + static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) }; static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) }; static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) }; @@ -290,6 +295,9 @@ static const unsigned int i2s_out_ch45_ao_pins[] = { PIN(GPIOAO_13, 0) }; static const unsigned int spdif_out_ao_6_pins[] = { PIN(GPIOAO_6, 0) }; static const unsigned int spdif_out_ao_13_pins[] = { PIN(GPIOAO_13, 0) }; +static const unsigned int ao_cec_pins[] = { PIN(GPIOAO_12, 0) }; +static const unsigned int ee_cec_pins[] = { PIN(GPIOAO_12, 0) }; + static struct meson_pmx_group meson_gxbb_periphs_groups[] = { GPIO_GROUP(GPIOZ_0, EE_OFF), GPIO_GROUP(GPIOZ_1, EE_OFF), @@ -462,6 +470,10 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = { GROUP(eth_txd1, 6, 4), GROUP(eth_txd2, 6, 3), GROUP(eth_txd3, 6, 2), + GROUP(spi_ss0, 5, 26), + GROUP(spi_sclk, 5, 27), + GROUP(spi_miso, 5, 28), + GROUP(spi_mosi, 5, 29), /* Bank H */ GROUP(hdmi_hpd, 1, 26), @@ -551,6 +563,8 @@ static struct meson_pmx_group meson_gxbb_aobus_groups[] = { GROUP(i2s_out_ch45_ao, 1, 1), GROUP(spdif_out_ao_6, 0, 16), GROUP(spdif_out_ao_13, 0, 4), + GROUP(ao_cec, 0, 15), + GROUP(ee_cec, 0, 14), }; static const char * const gpio_periphs_groups[] = { @@ -598,6 +612,10 @@ static const char * const nor_groups[] = { "nor_d", "nor_q", "nor_c", "nor_cs", }; +static const char * const spi_groups[] = { + "spi_mosi", "spi_miso", "spi_ss0", "spi_sclk", +}; + static const char * const sdcard_groups[] = { "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", "sdcard_cmd", "sdcard_clk", @@ -739,10 +757,15 @@ static const char * const spdif_out_ao_groups[] = { "spdif_out_ao_6", "spdif_out_ao_13", }; +static const char * const cec_ao_groups[] = { + "ao_cec", "ee_cec", +}; + static struct meson_pmx_func meson_gxbb_periphs_functions[] = { FUNCTION(gpio_periphs), FUNCTION(emmc), FUNCTION(nor), + FUNCTION(spi), FUNCTION(sdcard), FUNCTION(sdio), FUNCTION(nand), @@ -779,23 +802,24 @@ static struct meson_pmx_func meson_gxbb_aobus_functions[] = { FUNCTION(pwm_ao_b), FUNCTION(i2s_out_ao), FUNCTION(spdif_out_ao), + FUNCTION(cec_ao), }; static struct meson_bank meson_gxbb_periphs_banks[] = { - /* name first last pullen pull dir out in */ - BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_22, EE_OFF), 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), - BANK("Y", PIN(GPIOY_0, EE_OFF), PIN(GPIOY_16, EE_OFF), 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), - BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF), 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), - BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_3, EE_OFF), 1, 20, 1, 20, 3, 20, 4, 20, 5, 20), - BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), - BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF), 2, 20, 2, 20, 6, 20, 7, 20, 8, 20), - BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_17, EE_OFF), 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), - BANK("CLK", PIN(GPIOCLK_0, EE_OFF), PIN(GPIOCLK_3, EE_OFF), 3, 28, 3, 28, 9, 28, 10, 28, 11, 28), + /* name first last irq pullen pull dir out in */ + BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_22, EE_OFF), 106, 128, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), + BANK("Y", PIN(GPIOY_0, EE_OFF), PIN(GPIOY_16, EE_OFF), 89, 105, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), + BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF), 59, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), + BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_3, EE_OFF), 30, 33, 1, 20, 1, 20, 3, 20, 4, 20, 5, 20), + BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 14, 29, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), + BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF), 52, 58, 2, 20, 2, 20, 6, 20, 7, 20, 8, 20), + BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_17, EE_OFF), 34, 51, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), + BANK("CLK", PIN(GPIOCLK_0, EE_OFF), PIN(GPIOCLK_3, EE_OFF), 129, 132, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28), }; static struct meson_bank meson_gxbb_aobus_banks[] = { - /* name first last pullen pull dir out in */ - BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_13, 0), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), + /* name first last irq pullen pull dir out in */ + BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_13, 0), 0, 13, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), }; struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = { diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxl.c b/drivers/pinctrl/meson/pinctrl-meson-gxl.c index 998210eacf37..36c14b85fc7c 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxl.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxl.c @@ -89,6 +89,7 @@ static const struct pinctrl_pin_desc meson_gxl_periphs_pins[] = { MESON_PIN(GPIODV_15, EE_OFF), MESON_PIN(GPIODV_16, EE_OFF), MESON_PIN(GPIODV_17, EE_OFF), + MESON_PIN(GPIODV_18, EE_OFF), MESON_PIN(GPIODV_19, EE_OFF), MESON_PIN(GPIODV_20, EE_OFF), MESON_PIN(GPIODV_21, EE_OFF), @@ -141,6 +142,11 @@ static const unsigned int nor_q_pins[] = { PIN(BOOT_12, EE_OFF) }; static const unsigned int nor_c_pins[] = { PIN(BOOT_13, EE_OFF) }; static const unsigned int nor_cs_pins[] = { PIN(BOOT_15, EE_OFF) }; +static const unsigned int spi_mosi_pins[] = { PIN(GPIOX_8, EE_OFF) }; +static const unsigned int spi_miso_pins[] = { PIN(GPIOX_9, EE_OFF) }; +static const unsigned int spi_ss0_pins[] = { PIN(GPIOX_10, EE_OFF) }; +static const unsigned int spi_sclk_pins[] = { PIN(GPIOX_11, EE_OFF) }; + static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) }; static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) }; static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) }; @@ -234,6 +240,28 @@ static const unsigned int i2s_out_ch67_z_pins[] = { PIN(GPIOZ_7, EE_OFF) }; static const unsigned int spdif_out_h_pins[] = { PIN(GPIOH_4, EE_OFF) }; +static const unsigned int eth_link_led_pins[] = { PIN(GPIOZ_14, EE_OFF) }; +static const unsigned int eth_act_led_pins[] = { PIN(GPIOZ_15, EE_OFF) }; + +static const unsigned int tsin_a_d0_pins[] = { PIN(GPIODV_0, EE_OFF) }; +static const unsigned int tsin_a_d0_x_pins[] = { PIN(GPIOX_10, EE_OFF) }; +static const unsigned int tsin_a_clk_pins[] = { PIN(GPIODV_8, EE_OFF) }; +static const unsigned int tsin_a_clk_x_pins[] = { PIN(GPIOX_11, EE_OFF) }; +static const unsigned int tsin_a_sop_pins[] = { PIN(GPIODV_9, EE_OFF) }; +static const unsigned int tsin_a_sop_x_pins[] = { PIN(GPIOX_8, EE_OFF) }; +static const unsigned int tsin_a_d_valid_pins[] = { PIN(GPIODV_10, EE_OFF) }; +static const unsigned int tsin_a_d_valid_x_pins[] = { PIN(GPIOX_9, EE_OFF) }; +static const unsigned int tsin_a_fail_pins[] = { PIN(GPIODV_11, EE_OFF) }; +static const unsigned int tsin_a_dp_pins[] = { + PIN(GPIODV_1, EE_OFF), + PIN(GPIODV_2, EE_OFF), + PIN(GPIODV_3, EE_OFF), + PIN(GPIODV_4, EE_OFF), + PIN(GPIODV_5, EE_OFF), + PIN(GPIODV_6, EE_OFF), + PIN(GPIODV_7, EE_OFF), +}; + static const struct pinctrl_pin_desc meson_gxl_aobus_pins[] = { MESON_PIN(GPIOAO_0, 0), MESON_PIN(GPIOAO_1, 0), @@ -271,11 +299,14 @@ static const unsigned int pwm_ao_a_8_pins[] = { PIN(GPIOAO_8, 0) }; static const unsigned int pwm_ao_b_pins[] = { PIN(GPIOAO_9, 0) }; static const unsigned int pwm_ao_b_6_pins[] = { PIN(GPIOAO_6, 0) }; -static const unsigned int i2s_out_ch23_ao_pins[] = { PIN(GPIOAO_8, EE_OFF) }; -static const unsigned int i2s_out_ch45_ao_pins[] = { PIN(GPIOAO_9, EE_OFF) }; +static const unsigned int i2s_out_ch23_ao_pins[] = { PIN(GPIOAO_8, 0) }; +static const unsigned int i2s_out_ch45_ao_pins[] = { PIN(GPIOAO_9, 0) }; -static const unsigned int spdif_out_ao_6_pins[] = { PIN(GPIOAO_6, EE_OFF) }; -static const unsigned int spdif_out_ao_9_pins[] = { PIN(GPIOAO_9, EE_OFF) }; +static const unsigned int spdif_out_ao_6_pins[] = { PIN(GPIOAO_6, 0) }; +static const unsigned int spdif_out_ao_9_pins[] = { PIN(GPIOAO_9, 0) }; + +static const unsigned int ao_cec_pins[] = { PIN(GPIOAO_8, 0) }; +static const unsigned int ee_cec_pins[] = { PIN(GPIOAO_8, 0) }; static struct meson_pmx_group meson_gxl_periphs_groups[] = { GPIO_GROUP(GPIOZ_0, EE_OFF), @@ -405,6 +436,14 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = { GROUP(pwm_a, 5, 25), GROUP(pwm_e, 5, 15), GROUP(pwm_f_x, 5, 14), + GROUP(spi_mosi, 5, 3), + GROUP(spi_miso, 5, 2), + GROUP(spi_ss0, 5, 1), + GROUP(spi_sclk, 5, 0), + GROUP(tsin_a_sop_x, 6, 3), + GROUP(tsin_a_d_valid_x, 6, 2), + GROUP(tsin_a_d0_x, 6, 1), + GROUP(tsin_a_clk_x, 6, 0), /* Bank Z */ GROUP(eth_mdio, 4, 23), @@ -425,6 +464,8 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = { GROUP(i2s_out_ch23_z, 3, 26), GROUP(i2s_out_ch45_z, 3, 25), GROUP(i2s_out_ch67_z, 3, 24), + GROUP(eth_link_led, 4, 25), + GROUP(eth_act_led, 4, 24), /* Bank H */ GROUP(hdmi_hpd, 6, 31), @@ -451,6 +492,12 @@ static struct meson_pmx_group meson_gxl_periphs_groups[] = { GROUP(i2c_sck_c, 1, 10), GROUP(pwm_b, 2, 11), GROUP(pwm_d, 2, 12), + GROUP(tsin_a_d0, 2, 4), + GROUP(tsin_a_dp, 2, 3), + GROUP(tsin_a_clk, 2, 2), + GROUP(tsin_a_sop, 2, 1), + GROUP(tsin_a_d_valid, 2, 0), + GROUP(tsin_a_fail, 1, 31), /* Bank BOOT */ GROUP(emmc_nand_d07, 7, 31), @@ -518,6 +565,8 @@ static struct meson_pmx_group meson_gxl_aobus_groups[] = { GROUP(i2s_out_ch45_ao, 1, 1), GROUP(spdif_out_ao_6, 0, 16), GROUP(spdif_out_ao_9, 0, 4), + GROUP(ao_cec, 0, 15), + GROUP(ee_cec, 0, 14), }; static const char * const gpio_periphs_groups[] = { @@ -560,6 +609,10 @@ static const char * const nor_groups[] = { "nor_d", "nor_q", "nor_c", "nor_cs", }; +static const char * const spi_groups[] = { + "spi_mosi", "spi_miso", "spi_ss0", "spi_sclk", +}; + static const char * const sdcard_groups[] = { "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", "sdcard_cmd", "sdcard_clk", @@ -647,6 +700,16 @@ static const char * const spdif_out_groups[] = { "spdif_out_h", }; +static const char * const eth_led_groups[] = { + "eth_link_led", "eth_act_led", +}; + +static const char * const tsin_a_groups[] = { + "tsin_a_clk", "tsin_a_clk_x", "tsin_a_sop", "tsin_a_sop_x", + "tsin_a_d_valid", "tsin_a_d_valid_x", "tsin_a_d0", "tsin_a_d0_x", + "tsin_a_dp", "tsin_a_fail", +}; + static const char * const gpio_aobus_groups[] = { "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", @@ -689,10 +752,15 @@ static const char * const spdif_out_ao_groups[] = { "spdif_out_ao_6", "spdif_out_ao_9", }; +static const char * const cec_ao_groups[] = { + "ao_cec", "ee_cec", +}; + static struct meson_pmx_func meson_gxl_periphs_functions[] = { FUNCTION(gpio_periphs), FUNCTION(emmc), FUNCTION(nor), + FUNCTION(spi), FUNCTION(sdcard), FUNCTION(sdio), FUNCTION(nand), @@ -713,6 +781,8 @@ static struct meson_pmx_func meson_gxl_periphs_functions[] = { FUNCTION(hdmi_i2c), FUNCTION(i2s_out), FUNCTION(spdif_out), + FUNCTION(eth_led), + FUNCTION(tsin_a), }; static struct meson_pmx_func meson_gxl_aobus_functions[] = { @@ -726,22 +796,23 @@ static struct meson_pmx_func meson_gxl_aobus_functions[] = { FUNCTION(pwm_ao_b), FUNCTION(i2s_out_ao), FUNCTION(spdif_out_ao), + FUNCTION(cec_ao), }; static struct meson_bank meson_gxl_periphs_banks[] = { - /* name first last pullen pull dir out in */ - BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_18, EE_OFF), 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), - BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF), 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), - BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_9, EE_OFF), 1, 20, 1, 20, 3, 20, 4, 20, 5, 20), - BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), - BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF), 2, 20, 2, 20, 6, 20, 7, 20, 8, 20), - BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), - BANK("CLK", PIN(GPIOCLK_0, EE_OFF), PIN(GPIOCLK_1, EE_OFF), 3, 28, 3, 28, 9, 28, 10, 28, 11, 28), + /* name first last irq pullen pull dir out in */ + BANK("X", PIN(GPIOX_0, EE_OFF), PIN(GPIOX_18, EE_OFF), 89, 107, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), + BANK("DV", PIN(GPIODV_0, EE_OFF), PIN(GPIODV_29, EE_OFF), 83, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), + BANK("H", PIN(GPIOH_0, EE_OFF), PIN(GPIOH_9, EE_OFF), 26, 35, 1, 20, 1, 20, 3, 20, 4, 20, 5, 20), + BANK("Z", PIN(GPIOZ_0, EE_OFF), PIN(GPIOZ_15, EE_OFF), 10, 25, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), + BANK("CARD", PIN(CARD_0, EE_OFF), PIN(CARD_6, EE_OFF), 52, 58, 2, 20, 2, 20, 6, 20, 7, 20, 8, 20), + BANK("BOOT", PIN(BOOT_0, EE_OFF), PIN(BOOT_15, EE_OFF), 36, 51, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), + BANK("CLK", PIN(GPIOCLK_0, EE_OFF), PIN(GPIOCLK_1, EE_OFF), 108, 109, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28), }; static struct meson_bank meson_gxl_aobus_banks[] = { - /* name first last pullen pull dir out in */ - BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_9, 0), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), + /* name first last irq pullen pull dir out in */ + BANK("AO", PIN(GPIOAO_0, 0), PIN(GPIOAO_9, 0), 0, 9, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), }; struct meson_pinctrl_data meson_gxl_periphs_pinctrl_data = { diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h index 1aa871d5431e..890f296f5840 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.h +++ b/drivers/pinctrl/meson/pinctrl-meson.h @@ -81,6 +81,7 @@ enum meson_reg_type { * @name: bank name * @first: first pin of the bank * @last: last pin of the bank + * @irq: hwirq base number of the bank * @regs: array of register descriptors * * A bank represents a set of pins controlled by a contiguous set of @@ -92,6 +93,8 @@ struct meson_bank { const char *name; unsigned int first; unsigned int last; + int irq_first; + int irq_last; struct meson_reg_desc regs[NUM_REG]; }; @@ -147,12 +150,14 @@ struct meson_pinctrl { .num_groups = ARRAY_SIZE(fn ## _groups), \ } -#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ +#define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ { \ - .name = n, \ - .first = f, \ - .last = l, \ - .regs = { \ + .name = n, \ + .first = f, \ + .last = l, \ + .irq_first = fi, \ + .irq_last = li, \ + .regs = { \ [REG_PULLEN] = { per, peb }, \ [REG_PULL] = { pr, pb }, \ [REG_DIR] = { dr, db }, \ diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c index 07f1cb21c1b8..970f6f14502c 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8.c +++ b/drivers/pinctrl/meson/pinctrl-meson8.c @@ -205,6 +205,9 @@ static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) }; static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) }; static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) }; +static const unsigned int pwm_e_pins[] = { PIN(GPIOX_10, 0) }; +static const unsigned int pwm_b_x_pins[] = { PIN(GPIOX_11, 0) }; + /* bank Y */ static const unsigned int uart_tx_c_pins[] = { PIN(GPIOY_0, 0) }; static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_1, 0) }; @@ -219,6 +222,20 @@ static const unsigned int pcm_clk_b_pins[] = { PIN(GPIOY_7, 0) }; static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIOY_0, 0) }; static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIOY_1, 0) }; +static const unsigned int pwm_a_y_pins[] = { PIN(GPIOY_16, 0) }; + +static const unsigned int i2s_out_ch45_pins[] = { PIN(GPIOY_0, 0) }; +static const unsigned int i2s_out_ch23_pins[] = { PIN(GPIOY_1, 0) }; +static const unsigned int i2s_out_ch01_pins[] = { PIN(GPIOY_4, 0) }; +static const unsigned int i2s_in_ch01_pins[] = { PIN(GPIOY_5, 0) }; +static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOY_6, 0) }; +static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOY_7, 0) }; +static const unsigned int i2s_am_clk_pins[] = { PIN(GPIOY_8, 0) }; +static const unsigned int i2s_out_ch78_pins[] = { PIN(GPIOY_9, 0) }; + +static const unsigned int spdif_in_pins[] = { PIN(GPIOY_2, 0) }; +static const unsigned int spdif_out_pins[] = { PIN(GPIOY_3, 0) }; + /* bank DV */ static const unsigned int dvin_rgb_pins[] = { PIN(GPIODV_0, 0), PIN(GPIODV_1, 0), PIN(GPIODV_2, 0), PIN(GPIODV_3, 0), @@ -264,6 +281,10 @@ static const unsigned int uart_rts_b1_pins[] = { PIN(GPIODV_27, 0) }; static const unsigned int vga_vs_pins[] = { PIN(GPIODV_24, 0) }; static const unsigned int vga_hs_pins[] = { PIN(GPIODV_25, 0) }; +static const unsigned int pwm_c_dv9_pins[] = { PIN(GPIODV_9, 0) }; +static const unsigned int pwm_c_dv29_pins[] = { PIN(GPIODV_29, 0) }; +static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, 0) }; + /* bank H */ static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) }; static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) }; @@ -312,6 +333,11 @@ static const unsigned int i2c_sck_a1_pins[] = { PIN(GPIOZ_1, 0) }; static const unsigned int i2c_sda_a2_pins[] = { PIN(GPIOZ_0, 0) }; static const unsigned int i2c_sck_a2_pins[] = { PIN(GPIOZ_1, 0) }; +static const unsigned int pwm_a_z0_pins[] = { PIN(GPIOZ_0, 0) }; +static const unsigned int pwm_a_z7_pins[] = { PIN(GPIOZ_7, 0) }; +static const unsigned int pwm_b_z_pins[] = { PIN(GPIOZ_1, 0) }; +static const unsigned int pwm_c_z_pins[] = { PIN(GPIOZ_8, 0) }; + /* bank BOOT */ static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) }; static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) }; @@ -369,6 +395,7 @@ static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) }; static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) }; static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) }; +static const unsigned int remote_output_ao_pins[] = { PIN(GPIOAO_13, AO_OFF) }; static const unsigned int i2c_slave_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; static const unsigned int i2c_slave_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; @@ -382,6 +409,15 @@ static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) }; static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) }; static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) }; +static const unsigned int pwm_f_ao_pins[] = { PIN(GPIO_TEST_N, AO_OFF) }; + +static const unsigned int i2s_am_clk_out_ao_pins[] = { PIN(GPIOAO_8, AO_OFF) }; +static const unsigned int i2s_ao_clk_out_ao_pins[] = { PIN(GPIOAO_9, AO_OFF) }; +static const unsigned int i2s_lr_clk_out_ao_pins[] = { PIN(GPIOAO_10, AO_OFF) }; +static const unsigned int i2s_out_ch01_ao_pins[] = { PIN(GPIOAO_11, AO_OFF) }; + +static const unsigned int hdmi_cec_ao_pins[] = { PIN(GPIOAO_12, AO_OFF) }; + static struct meson_pmx_group meson8_cbus_groups[] = { GPIO_GROUP(GPIOX_0, 0), GPIO_GROUP(GPIOX_1, 0), @@ -523,6 +559,9 @@ static struct meson_pmx_group meson8_cbus_groups[] = { GROUP(xtal_32k_out, 3, 22), GROUP(xtal_24m_out, 3, 23), + GROUP(pwm_e, 9, 19), + GROUP(pwm_b_x, 2, 3), + /* bank Y */ GROUP(uart_tx_c, 1, 19), GROUP(uart_rx_c, 1, 18), @@ -537,6 +576,20 @@ static struct meson_pmx_group meson8_cbus_groups[] = { GROUP(i2c_sda_c0, 1, 15), GROUP(i2c_sck_c0, 1, 14), + GROUP(pwm_a_y, 9, 14), + + GROUP(i2s_out_ch45, 1, 10), + GROUP(i2s_out_ch23, 1, 19), + GROUP(i2s_out_ch01, 1, 6), + GROUP(i2s_in_ch01, 1, 5), + GROUP(i2s_lr_clk_in, 1, 4), + GROUP(i2s_ao_clk_in, 1, 2), + GROUP(i2s_am_clk, 1, 0), + GROUP(i2s_out_ch78, 1, 11), + + GROUP(spdif_in, 1, 8), + GROUP(spdif_out, 1, 7), + /* bank DV */ GROUP(dvin_rgb, 0, 6), GROUP(dvin_vs, 0, 9), @@ -571,6 +624,10 @@ static struct meson_pmx_group meson8_cbus_groups[] = { GROUP(vga_vs, 0, 21), GROUP(vga_hs, 0, 20), + GROUP(pwm_c_dv9, 3, 24), + GROUP(pwm_c_dv29, 3, 25), + GROUP(pwm_d, 3, 26), + /* bank H */ GROUP(hdmi_hpd, 1, 26), GROUP(hdmi_sda, 1, 25), @@ -619,6 +676,11 @@ static struct meson_pmx_group meson8_cbus_groups[] = { GROUP(i2c_sda_a2, 5, 7), GROUP(i2c_sck_a2, 5, 6), + GROUP(pwm_a_z0, 9, 16), + GROUP(pwm_a_z7, 2, 0), + GROUP(pwm_b_z, 9, 15), + GROUP(pwm_c_z, 2, 1), + /* bank BOOT */ GROUP(sd_d0_c, 6, 29), GROUP(sd_d1_c, 6, 28), @@ -689,6 +751,7 @@ static struct meson_pmx_group meson8_aobus_groups[] = { GROUP(uart_rts_ao_a, 0, 9), GROUP(remote_input, 0, 0), + GROUP(remote_output_ao, 0, 31), GROUP(i2c_slave_sck_ao, 0, 2), GROUP(i2c_slave_sda_ao, 0, 1), @@ -701,6 +764,15 @@ static struct meson_pmx_group meson8_aobus_groups[] = { GROUP(i2c_mst_sck_ao, 0, 6), GROUP(i2c_mst_sda_ao, 0, 5), + + GROUP(pwm_f_ao, 0, 19), + + GROUP(i2s_am_clk_out_ao, 0, 30), + GROUP(i2s_ao_clk_out_ao, 0, 29), + GROUP(i2s_lr_clk_out_ao, 0, 28), + GROUP(i2s_out_ch01_ao, 0, 27), + + GROUP(hdmi_cec_ao, 0, 17), }; static const char * const gpio_groups[] = { @@ -828,6 +900,12 @@ static const char * const i2c_b_groups[] = { "i2c_sda_b", "i2c_sck_b" }; +static const char * const i2s_groups[] = { + "i2s_out_ch45", "i2s_out_ch23_pins", "i2s_out_ch01_pins", + "i2s_in_ch01_pins", "i2s_lr_clk_in_pins", "i2s_ao_clk_in_pins", + "i2s_am_clk_pins", "i2s_out_ch78_pins" +}; + static const char * const sd_c_groups[] = { "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c", "sd_cmd_c", "sd_clk_c" @@ -849,6 +927,26 @@ static const char * const nor_groups[] = { "nor_d", "nor_q", "nor_c", "nor_cs" }; +static const char * const pwm_a_groups[] = { + "pwm_a_y", "pwm_a_z0", "pwm_a_z7" +}; + +static const char * const pwm_b_groups[] = { + "pwm_b_x", "pwm_b_z" +}; + +static const char * const pwm_c_groups[] = { + "pwm_c_dv9", "pwm_c_dv29", "pwm_c_z" +}; + +static const char * const pwm_d_groups[] = { + "pwm_d" +}; + +static const char * const pwm_e_groups[] = { + "pwm_e" +}; + static const char * const sd_b_groups[] = { "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b", "sd_d3_b", "sd_d2_b" @@ -858,12 +956,16 @@ static const char * const sdxc_b_groups[] = { "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b" }; +static const char * const spdif_groups[] = { + "spdif_in", "spdif_out" +}; + static const char * const uart_ao_groups[] = { "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a" }; static const char * const remote_groups[] = { - "remote_input" + "remote_input", "remote_output_ao" }; static const char * const i2c_slave_ao_groups[] = { @@ -878,6 +980,19 @@ static const char * const i2c_mst_ao_groups[] = { "i2c_mst_sck_ao", "i2c_mst_sda_ao" }; +static const char * const pwm_f_ao_groups[] = { + "pwm_f_ao" +}; + +static const char * const i2s_ao_groups[] = { + "i2s_am_clk_out_ao", "i2s_ao_clk_out_ao", "i2s_lr_clk_out_ao", + "i2s_out_ch01_ao" +}; + +static const char * const hdmi_cec_ao_groups[] = { + "hdmi_cec_ao" +}; + static struct meson_pmx_func meson8_cbus_functions[] = { FUNCTION(gpio), FUNCTION(sd_a), @@ -905,6 +1020,13 @@ static struct meson_pmx_func meson8_cbus_functions[] = { FUNCTION(nor), FUNCTION(sd_b), FUNCTION(sdxc_b), + FUNCTION(pwm_a), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(i2s), + FUNCTION(spdif), }; static struct meson_pmx_func meson8_aobus_functions[] = { @@ -913,22 +1035,25 @@ static struct meson_pmx_func meson8_aobus_functions[] = { FUNCTION(i2c_slave_ao), FUNCTION(uart_ao_b), FUNCTION(i2c_mst_ao), + FUNCTION(pwm_f_ao), + FUNCTION(i2s_ao), + FUNCTION(hdmi_cec_ao), }; static struct meson_bank meson8_cbus_banks[] = { - /* name first last pullen pull dir out in */ - BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), - BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_16, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), - BANK("DV", PIN(GPIODV_0, 0), PIN(GPIODV_29, 0), 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), - BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), - BANK("Z", PIN(GPIOZ_0, 0), PIN(GPIOZ_14, 0), 1, 0, 1, 0, 3, 17, 4, 17, 5, 17), - BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), - BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), + /* name first last irq pullen pull dir out in */ + BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 112, 133, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), + BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_16, 0), 95, 111, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), + BANK("DV", PIN(GPIODV_0, 0), PIN(GPIODV_29, 0), 65, 94, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), + BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 29, 38, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), + BANK("Z", PIN(GPIOZ_0, 0), PIN(GPIOZ_14, 0), 14, 28, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17), + BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 58, 64, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), + BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 39, 57, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), }; static struct meson_bank meson8_aobus_banks[] = { - /* name first last pullen pull dir out in */ - BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), + /* name first last irq pullen pull dir out in */ + BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 13, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), }; struct meson_pinctrl_data meson8_cbus_pinctrl_data = { diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c index bf747eb1f3f4..71f216b5b0b9 100644 --- a/drivers/pinctrl/meson/pinctrl-meson8b.c +++ b/drivers/pinctrl/meson/pinctrl-meson8b.c @@ -124,6 +124,12 @@ static const struct pinctrl_pin_desc meson8b_aobus_pins[] = { MESON_PIN(GPIOAO_11, AO_OFF), MESON_PIN(GPIOAO_12, AO_OFF), MESON_PIN(GPIOAO_13, AO_OFF), + + /* + * The following 2 pins are not mentionned in the public datasheet + * According to this datasheet, they can't be used with the gpio + * interrupt controller + */ MESON_PIN(GPIO_BSD_EN, AO_OFF), MESON_PIN(GPIO_TEST_N, AO_OFF), }; @@ -881,19 +887,25 @@ static struct meson_pmx_func meson8b_aobus_functions[] = { }; static struct meson_bank meson8b_cbus_banks[] = { - /* name first last pullen pull dir out in */ - BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), - BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_14, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), - BANK("DV", PIN(GPIODV_9, 0), PIN(GPIODV_29, 0), 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), - BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), - BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), - BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), - BANK("DIF", PIN(DIF_0_P, 0), PIN(DIF_4_N, 0), 5, 8, 5, 8, 12, 12, 13, 12, 14, 12), + /* name first last irq pullen pull dir out in */ + BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 97, 118, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), + BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_14, 0), 80, 96, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), + BANK("DV", PIN(GPIODV_9, 0), PIN(GPIODV_29, 0), 59, 79, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), + BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 14, 23, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), + BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 43, 49, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), + BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 24, 42, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), + + /* + * The following bank is not mentionned in the public datasheet + * There is no information whether it can be used with the gpio + * interrupt controller + */ + BANK("DIF", PIN(DIF_0_P, 0), PIN(DIF_4_N, 0), -1, -1, 5, 8, 5, 8, 12, 12, 13, 12, 14, 12), }; static struct meson_bank meson8b_aobus_banks[] = { - /* name first last pullen pull dir out in */ - BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), + /* name first last irq pullen pull dir out in */ + BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 13, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), }; struct meson_pinctrl_data meson8b_cbus_pinctrl_data = { diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig index 5bade32d3089..d9773b77ff9f 100644 --- a/drivers/pinctrl/mvebu/Kconfig +++ b/drivers/pinctrl/mvebu/Kconfig @@ -1,5 +1,3 @@ -if PLAT_ORION - config PINCTRL_MVEBU bool select PINMUX @@ -30,6 +28,14 @@ config PINCTRL_ARMADA_39X bool select PINCTRL_MVEBU +config PINCTRL_ARMADA_AP806 + bool + select PINCTRL_MVEBU + +config PINCTRL_ARMADA_CP110 + bool + select PINCTRL_MVEBU + config PINCTRL_ARMADA_XP bool select PINCTRL_MVEBU @@ -38,8 +44,6 @@ config PINCTRL_ORION bool select PINCTRL_MVEBU -endif - config PINCTRL_ARMADA_37XX bool select GENERIC_PINCONF diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile index 60c245a60f39..5b03fd55e28d 100644 --- a/drivers/pinctrl/mvebu/Makefile +++ b/drivers/pinctrl/mvebu/Makefile @@ -5,6 +5,8 @@ obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o obj-$(CONFIG_PINCTRL_ARMADA_39X) += pinctrl-armada-39x.o +obj-$(CONFIG_PINCTRL_ARMADA_AP806) += pinctrl-armada-ap806.o +obj-$(CONFIG_PINCTRL_ARMADA_CP110) += pinctrl-armada-cp110.o obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o obj-$(CONFIG_PINCTRL_ARMADA_37XX) += pinctrl-armada-37xx.o obj-$(CONFIG_PINCTRL_ORION) += pinctrl-orion.o diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 5c96f5558310..f024e25787fc 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -13,7 +13,9 @@ #include <linux/gpio/driver.h> #include <linux/mfd/syscon.h> #include <linux/of.h> +#include <linux/of_address.h> #include <linux/of_device.h> +#include <linux/of_irq.h> #include <linux/pinctrl/pinconf-generic.h> #include <linux/pinctrl/pinconf.h> #include <linux/pinctrl/pinctrl.h> @@ -30,6 +32,11 @@ #define OUTPUT_CTL 0x20 #define SELECTION 0x30 +#define IRQ_EN 0x0 +#define IRQ_POL 0x08 +#define IRQ_STATUS 0x10 +#define IRQ_WKUP 0x18 + #define NB_FUNCS 2 #define GPIO_PER_REG 32 @@ -75,9 +82,12 @@ struct armada_37xx_pmx_func { struct armada_37xx_pinctrl { struct regmap *regmap; + void __iomem *base; const struct armada_37xx_pin_data *data; struct device *dev; struct gpio_chip gpio_chip; + struct irq_chip irq_chip; + spinlock_t irq_lock; struct pinctrl_desc pctl; struct pinctrl_dev *pctl_dev; struct armada_37xx_pin_group *groups; @@ -147,8 +157,9 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"), PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"), PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"), - PIN_GRP_EXTRA("uart2", 9, 2, BIT(13) | BIT(14) | BIT(19), - BIT(13) | BIT(14), BIT(19), 18, 2, "gpio", "uart"), + PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19), + BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19), + 18, 2, "gpio", "uart"), PIN_GRP_GPIO("led0_od", 11, 1, BIT(20), "led"), PIN_GRP_GPIO("led1_od", 12, 1, BIT(21), "led"), PIN_GRP_GPIO("led2_od", 13, 1, BIT(22), "led"), @@ -159,8 +170,8 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"), PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"), - PIN_GRP_GPIO("sdio_sb", 24, 5, BIT(2), "sdio"), - PIN_GRP_EXTRA("rgmii", 6, 14, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"), + PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"), + PIN_GRP_EXTRA("rgmii", 6, 12, BIT(3), 0, BIT(3), 23, 1, "mii", "gpio"), PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"), PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"), PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"), @@ -346,6 +357,14 @@ static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev, return armada_37xx_pmx_set_by_name(pctldev, name, grp); } +static inline void armada_37xx_irq_update_reg(unsigned int *reg, + struct irq_data *d) +{ + int offset = irqd_to_hwirq(d); + + armada_37xx_update_reg(reg, offset); +} + static int armada_37xx_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) { @@ -468,6 +487,214 @@ static const struct gpio_chip armada_37xx_gpiolib_chip = { .owner = THIS_MODULE, }; +static void armada_37xx_irq_ack(struct irq_data *d) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); + u32 reg = IRQ_STATUS; + unsigned long flags; + + armada_37xx_irq_update_reg(®, d); + spin_lock_irqsave(&info->irq_lock, flags); + writel(d->mask, info->base + reg); + spin_unlock_irqrestore(&info->irq_lock, flags); +} + +static void armada_37xx_irq_mask(struct irq_data *d) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); + u32 val, reg = IRQ_EN; + unsigned long flags; + + armada_37xx_irq_update_reg(®, d); + spin_lock_irqsave(&info->irq_lock, flags); + val = readl(info->base + reg); + writel(val & ~d->mask, info->base + reg); + spin_unlock_irqrestore(&info->irq_lock, flags); +} + +static void armada_37xx_irq_unmask(struct irq_data *d) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); + u32 val, reg = IRQ_EN; + unsigned long flags; + + armada_37xx_irq_update_reg(®, d); + spin_lock_irqsave(&info->irq_lock, flags); + val = readl(info->base + reg); + writel(val | d->mask, info->base + reg); + spin_unlock_irqrestore(&info->irq_lock, flags); +} + +static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); + u32 val, reg = IRQ_WKUP; + unsigned long flags; + + armada_37xx_irq_update_reg(®, d); + spin_lock_irqsave(&info->irq_lock, flags); + val = readl(info->base + reg); + if (on) + val |= d->mask; + else + val &= ~d->mask; + writel(val, info->base + reg); + spin_unlock_irqrestore(&info->irq_lock, flags); + + return 0; +} + +static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(d); + struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); + u32 val, reg = IRQ_POL; + unsigned long flags; + + spin_lock_irqsave(&info->irq_lock, flags); + armada_37xx_irq_update_reg(®, d); + val = readl(info->base + reg); + switch (type) { + case IRQ_TYPE_EDGE_RISING: + val &= ~d->mask; + break; + case IRQ_TYPE_EDGE_FALLING: + val |= d->mask; + break; + default: + spin_unlock_irqrestore(&info->irq_lock, flags); + return -EINVAL; + } + writel(val, info->base + reg); + spin_unlock_irqrestore(&info->irq_lock, flags); + + return 0; +} + + +static void armada_37xx_irq_handler(struct irq_desc *desc) +{ + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct armada_37xx_pinctrl *info = gpiochip_get_data(gc); + struct irq_domain *d = gc->irqdomain; + int i; + + chained_irq_enter(chip, desc); + for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) { + u32 status; + unsigned long flags; + + spin_lock_irqsave(&info->irq_lock, flags); + status = readl_relaxed(info->base + IRQ_STATUS + 4 * i); + /* Manage only the interrupt that was enabled */ + status &= readl_relaxed(info->base + IRQ_EN + 4 * i); + spin_unlock_irqrestore(&info->irq_lock, flags); + while (status) { + u32 hwirq = ffs(status) - 1; + u32 virq = irq_find_mapping(d, hwirq + + i * GPIO_PER_REG); + + generic_handle_irq(virq); + + /* Update status in case a new IRQ appears */ + spin_lock_irqsave(&info->irq_lock, flags); + status = readl_relaxed(info->base + + IRQ_STATUS + 4 * i); + /* Manage only the interrupt that was enabled */ + status &= readl_relaxed(info->base + IRQ_EN + 4 * i); + spin_unlock_irqrestore(&info->irq_lock, flags); + } + } + chained_irq_exit(chip, desc); +} + +static int armada_37xx_irqchip_register(struct platform_device *pdev, + struct armada_37xx_pinctrl *info) +{ + struct device_node *np = info->dev->of_node; + int nrirqs = info->data->nr_pins; + struct gpio_chip *gc = &info->gpio_chip; + struct irq_chip *irqchip = &info->irq_chip; + struct resource res; + int ret = -ENODEV, i, nr_irq_parent; + + /* Check if we have at least one gpio-controller child node */ + for_each_child_of_node(info->dev->of_node, np) { + if (of_property_read_bool(np, "gpio-controller")) { + ret = 0; + break; + } + }; + if (ret) + return ret; + + nr_irq_parent = of_irq_count(np); + spin_lock_init(&info->irq_lock); + + if (!nr_irq_parent) { + dev_err(&pdev->dev, "Invalid or no IRQ\n"); + return 0; + } + + if (of_address_to_resource(info->dev->of_node, 1, &res)) { + dev_err(info->dev, "cannot find IO resource\n"); + return -ENOENT; + } + + info->base = devm_ioremap_resource(info->dev, &res); + if (IS_ERR(info->base)) + return PTR_ERR(info->base); + + irqchip->irq_ack = armada_37xx_irq_ack; + irqchip->irq_mask = armada_37xx_irq_mask; + irqchip->irq_unmask = armada_37xx_irq_unmask; + irqchip->irq_set_wake = armada_37xx_irq_set_wake; + irqchip->irq_set_type = armada_37xx_irq_set_type; + irqchip->name = info->data->name; + + ret = gpiochip_irqchip_add(gc, irqchip, 0, + handle_edge_irq, IRQ_TYPE_NONE); + if (ret) { + dev_info(&pdev->dev, "could not add irqchip\n"); + return ret; + } + + /* + * Many interrupts are connected to the parent interrupt + * controller. But we do not take advantage of this and use + * the chained irq with all of them. + */ + for (i = 0; i < nrirqs; i++) { + struct irq_data *d = irq_get_irq_data(gc->irq_base + i); + + /* + * The mask field is a "precomputed bitmask for + * accessing the chip registers" which was introduced + * for the generic irqchip framework. As we don't use + * this framework, we can reuse this field for our own + * usage. + */ + d->mask = BIT(i % GPIO_PER_REG); + } + + for (i = 0; i < nr_irq_parent; i++) { + int irq = irq_of_parse_and_map(np, i); + + if (irq < 0) + continue; + + gpiochip_set_chained_irqchip(gc, irqchip, irq, + armada_37xx_irq_handler); + } + + return 0; +} + static int armada_37xx_gpiochip_register(struct platform_device *pdev, struct armada_37xx_pinctrl *info) { @@ -496,6 +723,9 @@ static int armada_37xx_gpiochip_register(struct platform_device *pdev, ret = devm_gpiochip_add_data(&pdev->dev, gc, info); if (ret) return ret; + ret = armada_37xx_irqchip_register(pdev, info); + if (ret) + return ret; return 0; } diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c b/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c new file mode 100644 index 000000000000..66e442260a4e --- /dev/null +++ b/drivers/pinctrl/mvebu/pinctrl-armada-ap806.c @@ -0,0 +1,140 @@ +/* + * Marvell Armada ap806 pinctrl driver based on mvebu pinctrl core + * + * Copyright (C) 2017 Marvell + * + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> + * Hanna Hawa <hannah@marvell.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-mvebu.h" + +static struct mvebu_mpp_mode armada_ap806_mpp_modes[] = { + MPP_MODE(0, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "clk"), + MPP_FUNCTION(3, "spi0", "clk")), + MPP_MODE(1, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "cmd"), + MPP_FUNCTION(3, "spi0", "miso")), + MPP_MODE(2, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "d0"), + MPP_FUNCTION(3, "spi0", "mosi")), + MPP_MODE(3, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "d1"), + MPP_FUNCTION(3, "spi0", "cs0n")), + MPP_MODE(4, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "d2"), + MPP_FUNCTION(3, "i2c0", "sda")), + MPP_MODE(5, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "d3"), + MPP_FUNCTION(3, "i2c0", "sdk")), + MPP_MODE(6, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "ds")), + MPP_MODE(7, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "d4"), + MPP_FUNCTION(3, "uart1", "rxd")), + MPP_MODE(8, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "d5"), + MPP_FUNCTION(3, "uart1", "txd")), + MPP_MODE(9, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "d6"), + MPP_FUNCTION(3, "spi0", "cs1n")), + MPP_MODE(10, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "d7")), + MPP_MODE(11, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(3, "uart0", "txd")), + MPP_MODE(12, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "pw_off"), + MPP_FUNCTION(2, "sdio", "hw_rst")), + MPP_MODE(13, + MPP_FUNCTION(0, "gpio", NULL)), + MPP_MODE(14, + MPP_FUNCTION(0, "gpio", NULL)), + MPP_MODE(15, + MPP_FUNCTION(0, "gpio", NULL)), + MPP_MODE(16, + MPP_FUNCTION(0, "gpio", NULL)), + MPP_MODE(17, + MPP_FUNCTION(0, "gpio", NULL)), + MPP_MODE(18, + MPP_FUNCTION(0, "gpio", NULL)), + MPP_MODE(19, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(3, "uart0", "rxd"), + MPP_FUNCTION(4, "sdio", "pw_off")), +}; + +static struct mvebu_pinctrl_soc_info armada_ap806_pinctrl_info; + +static const struct of_device_id armada_ap806_pinctrl_of_match[] = { + { + .compatible = "marvell,ap806-pinctrl", + }, + { }, +}; + +static const struct mvebu_mpp_ctrl armada_ap806_mpp_controls[] = { + MPP_FUNC_CTRL(0, 19, NULL, mvebu_regmap_mpp_ctrl), +}; + +static struct pinctrl_gpio_range armada_ap806_mpp_gpio_ranges[] = { + MPP_GPIO_RANGE(0, 0, 0, 20), +}; + +static int armada_ap806_pinctrl_probe(struct platform_device *pdev) +{ + struct mvebu_pinctrl_soc_info *soc = &armada_ap806_pinctrl_info; + const struct of_device_id *match = + of_match_device(armada_ap806_pinctrl_of_match, &pdev->dev); + + if (!match || !pdev->dev.parent) + return -ENODEV; + + soc->variant = 0; /* no variants for Armada AP806 */ + soc->controls = armada_ap806_mpp_controls; + soc->ncontrols = ARRAY_SIZE(armada_ap806_mpp_controls); + soc->gpioranges = armada_ap806_mpp_gpio_ranges; + soc->ngpioranges = ARRAY_SIZE(armada_ap806_mpp_gpio_ranges); + soc->modes = armada_ap806_mpp_modes; + soc->nmodes = armada_ap806_mpp_controls[0].npins; + + pdev->dev.platform_data = soc; + + return mvebu_pinctrl_simple_regmap_probe(pdev, pdev->dev.parent, 0); +} + +static struct platform_driver armada_ap806_pinctrl_driver = { + .driver = { + .name = "armada-ap806-pinctrl", + .of_match_table = of_match_ptr(armada_ap806_pinctrl_of_match), + }, + .probe = armada_ap806_pinctrl_probe, +}; + +builtin_platform_driver(armada_ap806_pinctrl_driver); diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c new file mode 100644 index 000000000000..7f85beb45482 --- /dev/null +++ b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c @@ -0,0 +1,687 @@ +/* + * Marvell Armada CP110 pinctrl driver based on mvebu pinctrl core + * + * Copyright (C) 2017 Marvell + * + * Hanna Hawa <hannah@marvell.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <linux/err.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/mfd/syscon.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> + +#include "pinctrl-mvebu.h" + +/* + * Even if the pin controller is the same the MMP available depend on the SoC + * integration. + * - In Armada7K (single CP) almost all the MPPs are available (except the + * MMP 39 to 43) + * - In Armada8K (dual CP) the MPPs are split into 2 parts, MPPs 0-31 from + * CPS, and MPPs 32-62 from CPM, the below flags (V_ARMADA_8K_CPM, + * V_ARMADA_8K_CPS) set which MPP is available to the CPx. + * The x_PLUS enum mean that the MPP available for CPx and for Armada70x0 + */ +enum { + V_ARMADA_7K = BIT(0), + V_ARMADA_8K_CPM = BIT(1), + V_ARMADA_8K_CPS = BIT(2), + V_ARMADA_7K_8K_CPM = (V_ARMADA_7K | V_ARMADA_8K_CPM), + V_ARMADA_7K_8K_CPS = (V_ARMADA_7K | V_ARMADA_8K_CPS), +}; + +static struct mvebu_mpp_mode armada_cp110_mpp_modes[] = { + MPP_MODE(0, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ale1"), + MPP_FUNCTION(2, "au", "i2smclk"), + MPP_FUNCTION(3, "ge0", "rxd3"), + MPP_FUNCTION(4, "tdm", "pclk"), + MPP_FUNCTION(6, "ptp", "pulse"), + MPP_FUNCTION(7, "mss_i2c", "sda"), + MPP_FUNCTION(8, "uart0", "rxd"), + MPP_FUNCTION(9, "sata0", "present_act"), + MPP_FUNCTION(10, "ge", "mdio")), + MPP_MODE(1, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ale0"), + MPP_FUNCTION(2, "au", "i2sdo_spdifo"), + MPP_FUNCTION(3, "ge0", "rxd2"), + MPP_FUNCTION(4, "tdm", "drx"), + MPP_FUNCTION(6, "ptp", "clk"), + MPP_FUNCTION(7, "mss_i2c", "sck"), + MPP_FUNCTION(8, "uart0", "txd"), + MPP_FUNCTION(9, "sata1", "present_act"), + MPP_FUNCTION(10, "ge", "mdc")), + MPP_MODE(2, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ad15"), + MPP_FUNCTION(2, "au", "i2sextclk"), + MPP_FUNCTION(3, "ge0", "rxd1"), + MPP_FUNCTION(4, "tdm", "dtx"), + MPP_FUNCTION(5, "mss_uart", "rxd"), + MPP_FUNCTION(6, "ptp", "pclk_out"), + MPP_FUNCTION(7, "i2c1", "sck"), + MPP_FUNCTION(8, "uart1", "rxd"), + MPP_FUNCTION(9, "sata0", "present_act"), + MPP_FUNCTION(10, "xg", "mdc")), + MPP_MODE(3, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ad14"), + MPP_FUNCTION(2, "au", "i2slrclk"), + MPP_FUNCTION(3, "ge0", "rxd0"), + MPP_FUNCTION(4, "tdm", "fsync"), + MPP_FUNCTION(5, "mss_uart", "txd"), + MPP_FUNCTION(6, "pcie", "rstoutn"), + MPP_FUNCTION(7, "i2c1", "sda"), + MPP_FUNCTION(8, "uart1", "txd"), + MPP_FUNCTION(9, "sata1", "present_act"), + MPP_FUNCTION(10, "xg", "mdio")), + MPP_MODE(4, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ad13"), + MPP_FUNCTION(2, "au", "i2sbclk"), + MPP_FUNCTION(3, "ge0", "rxctl"), + MPP_FUNCTION(4, "tdm", "rstn"), + MPP_FUNCTION(5, "mss_uart", "rxd"), + MPP_FUNCTION(6, "uart1", "cts"), + MPP_FUNCTION(7, "pcie0", "clkreq"), + MPP_FUNCTION(8, "uart3", "rxd"), + MPP_FUNCTION(10, "ge", "mdc")), + MPP_MODE(5, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ad12"), + MPP_FUNCTION(2, "au", "i2sdi"), + MPP_FUNCTION(3, "ge0", "rxclk"), + MPP_FUNCTION(4, "tdm", "intn"), + MPP_FUNCTION(5, "mss_uart", "txd"), + MPP_FUNCTION(6, "uart1", "rts"), + MPP_FUNCTION(7, "pcie1", "clkreq"), + MPP_FUNCTION(8, "uart3", "txd"), + MPP_FUNCTION(10, "ge", "mdio")), + MPP_MODE(6, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ad11"), + MPP_FUNCTION(3, "ge0", "txd3"), + MPP_FUNCTION(4, "spi0", "csn2"), + MPP_FUNCTION(5, "au", "i2sextclk"), + MPP_FUNCTION(6, "sata1", "present_act"), + MPP_FUNCTION(7, "pcie2", "clkreq"), + MPP_FUNCTION(8, "uart0", "rxd"), + MPP_FUNCTION(9, "ptp", "pulse")), + MPP_MODE(7, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ad10"), + MPP_FUNCTION(3, "ge0", "txd2"), + MPP_FUNCTION(4, "spi0", "csn1"), + MPP_FUNCTION(5, "spi1", "csn1"), + MPP_FUNCTION(6, "sata0", "present_act"), + MPP_FUNCTION(7, "led", "data"), + MPP_FUNCTION(8, "uart0", "txd"), + MPP_FUNCTION(9, "ptp", "clk")), + MPP_MODE(8, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ad9"), + MPP_FUNCTION(3, "ge0", "txd1"), + MPP_FUNCTION(4, "spi0", "csn0"), + MPP_FUNCTION(5, "spi1", "csn0"), + MPP_FUNCTION(6, "uart0", "cts"), + MPP_FUNCTION(7, "led", "stb"), + MPP_FUNCTION(8, "uart2", "rxd"), + MPP_FUNCTION(9, "ptp", "pclk_out"), + MPP_FUNCTION(10, "synce1", "clk")), + MPP_MODE(9, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ad8"), + MPP_FUNCTION(3, "ge0", "txd0"), + MPP_FUNCTION(4, "spi0", "mosi"), + MPP_FUNCTION(5, "spi1", "mosi"), + MPP_FUNCTION(7, "pcie", "rstoutn"), + MPP_FUNCTION(10, "synce2", "clk")), + MPP_MODE(10, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "readyn"), + MPP_FUNCTION(3, "ge0", "txctl"), + MPP_FUNCTION(4, "spi0", "miso"), + MPP_FUNCTION(5, "spi1", "miso"), + MPP_FUNCTION(6, "uart0", "cts"), + MPP_FUNCTION(7, "sata1", "present_act")), + MPP_MODE(11, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "wen1"), + MPP_FUNCTION(3, "ge0", "txclkout"), + MPP_FUNCTION(4, "spi0", "clk"), + MPP_FUNCTION(5, "spi1", "clk"), + MPP_FUNCTION(6, "uart0", "rts"), + MPP_FUNCTION(7, "led", "clk"), + MPP_FUNCTION(8, "uart2", "txd"), + MPP_FUNCTION(9, "sata0", "present_act")), + MPP_MODE(12, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "clk_out"), + MPP_FUNCTION(2, "nf", "rbn1"), + MPP_FUNCTION(3, "spi1", "csn1"), + MPP_FUNCTION(4, "ge0", "rxclk")), + MPP_MODE(13, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "burstn"), + MPP_FUNCTION(2, "nf", "rbn0"), + MPP_FUNCTION(3, "spi1", "miso"), + MPP_FUNCTION(4, "ge0", "rxctl"), + MPP_FUNCTION(8, "mss_spi", "miso")), + MPP_MODE(14, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "bootcsn"), + MPP_FUNCTION(2, "dev", "csn0"), + MPP_FUNCTION(3, "spi1", "csn0"), + MPP_FUNCTION(4, "spi0", "csn3"), + MPP_FUNCTION(5, "au", "i2sextclk"), + MPP_FUNCTION(6, "spi0", "miso"), + MPP_FUNCTION(7, "sata0", "present_act"), + MPP_FUNCTION(8, "mss_spi", "csn")), + MPP_MODE(15, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ad7"), + MPP_FUNCTION(3, "spi1", "mosi"), + MPP_FUNCTION(6, "spi0", "mosi"), + MPP_FUNCTION(8, "mss_spi", "mosi"), + MPP_FUNCTION(11, "ptp", "pulse_cp2cp")), + MPP_MODE(16, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ad6"), + MPP_FUNCTION(3, "spi1", "clk"), + MPP_FUNCTION(8, "mss_spi", "clk")), + MPP_MODE(17, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ad5"), + MPP_FUNCTION(4, "ge0", "txd3")), + MPP_MODE(18, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ad4"), + MPP_FUNCTION(4, "ge0", "txd2"), + MPP_FUNCTION(11, "ptp", "clk_cp2cp")), + MPP_MODE(19, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ad3"), + MPP_FUNCTION(4, "ge0", "txd1"), + MPP_FUNCTION(11, "wakeup", "out_cp2cp")), + MPP_MODE(20, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ad2"), + MPP_FUNCTION(4, "ge0", "txd0")), + MPP_MODE(21, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ad1"), + MPP_FUNCTION(4, "ge0", "txctl"), + MPP_FUNCTION(11, "sei", "in_cp2cp")), + MPP_MODE(22, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "ad0"), + MPP_FUNCTION(4, "ge0", "txclkout"), + MPP_FUNCTION(11, "wakeup", "in_cp2cp")), + MPP_MODE(23, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "a1"), + MPP_FUNCTION(5, "au", "i2smclk"), + MPP_FUNCTION(11, "link", "rd_in_cp2cp")), + MPP_MODE(24, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "a0"), + MPP_FUNCTION(5, "au", "i2slrclk")), + MPP_MODE(25, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "oen"), + MPP_FUNCTION(5, "au", "i2sdo_spdifo")), + MPP_MODE(26, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "wen0"), + MPP_FUNCTION(5, "au", "i2sbclk")), + MPP_MODE(27, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "csn0"), + MPP_FUNCTION(2, "spi1", "miso"), + MPP_FUNCTION(3, "mss_gpio4", NULL), + MPP_FUNCTION(4, "ge0", "rxd3"), + MPP_FUNCTION(5, "spi0", "csn4"), + MPP_FUNCTION(8, "ge", "mdio"), + MPP_FUNCTION(9, "sata0", "present_act"), + MPP_FUNCTION(10, "uart0", "rts"), + MPP_FUNCTION(11, "rei", "in_cp2cp")), + MPP_MODE(28, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "csn1"), + MPP_FUNCTION(2, "spi1", "csn0"), + MPP_FUNCTION(3, "mss_gpio5", NULL), + MPP_FUNCTION(4, "ge0", "rxd2"), + MPP_FUNCTION(5, "spi0", "csn5"), + MPP_FUNCTION(6, "pcie2", "clkreq"), + MPP_FUNCTION(7, "ptp", "pulse"), + MPP_FUNCTION(8, "ge", "mdc"), + MPP_FUNCTION(9, "sata1", "present_act"), + MPP_FUNCTION(10, "uart0", "cts"), + MPP_FUNCTION(11, "led", "data")), + MPP_MODE(29, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "csn2"), + MPP_FUNCTION(2, "spi1", "mosi"), + MPP_FUNCTION(3, "mss_gpio6", NULL), + MPP_FUNCTION(4, "ge0", "rxd1"), + MPP_FUNCTION(5, "spi0", "csn6"), + MPP_FUNCTION(6, "pcie1", "clkreq"), + MPP_FUNCTION(7, "ptp", "clk"), + MPP_FUNCTION(8, "mss_i2c", "sda"), + MPP_FUNCTION(9, "sata0", "present_act"), + MPP_FUNCTION(10, "uart0", "rxd"), + MPP_FUNCTION(11, "led", "stb")), + MPP_MODE(30, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "csn3"), + MPP_FUNCTION(2, "spi1", "clk"), + MPP_FUNCTION(3, "mss_gpio7", NULL), + MPP_FUNCTION(4, "ge0", "rxd0"), + MPP_FUNCTION(5, "spi0", "csn7"), + MPP_FUNCTION(6, "pcie0", "clkreq"), + MPP_FUNCTION(7, "ptp", "pclk_out"), + MPP_FUNCTION(8, "mss_i2c", "sck"), + MPP_FUNCTION(9, "sata1", "present_act"), + MPP_FUNCTION(10, "uart0", "txd"), + MPP_FUNCTION(11, "led", "clk")), + MPP_MODE(31, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "dev", "a2"), + MPP_FUNCTION(3, "mss_gpio4", NULL), + MPP_FUNCTION(6, "pcie", "rstoutn"), + MPP_FUNCTION(8, "ge", "mdc")), + MPP_MODE(32, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "mii", "col"), + MPP_FUNCTION(2, "mii", "txerr"), + MPP_FUNCTION(3, "mss_spi", "miso"), + MPP_FUNCTION(4, "tdm", "drx"), + MPP_FUNCTION(5, "au", "i2sextclk"), + MPP_FUNCTION(6, "au", "i2sdi"), + MPP_FUNCTION(7, "ge", "mdio"), + MPP_FUNCTION(8, "sdio", "v18_en"), + MPP_FUNCTION(9, "pcie1", "clkreq"), + MPP_FUNCTION(10, "mss_gpio0", NULL)), + MPP_MODE(33, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "mii", "txclk"), + MPP_FUNCTION(2, "sdio", "pwr10"), + MPP_FUNCTION(3, "mss_spi", "csn"), + MPP_FUNCTION(4, "tdm", "fsync"), + MPP_FUNCTION(5, "au", "i2smclk"), + MPP_FUNCTION(6, "sdio", "bus_pwr"), + MPP_FUNCTION(8, "xg", "mdio"), + MPP_FUNCTION(9, "pcie2", "clkreq"), + MPP_FUNCTION(10, "mss_gpio1", NULL)), + MPP_MODE(34, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "mii", "rxerr"), + MPP_FUNCTION(2, "sdio", "pwr11"), + MPP_FUNCTION(3, "mss_spi", "mosi"), + MPP_FUNCTION(4, "tdm", "dtx"), + MPP_FUNCTION(5, "au", "i2slrclk"), + MPP_FUNCTION(6, "sdio", "wr_protect"), + MPP_FUNCTION(7, "ge", "mdc"), + MPP_FUNCTION(9, "pcie0", "clkreq"), + MPP_FUNCTION(10, "mss_gpio2", NULL)), + MPP_MODE(35, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sata1", "present_act"), + MPP_FUNCTION(2, "i2c1", "sda"), + MPP_FUNCTION(3, "mss_spi", "clk"), + MPP_FUNCTION(4, "tdm", "pclk"), + MPP_FUNCTION(5, "au", "i2sdo_spdifo"), + MPP_FUNCTION(6, "sdio", "card_detect"), + MPP_FUNCTION(7, "xg", "mdio"), + MPP_FUNCTION(8, "ge", "mdio"), + MPP_FUNCTION(9, "pcie", "rstoutn"), + MPP_FUNCTION(10, "mss_gpio3", NULL)), + MPP_MODE(36, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "synce2", "clk"), + MPP_FUNCTION(2, "i2c1", "sck"), + MPP_FUNCTION(3, "ptp", "clk"), + MPP_FUNCTION(4, "synce1", "clk"), + MPP_FUNCTION(5, "au", "i2sbclk"), + MPP_FUNCTION(6, "sata0", "present_act"), + MPP_FUNCTION(7, "xg", "mdc"), + MPP_FUNCTION(8, "ge", "mdc"), + MPP_FUNCTION(9, "pcie2", "clkreq"), + MPP_FUNCTION(10, "mss_gpio5", NULL)), + MPP_MODE(37, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "uart2", "rxd"), + MPP_FUNCTION(2, "i2c0", "sck"), + MPP_FUNCTION(3, "ptp", "pclk_out"), + MPP_FUNCTION(4, "tdm", "intn"), + MPP_FUNCTION(5, "mss_i2c", "sck"), + MPP_FUNCTION(6, "sata1", "present_act"), + MPP_FUNCTION(7, "ge", "mdc"), + MPP_FUNCTION(8, "xg", "mdc"), + MPP_FUNCTION(9, "pcie1", "clkreq"), + MPP_FUNCTION(10, "mss_gpio6", NULL), + MPP_FUNCTION(11, "link", "rd_out_cp2cp")), + MPP_MODE(38, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "uart2", "txd"), + MPP_FUNCTION(2, "i2c0", "sda"), + MPP_FUNCTION(3, "ptp", "pulse"), + MPP_FUNCTION(4, "tdm", "rstn"), + MPP_FUNCTION(5, "mss_i2c", "sda"), + MPP_FUNCTION(6, "sata0", "present_act"), + MPP_FUNCTION(7, "ge", "mdio"), + MPP_FUNCTION(8, "xg", "mdio"), + MPP_FUNCTION(9, "au", "i2sextclk"), + MPP_FUNCTION(10, "mss_gpio7", NULL), + MPP_FUNCTION(11, "ptp", "pulse_cp2cp")), + MPP_MODE(39, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "wr_protect"), + MPP_FUNCTION(4, "au", "i2sbclk"), + MPP_FUNCTION(5, "ptp", "clk"), + MPP_FUNCTION(6, "spi0", "csn1"), + MPP_FUNCTION(9, "sata1", "present_act"), + MPP_FUNCTION(10, "mss_gpio0", NULL)), + MPP_MODE(40, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "pwr11"), + MPP_FUNCTION(2, "synce1", "clk"), + MPP_FUNCTION(3, "mss_i2c", "sda"), + MPP_FUNCTION(4, "au", "i2sdo_spdifo"), + MPP_FUNCTION(5, "ptp", "pclk_out"), + MPP_FUNCTION(6, "spi0", "clk"), + MPP_FUNCTION(7, "uart1", "txd"), + MPP_FUNCTION(8, "ge", "mdio"), + MPP_FUNCTION(9, "sata0", "present_act"), + MPP_FUNCTION(10, "mss_gpio1", NULL)), + MPP_MODE(41, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "pwr10"), + MPP_FUNCTION(2, "sdio", "bus_pwr"), + MPP_FUNCTION(3, "mss_i2c", "sck"), + MPP_FUNCTION(4, "au", "i2slrclk"), + MPP_FUNCTION(5, "ptp", "pulse"), + MPP_FUNCTION(6, "spi0", "mosi"), + MPP_FUNCTION(7, "uart1", "rxd"), + MPP_FUNCTION(8, "ge", "mdc"), + MPP_FUNCTION(9, "sata1", "present_act"), + MPP_FUNCTION(10, "mss_gpio2", NULL), + MPP_FUNCTION(11, "rei", "out_cp2cp")), + MPP_MODE(42, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "v18_en"), + MPP_FUNCTION(2, "sdio", "wr_protect"), + MPP_FUNCTION(3, "synce2", "clk"), + MPP_FUNCTION(4, "au", "i2smclk"), + MPP_FUNCTION(5, "mss_uart", "txd"), + MPP_FUNCTION(6, "spi0", "miso"), + MPP_FUNCTION(7, "uart1", "cts"), + MPP_FUNCTION(8, "xg", "mdc"), + MPP_FUNCTION(9, "sata0", "present_act"), + MPP_FUNCTION(10, "mss_gpio4", NULL)), + MPP_MODE(43, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "sdio", "card_detect"), + MPP_FUNCTION(3, "synce1", "clk"), + MPP_FUNCTION(4, "au", "i2sextclk"), + MPP_FUNCTION(5, "mss_uart", "rxd"), + MPP_FUNCTION(6, "spi0", "csn0"), + MPP_FUNCTION(7, "uart1", "rts"), + MPP_FUNCTION(8, "xg", "mdio"), + MPP_FUNCTION(9, "sata1", "present_act"), + MPP_FUNCTION(10, "mss_gpio5", NULL), + MPP_FUNCTION(11, "wakeup", "out_cp2cp")), + MPP_MODE(44, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "ge1", "txd2"), + MPP_FUNCTION(7, "uart0", "rts"), + MPP_FUNCTION(11, "ptp", "clk_cp2cp")), + MPP_MODE(45, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "ge1", "txd3"), + MPP_FUNCTION(7, "uart0", "txd"), + MPP_FUNCTION(9, "pcie", "rstoutn")), + MPP_MODE(46, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "ge1", "txd1"), + MPP_FUNCTION(7, "uart1", "rts")), + MPP_MODE(47, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "ge1", "txd0"), + MPP_FUNCTION(5, "spi1", "clk"), + MPP_FUNCTION(7, "uart1", "txd"), + MPP_FUNCTION(8, "ge", "mdc")), + MPP_MODE(48, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "ge1", "txctl_txen"), + MPP_FUNCTION(5, "spi1", "mosi"), + MPP_FUNCTION(8, "xg", "mdc"), + MPP_FUNCTION(11, "wakeup", "in_cp2cp")), + MPP_MODE(49, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "ge1", "txclkout"), + MPP_FUNCTION(2, "mii", "crs"), + MPP_FUNCTION(5, "spi1", "miso"), + MPP_FUNCTION(7, "uart1", "rxd"), + MPP_FUNCTION(8, "ge", "mdio"), + MPP_FUNCTION(9, "pcie0", "clkreq"), + MPP_FUNCTION(10, "sdio", "v18_en"), + MPP_FUNCTION(11, "sei", "out_cp2cp")), + MPP_MODE(50, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "ge1", "rxclk"), + MPP_FUNCTION(2, "mss_i2c", "sda"), + MPP_FUNCTION(5, "spi1", "csn0"), + MPP_FUNCTION(6, "uart2", "txd"), + MPP_FUNCTION(7, "uart0", "rxd"), + MPP_FUNCTION(8, "xg", "mdio"), + MPP_FUNCTION(10, "sdio", "pwr11")), + MPP_MODE(51, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "ge1", "rxd0"), + MPP_FUNCTION(2, "mss_i2c", "sck"), + MPP_FUNCTION(5, "spi1", "csn1"), + MPP_FUNCTION(6, "uart2", "rxd"), + MPP_FUNCTION(7, "uart0", "cts"), + MPP_FUNCTION(10, "sdio", "pwr10")), + MPP_MODE(52, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "ge1", "rxd1"), + MPP_FUNCTION(2, "synce1", "clk"), + MPP_FUNCTION(4, "synce2", "clk"), + MPP_FUNCTION(5, "spi1", "csn2"), + MPP_FUNCTION(7, "uart1", "cts"), + MPP_FUNCTION(8, "led", "clk"), + MPP_FUNCTION(9, "pcie", "rstoutn"), + MPP_FUNCTION(10, "pcie0", "clkreq")), + MPP_MODE(53, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "ge1", "rxd2"), + MPP_FUNCTION(3, "ptp", "clk"), + MPP_FUNCTION(5, "spi1", "csn3"), + MPP_FUNCTION(7, "uart1", "rxd"), + MPP_FUNCTION(8, "led", "stb"), + MPP_FUNCTION(11, "sdio", "led")), + MPP_MODE(54, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "ge1", "rxd3"), + MPP_FUNCTION(2, "synce2", "clk"), + MPP_FUNCTION(3, "ptp", "pclk_out"), + MPP_FUNCTION(4, "synce1", "clk"), + MPP_FUNCTION(8, "led", "data"), + MPP_FUNCTION(10, "sdio", "hw_rst"), + MPP_FUNCTION(11, "sdio", "wr_protect")), + MPP_MODE(55, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "ge1", "rxctl_rxdv"), + MPP_FUNCTION(3, "ptp", "pulse"), + MPP_FUNCTION(10, "sdio", "led"), + MPP_FUNCTION(11, "sdio", "card_detect")), + MPP_MODE(56, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(4, "tdm", "drx"), + MPP_FUNCTION(5, "au", "i2sdo_spdifo"), + MPP_FUNCTION(6, "spi0", "clk"), + MPP_FUNCTION(7, "uart1", "rxd"), + MPP_FUNCTION(9, "sata1", "present_act"), + MPP_FUNCTION(14, "sdio", "clk")), + MPP_MODE(57, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(2, "mss_i2c", "sda"), + MPP_FUNCTION(3, "ptp", "pclk_out"), + MPP_FUNCTION(4, "tdm", "intn"), + MPP_FUNCTION(5, "au", "i2sbclk"), + MPP_FUNCTION(6, "spi0", "mosi"), + MPP_FUNCTION(7, "uart1", "txd"), + MPP_FUNCTION(9, "sata0", "present_act"), + MPP_FUNCTION(14, "sdio", "cmd")), + MPP_MODE(58, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(2, "mss_i2c", "sck"), + MPP_FUNCTION(3, "ptp", "clk"), + MPP_FUNCTION(4, "tdm", "rstn"), + MPP_FUNCTION(5, "au", "i2sdi"), + MPP_FUNCTION(6, "spi0", "miso"), + MPP_FUNCTION(7, "uart1", "cts"), + MPP_FUNCTION(8, "led", "clk"), + MPP_FUNCTION(14, "sdio", "d0")), + MPP_MODE(59, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "mss_gpio7", NULL), + MPP_FUNCTION(2, "synce2", "clk"), + MPP_FUNCTION(4, "tdm", "fsync"), + MPP_FUNCTION(5, "au", "i2slrclk"), + MPP_FUNCTION(6, "spi0", "csn0"), + MPP_FUNCTION(7, "uart0", "cts"), + MPP_FUNCTION(8, "led", "stb"), + MPP_FUNCTION(9, "uart1", "txd"), + MPP_FUNCTION(14, "sdio", "d1")), + MPP_MODE(60, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "mss_gpio6", NULL), + MPP_FUNCTION(3, "ptp", "pulse"), + MPP_FUNCTION(4, "tdm", "dtx"), + MPP_FUNCTION(5, "au", "i2smclk"), + MPP_FUNCTION(6, "spi0", "csn1"), + MPP_FUNCTION(7, "uart0", "rts"), + MPP_FUNCTION(8, "led", "data"), + MPP_FUNCTION(9, "uart1", "rxd"), + MPP_FUNCTION(14, "sdio", "d2")), + MPP_MODE(61, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "mss_gpio5", NULL), + MPP_FUNCTION(3, "ptp", "clk"), + MPP_FUNCTION(4, "tdm", "pclk"), + MPP_FUNCTION(5, "au", "i2sextclk"), + MPP_FUNCTION(6, "spi0", "csn2"), + MPP_FUNCTION(7, "uart0", "txd"), + MPP_FUNCTION(8, "uart2", "txd"), + MPP_FUNCTION(9, "sata1", "present_act"), + MPP_FUNCTION(10, "ge", "mdio"), + MPP_FUNCTION(14, "sdio", "d3")), + MPP_MODE(62, + MPP_FUNCTION(0, "gpio", NULL), + MPP_FUNCTION(1, "mss_gpio4", NULL), + MPP_FUNCTION(2, "synce1", "clk"), + MPP_FUNCTION(3, "ptp", "pclk_out"), + MPP_FUNCTION(5, "sata1", "present_act"), + MPP_FUNCTION(6, "spi0", "csn3"), + MPP_FUNCTION(7, "uart0", "rxd"), + MPP_FUNCTION(8, "uart2", "rxd"), + MPP_FUNCTION(9, "sata0", "present_act"), + MPP_FUNCTION(10, "ge", "mdc")), +}; + +static const struct of_device_id armada_cp110_pinctrl_of_match[] = { + { + .compatible = "marvell,armada-7k-pinctrl", + .data = (void *) V_ARMADA_7K, + }, + { + .compatible = "marvell,armada-8k-cpm-pinctrl", + .data = (void *) V_ARMADA_8K_CPM, + }, + { + .compatible = "marvell,armada-8k-cps-pinctrl", + .data = (void *) V_ARMADA_8K_CPS, + }, + { }, +}; + +static const struct mvebu_mpp_ctrl armada_cp110_mpp_controls[] = { + MPP_FUNC_CTRL(0, 62, NULL, mvebu_regmap_mpp_ctrl), +}; + +static void mvebu_pinctrl_assign_variant(struct mvebu_mpp_mode *m, + u8 variant) +{ + struct mvebu_mpp_ctrl_setting *s; + + for (s = m->settings ; s->name ; s++) + s->variant = variant; +} + +static int armada_cp110_pinctrl_probe(struct platform_device *pdev) +{ + struct mvebu_pinctrl_soc_info *soc; + const struct of_device_id *match = + of_match_device(armada_cp110_pinctrl_of_match, &pdev->dev); + int i; + + if (!pdev->dev.parent) + return -ENODEV; + + soc = devm_kzalloc(&pdev->dev, + sizeof(struct mvebu_pinctrl_soc_info), GFP_KERNEL); + if (!soc) + return -ENOMEM; + + soc->variant = (unsigned long) match->data & 0xff; + soc->controls = armada_cp110_mpp_controls; + soc->ncontrols = ARRAY_SIZE(armada_cp110_mpp_controls); + soc->modes = armada_cp110_mpp_modes; + soc->nmodes = ARRAY_SIZE(armada_cp110_mpp_modes); + for (i = 0; i < ARRAY_SIZE(armada_cp110_mpp_modes); i++) { + struct mvebu_mpp_mode *m = &armada_cp110_mpp_modes[i]; + + switch (i) { + case 0 ... 31: + mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPS); + break; + case 32 ... 38: + mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPM); + break; + case 39 ... 43: + mvebu_pinctrl_assign_variant(m, V_ARMADA_8K_CPM); + break; + case 44 ... 62: + mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPM); + break; + } + } + pdev->dev.platform_data = soc; + + return mvebu_pinctrl_simple_regmap_probe(pdev, pdev->dev.parent, 0); +} + +static struct platform_driver armada_cp110_pinctrl_driver = { + .driver = { + .name = "armada-cp110-pinctrl", + .of_match_table = of_match_ptr(armada_cp110_pinctrl_of_match), + }, + .probe = armada_cp110_pinctrl_probe, +}; + +builtin_platform_driver(armada_cp110_pinctrl_driver); diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index e4dda12d371a..163d4614b0f8 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -810,21 +810,17 @@ int mvebu_regmap_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data, } int mvebu_pinctrl_simple_regmap_probe(struct platform_device *pdev, - struct device *syscon_dev) + struct device *syscon_dev, u32 offset) { struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev); struct mvebu_mpp_ctrl_data *mpp_data; struct regmap *regmap; - u32 offset; int i; regmap = syscon_node_to_regmap(syscon_dev->of_node); if (IS_ERR(regmap)) return PTR_ERR(regmap); - if (of_property_read_u32(pdev->dev.of_node, "offset", &offset)) - return -EINVAL; - mpp_data = devm_kcalloc(&pdev->dev, soc->ncontrols, sizeof(*mpp_data), GFP_KERNEL); if (!mpp_data) diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.h b/drivers/pinctrl/mvebu/pinctrl-mvebu.h index c90704e74884..75bba436bf59 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.h +++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.h @@ -210,6 +210,6 @@ int mvebu_regmap_mpp_ctrl_set(struct mvebu_mpp_ctrl_data *data, unsigned pid, int mvebu_pinctrl_probe(struct platform_device *pdev); int mvebu_pinctrl_simple_mmio_probe(struct platform_device *pdev); int mvebu_pinctrl_simple_regmap_probe(struct platform_device *pdev, - struct device *syscon_dev); + struct device *syscon_dev, u32 offset); #endif diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c index 720a19fd38d2..fc0c230aa11f 100644 --- a/drivers/pinctrl/pinconf-generic.c +++ b/drivers/pinctrl/pinconf-generic.c @@ -44,6 +44,7 @@ static const struct pin_config_item conf_items[] = { PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL, false), PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL, false), PCONFDUMP(PIN_CONFIG_LOW_POWER_MODE, "pin low power", "mode", true), + PCONFDUMP(PIN_CONFIG_OUTPUT_ENABLE, "output enabled", NULL, false), PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true), PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true), PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true), @@ -172,6 +173,8 @@ static const struct pinconf_generic_params dt_params[] = { { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 }, { "low-power-enable", PIN_CONFIG_LOW_POWER_MODE, 1 }, + { "output-disable", PIN_CONFIG_OUTPUT_ENABLE, 0 }, + { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 }, { "output-high", PIN_CONFIG_OUTPUT, 1, }, { "output-low", PIN_CONFIG_OUTPUT, 0, }, { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c index a02dba35fcf3..7fc417e4ae96 100644 --- a/drivers/pinctrl/pinconf.c +++ b/drivers/pinctrl/pinconf.c @@ -87,9 +87,8 @@ int pin_config_group_get(const char *dev_name, const char *pin_group, ops = pctldev->desc->confops; if (!ops || !ops->pin_config_group_get) { - dev_dbg(pctldev->dev, "cannot get configuration for pin " - "group, missing group config get function in " - "driver\n"); + dev_dbg(pctldev->dev, + "cannot get configuration for pin group, missing group config get function in driver\n"); ret = -ENOTSUPP; goto unlock; } @@ -232,7 +231,7 @@ static void pinconf_show_config(struct seq_file *s, struct pinctrl_dev *pctldev, configs[i]); else seq_printf(s, "%08lx", configs[i]); - seq_puts(s, "\n"); + seq_putc(s, '\n'); } } @@ -244,10 +243,10 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map) switch (map->type) { case PIN_MAP_TYPE_CONFIGS_PIN: - seq_printf(s, "pin "); + seq_puts(s, "pin "); break; case PIN_MAP_TYPE_CONFIGS_GROUP: - seq_printf(s, "group "); + seq_puts(s, "group "); break; default: break; @@ -319,14 +318,13 @@ static int pinconf_pins_show(struct seq_file *s, void *what) pin = pctldev->desc->pins[i].number; desc = pin_desc_get(pctldev, pin); /* Skip if we cannot search the pin */ - if (desc == NULL) + if (!desc) continue; seq_printf(s, "pin %d (%s): ", pin, desc->name); pinconf_dump_pin(pctldev, s, pin); - - seq_printf(s, "\n"); + seq_putc(s, '\n'); } mutex_unlock(&pctldev->mutex); @@ -361,8 +359,7 @@ static int pinconf_groups_show(struct seq_file *s, void *what) seq_printf(s, "%u (%s): ", selector, gname); pinconf_dump_group(pctldev, s, selector, gname); - seq_printf(s, "\n"); - + seq_putc(s, '\n'); selector++; } @@ -397,9 +394,9 @@ static const struct file_operations pinconf_groups_ops = { struct dbg_cfg { enum pinctrl_map_type map_type; - char dev_name[MAX_NAME_LEN+1]; - char state_name[MAX_NAME_LEN+1]; - char pin_name[MAX_NAME_LEN+1]; + char dev_name[MAX_NAME_LEN + 1]; + char state_name[MAX_NAME_LEN + 1]; + char pin_name[MAX_NAME_LEN + 1]; }; /* @@ -485,7 +482,7 @@ static ssize_t pinconf_dbg_config_write(struct file *file, const struct pinconf_ops *confops = NULL; struct dbg_cfg *dbg = &pinconf_dbg_conf; const struct pinctrl_map_configs *configs; - char config[MAX_NAME_LEN+1]; + char config[MAX_NAME_LEN + 1]; char buf[128]; char *b = &buf[0]; int buf_size; @@ -526,7 +523,7 @@ static ssize_t pinconf_dbg_config_write(struct file *file, /* get arg 'device_name' */ token = strsep(&b, " "); - if (token == NULL) + if (!token) return -EINVAL; if (strlen(token) >= MAX_NAME_LEN) return -EINVAL; @@ -534,7 +531,7 @@ static ssize_t pinconf_dbg_config_write(struct file *file, /* get arg 'state_name' */ token = strsep(&b, " "); - if (token == NULL) + if (!token) return -EINVAL; if (strlen(token) >= MAX_NAME_LEN) return -EINVAL; @@ -542,7 +539,7 @@ static ssize_t pinconf_dbg_config_write(struct file *file, /* get arg 'pin_name' */ token = strsep(&b, " "); - if (token == NULL) + if (!token) return -EINVAL; if (strlen(token) >= MAX_NAME_LEN) return -EINVAL; @@ -550,7 +547,7 @@ static ssize_t pinconf_dbg_config_write(struct file *file, /* get new_value of config' */ token = strsep(&b, " "); - if (token == NULL) + if (!token) return -EINVAL; if (strlen(token) >= MAX_NAME_LEN) return -EINVAL; diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index e432ec887479..e6779d4352a2 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -8,6 +8,10 @@ * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. + * + * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> + * Shyam Sundar S K <Shyam-sundar.S-k@amd.com> + * */ #include <linux/err.h> diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c new file mode 100644 index 000000000000..d8e8842967d6 --- /dev/null +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -0,0 +1,852 @@ +/* + * Ingenic SoCs pinctrl driver + * + * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> + * + * License terms: GNU General Public License (GPL) version 2 + */ + +#include <linux/compiler.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/slab.h> + +#include "core.h" +#include "pinconf.h" +#include "pinmux.h" + +#define JZ4740_GPIO_DATA 0x10 +#define JZ4740_GPIO_PULL_DIS 0x30 +#define JZ4740_GPIO_FUNC 0x40 +#define JZ4740_GPIO_SELECT 0x50 +#define JZ4740_GPIO_DIR 0x60 +#define JZ4740_GPIO_TRIG 0x70 +#define JZ4740_GPIO_FLAG 0x80 + +#define JZ4770_GPIO_INT 0x10 +#define JZ4770_GPIO_MSK 0x20 +#define JZ4770_GPIO_PAT1 0x30 +#define JZ4770_GPIO_PAT0 0x40 +#define JZ4770_GPIO_FLAG 0x50 +#define JZ4770_GPIO_PEN 0x70 + +#define REG_SET(x) ((x) + 0x4) +#define REG_CLEAR(x) ((x) + 0x8) + +#define PINS_PER_GPIO_CHIP 32 + +enum jz_version { + ID_JZ4740, + ID_JZ4770, + ID_JZ4780, +}; + +struct ingenic_chip_info { + unsigned int num_chips; + + const struct group_desc *groups; + unsigned int num_groups; + + const struct function_desc *functions; + unsigned int num_functions; + + const u32 *pull_ups, *pull_downs; +}; + +struct ingenic_pinctrl { + struct device *dev; + struct regmap *map; + struct pinctrl_dev *pctl; + struct pinctrl_pin_desc *pdesc; + enum jz_version version; + + const struct ingenic_chip_info *info; +}; + +static const u32 jz4740_pull_ups[4] = { + 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, +}; + +static const u32 jz4740_pull_downs[4] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, }; +static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; +static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, }; +static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; +static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, }; +static int jz4740_lcd_8bit_pins[] = { + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54, +}; +static int jz4740_lcd_16bit_pins[] = { + 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55, +}; +static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, }; +static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, }; +static int jz4740_nand_cs1_pins[] = { 0x39, }; +static int jz4740_nand_cs2_pins[] = { 0x3a, }; +static int jz4740_nand_cs3_pins[] = { 0x3b, }; +static int jz4740_nand_cs4_pins[] = { 0x3c, }; +static int jz4740_pwm_pwm0_pins[] = { 0x77, }; +static int jz4740_pwm_pwm1_pins[] = { 0x78, }; +static int jz4740_pwm_pwm2_pins[] = { 0x79, }; +static int jz4740_pwm_pwm3_pins[] = { 0x7a, }; +static int jz4740_pwm_pwm4_pins[] = { 0x7b, }; +static int jz4740_pwm_pwm5_pins[] = { 0x7c, }; +static int jz4740_pwm_pwm6_pins[] = { 0x7e, }; +static int jz4740_pwm_pwm7_pins[] = { 0x7f, }; + +static int jz4740_mmc_1bit_funcs[] = { 0, 0, 0, }; +static int jz4740_mmc_4bit_funcs[] = { 0, 0, 0, }; +static int jz4740_uart0_data_funcs[] = { 1, 1, }; +static int jz4740_uart0_hwflow_funcs[] = { 1, 1, }; +static int jz4740_uart1_data_funcs[] = { 2, 2, }; +static int jz4740_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; +static int jz4740_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, }; +static int jz4740_lcd_18bit_funcs[] = { 0, 0, }; +static int jz4740_lcd_18bit_tft_funcs[] = { 0, 0, 0, 0, }; +static int jz4740_nand_cs1_funcs[] = { 0, }; +static int jz4740_nand_cs2_funcs[] = { 0, }; +static int jz4740_nand_cs3_funcs[] = { 0, }; +static int jz4740_nand_cs4_funcs[] = { 0, }; +static int jz4740_pwm_pwm0_funcs[] = { 0, }; +static int jz4740_pwm_pwm1_funcs[] = { 0, }; +static int jz4740_pwm_pwm2_funcs[] = { 0, }; +static int jz4740_pwm_pwm3_funcs[] = { 0, }; +static int jz4740_pwm_pwm4_funcs[] = { 0, }; +static int jz4740_pwm_pwm5_funcs[] = { 0, }; +static int jz4740_pwm_pwm6_funcs[] = { 0, }; +static int jz4740_pwm_pwm7_funcs[] = { 0, }; + +#define INGENIC_PIN_GROUP(name, id) \ + { \ + name, \ + id##_pins, \ + ARRAY_SIZE(id##_pins), \ + id##_funcs, \ + } + +static const struct group_desc jz4740_groups[] = { + INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit), + INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit), + INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data), + INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow), + INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data), + INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit), + INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit), + INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit), + INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft), + { "lcd-no-pins", }, + INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1), + INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2), + INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3), + INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4), + INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0), + INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1), + INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2), + INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3), + INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4), + INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5), + INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6), + INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7), +}; + +static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; +static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; +static const char *jz4740_uart1_groups[] = { "uart1-data", }; +static const char *jz4740_lcd_groups[] = { + "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins", +}; +static const char *jz4740_nand_groups[] = { + "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", +}; +static const char *jz4740_pwm0_groups[] = { "pwm0", }; +static const char *jz4740_pwm1_groups[] = { "pwm1", }; +static const char *jz4740_pwm2_groups[] = { "pwm2", }; +static const char *jz4740_pwm3_groups[] = { "pwm3", }; +static const char *jz4740_pwm4_groups[] = { "pwm4", }; +static const char *jz4740_pwm5_groups[] = { "pwm5", }; +static const char *jz4740_pwm6_groups[] = { "pwm6", }; +static const char *jz4740_pwm7_groups[] = { "pwm7", }; + +static const struct function_desc jz4740_functions[] = { + { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), }, + { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), }, + { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), }, + { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), }, + { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), }, + { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), }, + { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), }, + { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), }, + { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), }, + { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), }, + { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), }, + { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), }, + { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), }, +}; + +static const struct ingenic_chip_info jz4740_chip_info = { + .num_chips = 4, + .groups = jz4740_groups, + .num_groups = ARRAY_SIZE(jz4740_groups), + .functions = jz4740_functions, + .num_functions = ARRAY_SIZE(jz4740_functions), + .pull_ups = jz4740_pull_ups, + .pull_downs = jz4740_pull_downs, +}; + +static const u32 jz4770_pull_ups[6] = { + 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f, +}; + +static const u32 jz4770_pull_downs[6] = { + 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, +}; + +static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, }; +static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; +static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, }; +static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; +static int jz4770_uart2_data_pins[] = { 0x66, 0x67, }; +static int jz4770_uart2_hwflow_pins[] = { 0x65, 0x64, }; +static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, }; +static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, }; +static int jz4770_uart4_data_pins[] = { 0x54, 0x4a, }; +static int jz4770_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, }; +static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; +static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; +static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; +static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; +static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; +static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; +static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; +static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; +static int jz4770_nemc_data_pins[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, +}; +static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, }; +static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; +static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, }; +static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; +static int jz4770_nemc_cs1_pins[] = { 0x15, }; +static int jz4770_nemc_cs2_pins[] = { 0x16, }; +static int jz4770_nemc_cs3_pins[] = { 0x17, }; +static int jz4770_nemc_cs4_pins[] = { 0x18, }; +static int jz4770_nemc_cs5_pins[] = { 0x19, }; +static int jz4770_nemc_cs6_pins[] = { 0x1a, }; +static int jz4770_i2c0_pins[] = { 0x6e, 0x6f, }; +static int jz4770_i2c1_pins[] = { 0x8e, 0x8f, }; +static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, }; +static int jz4770_i2c3_pins[] = { 0x6a, 0x6b, }; +static int jz4770_i2c4_e_pins[] = { 0x8c, 0x8d, }; +static int jz4770_i2c4_f_pins[] = { 0xb9, 0xb8, }; +static int jz4770_cim_pins[] = { + 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, +}; +static int jz4770_lcd_32bit_pins[] = { + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, + 0x58, 0x59, 0x51, +}; +static int jz4770_pwm_pwm0_pins[] = { 0x80, }; +static int jz4770_pwm_pwm1_pins[] = { 0x81, }; +static int jz4770_pwm_pwm2_pins[] = { 0x82, }; +static int jz4770_pwm_pwm3_pins[] = { 0x83, }; +static int jz4770_pwm_pwm4_pins[] = { 0x84, }; +static int jz4770_pwm_pwm5_pins[] = { 0x85, }; +static int jz4770_pwm_pwm6_pins[] = { 0x6a, }; +static int jz4770_pwm_pwm7_pins[] = { 0x6b, }; + +static int jz4770_uart0_data_funcs[] = { 0, 0, }; +static int jz4770_uart0_hwflow_funcs[] = { 0, 0, }; +static int jz4770_uart1_data_funcs[] = { 0, 0, }; +static int jz4770_uart1_hwflow_funcs[] = { 0, 0, }; +static int jz4770_uart2_data_funcs[] = { 1, 1, }; +static int jz4770_uart2_hwflow_funcs[] = { 1, 1, }; +static int jz4770_uart3_data_funcs[] = { 0, 1, }; +static int jz4770_uart3_hwflow_funcs[] = { 0, 0, }; +static int jz4770_uart4_data_funcs[] = { 2, 2, }; +static int jz4770_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, }; +static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, }; +static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; +static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, }; +static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, }; +static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, }; +static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, }; +static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, }; +static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, }; +static int jz4770_nemc_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, }; +static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, }; +static int jz4770_nemc_rd_we_funcs[] = { 0, 0, }; +static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, }; +static int jz4770_nemc_cs1_funcs[] = { 0, }; +static int jz4770_nemc_cs2_funcs[] = { 0, }; +static int jz4770_nemc_cs3_funcs[] = { 0, }; +static int jz4770_nemc_cs4_funcs[] = { 0, }; +static int jz4770_nemc_cs5_funcs[] = { 0, }; +static int jz4770_nemc_cs6_funcs[] = { 0, }; +static int jz4770_i2c0_funcs[] = { 0, 0, }; +static int jz4770_i2c1_funcs[] = { 0, 0, }; +static int jz4770_i2c2_funcs[] = { 2, 2, }; +static int jz4770_i2c3_funcs[] = { 1, 1, }; +static int jz4770_i2c4_e_funcs[] = { 1, 1, }; +static int jz4770_i2c4_f_funcs[] = { 1, 1, }; +static int jz4770_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; +static int jz4770_lcd_32bit_funcs[] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, +}; +static int jz4770_pwm_pwm0_funcs[] = { 0, }; +static int jz4770_pwm_pwm1_funcs[] = { 0, }; +static int jz4770_pwm_pwm2_funcs[] = { 0, }; +static int jz4770_pwm_pwm3_funcs[] = { 0, }; +static int jz4770_pwm_pwm4_funcs[] = { 0, }; +static int jz4770_pwm_pwm5_funcs[] = { 0, }; +static int jz4770_pwm_pwm6_funcs[] = { 0, }; +static int jz4770_pwm_pwm7_funcs[] = { 0, }; + +static const struct group_desc jz4770_groups[] = { + INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data), + INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow), + INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data), + INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow), + INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data), + INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow), + INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data), + INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow), + INGENIC_PIN_GROUP("uart4-data", jz4770_uart4_data), + INGENIC_PIN_GROUP("mmc0-8bit-a", jz4770_mmc0_8bit_a), + INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a), + INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a), + INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e), + INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e), + INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d), + INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d), + INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e), + INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e), + INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_data), + INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale), + INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr), + INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we), + INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe), + INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1), + INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2), + INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3), + INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4), + INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5), + INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6), + INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0), + INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1), + INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2), + INGENIC_PIN_GROUP("i2c3-data", jz4770_i2c3), + INGENIC_PIN_GROUP("i2c4-data-e", jz4770_i2c4_e), + INGENIC_PIN_GROUP("i2c4-data-f", jz4770_i2c4_f), + INGENIC_PIN_GROUP("cim-data", jz4770_cim), + INGENIC_PIN_GROUP("lcd-32bit", jz4770_lcd_32bit), + { "lcd-no-pins", }, + INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0), + INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1), + INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2), + INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3), + INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4), + INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5), + INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6), + INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7), +}; + +static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; +static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; +static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; +static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; +static const char *jz4770_uart4_groups[] = { "uart4-data", }; +static const char *jz4770_mmc0_groups[] = { + "mmc0-8bit-a", "mmc0-4bit-a", "mmc0-1bit-a", + "mmc0-1bit-e", "mmc0-4bit-e", +}; +static const char *jz4770_mmc1_groups[] = { + "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e", +}; +static const char *jz4770_nemc_groups[] = { + "nemc-data", "nemc-cle-ale", "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", +}; +static const char *jz4770_cs1_groups[] = { "nemc-cs1", }; +static const char *jz4770_cs6_groups[] = { "nemc-cs6", }; +static const char *jz4770_i2c0_groups[] = { "i2c0-data", }; +static const char *jz4770_i2c1_groups[] = { "i2c1-data", }; +static const char *jz4770_i2c2_groups[] = { "i2c2-data", }; +static const char *jz4770_i2c3_groups[] = { "i2c3-data", }; +static const char *jz4770_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", }; +static const char *jz4770_cim_groups[] = { "cim-data", }; +static const char *jz4770_lcd_groups[] = { "lcd-32bit", "lcd-no-pins", }; +static const char *jz4770_pwm0_groups[] = { "pwm0", }; +static const char *jz4770_pwm1_groups[] = { "pwm1", }; +static const char *jz4770_pwm2_groups[] = { "pwm2", }; +static const char *jz4770_pwm3_groups[] = { "pwm3", }; +static const char *jz4770_pwm4_groups[] = { "pwm4", }; +static const char *jz4770_pwm5_groups[] = { "pwm5", }; +static const char *jz4770_pwm6_groups[] = { "pwm6", }; +static const char *jz4770_pwm7_groups[] = { "pwm7", }; + +static const struct function_desc jz4770_functions[] = { + { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, + { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, + { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), }, + { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, + { "uart4", jz4770_uart4_groups, ARRAY_SIZE(jz4770_uart4_groups), }, + { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), }, + { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), }, + { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), }, + { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, + { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, + { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, + { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, + { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, + { "i2c3", jz4770_i2c3_groups, ARRAY_SIZE(jz4770_i2c3_groups), }, + { "i2c4", jz4770_i2c4_groups, ARRAY_SIZE(jz4770_i2c4_groups), }, + { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), }, + { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, + { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, + { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, + { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, + { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, + { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, + { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, + { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, + { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, +}; + +static const struct ingenic_chip_info jz4770_chip_info = { + .num_chips = 6, + .groups = jz4770_groups, + .num_groups = ARRAY_SIZE(jz4770_groups), + .functions = jz4770_functions, + .num_functions = ARRAY_SIZE(jz4770_functions), + .pull_ups = jz4770_pull_ups, + .pull_downs = jz4770_pull_downs, +}; + +static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, + unsigned int pin, u8 reg, bool set) +{ + unsigned int idx = pin % PINS_PER_GPIO_CHIP; + unsigned int offt = pin / PINS_PER_GPIO_CHIP; + + regmap_write(jzpc->map, offt * 0x100 + + (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); +} + +static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, + unsigned int pin, u8 reg) +{ + unsigned int idx = pin % PINS_PER_GPIO_CHIP; + unsigned int offt = pin / PINS_PER_GPIO_CHIP; + unsigned int val; + + regmap_read(jzpc->map, offt * 0x100 + reg, &val); + + return val & BIT(idx); +} + +static struct pinctrl_ops ingenic_pctlops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinconf_generic_dt_free_map, +}; + +static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, + int pin, int func) +{ + unsigned int idx = pin % PINS_PER_GPIO_CHIP; + unsigned int offt = pin / PINS_PER_GPIO_CHIP; + + dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", + 'A' + offt, idx, func); + + if (jzpc->version >= ID_JZ4770) { + ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); + ingenic_config_pin(jzpc, pin, JZ4770_GPIO_MSK, false); + ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2); + ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1); + } else { + ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); + ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); + ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func > 0); + } + + return 0; +} + +static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int selector, unsigned int group) +{ + struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); + struct function_desc *func; + struct group_desc *grp; + unsigned int i; + + func = pinmux_generic_get_function(pctldev, selector); + if (!func) + return -EINVAL; + + grp = pinctrl_generic_get_group(pctldev, group); + if (!grp) + return -EINVAL; + + dev_dbg(pctldev->dev, "enable function %s group %s\n", + func->name, grp->name); + + for (i = 0; i < grp->num_pins; i++) { + int *pin_modes = grp->data; + + ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]); + } + + return 0; +} + +static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin, bool input) +{ + struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); + unsigned int idx = pin % PINS_PER_GPIO_CHIP; + unsigned int offt = pin / PINS_PER_GPIO_CHIP; + + dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", + 'A' + offt, idx, input ? "in" : "out"); + + if (jzpc->version >= ID_JZ4770) { + ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); + ingenic_config_pin(jzpc, pin, JZ4770_GPIO_MSK, true); + ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input); + } else { + ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false); + ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, input); + ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false); + } + + return 0; +} + +static struct pinmux_ops ingenic_pmxops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = ingenic_pinmux_set_mux, + .gpio_set_direction = ingenic_pinmux_gpio_set_direction, +}; + +static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *config) +{ + struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned int idx = pin % PINS_PER_GPIO_CHIP; + unsigned int offt = pin / PINS_PER_GPIO_CHIP; + bool pull; + + if (jzpc->version >= ID_JZ4770) + pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN); + else + pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + if (pull) + return -EINVAL; + break; + + case PIN_CONFIG_BIAS_PULL_UP: + if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx))) + return -EINVAL; + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx))) + return -EINVAL; + break; + + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, 1); + return 0; +} + +static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, + unsigned int pin, bool enabled) +{ + if (jzpc->version >= ID_JZ4770) + ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !enabled); + else + ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !enabled); +} + +static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); + unsigned int idx = pin % PINS_PER_GPIO_CHIP; + unsigned int offt = pin / PINS_PER_GPIO_CHIP; + unsigned int cfg; + + for (cfg = 0; cfg < num_configs; cfg++) { + switch (pinconf_to_config_param(configs[cfg])) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + continue; + default: + return -ENOTSUPP; + } + } + + for (cfg = 0; cfg < num_configs; cfg++) { + switch (pinconf_to_config_param(configs[cfg])) { + case PIN_CONFIG_BIAS_DISABLE: + dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", + 'A' + offt, idx); + ingenic_set_bias(jzpc, pin, false); + break; + + case PIN_CONFIG_BIAS_PULL_UP: + if (!(jzpc->info->pull_ups[offt] & BIT(idx))) + return -EINVAL; + dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", + 'A' + offt, idx); + ingenic_set_bias(jzpc, pin, true); + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + if (!(jzpc->info->pull_downs[offt] & BIT(idx))) + return -EINVAL; + dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", + 'A' + offt, idx); + ingenic_set_bias(jzpc, pin, true); + break; + + default: + unreachable(); + } + } + + return 0; +} + +static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev, + unsigned int group, unsigned long *config) +{ + const unsigned int *pins; + unsigned int i, npins, old = 0; + int ret; + + ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + for (i = 0; i < npins; i++) { + if (ingenic_pinconf_get(pctldev, pins[i], config)) + return -ENOTSUPP; + + /* configs do not match between two pins */ + if (i && (old != *config)) + return -ENOTSUPP; + + old = *config; + } + + return 0; +} + +static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned int group, unsigned long *configs, + unsigned int num_configs) +{ + const unsigned int *pins; + unsigned int i, npins; + int ret; + + ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); + if (ret) + return ret; + + for (i = 0; i < npins; i++) { + ret = ingenic_pinconf_set(pctldev, + pins[i], configs, num_configs); + if (ret) + return ret; + } + + return 0; +} + +static struct pinconf_ops ingenic_confops = { + .is_generic = true, + .pin_config_get = ingenic_pinconf_get, + .pin_config_set = ingenic_pinconf_set, + .pin_config_group_get = ingenic_pinconf_group_get, + .pin_config_group_set = ingenic_pinconf_group_set, +}; + +static const struct regmap_config ingenic_pinctrl_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static const struct of_device_id ingenic_pinctrl_of_match[] = { + { .compatible = "ingenic,jz4740-pinctrl", .data = (void *) ID_JZ4740 }, + { .compatible = "ingenic,jz4770-pinctrl", .data = (void *) ID_JZ4770 }, + { .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 }, + {}, +}; + +int ingenic_pinctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct ingenic_pinctrl *jzpc; + struct pinctrl_desc *pctl_desc; + void __iomem *base; + const struct platform_device_id *id = platform_get_device_id(pdev); + const struct of_device_id *of_id = of_match_device( + ingenic_pinctrl_of_match, dev); + const struct ingenic_chip_info *chip_info; + unsigned int i; + int err; + + jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL); + if (!jzpc) + return -ENOMEM; + + base = devm_ioremap_resource(dev, + platform_get_resource(pdev, IORESOURCE_MEM, 0)); + if (IS_ERR(base)) { + dev_err(dev, "Failed to ioremap registers\n"); + return PTR_ERR(base); + } + + jzpc->map = devm_regmap_init_mmio(dev, base, + &ingenic_pinctrl_regmap_config); + if (IS_ERR(jzpc->map)) { + dev_err(dev, "Failed to create regmap\n"); + return PTR_ERR(jzpc->map); + } + + jzpc->dev = dev; + + if (of_id) + jzpc->version = (enum jz_version)of_id->data; + else + jzpc->version = (enum jz_version)id->driver_data; + + if (jzpc->version >= ID_JZ4770) + chip_info = &jz4770_chip_info; + else + chip_info = &jz4740_chip_info; + jzpc->info = chip_info; + + pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); + if (!pctl_desc) + return -ENOMEM; + + /* fill in pinctrl_desc structure */ + pctl_desc->name = dev_name(dev); + pctl_desc->owner = THIS_MODULE; + pctl_desc->pctlops = &ingenic_pctlops; + pctl_desc->pmxops = &ingenic_pmxops; + pctl_desc->confops = &ingenic_confops; + pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP; + pctl_desc->pins = jzpc->pdesc = devm_kzalloc(&pdev->dev, + sizeof(*jzpc->pdesc) * pctl_desc->npins, GFP_KERNEL); + if (!jzpc->pdesc) + return -ENOMEM; + + for (i = 0; i < pctl_desc->npins; i++) { + jzpc->pdesc[i].number = i; + jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d", + 'A' + (i / PINS_PER_GPIO_CHIP), + i % PINS_PER_GPIO_CHIP); + } + + jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc); + if (IS_ERR(jzpc->pctl)) { + dev_err(dev, "Failed to register pinctrl\n"); + return PTR_ERR(jzpc->pctl); + } + + for (i = 0; i < chip_info->num_groups; i++) { + const struct group_desc *group = &chip_info->groups[i]; + + err = pinctrl_generic_add_group(jzpc->pctl, group->name, + group->pins, group->num_pins, group->data); + if (err) { + dev_err(dev, "Failed to register group %s\n", + group->name); + return err; + } + } + + for (i = 0; i < chip_info->num_functions; i++) { + const struct function_desc *func = &chip_info->functions[i]; + + err = pinmux_generic_add_function(jzpc->pctl, func->name, + func->group_names, func->num_group_names, + func->data); + if (err) { + dev_err(dev, "Failed to register function %s\n", + func->name); + return err; + } + } + + dev_set_drvdata(dev, jzpc->map); + + if (dev->of_node) { + err = of_platform_populate(dev->of_node, NULL, NULL, dev); + if (err) { + dev_err(dev, "Failed to probe GPIO devices\n"); + return err; + } + } + + return 0; +} + +static const struct platform_device_id ingenic_pinctrl_ids[] = { + { "jz4740-pinctrl", ID_JZ4740 }, + { "jz4770-pinctrl", ID_JZ4770 }, + { "jz4780-pinctrl", ID_JZ4780 }, + {}, +}; + +static struct platform_driver ingenic_pinctrl_driver = { + .driver = { + .name = "pinctrl-ingenic", + .of_match_table = of_match_ptr(ingenic_pinctrl_of_match), + .suppress_bind_attrs = true, + }, + .probe = ingenic_pinctrl_probe, + .id_table = ingenic_pinctrl_ids, +}; + +static int __init ingenic_pinctrl_drv_register(void) +{ + return platform_driver_register(&ingenic_pinctrl_driver); +} +postcore_initcall(ingenic_pinctrl_drv_register); diff --git a/drivers/gpio/gpio-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index 2a57d024481d..3e40d4245512 100644 --- a/drivers/gpio/gpio-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -1,14 +1,4 @@ -/* - * MCP23S08 SPI/I2C GPIO gpio expander driver - * - * The inputs and outputs of the mcp23s08, mcp23s17, mcp23008 and mcp23017 are - * supported. - * For the I2C versions of the chips (mcp23008 and mcp23017) generation of - * interrupts is also supported. - * The hardware of the SPI versions of the chips (mcp23s08 and mcp23s17) is - * also capable of generating interrupts, but the linux driver does not - * support that yet. - */ +/* MCP23S08 SPI/I2C GPIO driver */ #include <linux/kernel.h> #include <linux/device.h> @@ -21,11 +11,13 @@ #include <linux/slab.h> #include <asm/byteorder.h> #include <linux/interrupt.h> -#include <linux/of_irq.h> #include <linux/of_device.h> #include <linux/regmap.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf.h> +#include <linux/pinctrl/pinconf-generic.h> -/** +/* * MCP types supported by driver */ #define MCP_TYPE_S08 0 @@ -34,6 +26,8 @@ #define MCP_TYPE_017 3 #define MCP_TYPE_S18 4 +#define MCP_MAX_DEV_PER_CS 8 + /* Registers are all 8 bits wide. * * The mcp23s17 has twice as many bits, and can be configured to work @@ -64,19 +58,52 @@ struct mcp23s08 { bool irq_active_high; bool reg_shift; - u16 cache[11]; u16 irq_rise; u16 irq_fall; int irq; bool irq_controller; - /* lock protects the cached values */ + int cached_gpio; + /* lock protects regmap access with bypass/cache flags */ struct mutex lock; - struct mutex irq_lock; struct gpio_chip chip; struct regmap *regmap; struct device *dev; + + struct pinctrl_dev *pctldev; + struct pinctrl_desc pinctrl_desc; +}; + +static const struct reg_default mcp23x08_defaults[] = { + {.reg = MCP_IODIR, .def = 0xff}, + {.reg = MCP_IPOL, .def = 0x00}, + {.reg = MCP_GPINTEN, .def = 0x00}, + {.reg = MCP_DEFVAL, .def = 0x00}, + {.reg = MCP_INTCON, .def = 0x00}, + {.reg = MCP_IOCON, .def = 0x00}, + {.reg = MCP_GPPU, .def = 0x00}, + {.reg = MCP_OLAT, .def = 0x00}, +}; + +static const struct regmap_range mcp23x08_volatile_range = { + .range_min = MCP_INTF, + .range_max = MCP_GPIO, +}; + +static const struct regmap_access_table mcp23x08_volatile_table = { + .yes_ranges = &mcp23x08_volatile_range, + .n_yes_ranges = 1, +}; + +static const struct regmap_range mcp23x08_precious_range = { + .range_min = MCP_GPIO, + .range_max = MCP_GPIO, +}; + +static const struct regmap_access_table mcp23x08_precious_table = { + .yes_ranges = &mcp23x08_precious_range, + .n_yes_ranges = 1, }; static const struct regmap_config mcp23x08_regmap = { @@ -84,18 +111,203 @@ static const struct regmap_config mcp23x08_regmap = { .val_bits = 8, .reg_stride = 1, + .volatile_table = &mcp23x08_volatile_table, + .precious_table = &mcp23x08_precious_table, + .reg_defaults = mcp23x08_defaults, + .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults), + .cache_type = REGCACHE_FLAT, .max_register = MCP_OLAT, }; +static const struct reg_default mcp23x16_defaults[] = { + {.reg = MCP_IODIR << 1, .def = 0xffff}, + {.reg = MCP_IPOL << 1, .def = 0x0000}, + {.reg = MCP_GPINTEN << 1, .def = 0x0000}, + {.reg = MCP_DEFVAL << 1, .def = 0x0000}, + {.reg = MCP_INTCON << 1, .def = 0x0000}, + {.reg = MCP_IOCON << 1, .def = 0x0000}, + {.reg = MCP_GPPU << 1, .def = 0x0000}, + {.reg = MCP_OLAT << 1, .def = 0x0000}, +}; + +static const struct regmap_range mcp23x16_volatile_range = { + .range_min = MCP_INTF << 1, + .range_max = MCP_GPIO << 1, +}; + +static const struct regmap_access_table mcp23x16_volatile_table = { + .yes_ranges = &mcp23x16_volatile_range, + .n_yes_ranges = 1, +}; + +static const struct regmap_range mcp23x16_precious_range = { + .range_min = MCP_GPIO << 1, + .range_max = MCP_GPIO << 1, +}; + +static const struct regmap_access_table mcp23x16_precious_table = { + .yes_ranges = &mcp23x16_precious_range, + .n_yes_ranges = 1, +}; + static const struct regmap_config mcp23x17_regmap = { .reg_bits = 8, .val_bits = 16, .reg_stride = 2, .max_register = MCP_OLAT << 1, + .volatile_table = &mcp23x16_volatile_table, + .precious_table = &mcp23x16_precious_table, + .reg_defaults = mcp23x16_defaults, + .num_reg_defaults = ARRAY_SIZE(mcp23x16_defaults), + .cache_type = REGCACHE_FLAT, .val_format_endian = REGMAP_ENDIAN_LITTLE, }; +static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) +{ + return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); +} + +static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val) +{ + return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); +} + +static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg, + unsigned int mask, bool enabled) +{ + u16 val = enabled ? 0xffff : 0x0000; + return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift, + mask, val); +} + +static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg, + unsigned int pin, bool enabled) +{ + u16 mask = BIT(pin); + return mcp_set_mask(mcp, reg, mask, enabled); +} + +static const struct pinctrl_pin_desc mcp23x08_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), +}; + +static const struct pinctrl_pin_desc mcp23x17_pins[] = { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), +}; + +static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return 0; +} + +static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + return NULL; +} + +static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *num_pins) +{ + return -ENOTSUPP; +} + +static const struct pinctrl_ops mcp_pinctrl_ops = { + .get_groups_count = mcp_pinctrl_get_groups_count, + .get_group_name = mcp_pinctrl_get_group_name, + .get_group_pins = mcp_pinctrl_get_group_pins, +#ifdef CONFIG_OF + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinconf_generic_dt_free_map, +#endif +}; + +static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param = pinconf_to_config_param(*config); + unsigned int data, status; + int ret; + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + ret = mcp_read(mcp, MCP_GPPU, &data); + if (ret < 0) + return ret; + status = (data & BIT(pin)) ? 1 : 0; + break; + default: + dev_err(mcp->dev, "Invalid config param %04x\n", param); + return -ENOTSUPP; + } + + *config = 0; + + return status ? 0 : -EINVAL; +} + +static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev); + enum pin_config_param param; + u32 arg, mask; + u16 val; + int ret = 0; + int i; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + val = arg ? 0xFFFF : 0x0000; + mask = BIT(pin); + ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg); + break; + default: + dev_err(mcp->dev, "Invalid config param %04x\n", param); + return -ENOTSUPP; + } + } + + return ret; +} + +static const struct pinconf_ops mcp_pinconf_ops = { + .pin_config_get = mcp_pinconf_get, + .pin_config_set = mcp_pinconf_set, + .is_generic = true, +}; + /*----------------------------------------------------------------------*/ #ifdef CONFIG_SPI_MASTER @@ -158,30 +370,6 @@ static const struct regmap_bus mcp23sxx_spi_regmap = { #endif /* CONFIG_SPI_MASTER */ -static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) -{ - return regmap_read(mcp->regmap, reg << mcp->reg_shift, val); -} - -static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val) -{ - return regmap_write(mcp->regmap, reg << mcp->reg_shift, val); -} - -static int mcp_update_cache(struct mcp23s08 *mcp) -{ - int ret, reg, i; - - for (i = 0; i < ARRAY_SIZE(mcp->cache); i++) { - ret = mcp_read(mcp, i, ®); - if (ret < 0) - return ret; - mcp->cache[i] = reg; - } - - return 0; -} - /*----------------------------------------------------------------------*/ /* A given spi_device can represent up to eight mcp23sxx chips @@ -202,9 +390,9 @@ static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) int status; mutex_lock(&mcp->lock); - mcp->cache[MCP_IODIR] |= (1 << offset); - status = mcp_write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]); + status = mcp_set_bit(mcp, MCP_IODIR, offset, true); mutex_unlock(&mcp->lock); + return status; } @@ -219,33 +407,27 @@ static int mcp23s08_get(struct gpio_chip *chip, unsigned offset) ret = mcp_read(mcp, MCP_GPIO, &status); if (ret < 0) status = 0; - else { - mcp->cache[MCP_GPIO] = status; + else status = !!(status & (1 << offset)); - } + + mcp->cached_gpio = status; + mutex_unlock(&mcp->lock); return status; } -static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, int value) +static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value) { - unsigned olat = mcp->cache[MCP_OLAT]; - - if (value) - olat |= mask; - else - olat &= ~mask; - mcp->cache[MCP_OLAT] = olat; - return mcp_write(mcp, MCP_OLAT, olat); + return mcp_set_mask(mcp, MCP_OLAT, mask, value); } static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value) { struct mcp23s08 *mcp = gpiochip_get_data(chip); - unsigned mask = 1 << offset; + unsigned mask = BIT(offset); mutex_lock(&mcp->lock); - __mcp23s08_set(mcp, mask, value); + __mcp23s08_set(mcp, mask, !!value); mutex_unlock(&mcp->lock); } @@ -253,14 +435,13 @@ static int mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) { struct mcp23s08 *mcp = gpiochip_get_data(chip); - unsigned mask = 1 << offset; + unsigned mask = BIT(offset); int status; mutex_lock(&mcp->lock); status = __mcp23s08_set(mcp, mask, value); if (status == 0) { - mcp->cache[MCP_IODIR] &= ~mask; - status = mcp_write(mcp, MCP_IODIR, mcp->cache[MCP_IODIR]); + status = mcp_set_mask(mcp, MCP_IODIR, mask, false); } mutex_unlock(&mcp->lock); return status; @@ -270,7 +451,7 @@ mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value) static irqreturn_t mcp23s08_irq(int irq, void *data) { struct mcp23s08 *mcp = data; - int intcap, intf, i, gpio, gpio_orig, intcap_mask; + int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval; unsigned int child_irq; bool intf_set, intcap_changed, gpio_bit_changed, defval_changed, gpio_set; @@ -281,25 +462,31 @@ static irqreturn_t mcp23s08_irq(int irq, void *data) return IRQ_HANDLED; } - mcp->cache[MCP_INTF] = intf; - if (mcp_read(mcp, MCP_INTCAP, &intcap) < 0) { mutex_unlock(&mcp->lock); return IRQ_HANDLED; } - mcp->cache[MCP_INTCAP] = intcap; + if (mcp_read(mcp, MCP_INTCON, &intcon) < 0) { + mutex_unlock(&mcp->lock); + return IRQ_HANDLED; + } + + if (mcp_read(mcp, MCP_DEFVAL, &defval) < 0) { + mutex_unlock(&mcp->lock); + return IRQ_HANDLED; + } /* This clears the interrupt(configurable on S18) */ if (mcp_read(mcp, MCP_GPIO, &gpio) < 0) { mutex_unlock(&mcp->lock); return IRQ_HANDLED; } - gpio_orig = mcp->cache[MCP_GPIO]; - mcp->cache[MCP_GPIO] = gpio; + gpio_orig = mcp->cached_gpio; + mcp->cached_gpio = gpio; mutex_unlock(&mcp->lock); - if (mcp->cache[MCP_INTF] == 0) { + if (intf == 0) { /* There is no interrupt pending */ return IRQ_HANDLED; } @@ -327,7 +514,7 @@ static irqreturn_t mcp23s08_irq(int irq, void *data) * to see if the input has changed. */ - intf_set = BIT(i) & mcp->cache[MCP_INTF]; + intf_set = intf & BIT(i); if (i < 8 && intf_set) intcap_mask = 0x00FF; else if (i >= 8 && intf_set) @@ -336,14 +523,14 @@ static irqreturn_t mcp23s08_irq(int irq, void *data) intcap_mask = 0x00; intcap_changed = (intcap_mask & - (BIT(i) & mcp->cache[MCP_INTCAP])) != + (intcap & BIT(i))) != (intcap_mask & (BIT(i) & gpio_orig)); - gpio_set = BIT(i) & mcp->cache[MCP_GPIO]; + gpio_set = BIT(i) & gpio; gpio_bit_changed = (BIT(i) & gpio_orig) != - (BIT(i) & mcp->cache[MCP_GPIO]); - defval_changed = (BIT(i) & mcp->cache[MCP_INTCON]) && - ((BIT(i) & mcp->cache[MCP_GPIO]) != - (BIT(i) & mcp->cache[MCP_DEFVAL])); + (BIT(i) & gpio); + defval_changed = (BIT(i) & intcon) && + ((BIT(i) & gpio) != + (BIT(i) & defval)); if (((gpio_bit_changed || intcap_changed) && (BIT(i) & mcp->irq_rise) && gpio_set) || @@ -364,7 +551,7 @@ static void mcp23s08_irq_mask(struct irq_data *data) struct mcp23s08 *mcp = gpiochip_get_data(gc); unsigned int pos = data->hwirq; - mcp->cache[MCP_GPINTEN] &= ~BIT(pos); + mcp_set_bit(mcp, MCP_GPINTEN, pos, false); } static void mcp23s08_irq_unmask(struct irq_data *data) @@ -373,7 +560,7 @@ static void mcp23s08_irq_unmask(struct irq_data *data) struct mcp23s08 *mcp = gpiochip_get_data(gc); unsigned int pos = data->hwirq; - mcp->cache[MCP_GPINTEN] |= BIT(pos); + mcp_set_bit(mcp, MCP_GPINTEN, pos, true); } static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) @@ -384,23 +571,23 @@ static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) int status = 0; if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { - mcp->cache[MCP_INTCON] &= ~BIT(pos); + mcp_set_bit(mcp, MCP_INTCON, pos, false); mcp->irq_rise |= BIT(pos); mcp->irq_fall |= BIT(pos); } else if (type & IRQ_TYPE_EDGE_RISING) { - mcp->cache[MCP_INTCON] &= ~BIT(pos); + mcp_set_bit(mcp, MCP_INTCON, pos, false); mcp->irq_rise |= BIT(pos); mcp->irq_fall &= ~BIT(pos); } else if (type & IRQ_TYPE_EDGE_FALLING) { - mcp->cache[MCP_INTCON] &= ~BIT(pos); + mcp_set_bit(mcp, MCP_INTCON, pos, false); mcp->irq_rise &= ~BIT(pos); mcp->irq_fall |= BIT(pos); } else if (type & IRQ_TYPE_LEVEL_HIGH) { - mcp->cache[MCP_INTCON] |= BIT(pos); - mcp->cache[MCP_DEFVAL] &= ~BIT(pos); + mcp_set_bit(mcp, MCP_INTCON, pos, true); + mcp_set_bit(mcp, MCP_DEFVAL, pos, false); } else if (type & IRQ_TYPE_LEVEL_LOW) { - mcp->cache[MCP_INTCON] |= BIT(pos); - mcp->cache[MCP_DEFVAL] |= BIT(pos); + mcp_set_bit(mcp, MCP_INTCON, pos, true); + mcp_set_bit(mcp, MCP_DEFVAL, pos, true); } else return -EINVAL; @@ -412,7 +599,8 @@ static void mcp23s08_irq_bus_lock(struct irq_data *data) struct gpio_chip *gc = irq_data_get_irq_chip_data(data); struct mcp23s08 *mcp = gpiochip_get_data(gc); - mutex_lock(&mcp->irq_lock); + mutex_lock(&mcp->lock); + regcache_cache_only(mcp->regmap, true); } static void mcp23s08_irq_bus_unlock(struct irq_data *data) @@ -420,12 +608,10 @@ static void mcp23s08_irq_bus_unlock(struct irq_data *data) struct gpio_chip *gc = irq_data_get_irq_chip_data(data); struct mcp23s08 *mcp = gpiochip_get_data(gc); - mutex_lock(&mcp->lock); - mcp_write(mcp, MCP_GPINTEN, mcp->cache[MCP_GPINTEN]); - mcp_write(mcp, MCP_DEFVAL, mcp->cache[MCP_DEFVAL]); - mcp_write(mcp, MCP_INTCON, mcp->cache[MCP_INTCON]); + regcache_cache_only(mcp->regmap, false); + regcache_sync(mcp->regmap); + mutex_unlock(&mcp->lock); - mutex_unlock(&mcp->irq_lock); } static struct irq_chip mcp23s08_irq_chip = { @@ -443,8 +629,6 @@ static int mcp23s08_irq_setup(struct mcp23s08 *mcp) int err; unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED; - mutex_init(&mcp->irq_lock); - if (mcp->irq_active_high) irqflags |= IRQF_TRIGGER_HIGH; else @@ -484,6 +668,47 @@ static int mcp23s08_irq_setup(struct mcp23s08 *mcp) #include <linux/seq_file.h> /* + * This compares the chip's registers with the register + * cache and corrects any incorrectly set register. This + * can be used to fix state for MCP23xxx, that temporary + * lost its power supply. + */ +#define MCP23S08_CONFIG_REGS 8 +static int __check_mcp23s08_reg_cache(struct mcp23s08 *mcp) +{ + int cached[MCP23S08_CONFIG_REGS]; + int err = 0, i; + + /* read cached config registers */ + for (i = 0; i < MCP23S08_CONFIG_REGS; i++) { + err = mcp_read(mcp, i, &cached[i]); + if (err) + goto out; + } + + regcache_cache_bypass(mcp->regmap, true); + + for (i = 0; i < MCP23S08_CONFIG_REGS; i++) { + int uncached; + err = mcp_read(mcp, i, &uncached); + if (err) + goto out; + + if (uncached != cached[i]) { + dev_err(mcp->dev, "restoring reg 0x%02x from 0x%04x to 0x%04x (power-loss?)\n", + i, uncached, cached[i]); + mcp_write(mcp, i, cached[i]); + } + } + +out: + if (err) + dev_err(mcp->dev, "read error: reg=%02x, err=%d", i, err); + regcache_cache_bypass(mcp->regmap, false); + return err; +} + +/* * This shows more info than the generic gpio dump code: * pullups, deglitching, open drain drive. */ @@ -493,6 +718,7 @@ static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip) char bank; int t; unsigned mask; + int iodir, gpio, gppu; mcp = gpiochip_get_data(chip); @@ -500,14 +726,30 @@ static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip) bank = '0' + ((mcp->addr >> 1) & 0x7); mutex_lock(&mcp->lock); - t = mcp_update_cache(mcp); - if (t < 0) { - seq_printf(s, " I/O ERROR %d\n", t); + + t = __check_mcp23s08_reg_cache(mcp); + if (t) { + seq_printf(s, " I/O Error\n"); + goto done; + } + t = mcp_read(mcp, MCP_IODIR, &iodir); + if (t) { + seq_printf(s, " I/O Error\n"); + goto done; + } + t = mcp_read(mcp, MCP_GPIO, &gpio); + if (t) { + seq_printf(s, " I/O Error\n"); + goto done; + } + t = mcp_read(mcp, MCP_GPPU, &gppu); + if (t) { + seq_printf(s, " I/O Error\n"); goto done; } - for (t = 0, mask = 1; t < chip->ngpio; t++, mask <<= 1) { - const char *label; + for (t = 0, mask = BIT(0); t < chip->ngpio; t++, mask <<= 1) { + const char *label; label = gpiochip_is_requested(chip, t); if (!label) @@ -515,9 +757,9 @@ static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip) seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s", chip->base + t, bank, t, label, - (mcp->cache[MCP_IODIR] & mask) ? "in " : "out", - (mcp->cache[MCP_GPIO] & mask) ? "hi" : "lo", - (mcp->cache[MCP_GPPU] & mask) ? "up" : " "); + (iodir & mask) ? "in " : "out", + (gpio & mask) ? "hi" : "lo", + (gppu & mask) ? "up" : " "); /* NOTE: ignoring the irq-related registers */ seq_puts(s, "\n"); } @@ -533,7 +775,7 @@ done: static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, void *data, unsigned addr, unsigned type, - struct mcp23s08_platform_data *pdata, int cs) + unsigned int base, int cs) { int status, ret; bool mirror = false; @@ -605,7 +847,7 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, if (IS_ERR(mcp->regmap)) return PTR_ERR(mcp->regmap); - mcp->chip.base = pdata->base; + mcp->chip.base = base; mcp->chip.can_sleep = true; mcp->chip.parent = dev; mcp->chip.owner = THIS_MODULE; @@ -618,13 +860,14 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, if (ret < 0) goto fail; - mcp->irq_controller = pdata->irq_controller; + mcp->irq_controller = + device_property_read_bool(dev, "interrupt-controller"); if (mcp->irq && mcp->irq_controller) { mcp->irq_active_high = - of_property_read_bool(mcp->chip.parent->of_node, + device_property_read_bool(dev, "microchip,irq-active-high"); - mirror = pdata->mirror; + mirror = device_property_read_bool(dev, "microchip,irq-mirror"); } if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror || @@ -648,32 +891,7 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, goto fail; } - /* configure ~100K pullups */ - ret = mcp_write(mcp, MCP_GPPU, pdata->chip[cs].pullups); - if (ret < 0) - goto fail; - - ret = mcp_update_cache(mcp); - if (ret < 0) - goto fail; - - /* disable inverter on input */ - if (mcp->cache[MCP_IPOL] != 0) { - mcp->cache[MCP_IPOL] = 0; - ret = mcp_write(mcp, MCP_IPOL, 0); - if (ret < 0) - goto fail; - } - - /* disable irqs */ - if (mcp->cache[MCP_GPINTEN] != 0) { - mcp->cache[MCP_GPINTEN] = 0; - ret = mcp_write(mcp, MCP_GPINTEN, 0); - if (ret < 0) - goto fail; - } - - ret = gpiochip_add_data(&mcp->chip, mcp); + ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp); if (ret < 0) goto fail; @@ -682,6 +900,23 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, if (ret) goto fail; } + + mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; + mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; + mcp->pinctrl_desc.confops = &mcp_pinconf_ops; + mcp->pinctrl_desc.npins = mcp->chip.ngpio; + if (mcp->pinctrl_desc.npins == 8) + mcp->pinctrl_desc.pins = mcp23x08_pins; + else if (mcp->pinctrl_desc.npins == 16) + mcp->pinctrl_desc.pins = mcp23x17_pins; + mcp->pinctrl_desc.owner = THIS_MODULE; + + mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp); + if (IS_ERR(mcp->pctldev)) { + ret = PTR_ERR(mcp->pctldev); + goto fail; + } + fail: if (ret < 0) dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret); @@ -753,60 +988,26 @@ static int mcp230xx_probe(struct i2c_client *client, struct mcp23s08_platform_data *pdata, local_pdata; struct mcp23s08 *mcp; int status; - const struct of_device_id *match; - match = of_match_device(of_match_ptr(mcp23s08_i2c_of_match), - &client->dev); - if (match) { + pdata = dev_get_platdata(&client->dev); + if (!pdata) { pdata = &local_pdata; pdata->base = -1; - pdata->chip[0].pullups = 0; - pdata->irq_controller = of_property_read_bool( - client->dev.of_node, - "interrupt-controller"); - pdata->mirror = of_property_read_bool(client->dev.of_node, - "microchip,irq-mirror"); - client->irq = irq_of_parse_and_map(client->dev.of_node, 0); - } else { - pdata = dev_get_platdata(&client->dev); - if (!pdata) { - pdata = devm_kzalloc(&client->dev, - sizeof(struct mcp23s08_platform_data), - GFP_KERNEL); - if (!pdata) - return -ENOMEM; - pdata->base = -1; - } } - mcp = kzalloc(sizeof(*mcp), GFP_KERNEL); + mcp = devm_kzalloc(&client->dev, sizeof(*mcp), GFP_KERNEL); if (!mcp) return -ENOMEM; mcp->irq = client->irq; status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, - id->driver_data, pdata, 0); + id->driver_data, pdata->base, 0); if (status) - goto fail; + return status; i2c_set_clientdata(client, mcp); return 0; - -fail: - kfree(mcp); - - return status; -} - -static int mcp230xx_remove(struct i2c_client *client) -{ - struct mcp23s08 *mcp = i2c_get_clientdata(client); - - gpiochip_remove(&mcp->chip); - kfree(mcp); - - return 0; } static const struct i2c_device_id mcp230xx_id[] = { @@ -822,7 +1023,6 @@ static struct i2c_driver mcp230xx_driver = { .of_match_table = of_match_ptr(mcp23s08_i2c_of_match), }, .probe = mcp230xx_probe, - .remove = mcp230xx_remove, .id_table = mcp230xx_id, }; @@ -856,60 +1056,40 @@ static int mcp23s08_probe(struct spi_device *spi) int status, type; unsigned ngpio = 0; const struct of_device_id *match; - u32 spi_present_mask = 0; match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); - if (match) { + if (match) type = (int)(uintptr_t)match->data; - status = of_property_read_u32(spi->dev.of_node, - "microchip,spi-present-mask", &spi_present_mask); + else + type = spi_get_device_id(spi)->driver_data; + + pdata = dev_get_platdata(&spi->dev); + if (!pdata) { + pdata = &local_pdata; + pdata->base = -1; + + status = device_property_read_u32(&spi->dev, + "microchip,spi-present-mask", &pdata->spi_present_mask); if (status) { - status = of_property_read_u32(spi->dev.of_node, - "mcp,spi-present-mask", &spi_present_mask); + status = device_property_read_u32(&spi->dev, + "mcp,spi-present-mask", + &pdata->spi_present_mask); + if (status) { - dev_err(&spi->dev, - "DT has no spi-present-mask\n"); + dev_err(&spi->dev, "missing spi-present-mask"); return -ENODEV; } } - if ((spi_present_mask <= 0) || (spi_present_mask >= 256)) { - dev_err(&spi->dev, "invalid spi-present-mask\n"); - return -ENODEV; - } + } - pdata = &local_pdata; - pdata->base = -1; - for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { - pdata->chip[addr].pullups = 0; - if (spi_present_mask & (1 << addr)) - chips++; - } - pdata->irq_controller = of_property_read_bool( - spi->dev.of_node, - "interrupt-controller"); - pdata->mirror = of_property_read_bool(spi->dev.of_node, - "microchip,irq-mirror"); - } else { - type = spi_get_device_id(spi)->driver_data; - pdata = dev_get_platdata(&spi->dev); - if (!pdata) { - pdata = devm_kzalloc(&spi->dev, - sizeof(struct mcp23s08_platform_data), - GFP_KERNEL); - pdata->base = -1; - } + if (!pdata->spi_present_mask || pdata->spi_present_mask > 0xff) { + dev_err(&spi->dev, "invalid spi-present-mask"); + return -ENODEV; + } - for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { - if (!pdata->chip[addr].is_present) - continue; + for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { + if (pdata->spi_present_mask & BIT(addr)) chips++; - if ((type == MCP_TYPE_S08) && (addr > 3)) { - dev_err(&spi->dev, - "mcp23s08 only supports address 0..3\n"); - return -EINVAL; - } - spi_present_mask |= 1 << addr; - } } if (!chips) @@ -923,19 +1103,17 @@ static int mcp23s08_probe(struct spi_device *spi) spi_set_drvdata(spi, data); - spi->irq = irq_of_parse_and_map(spi->dev.of_node, 0); - - for (addr = 0; addr < ARRAY_SIZE(pdata->chip); addr++) { - if (!(spi_present_mask & (1 << addr))) + for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { + if (!(pdata->spi_present_mask & BIT(addr))) continue; chips--; data->mcp[addr] = &data->chip[chips]; data->mcp[addr]->irq = spi->irq; status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, - 0x40 | (addr << 1), type, pdata, - addr); + 0x40 | (addr << 1), type, + pdata->base, addr); if (status < 0) - goto fail; + return status; if (pdata->base != -1) pdata->base += data->mcp[addr]->chip.ngpio; @@ -943,36 +1121,6 @@ static int mcp23s08_probe(struct spi_device *spi) } data->ngpio = ngpio; - /* NOTE: these chips have a relatively sane IRQ framework, with - * per-signal masking and level/edge triggering. It's not yet - * handled here... - */ - - return 0; - -fail: - for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) { - - if (!data->mcp[addr]) - continue; - gpiochip_remove(&data->mcp[addr]->chip); - } - return status; -} - -static int mcp23s08_remove(struct spi_device *spi) -{ - struct mcp23s08_driver_data *data = spi_get_drvdata(spi); - unsigned addr; - - for (addr = 0; addr < ARRAY_SIZE(data->mcp); addr++) { - - if (!data->mcp[addr]) - continue; - - gpiochip_remove(&data->mcp[addr]->chip); - } - return 0; } @@ -986,7 +1134,6 @@ MODULE_DEVICE_TABLE(spi, mcp23s08_ids); static struct spi_driver mcp23s08_driver = { .probe = mcp23s08_probe, - .remove = mcp23s08_remove, .id_table = mcp23s08_ids, .driver = { .name = "mcp23s08", diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 9dd981ddbb17..e831647c56a6 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -143,6 +143,7 @@ struct rockchip_drv { * @gpio_chip: gpiolib chip * @grange: gpio range * @slock: spinlock for the gpio bank + * @route_mask: bits describing the routing pins of per bank */ struct rockchip_pin_bank { void __iomem *reg_base; @@ -165,6 +166,7 @@ struct rockchip_pin_bank { struct pinctrl_gpio_range grange; raw_spinlock_t slock; u32 toggle_edge_mode; + u32 route_mask; }; #define PIN_BANK(id, pins, label) \ @@ -288,6 +290,22 @@ struct rockchip_pin_bank { } /** + * struct rockchip_mux_recalced_data: represent a pin iomux data. + * @bank_num: bank number. + * @pin: index at register or used to calc index. + * @func: the min pin. + * @route_offset: the max pin. + * @route_val: the register offset. + */ +struct rockchip_mux_route_data { + u8 bank_num; + u8 pin; + u8 func; + u32 route_offset; + u32 route_val; +}; + +/** */ struct rockchip_pin_ctrl { struct rockchip_pin_bank *pin_banks; @@ -299,6 +317,8 @@ struct rockchip_pin_ctrl { int pmu_mux_offset; int grf_drv_offset; int pmu_drv_offset; + struct rockchip_mux_route_data *iomux_routes; + u32 niomux_routes; void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num, struct regmap **regmap, @@ -580,6 +600,280 @@ static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg, *bit = data->bit; } +static struct rockchip_mux_route_data rk3228_mux_route_data[] = { + { + /* pwm0-0 */ + .bank_num = 0, + .pin = 26, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16), + }, { + /* pwm0-1 */ + .bank_num = 3, + .pin = 21, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16) | BIT(0), + }, { + /* pwm1-0 */ + .bank_num = 0, + .pin = 27, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16 + 1), + }, { + /* pwm1-1 */ + .bank_num = 0, + .pin = 30, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 1) | BIT(1), + }, { + /* pwm2-0 */ + .bank_num = 0, + .pin = 28, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16 + 2), + }, { + /* pwm2-1 */ + .bank_num = 1, + .pin = 12, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 2) | BIT(2), + }, { + /* pwm3-0 */ + .bank_num = 3, + .pin = 26, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16 + 3), + }, { + /* pwm3-1 */ + .bank_num = 1, + .pin = 11, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 3) | BIT(3), + }, { + /* sdio-0_d0 */ + .bank_num = 1, + .pin = 1, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16 + 4), + }, { + /* sdio-1_d0 */ + .bank_num = 3, + .pin = 2, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16 + 4) | BIT(4), + }, { + /* spi-0_rx */ + .bank_num = 0, + .pin = 13, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 5), + }, { + /* spi-1_rx */ + .bank_num = 2, + .pin = 0, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 5) | BIT(5), + }, { + /* emmc-0_cmd */ + .bank_num = 1, + .pin = 22, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 7), + }, { + /* emmc-1_cmd */ + .bank_num = 2, + .pin = 4, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 7) | BIT(7), + }, { + /* uart2-0_rx */ + .bank_num = 1, + .pin = 19, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 8), + }, { + /* uart2-1_rx */ + .bank_num = 1, + .pin = 10, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 8) | BIT(8), + }, { + /* uart1-0_rx */ + .bank_num = 1, + .pin = 10, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16 + 11), + }, { + /* uart1-1_rx */ + .bank_num = 3, + .pin = 13, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16 + 11) | BIT(11), + }, +}; + +static struct rockchip_mux_route_data rk3328_mux_route_data[] = { + { + /* uart2dbg_rxm0 */ + .bank_num = 1, + .pin = 1, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16) | BIT(16 + 1), + }, { + /* uart2dbg_rxm1 */ + .bank_num = 2, + .pin = 1, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16) | BIT(16 + 1) | BIT(0), + }, { + /* gmac-m1-optimized_rxd0 */ + .bank_num = 1, + .pin = 11, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 2) | BIT(16 + 10) | BIT(2) | BIT(10), + }, { + /* pdm_sdi0m0 */ + .bank_num = 2, + .pin = 19, + .func = 2, + .route_offset = 0x50, + .route_val = BIT(16 + 3), + }, { + /* pdm_sdi0m1 */ + .bank_num = 1, + .pin = 23, + .func = 3, + .route_offset = 0x50, + .route_val = BIT(16 + 3) | BIT(3), + }, { + /* spi_rxdm2 */ + .bank_num = 3, + .pin = 2, + .func = 4, + .route_offset = 0x50, + .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5), + }, { + /* i2s2_sdim0 */ + .bank_num = 1, + .pin = 24, + .func = 1, + .route_offset = 0x50, + .route_val = BIT(16 + 6), + }, { + /* i2s2_sdim1 */ + .bank_num = 3, + .pin = 2, + .func = 6, + .route_offset = 0x50, + .route_val = BIT(16 + 6) | BIT(6), + }, { + /* card_iom1 */ + .bank_num = 2, + .pin = 22, + .func = 3, + .route_offset = 0x50, + .route_val = BIT(16 + 7) | BIT(7), + }, { + /* tsp_d5m1 */ + .bank_num = 2, + .pin = 16, + .func = 3, + .route_offset = 0x50, + .route_val = BIT(16 + 8) | BIT(8), + }, { + /* cif_data5m1 */ + .bank_num = 2, + .pin = 16, + .func = 4, + .route_offset = 0x50, + .route_val = BIT(16 + 9) | BIT(9), + }, +}; + +static struct rockchip_mux_route_data rk3399_mux_route_data[] = { + { + /* uart2dbga_rx */ + .bank_num = 4, + .pin = 8, + .func = 2, + .route_offset = 0xe21c, + .route_val = BIT(16 + 10) | BIT(16 + 11), + }, { + /* uart2dbgb_rx */ + .bank_num = 4, + .pin = 16, + .func = 2, + .route_offset = 0xe21c, + .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10), + }, { + /* uart2dbgc_rx */ + .bank_num = 4, + .pin = 19, + .func = 1, + .route_offset = 0xe21c, + .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11), + }, { + /* pcie_clkreqn */ + .bank_num = 2, + .pin = 26, + .func = 2, + .route_offset = 0xe21c, + .route_val = BIT(16 + 14), + }, { + /* pcie_clkreqnb */ + .bank_num = 4, + .pin = 24, + .func = 1, + .route_offset = 0xe21c, + .route_val = BIT(16 + 14) | BIT(14), + }, +}; + +static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, + int mux, u32 *reg, u32 *value) +{ + struct rockchip_pinctrl *info = bank->drvdata; + struct rockchip_pin_ctrl *ctrl = info->ctrl; + struct rockchip_mux_route_data *data; + int i; + + for (i = 0; i < ctrl->niomux_routes; i++) { + data = &ctrl->iomux_routes[i]; + if ((data->bank_num == bank->bank_num) && + (data->pin == pin) && (data->func == mux)) + break; + } + + if (i >= ctrl->niomux_routes) + return false; + + *reg = data->route_offset; + *value = data->route_val; + + return true; +} + static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) { struct rockchip_pinctrl *info = bank->drvdata; @@ -678,7 +972,7 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct regmap *regmap; int reg, ret, mask, mux_type; u8 bit; - u32 data, rmask; + u32 data, rmask, route_reg, route_val; ret = rockchip_verify_mux(bank, pin, mux); if (ret < 0) @@ -714,6 +1008,15 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED)) ctrl->iomux_recalc(bank->bank_num, pin, ®, &bit, &mask); + if (bank->route_mask & BIT(pin)) { + if (rockchip_get_mux_route(bank, pin, mux, &route_reg, + &route_val)) { + ret = regmap_write(regmap, route_reg, route_val); + if (ret) + return ret; + } + } + data = (mask << (bit + 16)); rmask = data | (data >> 16); data |= (mux & mask) << bit; @@ -2549,6 +2852,16 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( bank_pins += 8; } + + /* calculate the per-bank route_mask */ + for (j = 0; j < ctrl->niomux_routes; j++) { + int pin = 0; + + if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { + pin = ctrl->iomux_routes[j].pin; + bank->route_mask |= BIT(pin); + } + } } return ctrl; @@ -2799,6 +3112,8 @@ static struct rockchip_pin_ctrl rk3228_pin_ctrl = { .label = "RK3228-GPIO", .type = RK3288, .grf_mux_offset = 0x0, + .iomux_routes = rk3228_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data), .pull_calc_reg = rk3228_calc_pull_reg_and_bit, .drv_calc_reg = rk3228_calc_drv_reg_and_bit, }; @@ -2866,6 +3181,8 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = { .label = "RK3328-GPIO", .type = RK3288, .grf_mux_offset = 0x0, + .iomux_routes = rk3328_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data), .pull_calc_reg = rk3228_calc_pull_reg_and_bit, .drv_calc_reg = rk3228_calc_drv_reg_and_bit, .iomux_recalc = rk3328_recalc_mux, @@ -2956,33 +3273,35 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = { .pmu_mux_offset = 0x0, .grf_drv_offset = 0xe100, .pmu_drv_offset = 0x80, + .iomux_routes = rk3399_mux_route_data, + .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data), .pull_calc_reg = rk3399_calc_pull_reg_and_bit, .drv_calc_reg = rk3399_calc_drv_reg_and_bit, }; static const struct of_device_id rockchip_pinctrl_dt_match[] = { { .compatible = "rockchip,rv1108-pinctrl", - .data = (void *)&rv1108_pin_ctrl }, + .data = &rv1108_pin_ctrl }, { .compatible = "rockchip,rk2928-pinctrl", - .data = (void *)&rk2928_pin_ctrl }, + .data = &rk2928_pin_ctrl }, { .compatible = "rockchip,rk3036-pinctrl", - .data = (void *)&rk3036_pin_ctrl }, + .data = &rk3036_pin_ctrl }, { .compatible = "rockchip,rk3066a-pinctrl", - .data = (void *)&rk3066a_pin_ctrl }, + .data = &rk3066a_pin_ctrl }, { .compatible = "rockchip,rk3066b-pinctrl", - .data = (void *)&rk3066b_pin_ctrl }, + .data = &rk3066b_pin_ctrl }, { .compatible = "rockchip,rk3188-pinctrl", - .data = (void *)&rk3188_pin_ctrl }, + .data = &rk3188_pin_ctrl }, { .compatible = "rockchip,rk3228-pinctrl", - .data = (void *)&rk3228_pin_ctrl }, + .data = &rk3228_pin_ctrl }, { .compatible = "rockchip,rk3288-pinctrl", - .data = (void *)&rk3288_pin_ctrl }, + .data = &rk3288_pin_ctrl }, { .compatible = "rockchip,rk3328-pinctrl", - .data = (void *)&rk3328_pin_ctrl }, + .data = &rk3328_pin_ctrl }, { .compatible = "rockchip,rk3368-pinctrl", - .data = (void *)&rk3368_pin_ctrl }, + .data = &rk3368_pin_ctrl }, { .compatible = "rockchip,rk3399-pinctrl", - .data = (void *)&rk3399_pin_ctrl }, + .data = &rk3399_pin_ctrl }, {}, }; diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c new file mode 100644 index 000000000000..dc164da10446 --- /dev/null +++ b/drivers/pinctrl/pinctrl-rza1.c @@ -0,0 +1,1308 @@ +/* + * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC + * + * Copyright (C) 2017 Jacopo Mondi + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/* + * This pin controller/gpio combined driver supports Renesas devices of RZ/A1 + * family. + * This includes SoCs which are sub- or super- sets of this particular line, + * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020). + */ + +#include <linux/bitops.h> +#include <linux/err.h> +#include <linux/gpio/driver.h> +#include <linux/init.h> +#include <linux/ioport.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/slab.h> + +#include "core.h" +#include "devicetree.h" +#include "pinconf.h" +#include "pinmux.h" + +#define DRIVER_NAME "pinctrl-rza1" + +#define RZA1_P_REG 0x0000 +#define RZA1_PPR_REG 0x0200 +#define RZA1_PM_REG 0x0300 +#define RZA1_PMC_REG 0x0400 +#define RZA1_PFC_REG 0x0500 +#define RZA1_PFCE_REG 0x0600 +#define RZA1_PFCEA_REG 0x0a00 +#define RZA1_PIBC_REG 0x4000 +#define RZA1_PBDC_REG 0x4100 +#define RZA1_PIPC_REG 0x4200 + +#define RZA1_ADDR(mem, reg, port) ((mem) + (reg) + ((port) * 4)) + +#define RZA1_NPORTS 12 +#define RZA1_PINS_PER_PORT 16 +#define RZA1_NPINS (RZA1_PINS_PER_PORT * RZA1_NPORTS) +#define RZA1_PIN_ID_TO_PORT(id) ((id) / RZA1_PINS_PER_PORT) +#define RZA1_PIN_ID_TO_PIN(id) ((id) % RZA1_PINS_PER_PORT) + +/* + * Use 16 lower bits [15:0] for pin identifier + * Use 16 higher bits [31:16] for pin mux function + */ +#define MUX_PIN_ID_MASK GENMASK(15, 0) +#define MUX_FUNC_MASK GENMASK(31, 16) + +#define MUX_FUNC_OFFS 16 +#define MUX_FUNC(pinconf) \ + ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) +#define MUX_FUNC_PFC_MASK BIT(0) +#define MUX_FUNC_PFCE_MASK BIT(1) +#define MUX_FUNC_PFCEA_MASK BIT(2) + +/* Pin mux flags */ +#define MUX_FLAGS_BIDIR BIT(0) +#define MUX_FLAGS_SWIO_INPUT BIT(1) +#define MUX_FLAGS_SWIO_OUTPUT BIT(2) + +/* ---------------------------------------------------------------------------- + * RZ/A1 pinmux flags + */ + +/** + * rza1_bidir_pin - describe a single pin that needs bidir flag applied. + */ +struct rza1_bidir_pin { + u8 pin: 4; + u8 func: 4; +}; + +/** + * rza1_bidir_entry - describe a list of pins that needs bidir flag applied. + * Each struct rza1_bidir_entry describes a port. + */ +struct rza1_bidir_entry { + const unsigned int npins; + const struct rza1_bidir_pin *pins; +}; + +/** + * rza1_swio_pin - describe a single pin that needs bidir flag applied. + */ +struct rza1_swio_pin { + u16 pin: 4; + u16 port: 4; + u16 func: 4; + u16 input: 1; +}; + +/** + * rza1_swio_entry - describe a list of pins that needs swio flag applied + */ +struct rza1_swio_entry { + const unsigned int npins; + const struct rza1_swio_pin *pins; +}; + +/** + * rza1_pinmux_conf - group together bidir and swio pinmux flag tables + */ +struct rza1_pinmux_conf { + const struct rza1_bidir_entry *bidir_entries; + const struct rza1_swio_entry *swio_entries; +}; + +/* ---------------------------------------------------------------------------- + * RZ/A1H (r7s72100) pinmux flags + */ + +static const struct rza1_bidir_pin rza1h_bidir_pins_p1[] = { + { .pin = 0, .func = 1 }, + { .pin = 1, .func = 1 }, + { .pin = 2, .func = 1 }, + { .pin = 3, .func = 1 }, + { .pin = 4, .func = 1 }, + { .pin = 5, .func = 1 }, + { .pin = 6, .func = 1 }, + { .pin = 7, .func = 1 }, +}; + +static const struct rza1_bidir_pin rza1h_bidir_pins_p2[] = { + { .pin = 0, .func = 1 }, + { .pin = 1, .func = 1 }, + { .pin = 2, .func = 1 }, + { .pin = 3, .func = 1 }, + { .pin = 4, .func = 1 }, + { .pin = 0, .func = 4 }, + { .pin = 1, .func = 4 }, + { .pin = 2, .func = 4 }, + { .pin = 3, .func = 4 }, + { .pin = 5, .func = 1 }, + { .pin = 6, .func = 1 }, + { .pin = 7, .func = 1 }, + { .pin = 8, .func = 1 }, + { .pin = 9, .func = 1 }, + { .pin = 10, .func = 1 }, + { .pin = 11, .func = 1 }, + { .pin = 12, .func = 1 }, + { .pin = 13, .func = 1 }, + { .pin = 14, .func = 1 }, + { .pin = 15, .func = 1 }, + { .pin = 12, .func = 4 }, + { .pin = 13, .func = 4 }, + { .pin = 14, .func = 4 }, + { .pin = 15, .func = 4 }, +}; + +static const struct rza1_bidir_pin rza1h_bidir_pins_p3[] = { + { .pin = 3, .func = 2 }, + { .pin = 10, .func = 7 }, + { .pin = 11, .func = 7 }, + { .pin = 13, .func = 7 }, + { .pin = 14, .func = 7 }, + { .pin = 15, .func = 7 }, + { .pin = 10, .func = 8 }, + { .pin = 11, .func = 8 }, + { .pin = 13, .func = 8 }, + { .pin = 14, .func = 8 }, + { .pin = 15, .func = 8 }, +}; + +static const struct rza1_bidir_pin rza1h_bidir_pins_p4[] = { + { .pin = 0, .func = 8 }, + { .pin = 1, .func = 8 }, + { .pin = 2, .func = 8 }, + { .pin = 3, .func = 8 }, + { .pin = 10, .func = 3 }, + { .pin = 11, .func = 3 }, + { .pin = 13, .func = 3 }, + { .pin = 14, .func = 3 }, + { .pin = 15, .func = 3 }, + { .pin = 10, .func = 4 }, + { .pin = 11, .func = 4 }, + { .pin = 13, .func = 4 }, + { .pin = 14, .func = 4 }, + { .pin = 15, .func = 4 }, + { .pin = 12, .func = 5 }, + { .pin = 13, .func = 5 }, + { .pin = 14, .func = 5 }, + { .pin = 15, .func = 5 }, +}; + +static const struct rza1_bidir_pin rza1h_bidir_pins_p6[] = { + { .pin = 0, .func = 1 }, + { .pin = 1, .func = 1 }, + { .pin = 2, .func = 1 }, + { .pin = 3, .func = 1 }, + { .pin = 4, .func = 1 }, + { .pin = 5, .func = 1 }, + { .pin = 6, .func = 1 }, + { .pin = 7, .func = 1 }, + { .pin = 8, .func = 1 }, + { .pin = 9, .func = 1 }, + { .pin = 10, .func = 1 }, + { .pin = 11, .func = 1 }, + { .pin = 12, .func = 1 }, + { .pin = 13, .func = 1 }, + { .pin = 14, .func = 1 }, + { .pin = 15, .func = 1 }, +}; + +static const struct rza1_bidir_pin rza1h_bidir_pins_p7[] = { + { .pin = 13, .func = 3 }, +}; + +static const struct rza1_bidir_pin rza1h_bidir_pins_p8[] = { + { .pin = 8, .func = 3 }, + { .pin = 9, .func = 3 }, + { .pin = 10, .func = 3 }, + { .pin = 11, .func = 3 }, + { .pin = 14, .func = 2 }, + { .pin = 15, .func = 2 }, + { .pin = 14, .func = 3 }, + { .pin = 15, .func = 3 }, +}; + +static const struct rza1_bidir_pin rza1h_bidir_pins_p9[] = { + { .pin = 0, .func = 2 }, + { .pin = 1, .func = 2 }, + { .pin = 4, .func = 2 }, + { .pin = 5, .func = 2 }, + { .pin = 6, .func = 2 }, + { .pin = 7, .func = 2 }, +}; + +static const struct rza1_bidir_pin rza1h_bidir_pins_p11[] = { + { .pin = 6, .func = 2 }, + { .pin = 7, .func = 2 }, + { .pin = 9, .func = 2 }, + { .pin = 6, .func = 4 }, + { .pin = 7, .func = 4 }, + { .pin = 9, .func = 4 }, + { .pin = 10, .func = 2 }, + { .pin = 11, .func = 2 }, + { .pin = 10, .func = 4 }, + { .pin = 11, .func = 4 }, + { .pin = 12, .func = 4 }, + { .pin = 13, .func = 4 }, + { .pin = 14, .func = 4 }, + { .pin = 15, .func = 4 }, +}; + +static const struct rza1_swio_pin rza1h_swio_pins[] = { + { .port = 2, .pin = 7, .func = 4, .input = 0 }, + { .port = 2, .pin = 11, .func = 4, .input = 0 }, + { .port = 3, .pin = 7, .func = 3, .input = 0 }, + { .port = 3, .pin = 7, .func = 8, .input = 0 }, + { .port = 4, .pin = 7, .func = 5, .input = 0 }, + { .port = 4, .pin = 7, .func = 11, .input = 0 }, + { .port = 4, .pin = 15, .func = 6, .input = 0 }, + { .port = 5, .pin = 0, .func = 1, .input = 1 }, + { .port = 5, .pin = 1, .func = 1, .input = 1 }, + { .port = 5, .pin = 2, .func = 1, .input = 1 }, + { .port = 5, .pin = 3, .func = 1, .input = 1 }, + { .port = 5, .pin = 4, .func = 1, .input = 1 }, + { .port = 5, .pin = 5, .func = 1, .input = 1 }, + { .port = 5, .pin = 6, .func = 1, .input = 1 }, + { .port = 5, .pin = 7, .func = 1, .input = 1 }, + { .port = 7, .pin = 4, .func = 6, .input = 0 }, + { .port = 7, .pin = 11, .func = 2, .input = 0 }, + { .port = 8, .pin = 10, .func = 8, .input = 0 }, + { .port = 10, .pin = 15, .func = 2, .input = 0 }, +}; + +static const struct rza1_bidir_entry rza1h_bidir_entries[RZA1_NPORTS] = { + [1] = { ARRAY_SIZE(rza1h_bidir_pins_p1), rza1h_bidir_pins_p1 }, + [2] = { ARRAY_SIZE(rza1h_bidir_pins_p2), rza1h_bidir_pins_p2 }, + [3] = { ARRAY_SIZE(rza1h_bidir_pins_p3), rza1h_bidir_pins_p3 }, + [4] = { ARRAY_SIZE(rza1h_bidir_pins_p4), rza1h_bidir_pins_p4 }, + [6] = { ARRAY_SIZE(rza1h_bidir_pins_p6), rza1h_bidir_pins_p6 }, + [7] = { ARRAY_SIZE(rza1h_bidir_pins_p7), rza1h_bidir_pins_p7 }, + [8] = { ARRAY_SIZE(rza1h_bidir_pins_p8), rza1h_bidir_pins_p8 }, + [9] = { ARRAY_SIZE(rza1h_bidir_pins_p9), rza1h_bidir_pins_p9 }, + [11] = { ARRAY_SIZE(rza1h_bidir_pins_p11), rza1h_bidir_pins_p11 }, +}; + +static const struct rza1_swio_entry rza1h_swio_entries[] = { + [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins }, +}; + +/* RZ/A1H (r7s72100x) pinmux flags table */ +static const struct rza1_pinmux_conf rza1h_pmx_conf = { + .bidir_entries = rza1h_bidir_entries, + .swio_entries = rza1h_swio_entries, +}; + +/* ---------------------------------------------------------------------------- + * RZ/A1 types + */ +/** + * rza1_mux_conf - describes a pin multiplexing operation + * + * @id: the pin identifier from 0 to RZA1_NPINS + * @port: the port where pin sits on + * @pin: pin id + * @mux_func: alternate function id number + * @mux_flags: alternate function flags + * @value: output value to set the pin to + */ +struct rza1_mux_conf { + u16 id; + u8 port; + u8 pin; + u8 mux_func; + u8 mux_flags; + u8 value; +}; + +/** + * rza1_port - describes a pin port + * + * This is mostly useful to lock register writes per-bank and not globally. + * + * @lock: protect access to HW registers + * @id: port number + * @base: logical address base + * @pins: pins sitting on this port + */ +struct rza1_port { + spinlock_t lock; + unsigned int id; + void __iomem *base; + struct pinctrl_pin_desc *pins; +}; + +/** + * rza1_pinctrl - RZ pincontroller device + * + * @dev: parent device structure + * @mutex: protect [pinctrl|pinmux]_generic functions + * @base: logical address base + * @nports: number of pin controller ports + * @ports: pin controller banks + * @pins: pin array for pinctrl core + * @desc: pincontroller desc for pinctrl core + * @pctl: pinctrl device + * @data: device specific data + */ +struct rza1_pinctrl { + struct device *dev; + + struct mutex mutex; + + void __iomem *base; + + unsigned int nport; + struct rza1_port *ports; + + struct pinctrl_pin_desc *pins; + struct pinctrl_desc desc; + struct pinctrl_dev *pctl; + + const void *data; +}; + +/* ---------------------------------------------------------------------------- + * RZ/A1 pinmux flags + */ +static inline bool rza1_pinmux_get_bidir(unsigned int port, + unsigned int pin, + unsigned int func, + const struct rza1_bidir_entry *table) +{ + const struct rza1_bidir_entry *entry = &table[port]; + const struct rza1_bidir_pin *bidir_pin; + unsigned int i; + + for (i = 0; i < entry->npins; ++i) { + bidir_pin = &entry->pins[i]; + if (bidir_pin->pin == pin && bidir_pin->func == func) + return true; + } + + return false; +} + +static inline int rza1_pinmux_get_swio(unsigned int port, + unsigned int pin, + unsigned int func, + const struct rza1_swio_entry *table) +{ + const struct rza1_swio_pin *swio_pin; + unsigned int i; + + + for (i = 0; i < table->npins; ++i) { + swio_pin = &table->pins[i]; + if (swio_pin->port == port && swio_pin->pin == pin && + swio_pin->func == func) + return swio_pin->input; + } + + return -ENOENT; +} + +/** + * rza1_pinmux_get_flags() - return pinmux flags associated to a pin + */ +static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin, + unsigned int func, + struct rza1_pinctrl *rza1_pctl) + +{ + const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data; + const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries; + const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries; + unsigned int pmx_flags = 0; + int ret; + + if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries)) + pmx_flags |= MUX_FLAGS_BIDIR; + + ret = rza1_pinmux_get_swio(port, pin, func, swio_entries); + if (ret == 0) + pmx_flags |= MUX_FLAGS_SWIO_OUTPUT; + else if (ret > 0) + pmx_flags |= MUX_FLAGS_SWIO_INPUT; + + return pmx_flags; +} + +/* ---------------------------------------------------------------------------- + * RZ/A1 SoC operations + */ + +/** + * rza1_set_bit() - un-locked set/clear a single bit in pin configuration + * registers + */ +static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg, + unsigned int bit, bool set) +{ + void __iomem *mem = RZA1_ADDR(port->base, reg, port->id); + u16 val = ioread16(mem); + + if (set) + val |= BIT(bit); + else + val &= ~BIT(bit); + + iowrite16(val, mem); +} + +static inline unsigned int rza1_get_bit(struct rza1_port *port, + unsigned int reg, unsigned int bit) +{ + void __iomem *mem = RZA1_ADDR(port->base, reg, port->id); + + return ioread16(mem) & BIT(bit); +} + +/** + * rza1_pin_reset() - reset a pin to default initial state + * + * Reset pin state disabling input buffer and bi-directional control, + * and configure it as input port. + * Note that pin is now configured with direction as input but with input + * buffer disabled. This implies the pin value cannot be read in this state. + * + * @port: port where pin sits on + * @pin: pin offset + */ +static void rza1_pin_reset(struct rza1_port *port, unsigned int pin) +{ + unsigned long irqflags; + + spin_lock_irqsave(&port->lock, irqflags); + rza1_set_bit(port, RZA1_PIBC_REG, pin, 0); + rza1_set_bit(port, RZA1_PBDC_REG, pin, 0); + + rza1_set_bit(port, RZA1_PM_REG, pin, 1); + rza1_set_bit(port, RZA1_PMC_REG, pin, 0); + rza1_set_bit(port, RZA1_PIPC_REG, pin, 0); + spin_unlock_irqrestore(&port->lock, irqflags); +} + +static inline int rza1_pin_get_direction(struct rza1_port *port, + unsigned int pin) +{ + unsigned long irqflags; + int input; + + spin_lock_irqsave(&port->lock, irqflags); + input = rza1_get_bit(port, RZA1_PM_REG, pin); + spin_unlock_irqrestore(&port->lock, irqflags); + + return !!input; +} + +/** + * rza1_pin_set_direction() - set I/O direction on a pin in port mode + * + * When running in output port mode keep PBDC enabled to allow reading the + * pin value from PPR. + * + * @port: port where pin sits on + * @pin: pin offset + * @input: input enable/disable flag + */ +static inline void rza1_pin_set_direction(struct rza1_port *port, + unsigned int pin, bool input) +{ + unsigned long irqflags; + + spin_lock_irqsave(&port->lock, irqflags); + + rza1_set_bit(port, RZA1_PIBC_REG, pin, 1); + if (input) { + rza1_set_bit(port, RZA1_PM_REG, pin, 1); + rza1_set_bit(port, RZA1_PBDC_REG, pin, 0); + } else { + rza1_set_bit(port, RZA1_PM_REG, pin, 0); + rza1_set_bit(port, RZA1_PBDC_REG, pin, 1); + } + + spin_unlock_irqrestore(&port->lock, irqflags); +} + +static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin, + unsigned int value) +{ + unsigned long irqflags; + + spin_lock_irqsave(&port->lock, irqflags); + rza1_set_bit(port, RZA1_P_REG, pin, !!value); + spin_unlock_irqrestore(&port->lock, irqflags); +} + +static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin) +{ + unsigned long irqflags; + int val; + + spin_lock_irqsave(&port->lock, irqflags); + val = rza1_get_bit(port, RZA1_PPR_REG, pin); + spin_unlock_irqrestore(&port->lock, irqflags); + + return val; +} + +/** + * rza1_pin_mux_single() - configure pin multiplexing on a single pin + * + * @pinctrl: RZ/A1 pin controller device + * @mux_conf: pin multiplexing descriptor + */ +static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl, + struct rza1_mux_conf *mux_conf) +{ + struct rza1_port *port = &rza1_pctl->ports[mux_conf->port]; + unsigned int pin = mux_conf->pin; + u8 mux_func = mux_conf->mux_func; + u8 mux_flags = mux_conf->mux_flags; + u8 mux_flags_from_table; + + rza1_pin_reset(port, pin); + + /* SWIO pinmux flags coming from DT are high precedence */ + mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func, + rza1_pctl); + if (mux_flags) + mux_flags |= (mux_flags_from_table & MUX_FLAGS_BIDIR); + else + mux_flags = mux_flags_from_table; + + if (mux_flags & MUX_FLAGS_BIDIR) + rza1_set_bit(port, RZA1_PBDC_REG, pin, 1); + + /* + * Enable alternate function mode and select it. + * + * Be careful here: the pin mux sub-nodes in device tree + * enumerate alternate functions from 1 to 8; + * subtract 1 before using macros to match registers configuration + * which expects numbers from 0 to 7 instead. + * + * ---------------------------------------------------- + * Alternate mode selection table: + * + * PMC PFC PFCE PFCAE (mux_func - 1) + * 1 0 0 0 0 + * 1 1 0 0 1 + * 1 0 1 0 2 + * 1 1 1 0 3 + * 1 0 0 1 4 + * 1 1 0 1 5 + * 1 0 1 1 6 + * 1 1 1 1 7 + * ---------------------------------------------------- + */ + mux_func -= 1; + rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK); + rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK); + rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK); + + /* + * All alternate functions except a few need PIPCn = 1. + * If PIPCn has to stay disabled (SW IO mode), configure PMn according + * to I/O direction specified by pin configuration -after- PMC has been + * set to one. + */ + if (mux_flags & (MUX_FLAGS_SWIO_INPUT | MUX_FLAGS_SWIO_OUTPUT)) + rza1_set_bit(port, RZA1_PM_REG, pin, + mux_flags & MUX_FLAGS_SWIO_INPUT); + else + rza1_set_bit(port, RZA1_PIPC_REG, pin, 1); + + rza1_set_bit(port, RZA1_PMC_REG, pin, 1); + + return 0; +} + +/* ---------------------------------------------------------------------------- + * gpio operations + */ + +/** + * rza1_gpio_request() - configure pin in port mode + * + * Configure a pin as gpio (port mode). + * After reset, the pin is in input mode with input buffer disabled. + * To use the pin as input or output, set_direction shall be called first + * + * @chip: gpio chip where the gpio sits on + * @gpio: gpio offset + */ +static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio) +{ + struct rza1_port *port = gpiochip_get_data(chip); + + rza1_pin_reset(port, gpio); + + return 0; +} + +/** + * rza1_gpio_disable_free() - reset a pin + * + * Surprisingly, disable_free a gpio, is equivalent to request it. + * Reset pin to port mode, with input buffer disabled. This overwrites all + * port direction settings applied with set_direction + * + * @chip: gpio chip where the gpio sits on + * @gpio: gpio offset + */ +static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio) +{ + struct rza1_port *port = gpiochip_get_data(chip); + + rza1_pin_reset(port, gpio); +} + +static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) +{ + struct rza1_port *port = gpiochip_get_data(chip); + + return rza1_pin_get_direction(port, gpio); +} + +static int rza1_gpio_direction_input(struct gpio_chip *chip, + unsigned int gpio) +{ + struct rza1_port *port = gpiochip_get_data(chip); + + rza1_pin_set_direction(port, gpio, true); + + return 0; +} + +static int rza1_gpio_direction_output(struct gpio_chip *chip, + unsigned int gpio, + int value) +{ + struct rza1_port *port = gpiochip_get_data(chip); + + /* Set value before driving pin direction */ + rza1_pin_set(port, gpio, value); + rza1_pin_set_direction(port, gpio, false); + + return 0; +} + +/** + * rza1_gpio_get() - read a gpio pin value + * + * Read gpio pin value through PPR register. + * Requires bi-directional mode to work when reading the value of a pin + * in output mode + * + * @chip: gpio chip where the gpio sits on + * @gpio: gpio offset + */ +static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio) +{ + struct rza1_port *port = gpiochip_get_data(chip); + + return rza1_pin_get(port, gpio); +} + +static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio, + int value) +{ + struct rza1_port *port = gpiochip_get_data(chip); + + rza1_pin_set(port, gpio, value); +} + +static struct gpio_chip rza1_gpiochip_template = { + .request = rza1_gpio_request, + .free = rza1_gpio_free, + .get_direction = rza1_gpio_get_direction, + .direction_input = rza1_gpio_direction_input, + .direction_output = rza1_gpio_direction_output, + .get = rza1_gpio_get, + .set = rza1_gpio_set, +}; +/* ---------------------------------------------------------------------------- + * pinctrl operations + */ + +/** + * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its + * children sub-nodes + * + * @np: device tree node to parse + */ +static int rza1_dt_node_pin_count(struct device_node *np) +{ + struct device_node *child; + struct property *of_pins; + unsigned int npins; + + of_pins = of_find_property(np, "pinmux", NULL); + if (of_pins) + return of_pins->length / sizeof(u32); + + npins = 0; + for_each_child_of_node(np, child) { + of_pins = of_find_property(child, "pinmux", NULL); + if (!of_pins) + return -EINVAL; + + npins += of_pins->length / sizeof(u32); + } + + return npins; +} + +/** + * rza1_parse_pmx_function() - parse a pin mux sub-node + * + * @rza1_pctl: RZ/A1 pin controller device + * @np: of pmx sub-node + * @mux_confs: array of pin mux configurations to fill with parsed info + * @grpins: array of pin ids to mux + */ +static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl, + struct device_node *np, + struct rza1_mux_conf *mux_confs, + unsigned int *grpins) +{ + struct pinctrl_dev *pctldev = rza1_pctl->pctl; + char const *prop_name = "pinmux"; + unsigned long *pin_configs; + unsigned int npin_configs; + struct property *of_pins; + unsigned int npins; + u8 pinmux_flags; + unsigned int i; + int ret; + + of_pins = of_find_property(np, prop_name, NULL); + if (!of_pins) { + dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name); + return -ENOENT; + } + npins = of_pins->length / sizeof(u32); + + /* + * Collect pin configuration properties: they apply to all pins in + * this sub-node + */ + ret = pinconf_generic_parse_dt_config(np, pctldev, &pin_configs, + &npin_configs); + if (ret) { + dev_err(rza1_pctl->dev, + "Unable to parse pin configuration options for %s\n", + np->name); + return ret; + } + + /* + * Create a mask with pinmux flags from pin configuration; + * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction + * specified in device tree. + */ + pinmux_flags = 0; + for (i = 0; i < npin_configs && pinmux_flags == 0; i++) + switch (pinconf_to_config_param(pin_configs[i])) { + case PIN_CONFIG_INPUT_ENABLE: + pinmux_flags |= MUX_FLAGS_SWIO_INPUT; + break; + case PIN_CONFIG_OUTPUT: + pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT; + default: + break; + + } + + kfree(pin_configs); + + /* Collect pin positions and their mux settings. */ + for (i = 0; i < npins; ++i) { + u32 of_pinconf; + struct rza1_mux_conf *mux_conf = &mux_confs[i]; + + ret = of_property_read_u32_index(np, prop_name, i, &of_pinconf); + if (ret) + return ret; + + mux_conf->id = of_pinconf & MUX_PIN_ID_MASK; + mux_conf->port = RZA1_PIN_ID_TO_PORT(mux_conf->id); + mux_conf->pin = RZA1_PIN_ID_TO_PIN(mux_conf->id); + mux_conf->mux_func = MUX_FUNC(of_pinconf); + mux_conf->mux_flags = pinmux_flags; + + if (mux_conf->port >= RZA1_NPORTS || + mux_conf->pin >= RZA1_PINS_PER_PORT) { + dev_err(rza1_pctl->dev, + "Wrong port %u pin %u for %s property\n", + mux_conf->port, mux_conf->pin, prop_name); + return -EINVAL; + } + + grpins[i] = mux_conf->id; + } + + return npins; +} + +/** + * rza1_dt_node_to_map() - map a pin mux node to a function/group + * + * Parse and register a pin mux function. + * + * @pctldev: pin controller device + * @np: device tree node to parse + * @map: pointer to pin map (output) + * @num_maps: number of collected maps (output) + */ +static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np, + struct pinctrl_map **map, + unsigned int *num_maps) +{ + struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev); + struct rza1_mux_conf *mux_confs, *mux_conf; + unsigned int *grpins, *grpin; + struct device_node *child; + const char *grpname; + const char **fngrps; + int ret, npins; + + npins = rza1_dt_node_pin_count(np); + if (npins < 0) { + dev_err(rza1_pctl->dev, "invalid pinmux node structure\n"); + return -EINVAL; + } + + /* + * Functions are made of 1 group only; + * in fact, functions and groups are identical for this pin controller + * except that functions carry an array of per-pin mux configuration + * settings. + */ + mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs), + GFP_KERNEL); + grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins), + GFP_KERNEL); + fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL); + + if (!mux_confs || !grpins || !fngrps) + return -ENOMEM; + + /* + * Parse the pinmux node. + * If the node does not contain "pinmux" property (-ENOENT) + * that property shall be specified in all its children sub-nodes. + */ + mux_conf = &mux_confs[0]; + grpin = &grpins[0]; + + ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin); + if (ret == -ENOENT) + for_each_child_of_node(np, child) { + ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf, + grpin); + if (ret < 0) + return ret; + + grpin += ret; + mux_conf += ret; + } + else if (ret < 0) + return ret; + + /* Register pin group and function name to pinctrl_generic */ + grpname = np->name; + fngrps[0] = grpname; + + mutex_lock(&rza1_pctl->mutex); + ret = pinctrl_generic_add_group(pctldev, grpname, grpins, npins, + NULL); + if (ret) { + mutex_unlock(&rza1_pctl->mutex); + return ret; + } + + ret = pinmux_generic_add_function(pctldev, grpname, fngrps, 1, + mux_confs); + if (ret) + goto remove_group; + mutex_unlock(&rza1_pctl->mutex); + + dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n", + grpname, npins); + + /* Create map where to retrieve function and mux settings from */ + *num_maps = 0; + *map = kzalloc(sizeof(**map), GFP_KERNEL); + if (!*map) { + ret = -ENOMEM; + goto remove_function; + } + + (*map)->type = PIN_MAP_TYPE_MUX_GROUP; + (*map)->data.mux.group = np->name; + (*map)->data.mux.function = np->name; + *num_maps = 1; + + return 0; + +remove_function: + mutex_lock(&rza1_pctl->mutex); + pinmux_generic_remove_last_function(pctldev); + +remove_group: + pinctrl_generic_remove_last_group(pctldev); + mutex_unlock(&rza1_pctl->mutex); + + dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n", + grpname); + + return ret; +} + +static void rza1_dt_free_map(struct pinctrl_dev *pctldev, + struct pinctrl_map *map, unsigned int num_maps) +{ + kfree(map); +} + +static const struct pinctrl_ops rza1_pinctrl_ops = { + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, + .dt_node_to_map = rza1_dt_node_to_map, + .dt_free_map = rza1_dt_free_map, +}; + +/* ---------------------------------------------------------------------------- + * pinmux operations + */ + +/** + * rza1_set_mux() - retrieve pins from a group and apply their mux settings + * + * @pctldev: pin controller device + * @selector: function selector + * @group: group selector + */ +static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, + unsigned int group) +{ + struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev); + struct rza1_mux_conf *mux_confs; + struct function_desc *func; + struct group_desc *grp; + int i; + + grp = pinctrl_generic_get_group(pctldev, group); + if (!grp) + return -EINVAL; + + func = pinmux_generic_get_function(pctldev, selector); + if (!func) + return -EINVAL; + + mux_confs = (struct rza1_mux_conf *)func->data; + for (i = 0; i < grp->num_pins; ++i) { + int ret; + + ret = rza1_pin_mux_single(rza1_pctl, &mux_confs[i]); + if (ret) + return ret; + } + + return 0; +} + +static struct pinmux_ops rza1_pinmux_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = rza1_set_mux, + .strict = true, +}; + +/* ---------------------------------------------------------------------------- + * RZ/A1 pin controller driver operations + */ + +static unsigned int rza1_count_gpio_chips(struct device_node *np) +{ + struct device_node *child; + unsigned int count = 0; + + for_each_child_of_node(np, child) { + if (!of_property_read_bool(child, "gpio-controller")) + continue; + + count++; + } + + return count; +} + +/** + * rza1_parse_gpiochip() - parse and register a gpio chip and pin range + * + * The gpio controller subnode shall provide a "gpio-ranges" list property as + * defined by gpio device tree binding documentation. + * + * @rza1_pctl: RZ/A1 pin controller device + * @np: of gpio-controller node + * @chip: gpio chip to register to gpiolib + * @range: pin range to register to pinctrl core + */ +static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl, + struct device_node *np, + struct gpio_chip *chip, + struct pinctrl_gpio_range *range) +{ + const char *list_name = "gpio-ranges"; + struct of_phandle_args of_args; + unsigned int gpioport; + u32 pinctrl_base; + int ret; + + ret = of_parse_phandle_with_fixed_args(np, list_name, 3, 0, &of_args); + if (ret) { + dev_err(rza1_pctl->dev, "Unable to parse %s list property\n", + list_name); + return ret; + } + + /* + * Find out on which port this gpio-chip maps to by inspecting the + * second argument of the "gpio-ranges" property. + */ + pinctrl_base = of_args.args[1]; + gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base); + if (gpioport > RZA1_NPORTS) { + dev_err(rza1_pctl->dev, + "Invalid values in property %s\n", list_name); + return -EINVAL; + } + + *chip = rza1_gpiochip_template; + chip->base = -1; + chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%s-%u", + np->name, gpioport); + chip->ngpio = of_args.args[2]; + chip->of_node = np; + chip->parent = rza1_pctl->dev; + + range->id = gpioport; + range->name = chip->label; + range->pin_base = range->base = pinctrl_base; + range->npins = of_args.args[2]; + range->gc = chip; + + ret = devm_gpiochip_add_data(rza1_pctl->dev, chip, + &rza1_pctl->ports[gpioport]); + if (ret) + return ret; + + pinctrl_add_gpio_range(rza1_pctl->pctl, range); + + dev_info(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n", + chip->label, chip->ngpio); + + return 0; +} + +/** + * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges + * + * @rza1_pctl: RZ/A1 pin controller device + */ +static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl) +{ + struct device_node *np = rza1_pctl->dev->of_node; + struct pinctrl_gpio_range *gpio_ranges; + struct gpio_chip *gpio_chips; + struct device_node *child; + unsigned int ngpiochips; + unsigned int i; + int ret; + + ngpiochips = rza1_count_gpio_chips(np); + if (ngpiochips == 0) { + dev_dbg(rza1_pctl->dev, "No gpiochip registered\n"); + return 0; + } + + gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips, + sizeof(*gpio_chips), GFP_KERNEL); + gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips, + sizeof(*gpio_ranges), GFP_KERNEL); + if (!gpio_chips || !gpio_ranges) + return -ENOMEM; + + i = 0; + for_each_child_of_node(np, child) { + if (!of_property_read_bool(child, "gpio-controller")) + continue; + + ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i], + &gpio_ranges[i]); + if (ret) + goto gpiochip_remove; + + ++i; + } + + dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i); + + return 0; + +gpiochip_remove: + for (; i > 0; i--) + devm_gpiochip_remove(rza1_pctl->dev, &gpio_chips[i - 1]); + + return ret; +} + +/** + * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register + * them to pinctrl and gpio cores. + * + * @rza1_pctl: RZ/A1 pin controller device + */ +static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl) +{ + struct pinctrl_pin_desc *pins; + struct rza1_port *ports; + unsigned int i; + int ret; + + pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins), + GFP_KERNEL); + ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports), + GFP_KERNEL); + if (!pins || !ports) + return -ENOMEM; + + rza1_pctl->pins = pins; + rza1_pctl->desc.pins = pins; + rza1_pctl->desc.npins = RZA1_NPINS; + rza1_pctl->ports = ports; + + for (i = 0; i < RZA1_NPINS; ++i) { + unsigned int pin = RZA1_PIN_ID_TO_PIN(i); + unsigned int port = RZA1_PIN_ID_TO_PORT(i); + + pins[i].number = i; + pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, + "P%u-%u", port, pin); + + if (i % RZA1_PINS_PER_PORT == 0) { + /* + * Setup ports; + * they provide per-port lock and logical base address. + */ + unsigned int port_id = RZA1_PIN_ID_TO_PORT(i); + + ports[port_id].id = port_id; + ports[port_id].base = rza1_pctl->base; + ports[port_id].pins = &pins[i]; + spin_lock_init(&ports[port_id].lock); + } + } + + ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc, + rza1_pctl, &rza1_pctl->pctl); + if (ret) { + dev_err(rza1_pctl->dev, + "RZ/A1 pin controller registration failed\n"); + return ret; + } + + ret = pinctrl_enable(rza1_pctl->pctl); + if (ret) { + dev_err(rza1_pctl->dev, + "RZ/A1 pin controller failed to start\n"); + return ret; + } + + ret = rza1_gpio_register(rza1_pctl); + if (ret) { + dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n"); + return ret; + } + + return 0; +} + +static int rza1_pinctrl_probe(struct platform_device *pdev) +{ + struct rza1_pinctrl *rza1_pctl; + struct resource *res; + int ret; + + rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL); + if (!rza1_pctl) + return -ENOMEM; + + rza1_pctl->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + rza1_pctl->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(rza1_pctl->base)) + return PTR_ERR(rza1_pctl->base); + + mutex_init(&rza1_pctl->mutex); + + platform_set_drvdata(pdev, rza1_pctl); + + rza1_pctl->desc.name = DRIVER_NAME; + rza1_pctl->desc.pctlops = &rza1_pinctrl_ops; + rza1_pctl->desc.pmxops = &rza1_pinmux_ops; + rza1_pctl->desc.owner = THIS_MODULE; + rza1_pctl->data = of_device_get_match_data(&pdev->dev); + + ret = rza1_pinctrl_register(rza1_pctl); + if (ret) + return ret; + + dev_info(&pdev->dev, + "RZ/A1 pin controller and gpio successfully registered\n"); + + return 0; +} + +static const struct of_device_id rza1_pinctrl_of_match[] = { + { + .compatible = "renesas,r7s72100-ports", + .data = &rza1h_pmx_conf, + }, + { } +}; + +static struct platform_driver rza1_pinctrl_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = rza1_pinctrl_of_match, + }, + .probe = rza1_pinctrl_probe, +}; + +static int __init rza1_pinctrl_init(void) +{ + return platform_driver_register(&rza1_pinctrl_driver); +} +core_initcall(rza1_pinctrl_init); + +MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org"); +MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 9c267dcda094..b8b3d932cd73 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1270,8 +1270,6 @@ static void pcs_free_resources(struct pcs_device *pcs) #endif } -static const struct of_device_id pcs_of_match[]; - static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs) { const char *propname = "pinctrl-single,gpio-range"; @@ -1637,15 +1635,14 @@ static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs, static int pcs_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; - const struct of_device_id *match; struct pcs_pdata *pdata; struct resource *res; struct pcs_device *pcs; const struct pcs_soc_data *soc; int ret; - match = of_match_device(pcs_of_match, &pdev->dev); - if (!match) + soc = of_device_get_match_data(&pdev->dev); + if (WARN_ON(!soc)) return -EINVAL; pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); @@ -1658,7 +1655,6 @@ static int pcs_probe(struct platform_device *pdev) raw_spin_lock_init(&pcs->lock); mutex_init(&pcs->mutex); INIT_LIST_HEAD(&pcs->gpiofuncs); - soc = match->data; pcs->flags = soc->flags; memcpy(&pcs->socdata, soc, sizeof(*soc)); diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c index d4167e2c173a..f9e98a7d4f0c 100644 --- a/drivers/pinctrl/pinctrl-xway.c +++ b/drivers/pinctrl/pinctrl-xway.c @@ -1028,7 +1028,7 @@ static const struct ltq_pin_group xrx200_grps[] = { GRP_MUX("spi_cs5", SPI, xrx200_pins_spi_cs5), GRP_MUX("spi_cs6", SPI, xrx200_pins_spi_cs6), GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_rx), - GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_tx), + GRP_MUX("usif uart_tx", USIF, xrx200_pins_usif_uart_tx), GRP_MUX("usif uart_rts", USIF, xrx200_pins_usif_uart_rts), GRP_MUX("usif uart_cts", USIF, xrx200_pins_usif_uart_cts), GRP_MUX("usif uart_dtr", USIF, xrx200_pins_usif_uart_dtr), diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 3ebdc01f53c0..9e504dbc7fb5 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -39,6 +39,16 @@ config PINCTRL_IPQ8064 This is the pinctrl, pinmux, pinconf and gpiolib driver for the Qualcomm TLMM block found in the Qualcomm IPQ8064 platform. +config PINCTRL_IPQ8074 + tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for + the Qualcomm Technologies Inc. TLMM block found on the + Qualcomm Technologies Inc. IPQ8074 platform. Select this for + IPQ8074. + config PINCTRL_MSM8660 tristate "Qualcomm 8660 pin controller driver" depends on GPIOLIB && OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index ab47764dbc5c..06c8b2ace05f 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o +obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o diff --git a/drivers/pinctrl/qcom/pinctrl-ipq8074.c b/drivers/pinctrl/qcom/pinctrl-ipq8074.c new file mode 100644 index 000000000000..10fb076e2456 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-ipq8074.c @@ -0,0 +1,1076 @@ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_SIZE 0x1000 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = 0x4 + REG_SIZE * id, \ + .intr_cfg_reg = 0x8 + REG_SIZE * id, \ + .intr_status_reg = 0xc + REG_SIZE * id, \ + .intr_target_reg = 0x8 + REG_SIZE * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +static const struct pinctrl_pin_desc ipq8074_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); + +enum ipq8074_functions { + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_audio_rxbclk, + msm_mux_audio_rxd, + msm_mux_audio_rxfsync, + msm_mux_audio_rxmclk, + msm_mux_audio_txbclk, + msm_mux_audio_txd, + msm_mux_audio_txfsync, + msm_mux_audio_txmclk, + msm_mux_blsp0_i2c, + msm_mux_blsp0_spi, + msm_mux_blsp0_uart, + msm_mux_blsp1_i2c, + msm_mux_blsp1_spi, + msm_mux_blsp1_uart, + msm_mux_blsp2_i2c, + msm_mux_blsp2_spi, + msm_mux_blsp2_uart, + msm_mux_blsp3_i2c, + msm_mux_blsp3_spi, + msm_mux_blsp3_spi0, + msm_mux_blsp3_spi1, + msm_mux_blsp3_spi2, + msm_mux_blsp3_spi3, + msm_mux_blsp3_uart, + msm_mux_blsp4_i2c0, + msm_mux_blsp4_i2c1, + msm_mux_blsp4_spi0, + msm_mux_blsp4_spi1, + msm_mux_blsp4_uart0, + msm_mux_blsp4_uart1, + msm_mux_blsp5_i2c, + msm_mux_blsp5_spi, + msm_mux_blsp5_uart, + msm_mux_burn0, + msm_mux_burn1, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_cxc0, + msm_mux_cxc1, + msm_mux_dbg_out, + msm_mux_gcc_plltest, + msm_mux_gcc_tlmm, + msm_mux_gpio, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_led0, + msm_mux_led1, + msm_mux_led2, + msm_mux_mac0_sa0, + msm_mux_mac0_sa1, + msm_mux_mac1_sa0, + msm_mux_mac1_sa1, + msm_mux_mac1_sa2, + msm_mux_mac1_sa3, + msm_mux_mac2_sa0, + msm_mux_mac2_sa1, + msm_mux_mdc, + msm_mux_mdio, + msm_mux_pcie0_clk, + msm_mux_pcie0_rst, + msm_mux_pcie0_wake, + msm_mux_pcie1_clk, + msm_mux_pcie1_rst, + msm_mux_pcie1_wake, + msm_mux_pcm_drx, + msm_mux_pcm_dtx, + msm_mux_pcm_fsync, + msm_mux_pcm_pclk, + msm_mux_pcm_zsi0, + msm_mux_pcm_zsi1, + msm_mux_prng_rosc, + msm_mux_pta1_0, + msm_mux_pta1_1, + msm_mux_pta1_2, + msm_mux_pta2_0, + msm_mux_pta2_1, + msm_mux_pta2_2, + msm_mux_pwm0, + msm_mux_pwm1, + msm_mux_pwm2, + msm_mux_pwm3, + msm_mux_qdss_cti_trig_in_a0, + msm_mux_qdss_cti_trig_in_a1, + msm_mux_qdss_cti_trig_in_b0, + msm_mux_qdss_cti_trig_in_b1, + msm_mux_qdss_cti_trig_out_a0, + msm_mux_qdss_cti_trig_out_a1, + msm_mux_qdss_cti_trig_out_b0, + msm_mux_qdss_cti_trig_out_b1, + msm_mux_qdss_traceclk_a, + msm_mux_qdss_traceclk_b, + msm_mux_qdss_tracectl_a, + msm_mux_qdss_tracectl_b, + msm_mux_qdss_tracedata_a, + msm_mux_qdss_tracedata_b, + msm_mux_qpic, + msm_mux_rx0, + msm_mux_rx1, + msm_mux_rx2, + msm_mux_sd_card, + msm_mux_sd_write, + msm_mux_tsens_max, + msm_mux_wci2a, + msm_mux_wci2b, + msm_mux_wci2c, + msm_mux_wci2d, + msm_mux_NA, +}; + +static const char * const qpic_groups[] = { + "gpio0", /* LCD_TE */ + "gpio1", /* BUSY_N */ + "gpio2", /* LCD_RS_N */ + "gpio3", /* WE_N */ + "gpio4", /* OE_N */ + "gpio5", /* DATA[0] */ + "gpio6", /* DATA[1] */ + "gpio7", /* DATA[2] */ + "gpio8", /* DATA[3] */ + "gpio9", /* CS_CSR_LCD */ + "gpio10", /* CLE */ + "gpio11", /* NAND_CS_N */ + "gpio12", /* DATA[4] */ + "gpio13", /* DATA[5] */ + "gpio14", /* DATA[6] */ + "gpio15", /* DATA[7] */ + "gpio16", /* DATA[8] */ + "gpio17", /* ALE */ +}; + +static const char * const blsp5_i2c_groups[] = { + "gpio0", "gpio2", +}; + +static const char * const blsp5_spi_groups[] = { + "gpio0", "gpio2", "gpio9", "gpio16", +}; + +static const char * const wci2a_groups[] = { + "gpio0", "gpio2", +}; + +static const char * const blsp3_spi3_groups[] = { + "gpio0", "gpio2", "gpio9", +}; + +static const char * const burn0_groups[] = { + "gpio0", +}; + +static const char * const pcm_zsi0_groups[] = { + "gpio1", +}; + +static const char * const blsp5_uart_groups[] = { + "gpio0", "gpio2", "gpio9", "gpio16", +}; + +static const char * const mac1_sa2_groups[] = { + "gpio1", "gpio11", +}; + +static const char * const blsp3_spi0_groups[] = { + "gpio1", "gpio3", "gpio4", +}; + +static const char * const burn1_groups[] = { + "gpio1", +}; + +static const char * const mac0_sa1_groups[] = { + "gpio3", "gpio4", +}; + +static const char * const qdss_cti_trig_out_b0_groups[] = { + "gpio3", +}; + +static const char * const qdss_cti_trig_in_b0_groups[] = { + "gpio4", +}; + +static const char * const blsp4_uart0_groups[] = { + "gpio5", "gpio6", "gpio7", "gpio8", +}; + +static const char * const blsp4_i2c0_groups[] = { + "gpio5", "gpio6", +}; + +static const char * const blsp4_spi0_groups[] = { + "gpio5", "gpio6", "gpio7", "gpio8", +}; + +static const char * const mac2_sa1_groups[] = { + "gpio5", "gpio6", +}; + +static const char * const qdss_cti_trig_out_b1_groups[] = { + "gpio5", +}; + +static const char * const qdss_cti_trig_in_b1_groups[] = { + "gpio6", +}; + +static const char * const cxc0_groups[] = { + "gpio9", "gpio16", +}; + +static const char * const mac1_sa3_groups[] = { + "gpio9", "gpio16", +}; + +static const char * const qdss_cti_trig_in_a1_groups[] = { + "gpio9", +}; + +static const char * const qdss_cti_trig_out_a1_groups[] = { + "gpio10", +}; + +static const char * const wci2c_groups[] = { + "gpio11", "gpio17", +}; + +static const char * const qdss_cti_trig_in_a0_groups[] = { + "gpio11", +}; + +static const char * const qdss_cti_trig_out_a0_groups[] = { + "gpio12", +}; + +static const char * const qdss_traceclk_b_groups[] = { + "gpio14", +}; + +static const char * const qdss_tracectl_b_groups[] = { + "gpio15", +}; + +static const char * const pcm_zsi1_groups[] = { + "gpio16", +}; + +static const char * const qdss_tracedata_b_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", + "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", +}; + +static const char * const led0_groups[] = { + "gpio18", +}; + +static const char * const pwm0_groups[] = { + "gpio18", "gpio21", "gpio25", "gpio29", "gpio63", +}; + +static const char * const led1_groups[] = { + "gpio19", +}; + +static const char * const pwm1_groups[] = { + "gpio19", "gpio22", "gpio26", "gpio30", "gpio64", +}; + +static const char * const led2_groups[] = { + "gpio20", +}; + +static const char * const pwm2_groups[] = { + "gpio20", "gpio23", "gpio27", "gpio31", "gpio66", +}; + +static const char * const blsp4_uart1_groups[] = { + "gpio21", "gpio22", "gpio23", "gpio24", +}; + +static const char * const blsp4_i2c1_groups[] = { + "gpio21", "gpio22", +}; + +static const char * const blsp4_spi1_groups[] = { + "gpio21", "gpio22", "gpio23", "gpio24", +}; + +static const char * const wci2d_groups[] = { + "gpio21", "gpio22", +}; + +static const char * const mac1_sa1_groups[] = { + "gpio21", "gpio22", +}; + +static const char * const blsp3_spi2_groups[] = { + "gpio21", "gpio22", "gpio23", +}; + +static const char * const pwm3_groups[] = { + "gpio24", "gpio28", "gpio32", "gpio67", +}; + +static const char * const audio_txmclk_groups[] = { + "gpio25", +}; + +static const char * const audio_txbclk_groups[] = { + "gpio26", +}; + +static const char * const audio_txfsync_groups[] = { + "gpio27", +}; + +static const char * const audio_txd_groups[] = { + "gpio28", +}; + +static const char * const audio_rxmclk_groups[] = { + "gpio29", +}; + +static const char * const atest_char0_groups[] = { + "gpio29", +}; + +static const char * const audio_rxbclk_groups[] = { + "gpio30", +}; + +static const char * const atest_char1_groups[] = { + "gpio30", +}; + +static const char * const audio_rxfsync_groups[] = { + "gpio31", +}; + +static const char * const atest_char2_groups[] = { + "gpio31", +}; + +static const char * const audio_rxd_groups[] = { + "gpio32", +}; + +static const char * const atest_char3_groups[] = { + "gpio32", +}; + +static const char * const pcm_drx_groups[] = { + "gpio33", +}; + +static const char * const mac1_sa0_groups[] = { + "gpio33", "gpio34", +}; + +static const char * const mac0_sa0_groups[] = { + "gpio33", "gpio34", +}; + +static const char * const pcm_dtx_groups[] = { + "gpio34", +}; + +static const char * const pcm_fsync_groups[] = { + "gpio35", +}; + +static const char * const mac2_sa0_groups[] = { + "gpio35", "gpio36", +}; + +static const char * const qdss_traceclk_a_groups[] = { + "gpio35", +}; + +static const char * const pcm_pclk_groups[] = { + "gpio36", +}; + +static const char * const qdss_tracectl_a_groups[] = { + "gpio36", +}; + +static const char * const atest_char_groups[] = { + "gpio37", +}; + +static const char * const qdss_tracedata_a_groups[] = { + "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", + "gpio51", "gpio52", +}; + +static const char * const blsp0_uart_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", +}; + +static const char * const blsp0_i2c_groups[] = { + "gpio38", "gpio39", +}; + +static const char * const blsp0_spi_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", +}; + +static const char * const blsp1_uart_groups[] = { + "gpio42", "gpio43", "gpio44", "gpio45", +}; + +static const char * const blsp1_i2c_groups[] = { + "gpio42", "gpio43", +}; + +static const char * const blsp1_spi_groups[] = { + "gpio42", "gpio43", "gpio44", "gpio45", +}; + +static const char * const blsp2_uart_groups[] = { + "gpio46", "gpio47", "gpio48", "gpio49", +}; + +static const char * const blsp2_i2c_groups[] = { + "gpio46", "gpio47", +}; + +static const char * const blsp2_spi_groups[] = { + "gpio46", "gpio47", "gpio48", "gpio49", +}; + +static const char * const blsp3_uart_groups[] = { + "gpio50", "gpio51", "gpio52", "gpio53", +}; + +static const char * const blsp3_i2c_groups[] = { + "gpio50", "gpio51", +}; + +static const char * const blsp3_spi_groups[] = { + "gpio50", "gpio51", "gpio52", "gpio53", +}; + +static const char * const pta2_0_groups[] = { + "gpio54", +}; + +static const char * const wci2b_groups[] = { + "gpio54", "gpio56", +}; + +static const char * const cxc1_groups[] = { + "gpio54", "gpio56", +}; + +static const char * const blsp3_spi1_groups[] = { + "gpio54", "gpio55", "gpio56", +}; + +static const char * const pta2_1_groups[] = { + "gpio55", +}; + +static const char * const pta2_2_groups[] = { + "gpio56", +}; + +static const char * const pcie0_clk_groups[] = { + "gpio57", +}; + +static const char * const dbg_out_groups[] = { + "gpio57", +}; + +static const char * const cri_trng0_groups[] = { + "gpio57", +}; + +static const char * const pcie0_rst_groups[] = { + "gpio58", +}; + +static const char * const cri_trng1_groups[] = { + "gpio58", +}; + +static const char * const pcie0_wake_groups[] = { + "gpio59", +}; + +static const char * const cri_trng_groups[] = { + "gpio59", +}; + +static const char * const pcie1_clk_groups[] = { + "gpio60", +}; + +static const char * const rx2_groups[] = { + "gpio60", +}; + +static const char * const ldo_update_groups[] = { + "gpio60", +}; + +static const char * const pcie1_rst_groups[] = { + "gpio61", +}; + +static const char * const ldo_en_groups[] = { + "gpio61", +}; + +static const char * const pcie1_wake_groups[] = { + "gpio62", +}; + +static const char * const gcc_plltest_groups[] = { + "gpio62", "gpio63", +}; + +static const char * const sd_card_groups[] = { + "gpio63", +}; + +static const char * const pta1_1_groups[] = { + "gpio64", +}; + +static const char * const rx1_groups[] = { + "gpio64", +}; + +static const char * const pta1_2_groups[] = { + "gpio65", +}; + +static const char * const gcc_tlmm_groups[] = { + "gpio65", +}; + +static const char * const pta1_0_groups[] = { + "gpio66", +}; + +static const char * const prng_rosc_groups[] = { + "gpio66", +}; + +static const char * const sd_write_groups[] = { + "gpio67", +}; + +static const char * const rx0_groups[] = { + "gpio67", +}; + +static const char * const tsens_max_groups[] = { + "gpio67", +}; + +static const char * const mdc_groups[] = { + "gpio68", +}; + +static const char * const mdio_groups[] = { + "gpio69", +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", +}; + +static const struct msm_function ipq8074_functions[] = { + FUNCTION(atest_char), + FUNCTION(atest_char0), + FUNCTION(atest_char1), + FUNCTION(atest_char2), + FUNCTION(atest_char3), + FUNCTION(audio_rxbclk), + FUNCTION(audio_rxd), + FUNCTION(audio_rxfsync), + FUNCTION(audio_rxmclk), + FUNCTION(audio_txbclk), + FUNCTION(audio_txd), + FUNCTION(audio_txfsync), + FUNCTION(audio_txmclk), + FUNCTION(blsp0_i2c), + FUNCTION(blsp0_spi), + FUNCTION(blsp0_uart), + FUNCTION(blsp1_i2c), + FUNCTION(blsp1_spi), + FUNCTION(blsp1_uart), + FUNCTION(blsp2_i2c), + FUNCTION(blsp2_spi), + FUNCTION(blsp2_uart), + FUNCTION(blsp3_i2c), + FUNCTION(blsp3_spi), + FUNCTION(blsp3_spi0), + FUNCTION(blsp3_spi1), + FUNCTION(blsp3_spi2), + FUNCTION(blsp3_spi3), + FUNCTION(blsp3_uart), + FUNCTION(blsp4_i2c0), + FUNCTION(blsp4_i2c1), + FUNCTION(blsp4_spi0), + FUNCTION(blsp4_spi1), + FUNCTION(blsp4_uart0), + FUNCTION(blsp4_uart1), + FUNCTION(blsp5_i2c), + FUNCTION(blsp5_spi), + FUNCTION(blsp5_uart), + FUNCTION(burn0), + FUNCTION(burn1), + FUNCTION(cri_trng), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(cxc0), + FUNCTION(cxc1), + FUNCTION(dbg_out), + FUNCTION(gcc_plltest), + FUNCTION(gcc_tlmm), + FUNCTION(gpio), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(led0), + FUNCTION(led1), + FUNCTION(led2), + FUNCTION(mac0_sa0), + FUNCTION(mac0_sa1), + FUNCTION(mac1_sa0), + FUNCTION(mac1_sa1), + FUNCTION(mac1_sa2), + FUNCTION(mac1_sa3), + FUNCTION(mac2_sa0), + FUNCTION(mac2_sa1), + FUNCTION(mdc), + FUNCTION(mdio), + FUNCTION(pcie0_clk), + FUNCTION(pcie0_rst), + FUNCTION(pcie0_wake), + FUNCTION(pcie1_clk), + FUNCTION(pcie1_rst), + FUNCTION(pcie1_wake), + FUNCTION(pcm_drx), + FUNCTION(pcm_dtx), + FUNCTION(pcm_fsync), + FUNCTION(pcm_pclk), + FUNCTION(pcm_zsi0), + FUNCTION(pcm_zsi1), + FUNCTION(prng_rosc), + FUNCTION(pta1_0), + FUNCTION(pta1_1), + FUNCTION(pta1_2), + FUNCTION(pta2_0), + FUNCTION(pta2_1), + FUNCTION(pta2_2), + FUNCTION(pwm0), + FUNCTION(pwm1), + FUNCTION(pwm2), + FUNCTION(pwm3), + FUNCTION(qdss_cti_trig_in_a0), + FUNCTION(qdss_cti_trig_in_a1), + FUNCTION(qdss_cti_trig_in_b0), + FUNCTION(qdss_cti_trig_in_b1), + FUNCTION(qdss_cti_trig_out_a0), + FUNCTION(qdss_cti_trig_out_a1), + FUNCTION(qdss_cti_trig_out_b0), + FUNCTION(qdss_cti_trig_out_b1), + FUNCTION(qdss_traceclk_a), + FUNCTION(qdss_traceclk_b), + FUNCTION(qdss_tracectl_a), + FUNCTION(qdss_tracectl_b), + FUNCTION(qdss_tracedata_a), + FUNCTION(qdss_tracedata_b), + FUNCTION(qpic), + FUNCTION(rx0), + FUNCTION(rx1), + FUNCTION(rx2), + FUNCTION(sd_card), + FUNCTION(sd_write), + FUNCTION(tsens_max), + FUNCTION(wci2a), + FUNCTION(wci2b), + FUNCTION(wci2c), + FUNCTION(wci2d), +}; + +static const struct msm_pingroup ipq8074_groups[] = { + PINGROUP(0, qpic, blsp5_uart, blsp5_i2c, blsp5_spi, wci2a, + blsp3_spi3, NA, burn0, NA), + PINGROUP(1, qpic, pcm_zsi0, mac1_sa2, blsp3_spi0, NA, burn1, NA, NA, + NA), + PINGROUP(2, qpic, blsp5_uart, blsp5_i2c, blsp5_spi, wci2a, + blsp3_spi3, NA, NA, NA), + PINGROUP(3, qpic, mac0_sa1, blsp3_spi0, qdss_cti_trig_out_b0, NA, NA, + NA, NA, NA), + PINGROUP(4, qpic, mac0_sa1, blsp3_spi0, qdss_cti_trig_in_b0, NA, NA, + NA, NA, NA), + PINGROUP(5, qpic, blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac2_sa1, + qdss_cti_trig_out_b1, NA, NA, NA), + PINGROUP(6, qpic, blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac2_sa1, + qdss_cti_trig_in_b1, NA, NA, NA), + PINGROUP(7, qpic, blsp4_uart0, blsp4_spi0, NA, NA, NA, NA, NA, NA), + PINGROUP(8, qpic, blsp4_uart0, blsp4_spi0, NA, NA, NA, NA, NA, NA), + PINGROUP(9, qpic, blsp5_uart, blsp5_spi, cxc0, mac1_sa3, blsp3_spi3, + qdss_cti_trig_in_a1, NA, NA), + PINGROUP(10, qpic, qdss_cti_trig_out_a1, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(11, qpic, wci2c, mac1_sa2, qdss_cti_trig_in_a0, NA, NA, NA, + NA, NA), + PINGROUP(12, qpic, qdss_cti_trig_out_a0, NA, NA, NA, NA, NA, NA, + NA), + PINGROUP(13, qpic, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(14, qpic, qdss_traceclk_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, qpic, qdss_tracectl_b, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, qpic, blsp5_uart, pcm_zsi1, blsp5_spi, cxc0, mac1_sa3, + qdss_tracedata_b, NA, NA), + PINGROUP(17, qpic, wci2c, qdss_tracedata_b, NA, NA, NA, NA, NA, NA), + PINGROUP(18, led0, pwm0, qdss_tracedata_b, NA, NA, NA, NA, NA, NA), + PINGROUP(19, led1, pwm1, NA, qdss_tracedata_b, NA, NA, NA, NA, NA), + PINGROUP(20, led2, pwm2, NA, qdss_tracedata_b, NA, NA, NA, NA, NA), + PINGROUP(21, pwm0, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci2d, mac1_sa1, + blsp3_spi2, NA, qdss_tracedata_b), + PINGROUP(22, pwm1, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci2d, mac1_sa1, + blsp3_spi2, NA, qdss_tracedata_b), + PINGROUP(23, pwm2, blsp4_uart1, blsp4_spi1, blsp3_spi2, NA, + qdss_tracedata_b, NA, NA, NA), + PINGROUP(24, pwm3, blsp4_uart1, blsp4_spi1, NA, qdss_tracedata_b, NA, + NA, NA, NA), + PINGROUP(25, audio_txmclk, pwm0, NA, qdss_tracedata_b, NA, NA, NA, NA, + NA), + PINGROUP(26, audio_txbclk, pwm1, NA, qdss_tracedata_b, NA, NA, NA, NA, + NA), + PINGROUP(27, audio_txfsync, pwm2, NA, qdss_tracedata_b, NA, NA, NA, + NA, NA), + PINGROUP(28, audio_txd, pwm3, NA, qdss_tracedata_b, NA, NA, NA, NA, + NA), + PINGROUP(29, audio_rxmclk, pwm0, atest_char0, NA, qdss_tracedata_b, + NA, NA, NA, NA), + PINGROUP(30, audio_rxbclk, pwm1, atest_char1, NA, qdss_tracedata_b, + NA, NA, NA, NA), + PINGROUP(31, audio_rxfsync, pwm2, atest_char2, NA, qdss_tracedata_b, + NA, NA, NA, NA), + PINGROUP(32, audio_rxd, pwm3, atest_char3, NA, NA, NA, NA, NA, NA), + PINGROUP(33, pcm_drx, mac1_sa0, mac0_sa0, NA, NA, NA, NA, NA, NA), + PINGROUP(34, pcm_dtx, mac1_sa0, mac0_sa0, NA, NA, NA, NA, NA, NA), + PINGROUP(35, pcm_fsync, mac2_sa0, qdss_traceclk_a, NA, NA, NA, NA, NA, NA), + PINGROUP(36, pcm_pclk, mac2_sa0, NA, qdss_tracectl_a, NA, NA, NA, NA, NA), + PINGROUP(37, atest_char, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA), + PINGROUP(38, blsp0_uart, blsp0_i2c, blsp0_spi, NA, qdss_tracedata_a, + NA, NA, NA, NA), + PINGROUP(39, blsp0_uart, blsp0_i2c, blsp0_spi, NA, qdss_tracedata_a, + NA, NA, NA, NA), + PINGROUP(40, blsp0_uart, blsp0_spi, NA, qdss_tracedata_a, NA, NA, NA, + NA, NA), + PINGROUP(41, blsp0_uart, blsp0_spi, NA, qdss_tracedata_a, NA, NA, NA, + NA, NA), + PINGROUP(42, blsp1_uart, blsp1_i2c, blsp1_spi, NA, qdss_tracedata_a, + NA, NA, NA, NA), + PINGROUP(43, blsp1_uart, blsp1_i2c, blsp1_spi, NA, qdss_tracedata_a, + NA, NA, NA, NA), + PINGROUP(44, blsp1_uart, blsp1_spi, NA, qdss_tracedata_a, NA, NA, NA, + NA, NA), + PINGROUP(45, blsp1_uart, blsp1_spi, qdss_tracedata_a, NA, NA, NA, NA, + NA, NA), + PINGROUP(46, blsp2_uart, blsp2_i2c, blsp2_spi, qdss_tracedata_a, NA, + NA, NA, NA, NA), + PINGROUP(47, blsp2_uart, blsp2_i2c, blsp2_spi, NA, qdss_tracedata_a, + NA, NA, NA, NA), + PINGROUP(48, blsp2_uart, blsp2_spi, NA, qdss_tracedata_a, NA, NA, NA, + NA, NA), + PINGROUP(49, blsp2_uart, blsp2_spi, NA, qdss_tracedata_a, NA, NA, NA, + NA, NA), + PINGROUP(50, blsp3_uart, blsp3_i2c, blsp3_spi, NA, qdss_tracedata_a, + NA, NA, NA, NA), + PINGROUP(51, blsp3_uart, blsp3_i2c, blsp3_spi, NA, qdss_tracedata_a, + NA, NA, NA, NA), + PINGROUP(52, blsp3_uart, blsp3_spi, NA, qdss_tracedata_a, NA, NA, NA, + NA, NA), + PINGROUP(53, blsp3_uart, blsp3_spi, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, pta2_0, wci2b, cxc1, blsp3_spi1, NA, NA, NA, NA, NA), + PINGROUP(55, pta2_1, blsp3_spi1, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, pta2_2, wci2b, cxc1, blsp3_spi1, NA, NA, NA, NA, NA), + PINGROUP(57, pcie0_clk, NA, dbg_out, cri_trng0, NA, NA, NA, NA, NA), + PINGROUP(58, pcie0_rst, NA, cri_trng1, NA, NA, NA, NA, NA, NA), + PINGROUP(59, pcie0_wake, NA, cri_trng, NA, NA, NA, NA, NA, NA), + PINGROUP(60, pcie1_clk, rx2, ldo_update, NA, NA, NA, NA, NA, NA), + PINGROUP(61, pcie1_rst, ldo_en, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, pcie1_wake, gcc_plltest, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, sd_card, pwm0, NA, gcc_plltest, NA, NA, NA, NA, NA), + PINGROUP(64, pta1_1, pwm1, NA, rx1, NA, NA, NA, NA, NA), + PINGROUP(65, pta1_2, NA, gcc_tlmm, NA, NA, NA, NA, NA, NA), + PINGROUP(66, pta1_0, pwm2, prng_rosc, NA, NA, NA, NA, NA, NA), + PINGROUP(67, sd_write, pwm3, rx0, tsens_max, NA, NA, NA, NA, NA), + PINGROUP(68, mdc, NA, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, mdio, NA, NA, NA, NA, NA, NA, NA, NA), +}; + +static const struct msm_pinctrl_soc_data ipq8074_pinctrl = { + .pins = ipq8074_pins, + .npins = ARRAY_SIZE(ipq8074_pins), + .functions = ipq8074_functions, + .nfunctions = ARRAY_SIZE(ipq8074_functions), + .groups = ipq8074_groups, + .ngroups = ARRAY_SIZE(ipq8074_groups), + .ngpios = 70, +}; + +static int ipq8074_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &ipq8074_pinctrl); +} + +static const struct of_device_id ipq8074_pinctrl_of_match[] = { + { .compatible = "qcom,ipq8074-pinctrl", }, + { }, +}; + +static struct platform_driver ipq8074_pinctrl_driver = { + .driver = { + .name = "ipq8074-pinctrl", + .of_match_table = ipq8074_pinctrl_of_match, + }, + .probe = ipq8074_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init ipq8074_pinctrl_init(void) +{ + return platform_driver_register(&ipq8074_pinctrl_driver); +} +arch_initcall(ipq8074_pinctrl_init); + +static void __exit ipq8074_pinctrl_exit(void) +{ + platform_driver_unregister(&ipq8074_pinctrl_driver); +} +module_exit(ipq8074_pinctrl_exit); + +MODULE_DESCRIPTION("Qualcomm ipq8074 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, ipq8074_pinctrl_of_match); diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig index d0461cd5d707..0357f9701eb9 100644 --- a/drivers/pinctrl/samsung/Kconfig +++ b/drivers/pinctrl/samsung/Kconfig @@ -10,6 +10,16 @@ config PINCTRL_EXYNOS bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440" depends on OF && GPIOLIB && (ARCH_EXYNOS || ARCH_S5PV210) select PINCTRL_SAMSUNG + select PINCTRL_EXYNOS_ARM if ARM && (ARCH_EXYNOS || ARCH_S5PV210) + select PINCTRL_EXYNOS_ARM64 if ARM64 && ARCH_EXYNOS + +config PINCTRL_EXYNOS_ARM + bool "ARMv7-specific pinctrl driver data for Exynos (except Exynos5440)" if COMPILE_TEST + depends on PINCTRL_EXYNOS + +config PINCTRL_EXYNOS_ARM64 + bool "ARMv8-specific pinctrl driver data for Exynos" if COMPILE_TEST + depends on PINCTRL_EXYNOS config PINCTRL_EXYNOS5440 bool "Samsung EXYNOS5440 SoC pinctrl driver" diff --git a/drivers/pinctrl/samsung/Makefile b/drivers/pinctrl/samsung/Makefile index 70160c059edd..595995851ea5 100644 --- a/drivers/pinctrl/samsung/Makefile +++ b/drivers/pinctrl/samsung/Makefile @@ -2,6 +2,8 @@ obj-$(CONFIG_PINCTRL_SAMSUNG) += pinctrl-samsung.o obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o +obj-$(CONFIG_PINCTRL_EXYNOS_ARM) += pinctrl-exynos-arm.o +obj-$(CONFIG_PINCTRL_EXYNOS_ARM64) += pinctrl-exynos-arm64.o obj-$(CONFIG_PINCTRL_EXYNOS5440) += pinctrl-exynos5440.o obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c new file mode 100644 index 000000000000..071084d3ee9c --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c @@ -0,0 +1,815 @@ +/* + * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2012 Linaro Ltd + * http://www.linaro.org + * + * Author: Thomas Abraham <thomas.ab@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file contains the Samsung Exynos specific information required by the + * the Samsung pinctrl/gpiolib driver. It also includes the implementation of + * external gpio and wakeup interrupt support. + */ + +#include <linux/device.h> +#include <linux/of_address.h> +#include <linux/slab.h> +#include <linux/err.h> +#include <linux/soc/samsung/exynos-regs-pmu.h> + +#include "pinctrl-samsung.h" +#include "pinctrl-exynos.h" + +static const struct samsung_pin_bank_type bank_type_off = { + .fld_width = { 4, 1, 2, 2, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +static const struct samsung_pin_bank_type bank_type_alive = { + .fld_width = { 4, 1, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + +/* Retention control for S5PV210 are located at the end of clock controller */ +#define S5P_OTHERS 0xE000 + +#define S5P_OTHERS_RET_IO (1 << 31) +#define S5P_OTHERS_RET_CF (1 << 30) +#define S5P_OTHERS_RET_MMC (1 << 29) +#define S5P_OTHERS_RET_UART (1 << 28) + +static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata) +{ + void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; + u32 tmp; + + tmp = __raw_readl(clk_base + S5P_OTHERS); + tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC | + S5P_OTHERS_RET_UART); + __raw_writel(tmp, clk_base + S5P_OTHERS); +} + +static struct samsung_retention_ctrl * +s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata, + const struct samsung_retention_data *data) +{ + struct samsung_retention_ctrl *ctrl; + struct device_node *np; + void __iomem *clk_base; + + ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); + if (!ctrl) + return ERR_PTR(-ENOMEM); + + np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); + if (!np) { + pr_err("%s: failed to find clock controller DT node\n", + __func__); + return ERR_PTR(-ENODEV); + } + + clk_base = of_iomap(np, 0); + if (!clk_base) { + pr_err("%s: failed to map clock registers\n", __func__); + return ERR_PTR(-EINVAL); + } + + ctrl->priv = (void __force *)clk_base; + ctrl->disable = s5pv210_retention_disable; + + return ctrl; +} + +static const struct samsung_retention_data s5pv210_retention_data __initconst = { + .init = s5pv210_retention_init, +}; + +/* pin banks of s5pv210 pin-controller */ +static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c), + EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24), + EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28), + EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c), + EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30), + EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34), + EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38), + EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c), + EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40), + EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"), + EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44), + EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48), + EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c), + EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50), + EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54), + EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"), + EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"), + EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"), + EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"), + EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"), + EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"), + EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"), + EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c), +}; + +const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = s5pv210_pin_bank, + .nr_banks = ARRAY_SIZE(s5pv210_pin_bank), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &s5pv210_retention_data, + }, +}; + +/* Pad retention control code for accessing PMU regmap */ +static atomic_t exynos_shared_retention_refcnt; + +/* pin banks of exynos3250 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18), +}; + +/* pin banks of exynos3250 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = { + EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"), + EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"), + EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08), + EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), + EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), + EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30), + EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34), + EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), +}; + +/* + * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle + * them all together + */ +static const u32 exynos3250_retention_regs[] = { + S5P_PAD_RET_MAUDIO_OPTION, + S5P_PAD_RET_GPIO_OPTION, + S5P_PAD_RET_UART_OPTION, + S5P_PAD_RET_MMCA_OPTION, + S5P_PAD_RET_MMCB_OPTION, + S5P_PAD_RET_EBIA_OPTION, + S5P_PAD_RET_EBIB_OPTION, + S5P_PAD_RET_MMC2_OPTION, + S5P_PAD_RET_SPI_OPTION, +}; + +static const struct samsung_retention_data exynos3250_retention_data __initconst = { + .regs = exynos3250_retention_regs, + .nr_regs = ARRAY_SIZE(exynos3250_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + +/* + * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes + * two gpio/pin-mux/pinconfig controllers. + */ +const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos3250_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos3250_retention_data, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos3250_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos3250_retention_data, + }, +}; + +/* pin banks of exynos4210 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), + EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), + EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24), + EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28), + EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), + EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), + EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), + EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), +}; + +/* pin banks of exynos4210 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), + EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), + EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), + EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), + EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18), + EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), + EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos4210 pin-controller 2 */ +static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = { + EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), +}; + +/* PMU pad retention groups registers for Exynos4 (without audio) */ +static const u32 exynos4_retention_regs[] = { + S5P_PAD_RET_GPIO_OPTION, + S5P_PAD_RET_UART_OPTION, + S5P_PAD_RET_MMCA_OPTION, + S5P_PAD_RET_MMCB_OPTION, + S5P_PAD_RET_EBIA_OPTION, + S5P_PAD_RET_EBIB_OPTION, +}; + +static const struct samsung_retention_data exynos4_retention_data __initconst = { + .regs = exynos4_retention_regs, + .nr_regs = ARRAY_SIZE(exynos4_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + +/* PMU retention control for audio pins can be tied to audio pin bank */ +static const u32 exynos4_audio_retention_regs[] = { + S5P_PAD_RET_MAUDIO_OPTION, +}; + +static const struct samsung_retention_data exynos4_audio_retention_data __initconst = { + .regs = exynos4_audio_retention_regs, + .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .init = exynos_retention_init, +}; + +/* + * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes + * three gpio/pin-mux/pinconfig controllers. + */ +const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos4210_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos4210_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos4210_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), + .retention_data = &exynos4_audio_retention_data, + }, +}; + +/* pin banks of exynos4x12 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), + EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), + EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), + EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), + EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40), + EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44), +}; + +/* pin banks of exynos4x12 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = { + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), + EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), + EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), + EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), + EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18), + EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), + EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), + EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), + EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos4x12 pin-controller 2 */ +static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* pin banks of exynos4x12 pin-controller 3 */ +static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10), +}; + +/* + * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos4x12_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos4x12_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos4x12_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_audio_retention_data, + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos4x12_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +/* pin banks of exynos5250 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), + EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20), + EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28), + EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30), + EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34), + EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5250 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), + EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), + EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), + EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20), +}; + +/* pin banks of exynos5250 pin-controller 2 */ +static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), +}; + +/* pin banks of exynos5250 pin-controller 3 */ +static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* + * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5250_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5250_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_retention_data, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5250_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5250_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos4_audio_retention_data, + }, +}; + +/* pin banks of exynos5260 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = { + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), + EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), + EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), + EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34), + EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), + EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c), + EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), + EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5260 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), + EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), +}; + +/* pin banks of exynos5260 pin-controller 2 */ +static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), +}; + +/* + * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes + * three gpio/pin-mux/pinconfig controllers. + */ +const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5260_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5260_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5260_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + }, +}; + +/* pin banks of exynos5410 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), + EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20), + EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24), + EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28), + EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"), + EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c), + EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30), + EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34), + EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38), + EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c), + EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40), + EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44), + EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48), + EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c), + EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50), + EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"), + EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"), + EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5410 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = { + EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c), + EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20), +}; + +/* pin banks of exynos5410 pin-controller 2 */ +static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), +}; + +/* pin banks of exynos5410 pin-controller 3 */ +static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* + * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5410_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5410_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5410_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5410_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + }, +}; + +/* pin banks of exynos5420 pin-controller 0 */ +static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), +}; + +/* pin banks of exynos5420 pin-controller 1 */ +static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04), + EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), + EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14), + EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"), + EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"), + EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"), + EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"), + EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"), + EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"), + EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"), +}; + +/* pin banks of exynos5420 pin-controller 2 */ +static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), + EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), + EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), + EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), + EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c), +}; + +/* pin banks of exynos5420 pin-controller 3 */ +static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), + EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), + EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c), + EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20), +}; + +/* pin banks of exynos5420 pin-controller 4 */ +static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), +}; + +/* PMU pad retention groups registers for Exynos5420 (without audio) */ +static const u32 exynos5420_retention_regs[] = { + EXYNOS_PAD_RET_DRAM_OPTION, + EXYNOS_PAD_RET_JTAG_OPTION, + EXYNOS5420_PAD_RET_GPIO_OPTION, + EXYNOS5420_PAD_RET_UART_OPTION, + EXYNOS5420_PAD_RET_MMCA_OPTION, + EXYNOS5420_PAD_RET_MMCB_OPTION, + EXYNOS5420_PAD_RET_MMCC_OPTION, + EXYNOS5420_PAD_RET_HSI_OPTION, + EXYNOS_PAD_RET_EBIA_OPTION, + EXYNOS_PAD_RET_EBIB_OPTION, + EXYNOS5420_PAD_RET_SPI_OPTION, + EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, +}; + +static const struct samsung_retention_data exynos5420_retention_data __initconst = { + .regs = exynos5420_retention_regs, + .nr_regs = ARRAY_SIZE(exynos5420_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + +/* + * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes + * four gpio/pin-mux/pinconfig controllers. + */ +const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5420_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), + .eint_gpio_init = exynos_eint_gpio_init, + .eint_wkup_init = exynos_eint_wkup_init, + .retention_data = &exynos5420_retention_data, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5420_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .retention_data = &exynos5420_retention_data, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5420_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .retention_data = &exynos5420_retention_data, + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5420_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .retention_data = &exynos5420_retention_data, + }, { + /* pin-controller instance 4 data */ + .pin_banks = exynos5420_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .retention_data = &exynos4_audio_retention_data, + }, +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c new file mode 100644 index 000000000000..08e9fdb58fd2 --- /dev/null +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -0,0 +1,399 @@ +/* + * Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver + * with eint support. + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2012 Linaro Ltd + * http://www.linaro.org + * Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This file contains the Samsung Exynos specific information required by the + * the Samsung pinctrl/gpiolib driver. It also includes the implementation of + * external gpio and wakeup interrupt support. + */ + +#include <linux/slab.h> +#include <linux/soc/samsung/exynos-regs-pmu.h> + +#include "pinctrl-samsung.h" +#include "pinctrl-exynos.h" + +static const struct samsung_pin_bank_type bank_type_off = { + .fld_width = { 4, 1, 2, 2, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +static const struct samsung_pin_bank_type bank_type_alive = { + .fld_width = { 4, 1, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + +/* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */ +static const struct samsung_pin_bank_type exynos5433_bank_type_off = { + .fld_width = { 4, 1, 2, 4, 2, 2, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, +}; + +static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { + .fld_width = { 4, 1, 2, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + +/* Pad retention control code for accessing PMU regmap */ +static atomic_t exynos_shared_retention_refcnt; + +/* pin banks of exynos5433 pin-controller - ALIVE */ +static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = { + EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), + EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), + EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), + EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1), + EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1), + EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1), + EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1), + EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1), +}; + +/* pin banks of exynos5433 pin-controller - AUD */ +static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = { + EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), + EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), +}; + +/* pin banks of exynos5433 pin-controller - CPIF */ +static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = { + EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00), +}; + +/* pin banks of exynos5433 pin-controller - eSE */ +static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = { + EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00), +}; + +/* pin banks of exynos5433 pin-controller - FINGER */ +static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = { + EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00), +}; + +/* pin banks of exynos5433 pin-controller - FSYS */ +static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = { + EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00), + EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04), + EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08), + EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c), + EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10), + EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14), +}; + +/* pin banks of exynos5433 pin-controller - IMEM */ +static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = { + EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), +}; + +/* pin banks of exynos5433 pin-controller - NFC */ +static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = { + EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), +}; + +/* pin banks of exynos5433 pin-controller - PERIC */ +static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = { + EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00), + EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04), + EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08), + EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c), + EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10), + EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14), + EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18), + EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c), + EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20), + EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24), + EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28), + EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c), + EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30), + EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34), + EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38), + EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c), + EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), +}; + +/* pin banks of exynos5433 pin-controller - TOUCH */ +static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = { + EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), +}; + +/* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */ +static const u32 exynos5433_retention_regs[] = { + EXYNOS5433_PAD_RETENTION_TOP_OPTION, + EXYNOS5433_PAD_RETENTION_UART_OPTION, + EXYNOS5433_PAD_RETENTION_EBIA_OPTION, + EXYNOS5433_PAD_RETENTION_EBIB_OPTION, + EXYNOS5433_PAD_RETENTION_SPI_OPTION, + EXYNOS5433_PAD_RETENTION_MIF_OPTION, + EXYNOS5433_PAD_RETENTION_USBXTI_OPTION, + EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION, + EXYNOS5433_PAD_RETENTION_UFS_OPTION, + EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION, +}; + +static const struct samsung_retention_data exynos5433_retention_data __initconst = { + .regs = exynos5433_retention_regs, + .nr_regs = ARRAY_SIZE(exynos5433_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .refcnt = &exynos_shared_retention_refcnt, + .init = exynos_retention_init, +}; + +/* PMU retention control for audio pins can be tied to audio pin bank */ +static const u32 exynos5433_audio_retention_regs[] = { + EXYNOS5433_PAD_RETENTION_AUD_OPTION, +}; + +static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = { + .regs = exynos5433_audio_retention_regs, + .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .init = exynos_retention_init, +}; + +/* PMU retention control for mmc pins can be tied to fsys pin bank */ +static const u32 exynos5433_fsys_retention_regs[] = { + EXYNOS5433_PAD_RETENTION_MMC0_OPTION, + EXYNOS5433_PAD_RETENTION_MMC1_OPTION, + EXYNOS5433_PAD_RETENTION_MMC2_OPTION, +}; + +static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = { + .regs = exynos5433_fsys_retention_regs, + .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs), + .value = EXYNOS_WAKEUP_FROM_LOWPWR, + .init = exynos_retention_init, +}; + +/* + * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes + * ten gpio/pin-mux/pinconfig controllers. + */ +const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 data */ + .pin_banks = exynos5433_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .nr_ext_resources = 1, + .retention_data = &exynos5433_retention_data, + }, { + /* pin-controller instance 1 data */ + .pin_banks = exynos5433_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_audio_retention_data, + }, { + /* pin-controller instance 2 data */ + .pin_banks = exynos5433_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_retention_data, + }, { + /* pin-controller instance 3 data */ + .pin_banks = exynos5433_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_retention_data, + }, { + /* pin-controller instance 4 data */ + .pin_banks = exynos5433_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_retention_data, + }, { + /* pin-controller instance 5 data */ + .pin_banks = exynos5433_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_fsys_retention_data, + }, { + /* pin-controller instance 6 data */ + .pin_banks = exynos5433_pin_banks6, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_retention_data, + }, { + /* pin-controller instance 7 data */ + .pin_banks = exynos5433_pin_banks7, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_retention_data, + }, { + /* pin-controller instance 8 data */ + .pin_banks = exynos5433_pin_banks8, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_retention_data, + }, { + /* pin-controller instance 9 data */ + .pin_banks = exynos5433_pin_banks9, + .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9), + .eint_gpio_init = exynos_eint_gpio_init, + .suspend = exynos_pinctrl_suspend, + .resume = exynos_pinctrl_resume, + .retention_data = &exynos5433_retention_data, + }, +}; + +/* pin banks of exynos7 pin-controller - ALIVE */ +static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { + EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), + EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), + EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), + EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), +}; + +/* pin banks of exynos7 pin-controller - BUS0 */ +static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = { + EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04), + EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08), + EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c), + EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), + EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), + EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), + EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c), + EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20), + EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24), + EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28), + EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c), + EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30), + EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), + EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38), +}; + +/* pin banks of exynos7 pin-controller - NFC */ +static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = { + EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), +}; + +/* pin banks of exynos7 pin-controller - TOUCH */ +static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = { + EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), +}; + +/* pin banks of exynos7 pin-controller - FF */ +static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = { + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00), +}; + +/* pin banks of exynos7 pin-controller - ESE */ +static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = { + EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00), +}; + +/* pin banks of exynos7 pin-controller - FSYS0 */ +static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00), +}; + +/* pin banks of exynos7 pin-controller - FSYS1 */ +static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = { + EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), + EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08), + EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c), +}; + +/* pin banks of exynos7 pin-controller - BUS1 */ +static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = { + EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00), + EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04), + EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08), + EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c), + EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10), + EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14), + EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18), + EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c), + EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20), + EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24), +}; + +static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = { + EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), + EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), +}; + +const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { + { + /* pin-controller instance 0 Alive data */ + .pin_banks = exynos7_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks0), + .eint_wkup_init = exynos_eint_wkup_init, + }, { + /* pin-controller instance 1 BUS0 data */ + .pin_banks = exynos7_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks1), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 2 NFC data */ + .pin_banks = exynos7_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks2), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 3 TOUCH data */ + .pin_banks = exynos7_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks3), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 4 FF data */ + .pin_banks = exynos7_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks4), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 5 ESE data */ + .pin_banks = exynos7_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks5), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 6 FSYS0 data */ + .pin_banks = exynos7_pin_banks6, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks6), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 7 FSYS1 data */ + .pin_banks = exynos7_pin_banks7, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks7), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 8 BUS1 data */ + .pin_banks = exynos7_pin_banks8, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks8), + .eint_gpio_init = exynos_eint_gpio_init, + }, { + /* pin-controller instance 9 AUD data */ + .pin_banks = exynos7_pin_banks9, + .nr_banks = ARRAY_SIZE(exynos7_pin_banks9), + .eint_gpio_init = exynos_eint_gpio_init, + }, +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 7b0e6cc35e04..731530a9ce38 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -18,21 +18,18 @@ * external gpio and wakeup interrupt support. */ -#include <linux/module.h> #include <linux/device.h> #include <linux/interrupt.h> #include <linux/irqdomain.h> #include <linux/irq.h> #include <linux/irqchip/chained_irq.h> -#include <linux/of_address.h> +#include <linux/of.h> #include <linux/of_irq.h> -#include <linux/io.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/regmap.h> #include <linux/err.h> #include <linux/soc/samsung/exynos-pmu.h> -#include <linux/soc/samsung/exynos-regs-pmu.h> #include "pinctrl-samsung.h" #include "pinctrl-exynos.h" @@ -50,27 +47,6 @@ static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip) return container_of(chip, struct exynos_irq_chip, chip); } -static const struct samsung_pin_bank_type bank_type_off = { - .fld_width = { 4, 1, 2, 2, 2, 2, }, - .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, -}; - -static const struct samsung_pin_bank_type bank_type_alive = { - .fld_width = { 4, 1, 2, 2, }, - .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, -}; - -/* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */ -static const struct samsung_pin_bank_type exynos5433_bank_type_off = { - .fld_width = { 4, 1, 2, 4, 2, 2, }, - .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, -}; - -static const struct samsung_pin_bank_type exynos5433_bank_type_alive = { - .fld_width = { 4, 1, 2, 4, }, - .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, -}; - static void exynos_irq_mask(struct irq_data *irqd) { struct irq_chip *chip = irq_data_get_irq_chip(irqd); @@ -205,8 +181,6 @@ static int exynos_irq_request_resources(struct irq_data *irqd) spin_unlock_irqrestore(&bank->slock, flags); - exynos_irq_unmask(irqd); - return 0; } @@ -226,8 +200,6 @@ static void exynos_irq_release_resources(struct irq_data *irqd) shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; - exynos_irq_mask(irqd); - spin_lock_irqsave(&bank->slock, flags); con = readl(bank->eint_base + reg_con); @@ -308,7 +280,7 @@ struct exynos_eint_gpio_save { * exynos_eint_gpio_init() - setup handling of external gpio interrupts. * @d: driver data of samsung pinctrl driver. */ -static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) +int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) { struct samsung_pin_bank *bank; struct device *dev = d->dev; @@ -387,7 +359,7 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) /* * irq_chip for wakeup interrupts */ -static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = { +static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = { .chip = { .name = "exynos4210_wkup_irq_chip", .irq_unmask = exynos_irq_unmask, @@ -403,7 +375,7 @@ static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = { .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, }; -static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = { +static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = { .chip = { .name = "exynos7_wkup_irq_chip", .irq_unmask = exynos_irq_unmask, @@ -483,7 +455,7 @@ static void exynos_irq_demux_eint16_31(struct irq_desc *desc) * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. * @d: driver data of samsung pinctrl driver. */ -static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) +int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) { struct device *dev = d->dev; struct device_node *wkup_np = NULL; @@ -503,6 +475,8 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) if (match) { irq_chip = kmemdup(match->data, sizeof(*irq_chip), GFP_KERNEL); + if (!irq_chip) + return -ENOMEM; wkup_np = np; break; } @@ -599,7 +573,7 @@ static void exynos_pinctrl_suspend_bank( pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); } -static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) +void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) { struct samsung_pin_bank *bank = drvdata->pin_banks; int i; @@ -634,7 +608,7 @@ static void exynos_pinctrl_resume_bank( + 2 * bank->eint_offset + 4); } -static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) +void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) { struct samsung_pin_bank *bank = drvdata->pin_banks; int i; @@ -644,114 +618,6 @@ static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) exynos_pinctrl_resume_bank(drvdata, bank); } -/* Retention control for S5PV210 are located at the end of clock controller */ -#define S5P_OTHERS 0xE000 - -#define S5P_OTHERS_RET_IO (1 << 31) -#define S5P_OTHERS_RET_CF (1 << 30) -#define S5P_OTHERS_RET_MMC (1 << 29) -#define S5P_OTHERS_RET_UART (1 << 28) - -static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata) -{ - void *clk_base = drvdata->retention_ctrl->priv; - u32 tmp; - - tmp = __raw_readl(clk_base + S5P_OTHERS); - tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC | - S5P_OTHERS_RET_UART); - __raw_writel(tmp, clk_base + S5P_OTHERS); -} - -static struct samsung_retention_ctrl * -s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata, - const struct samsung_retention_data *data) -{ - struct samsung_retention_ctrl *ctrl; - struct device_node *np; - void *clk_base; - - ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); - if (!ctrl) - return ERR_PTR(-ENOMEM); - - np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock"); - if (!np) { - pr_err("%s: failed to find clock controller DT node\n", - __func__); - return ERR_PTR(-ENODEV); - } - - clk_base = of_iomap(np, 0); - if (!clk_base) { - pr_err("%s: failed to map clock registers\n", __func__); - return ERR_PTR(-EINVAL); - } - - ctrl->priv = clk_base; - ctrl->disable = s5pv210_retention_disable; - - return ctrl; -} - -static const struct samsung_retention_data s5pv210_retention_data __initconst = { - .init = s5pv210_retention_init, -}; - -/* pin banks of s5pv210 pin-controller */ -static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), - EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), - EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), - EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c), - EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20), - EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24), - EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28), - EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c), - EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30), - EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34), - EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38), - EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c), - EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40), - EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"), - EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44), - EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48), - EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c), - EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50), - EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54), - EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"), - EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"), - EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"), - EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"), - EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"), - EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"), - EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"), - EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c), -}; - -const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = { - { - /* pin-controller instance 0 data */ - .pin_banks = s5pv210_pin_bank, - .nr_banks = ARRAY_SIZE(s5pv210_pin_bank), - .eint_gpio_init = exynos_eint_gpio_init, - .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &s5pv210_retention_data, - }, -}; - -/* Pad retention control code for accessing PMU regmap */ -static atomic_t exynos_shared_retention_refcnt; - static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) { if (drvdata->retention_ctrl->refcnt) @@ -771,7 +637,7 @@ static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata) regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); } -static struct samsung_retention_ctrl * +struct samsung_retention_ctrl * exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, const struct samsung_retention_data *data) { @@ -801,1022 +667,3 @@ exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, return ctrl; } - -/* pin banks of exynos3250 pin-controller 0 */ -static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), - EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), - EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18), -}; - -/* pin banks of exynos3250 pin-controller 1 */ -static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = { - EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"), - EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"), - EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08), - EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), - EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18), - EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), - EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), - EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c), - EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30), - EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34), - EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), -}; - -/* - * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle - * them all together - */ -static const u32 exynos3250_retention_regs[] = { - S5P_PAD_RET_MAUDIO_OPTION, - S5P_PAD_RET_GPIO_OPTION, - S5P_PAD_RET_UART_OPTION, - S5P_PAD_RET_MMCA_OPTION, - S5P_PAD_RET_MMCB_OPTION, - S5P_PAD_RET_EBIA_OPTION, - S5P_PAD_RET_EBIB_OPTION, - S5P_PAD_RET_MMC2_OPTION, - S5P_PAD_RET_SPI_OPTION, -}; - -static const struct samsung_retention_data exynos3250_retention_data __initconst = { - .regs = exynos3250_retention_regs, - .nr_regs = ARRAY_SIZE(exynos3250_retention_regs), - .value = EXYNOS_WAKEUP_FROM_LOWPWR, - .refcnt = &exynos_shared_retention_refcnt, - .init = exynos_retention_init, -}; - -/* - * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes - * two gpio/pin-mux/pinconfig controllers. - */ -const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = { - { - /* pin-controller instance 0 data */ - .pin_banks = exynos3250_pin_banks0, - .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos3250_retention_data, - }, { - /* pin-controller instance 1 data */ - .pin_banks = exynos3250_pin_banks1, - .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, - .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos3250_retention_data, - }, -}; - -/* pin banks of exynos4210 pin-controller 0 */ -static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), - EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), - EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), - EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c), - EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20), - EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24), - EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28), - EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c), - EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), - EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), - EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), - EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), -}; - -/* pin banks of exynos4210 pin-controller 1 */ -static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00), - EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04), - EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), - EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), - EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), - EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), - EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18), - EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c), - EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), - EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), - EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), - EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), - EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), - EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), - EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), - EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), - EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), -}; - -/* pin banks of exynos4210 pin-controller 2 */ -static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = { - EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"), -}; - -/* PMU pad retention groups registers for Exynos4 (without audio) */ -static const u32 exynos4_retention_regs[] = { - S5P_PAD_RET_GPIO_OPTION, - S5P_PAD_RET_UART_OPTION, - S5P_PAD_RET_MMCA_OPTION, - S5P_PAD_RET_MMCB_OPTION, - S5P_PAD_RET_EBIA_OPTION, - S5P_PAD_RET_EBIB_OPTION, -}; - -static const struct samsung_retention_data exynos4_retention_data __initconst = { - .regs = exynos4_retention_regs, - .nr_regs = ARRAY_SIZE(exynos4_retention_regs), - .value = EXYNOS_WAKEUP_FROM_LOWPWR, - .refcnt = &exynos_shared_retention_refcnt, - .init = exynos_retention_init, -}; - -/* PMU retention control for audio pins can be tied to audio pin bank */ -static const u32 exynos4_audio_retention_regs[] = { - S5P_PAD_RET_MAUDIO_OPTION, -}; - -static const struct samsung_retention_data exynos4_audio_retention_data __initconst = { - .regs = exynos4_audio_retention_regs, - .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs), - .value = EXYNOS_WAKEUP_FROM_LOWPWR, - .init = exynos_retention_init, -}; - -/* - * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes - * three gpio/pin-mux/pinconfig controllers. - */ -const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = { - { - /* pin-controller instance 0 data */ - .pin_banks = exynos4210_pin_banks0, - .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos4_retention_data, - }, { - /* pin-controller instance 1 data */ - .pin_banks = exynos4210_pin_banks1, - .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, - .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos4_retention_data, - }, { - /* pin-controller instance 2 data */ - .pin_banks = exynos4210_pin_banks2, - .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2), - .retention_data = &exynos4_audio_retention_data, - }, -}; - -/* pin banks of exynos4x12 pin-controller 0 */ -static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), - EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14), - EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18), - EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30), - EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34), - EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38), - EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c), - EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40), - EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44), -}; - -/* pin banks of exynos4x12 pin-controller 1 */ -static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = { - EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08), - EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c), - EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10), - EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14), - EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18), - EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c), - EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20), - EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24), - EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28), - EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c), - EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30), - EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34), - EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"), - EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"), - EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"), - EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"), - EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"), - EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"), - EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"), - EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), -}; - -/* pin banks of exynos4x12 pin-controller 2 */ -static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = { - EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), -}; - -/* pin banks of exynos4x12 pin-controller 3 */ -static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), - EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08), - EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c), - EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10), -}; - -/* - * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes - * four gpio/pin-mux/pinconfig controllers. - */ -const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = { - { - /* pin-controller instance 0 data */ - .pin_banks = exynos4x12_pin_banks0, - .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos4_retention_data, - }, { - /* pin-controller instance 1 data */ - .pin_banks = exynos4x12_pin_banks1, - .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, - .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos4_retention_data, - }, { - /* pin-controller instance 2 data */ - .pin_banks = exynos4x12_pin_banks2, - .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos4_audio_retention_data, - }, { - /* pin-controller instance 3 data */ - .pin_banks = exynos4x12_pin_banks3, - .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - }, -}; - -/* pin banks of exynos5250 pin-controller 0 */ -static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), - EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), - EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), - EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), - EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20), - EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24), - EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28), - EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c), - EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30), - EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34), - EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"), - EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"), - EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"), - EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"), - EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"), - EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"), - EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"), - EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), -}; - -/* pin banks of exynos5250 pin-controller 1 */ -static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), - EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), - EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08), - EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c), - EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), - EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), - EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), - EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c), - EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20), -}; - -/* pin banks of exynos5250 pin-controller 2 */ -static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), - EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), - EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), - EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), -}; - -/* pin banks of exynos5250 pin-controller 3 */ -static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = { - EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), -}; - -/* - * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes - * four gpio/pin-mux/pinconfig controllers. - */ -const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = { - { - /* pin-controller instance 0 data */ - .pin_banks = exynos5250_pin_banks0, - .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0), - .eint_gpio_init = exynos_eint_gpio_init, - .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos4_retention_data, - }, { - /* pin-controller instance 1 data */ - .pin_banks = exynos5250_pin_banks1, - .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos4_retention_data, - }, { - /* pin-controller instance 2 data */ - .pin_banks = exynos5250_pin_banks2, - .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - }, { - /* pin-controller instance 3 data */ - .pin_banks = exynos5250_pin_banks3, - .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos4_audio_retention_data, - }, -}; - -/* pin banks of exynos5260 pin-controller 0 */ -static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = { - EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), - EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10), - EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14), - EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18), - EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c), - EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20), - EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24), - EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28), - EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c), - EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30), - EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34), - EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38), - EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c), - EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40), - EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c), -}; - -/* pin banks of exynos5260 pin-controller 1 */ -static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = { - EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00), - EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04), - EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), - EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), - EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10), -}; - -/* pin banks of exynos5260 pin-controller 2 */ -static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = { - EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), - EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), -}; - -/* - * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes - * three gpio/pin-mux/pinconfig controllers. - */ -const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = { - { - /* pin-controller instance 0 data */ - .pin_banks = exynos5260_pin_banks0, - .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0), - .eint_gpio_init = exynos_eint_gpio_init, - .eint_wkup_init = exynos_eint_wkup_init, - }, { - /* pin-controller instance 1 data */ - .pin_banks = exynos5260_pin_banks1, - .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, - }, { - /* pin-controller instance 2 data */ - .pin_banks = exynos5260_pin_banks2, - .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2), - .eint_gpio_init = exynos_eint_gpio_init, - }, -}; - -/* pin banks of exynos5410 pin-controller 0 */ -static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), - EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), - EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18), - EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c), - EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20), - EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24), - EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28), - EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"), - EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c), - EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30), - EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34), - EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38), - EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c), - EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40), - EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44), - EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48), - EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c), - EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50), - EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"), - EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"), - EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"), - EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"), - EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"), - EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"), - EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"), - EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"), - EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"), - EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), -}; - -/* pin banks of exynos5410 pin-controller 1 */ -static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = { - EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00), - EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08), - EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c), - EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10), - EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14), - EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18), - EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c), - EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20), -}; - -/* pin banks of exynos5410 pin-controller 2 */ -static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00), - EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08), - EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c), - EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10), -}; - -/* pin banks of exynos5410 pin-controller 3 */ -static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = { - EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), -}; - -/* - * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes - * four gpio/pin-mux/pinconfig controllers. - */ -const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = { - { - /* pin-controller instance 0 data */ - .pin_banks = exynos5410_pin_banks0, - .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0), - .eint_gpio_init = exynos_eint_gpio_init, - .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - }, { - /* pin-controller instance 1 data */ - .pin_banks = exynos5410_pin_banks1, - .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - }, { - /* pin-controller instance 2 data */ - .pin_banks = exynos5410_pin_banks2, - .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - }, { - /* pin-controller instance 3 data */ - .pin_banks = exynos5410_pin_banks3, - .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - }, -}; - -/* pin banks of exynos5420 pin-controller 0 */ -static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c), -}; - -/* pin banks of exynos5420 pin-controller 1 */ -static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00), - EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04), - EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08), - EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c), - EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10), - EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14), - EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"), - EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"), - EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"), - EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"), - EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"), - EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"), - EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"), -}; - -/* pin banks of exynos5420 pin-controller 2 */ -static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00), - EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04), - EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08), - EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c), - EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10), - EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14), - EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18), - EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c), -}; - -/* pin banks of exynos5420 pin-controller 3 */ -static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c), - EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14), - EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18), - EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c), - EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20), -}; - -/* pin banks of exynos5420 pin-controller 4 */ -static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = { - EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00), -}; - -/* PMU pad retention groups registers for Exynos5420 (without audio) */ -static const u32 exynos5420_retention_regs[] = { - EXYNOS_PAD_RET_DRAM_OPTION, - EXYNOS_PAD_RET_JTAG_OPTION, - EXYNOS5420_PAD_RET_GPIO_OPTION, - EXYNOS5420_PAD_RET_UART_OPTION, - EXYNOS5420_PAD_RET_MMCA_OPTION, - EXYNOS5420_PAD_RET_MMCB_OPTION, - EXYNOS5420_PAD_RET_MMCC_OPTION, - EXYNOS5420_PAD_RET_HSI_OPTION, - EXYNOS_PAD_RET_EBIA_OPTION, - EXYNOS_PAD_RET_EBIB_OPTION, - EXYNOS5420_PAD_RET_SPI_OPTION, - EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION, -}; - -static const struct samsung_retention_data exynos5420_retention_data __initconst = { - .regs = exynos5420_retention_regs, - .nr_regs = ARRAY_SIZE(exynos5420_retention_regs), - .value = EXYNOS_WAKEUP_FROM_LOWPWR, - .refcnt = &exynos_shared_retention_refcnt, - .init = exynos_retention_init, -}; - -/* - * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes - * four gpio/pin-mux/pinconfig controllers. - */ -const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = { - { - /* pin-controller instance 0 data */ - .pin_banks = exynos5420_pin_banks0, - .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0), - .eint_gpio_init = exynos_eint_gpio_init, - .eint_wkup_init = exynos_eint_wkup_init, - .retention_data = &exynos5420_retention_data, - }, { - /* pin-controller instance 1 data */ - .pin_banks = exynos5420_pin_banks1, - .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, - .retention_data = &exynos5420_retention_data, - }, { - /* pin-controller instance 2 data */ - .pin_banks = exynos5420_pin_banks2, - .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2), - .eint_gpio_init = exynos_eint_gpio_init, - .retention_data = &exynos5420_retention_data, - }, { - /* pin-controller instance 3 data */ - .pin_banks = exynos5420_pin_banks3, - .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3), - .eint_gpio_init = exynos_eint_gpio_init, - .retention_data = &exynos5420_retention_data, - }, { - /* pin-controller instance 4 data */ - .pin_banks = exynos5420_pin_banks4, - .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4), - .eint_gpio_init = exynos_eint_gpio_init, - .retention_data = &exynos4_audio_retention_data, - }, -}; - -/* pin banks of exynos5433 pin-controller - ALIVE */ -static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = { - EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), - EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), - EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), - EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), - EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1), - EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1), - EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1), - EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1), - EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1), -}; - -/* pin banks of exynos5433 pin-controller - AUD */ -static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = { - EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), - EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), -}; - -/* pin banks of exynos5433 pin-controller - CPIF */ -static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = { - EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00), -}; - -/* pin banks of exynos5433 pin-controller - eSE */ -static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = { - EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00), -}; - -/* pin banks of exynos5433 pin-controller - FINGER */ -static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = { - EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00), -}; - -/* pin banks of exynos5433 pin-controller - FSYS */ -static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = { - EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00), - EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04), - EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08), - EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c), - EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10), - EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14), -}; - -/* pin banks of exynos5433 pin-controller - IMEM */ -static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = { - EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00), -}; - -/* pin banks of exynos5433 pin-controller - NFC */ -static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = { - EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), -}; - -/* pin banks of exynos5433 pin-controller - PERIC */ -static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = { - EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00), - EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04), - EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08), - EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c), - EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10), - EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14), - EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18), - EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c), - EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20), - EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24), - EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28), - EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c), - EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30), - EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34), - EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38), - EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c), - EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40), -}; - -/* pin banks of exynos5433 pin-controller - TOUCH */ -static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = { - EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), -}; - -/* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */ -static const u32 exynos5433_retention_regs[] = { - EXYNOS5433_PAD_RETENTION_TOP_OPTION, - EXYNOS5433_PAD_RETENTION_UART_OPTION, - EXYNOS5433_PAD_RETENTION_EBIA_OPTION, - EXYNOS5433_PAD_RETENTION_EBIB_OPTION, - EXYNOS5433_PAD_RETENTION_SPI_OPTION, - EXYNOS5433_PAD_RETENTION_MIF_OPTION, - EXYNOS5433_PAD_RETENTION_USBXTI_OPTION, - EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION, - EXYNOS5433_PAD_RETENTION_UFS_OPTION, - EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION, -}; - -static const struct samsung_retention_data exynos5433_retention_data __initconst = { - .regs = exynos5433_retention_regs, - .nr_regs = ARRAY_SIZE(exynos5433_retention_regs), - .value = EXYNOS_WAKEUP_FROM_LOWPWR, - .refcnt = &exynos_shared_retention_refcnt, - .init = exynos_retention_init, -}; - -/* PMU retention control for audio pins can be tied to audio pin bank */ -static const u32 exynos5433_audio_retention_regs[] = { - EXYNOS5433_PAD_RETENTION_AUD_OPTION, -}; - -static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = { - .regs = exynos5433_audio_retention_regs, - .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs), - .value = EXYNOS_WAKEUP_FROM_LOWPWR, - .init = exynos_retention_init, -}; - -/* PMU retention control for mmc pins can be tied to fsys pin bank */ -static const u32 exynos5433_fsys_retention_regs[] = { - EXYNOS5433_PAD_RETENTION_MMC0_OPTION, - EXYNOS5433_PAD_RETENTION_MMC1_OPTION, - EXYNOS5433_PAD_RETENTION_MMC2_OPTION, -}; - -static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = { - .regs = exynos5433_fsys_retention_regs, - .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs), - .value = EXYNOS_WAKEUP_FROM_LOWPWR, - .init = exynos_retention_init, -}; - -/* - * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes - * ten gpio/pin-mux/pinconfig controllers. - */ -const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = { - { - /* pin-controller instance 0 data */ - .pin_banks = exynos5433_pin_banks0, - .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0), - .eint_wkup_init = exynos_eint_wkup_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .nr_ext_resources = 1, - .retention_data = &exynos5433_retention_data, - }, { - /* pin-controller instance 1 data */ - .pin_banks = exynos5433_pin_banks1, - .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos5433_audio_retention_data, - }, { - /* pin-controller instance 2 data */ - .pin_banks = exynos5433_pin_banks2, - .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos5433_retention_data, - }, { - /* pin-controller instance 3 data */ - .pin_banks = exynos5433_pin_banks3, - .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos5433_retention_data, - }, { - /* pin-controller instance 4 data */ - .pin_banks = exynos5433_pin_banks4, - .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos5433_retention_data, - }, { - /* pin-controller instance 5 data */ - .pin_banks = exynos5433_pin_banks5, - .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos5433_fsys_retention_data, - }, { - /* pin-controller instance 6 data */ - .pin_banks = exynos5433_pin_banks6, - .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos5433_retention_data, - }, { - /* pin-controller instance 7 data */ - .pin_banks = exynos5433_pin_banks7, - .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos5433_retention_data, - }, { - /* pin-controller instance 8 data */ - .pin_banks = exynos5433_pin_banks8, - .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos5433_retention_data, - }, { - /* pin-controller instance 9 data */ - .pin_banks = exynos5433_pin_banks9, - .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9), - .eint_gpio_init = exynos_eint_gpio_init, - .suspend = exynos_pinctrl_suspend, - .resume = exynos_pinctrl_resume, - .retention_data = &exynos5433_retention_data, - }, -}; - -/* pin banks of exynos7 pin-controller - ALIVE */ -static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { - EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), - EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), - EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), - EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), -}; - -/* pin banks of exynos7 pin-controller - BUS0 */ -static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = { - EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00), - EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04), - EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08), - EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c), - EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10), - EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), - EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18), - EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c), - EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20), - EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24), - EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28), - EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c), - EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30), - EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34), - EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38), -}; - -/* pin banks of exynos7 pin-controller - NFC */ -static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = { - EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00), -}; - -/* pin banks of exynos7 pin-controller - TOUCH */ -static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = { - EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00), -}; - -/* pin banks of exynos7 pin-controller - FF */ -static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = { - EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00), -}; - -/* pin banks of exynos7 pin-controller - ESE */ -static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = { - EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00), -}; - -/* pin banks of exynos7 pin-controller - FSYS0 */ -static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = { - EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00), -}; - -/* pin banks of exynos7 pin-controller - FSYS1 */ -static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = { - EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00), - EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04), - EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08), - EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c), -}; - -/* pin banks of exynos7 pin-controller - BUS1 */ -static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = { - EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00), - EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04), - EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08), - EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c), - EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10), - EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14), - EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18), - EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c), - EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20), - EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24), -}; - -static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = { - EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00), - EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04), -}; - -const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = { - { - /* pin-controller instance 0 Alive data */ - .pin_banks = exynos7_pin_banks0, - .nr_banks = ARRAY_SIZE(exynos7_pin_banks0), - .eint_wkup_init = exynos_eint_wkup_init, - }, { - /* pin-controller instance 1 BUS0 data */ - .pin_banks = exynos7_pin_banks1, - .nr_banks = ARRAY_SIZE(exynos7_pin_banks1), - .eint_gpio_init = exynos_eint_gpio_init, - }, { - /* pin-controller instance 2 NFC data */ - .pin_banks = exynos7_pin_banks2, - .nr_banks = ARRAY_SIZE(exynos7_pin_banks2), - .eint_gpio_init = exynos_eint_gpio_init, - }, { - /* pin-controller instance 3 TOUCH data */ - .pin_banks = exynos7_pin_banks3, - .nr_banks = ARRAY_SIZE(exynos7_pin_banks3), - .eint_gpio_init = exynos_eint_gpio_init, - }, { - /* pin-controller instance 4 FF data */ - .pin_banks = exynos7_pin_banks4, - .nr_banks = ARRAY_SIZE(exynos7_pin_banks4), - .eint_gpio_init = exynos_eint_gpio_init, - }, { - /* pin-controller instance 5 ESE data */ - .pin_banks = exynos7_pin_banks5, - .nr_banks = ARRAY_SIZE(exynos7_pin_banks5), - .eint_gpio_init = exynos_eint_gpio_init, - }, { - /* pin-controller instance 6 FSYS0 data */ - .pin_banks = exynos7_pin_banks6, - .nr_banks = ARRAY_SIZE(exynos7_pin_banks6), - .eint_gpio_init = exynos_eint_gpio_init, - }, { - /* pin-controller instance 7 FSYS1 data */ - .pin_banks = exynos7_pin_banks7, - .nr_banks = ARRAY_SIZE(exynos7_pin_banks7), - .eint_gpio_init = exynos_eint_gpio_init, - }, { - /* pin-controller instance 8 BUS1 data */ - .pin_banks = exynos7_pin_banks8, - .nr_banks = ARRAY_SIZE(exynos7_pin_banks8), - .eint_gpio_init = exynos_eint_gpio_init, - }, { - /* pin-controller instance 9 AUD data */ - .pin_banks = exynos7_pin_banks9, - .nr_banks = ARRAY_SIZE(exynos7_pin_banks9), - .eint_gpio_init = exynos_eint_gpio_init, - }, -}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h index cd046eb7d705..b90139715c8f 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -17,6 +17,9 @@ * (at your option) any later version. */ +#ifndef __PINCTRL_SAMSUNG_EXYNOS_H +#define __PINCTRL_SAMSUNG_EXYNOS_H + /* External GPIO and wakeup interrupt related definitions */ #define EXYNOS_GPIO_ECON_OFFSET 0x700 #define EXYNOS_GPIO_EFLTCON_OFFSET 0x800 @@ -131,3 +134,13 @@ struct exynos_muxed_weint_data { unsigned int nr_banks; struct samsung_pin_bank *banks[]; }; + +int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d); +int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d); +void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata); +void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata); +struct samsung_retention_ctrl * +exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, + const struct samsung_retention_data *data); + +#endif /* __PINCTRL_SAMSUNG_EXYNOS_H */ diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c index 3000df80709f..32a3a9fd65c4 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos5440.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c @@ -1,6 +1,8 @@ /* * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC. * + * Author: Thomas Abraham <thomas.ab@samsung.com> + * * Copyright (c) 2012 Samsung Electronics Co., Ltd. * http://www.samsung.com * @@ -10,7 +12,7 @@ * (at your option) any later version. */ -#include <linux/module.h> +#include <linux/init.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/slab.h> @@ -991,7 +993,6 @@ static const struct of_device_id exynos5440_pinctrl_dt_match[] = { { .compatible = "samsung,exynos5440-pinctrl" }, {}, }; -MODULE_DEVICE_TABLE(of, exynos5440_pinctrl_dt_match); static struct platform_driver exynos5440_pinctrl_driver = { .probe = exynos5440_pinctrl_probe, @@ -1007,13 +1008,3 @@ static int __init exynos5440_pinctrl_drv_register(void) return platform_driver_register(&exynos5440_pinctrl_driver); } postcore_initcall(exynos5440_pinctrl_drv_register); - -static void __exit exynos5440_pinctrl_drv_unregister(void) -{ - platform_driver_unregister(&exynos5440_pinctrl_driver); -} -module_exit(exynos5440_pinctrl_drv_unregister); - -MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>"); -MODULE_DESCRIPTION("Samsung EXYNOS5440 SoC pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c index b82a003546ae..49774851e84a 100644 --- a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c +++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c @@ -13,7 +13,7 @@ * external gpio and wakeup interrupt support. */ -#include <linux/module.h> +#include <linux/init.h> #include <linux/device.h> #include <linux/interrupt.h> #include <linux/irqdomain.h> diff --git a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c index f17890aa6e25..4a88d7446e87 100644 --- a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c +++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c @@ -15,7 +15,7 @@ * external gpio and wakeup interrupt support. */ -#include <linux/module.h> +#include <linux/init.h> #include <linux/device.h> #include <linux/interrupt.h> #include <linux/irqdomain.h> diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c index a4a0da5d2a32..f542642eed8d 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -20,7 +20,7 @@ * and wakeup interrupts can be hooked to. */ -#include <linux/module.h> +#include <linux/init.h> #include <linux/platform_device.h> #include <linux/io.h> #include <linux/slab.h> @@ -1183,27 +1183,29 @@ static int __maybe_unused samsung_pinctrl_resume(struct device *dev) } static const struct of_device_id samsung_pinctrl_dt_match[] = { -#ifdef CONFIG_PINCTRL_EXYNOS +#ifdef CONFIG_PINCTRL_EXYNOS_ARM { .compatible = "samsung,exynos3250-pinctrl", - .data = (void *)exynos3250_pin_ctrl }, + .data = exynos3250_pin_ctrl }, { .compatible = "samsung,exynos4210-pinctrl", - .data = (void *)exynos4210_pin_ctrl }, + .data = exynos4210_pin_ctrl }, { .compatible = "samsung,exynos4x12-pinctrl", - .data = (void *)exynos4x12_pin_ctrl }, + .data = exynos4x12_pin_ctrl }, { .compatible = "samsung,exynos5250-pinctrl", - .data = (void *)exynos5250_pin_ctrl }, + .data = exynos5250_pin_ctrl }, { .compatible = "samsung,exynos5260-pinctrl", - .data = (void *)exynos5260_pin_ctrl }, + .data = exynos5260_pin_ctrl }, { .compatible = "samsung,exynos5410-pinctrl", - .data = (void *)exynos5410_pin_ctrl }, + .data = exynos5410_pin_ctrl }, { .compatible = "samsung,exynos5420-pinctrl", - .data = (void *)exynos5420_pin_ctrl }, - { .compatible = "samsung,exynos5433-pinctrl", - .data = (void *)exynos5433_pin_ctrl }, + .data = exynos5420_pin_ctrl }, { .compatible = "samsung,s5pv210-pinctrl", - .data = (void *)s5pv210_pin_ctrl }, + .data = s5pv210_pin_ctrl }, +#endif +#ifdef CONFIG_PINCTRL_EXYNOS_ARM64 + { .compatible = "samsung,exynos5433-pinctrl", + .data = exynos5433_pin_ctrl }, { .compatible = "samsung,exynos7-pinctrl", - .data = (void *)exynos7_pin_ctrl }, + .data = exynos7_pin_ctrl }, #endif #ifdef CONFIG_PINCTRL_S3C64XX { .compatible = "samsung,s3c64xx-pinctrl", @@ -1221,7 +1223,6 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = { #endif {}, }; -MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match); static const struct dev_pm_ops samsung_pinctrl_pm_ops = { SET_LATE_SYSTEM_SLEEP_PM_OPS(samsung_pinctrl_suspend, @@ -1243,13 +1244,3 @@ static int __init samsung_pinctrl_drv_register(void) return platform_driver_register(&samsung_pinctrl_driver); } postcore_initcall(samsung_pinctrl_drv_register); - -static void __exit samsung_pinctrl_drv_unregister(void) -{ - platform_driver_unregister(&samsung_pinctrl_driver); -} -module_exit(samsung_pinctrl_drv_unregister); - -MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>"); -MODULE_DESCRIPTION("Samsung pinctrl driver"); -MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 07eca54bdc1c..24f76a05a5a9 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -34,6 +34,16 @@ config PINCTRL_PFC_R8A7740 depends on ARCH_R8A7740 select PINCTRL_SH_PFC_GPIO +config PINCTRL_PFC_R8A7743 + def_bool y + depends on ARCH_R8A7743 + select PINCTRL_SH_PFC + +config PINCTRL_PFC_R8A7745 + def_bool y + depends on ARCH_R8A7745 + select PINCTRL_SH_PFC + config PINCTRL_PFC_R8A7778 def_bool y depends on ARCH_R8A7778 diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 8e08684774af..33d28eed9ba3 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -3,6 +3,8 @@ obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o +obj-$(CONFIG_PINCTRL_PFC_R8A7743) += pfc-r8a7791.o +obj-$(CONFIG_PINCTRL_PFC_R8A7745) += pfc-r8a7794.o obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index 4a5a0feb931b..e72391d5e57d 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -485,6 +485,18 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7740_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7743 + { + .compatible = "renesas,pfc-r8a7743", + .data = &r8a7743_pinmux_info, + }, +#endif +#ifdef CONFIG_PINCTRL_PFC_R8A7745 + { + .compatible = "renesas,pfc-r8a7745", + .data = &r8a7745_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7778 { .compatible = "renesas,pfc-r8a7778", diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c index 2ed7eeb50aac..4c5ffbd75be7 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c @@ -1,8 +1,8 @@ /* - * r8a7791 processor support - PFC hardware block. + * r8a7791/r8a7743 processor support - PFC hardware block. * * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2014-2015 Cogent Embedded, Inc. + * Copyright (C) 2014-2017 Cogent Embedded, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 @@ -119,22 +119,22 @@ enum { /* IPSR0 */ FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15, - FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B, + FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B, FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B, FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B, FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK, /* IPSR1 */ - FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_SCL0, - FN_A9, FN_MSIOF1_SS2, FN_SDA0, + FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, + FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D, - FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D, - FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D, + FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D, + FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D, FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D, FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D, FN_A15, FN_BPFCLK_C, FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B, - FN_A17, FN_DACK2_B, FN_SDA0_C, + FN_A17, FN_DACK2_B, FN_I2C0_SDA_C, FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C, /* IPSR2 */ @@ -145,8 +145,8 @@ enum { FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD, FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD, FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD, - FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, - FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, + FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, + FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, FN_EX_CS1_N, FN_MSIOF2_SCK, FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1, @@ -169,12 +169,13 @@ enum { FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C, /* IPSR4 */ - FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, - FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, FN_MSIOF2_SYNC_C, FN_GLO_I0_D, - FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D, - FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C, - FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E, - FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E, + FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, + FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C, + FN_GLO_I0_D, + FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D, + FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C, + FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E, + FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E, FN_GLO_Q1_D, FN_HCTS1_N_E, FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E, FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3, @@ -210,10 +211,10 @@ enum { FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, - FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, - FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, - FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E, - FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E, + FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, + FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, + FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, + FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E, FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D, FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D, @@ -257,16 +258,16 @@ enum { FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX, /* IPSR9 */ - FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD, - FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, FN_SCIF3_SCK, FN_SCIFA3_SCK, + FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD, + FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_QSTVA_QVS, FN_DU1_DOTCLKOUT0, FN_QCLK, FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX, - FN_TX3_B, FN_SCL2_B, FN_PWM4, + FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4, FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS, FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE, - FN_CAN0_RX, FN_RX3_B, FN_SDA2_B, + FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B, FN_DU1_DISP, FN_QPOLA, FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D, @@ -274,15 +275,15 @@ enum { FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D, FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D, FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, - FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4, + FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL, FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, /* IPSR10 */ - FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4, + FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA, FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, - FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B, + FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B, FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, - FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B, + FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B, FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C, FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D, @@ -296,13 +297,13 @@ enum { FN_TS_SCK0_C, FN_ATAG1_N, FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C, FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C, - FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D, + FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D, /* IPSR11 */ - FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, - FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, + FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D, + FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B, FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, - FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, + FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B, FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B, FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, @@ -312,15 +313,15 @@ enum { FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO, FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC, FN_VI1_DATA7, FN_AVB_MDC, - FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, - FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, + FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, + FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, /* IPSR12 */ - FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, - FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, + FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, + FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA, FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, - FN_SCL2_D, FN_MSIOF1_RXD_E, - FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E, + FN_I2C2_SCL_D, FN_MSIOF1_RXD_E, + FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_I2C2_SDA_D, FN_MSIOF1_SCK_E, FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B, FN_CAN1_RX_C, FN_MSIOF1_SYNC_E, FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B, @@ -351,23 +352,23 @@ enum { FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B, FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B, FN_SD1_DATA3, FN_IERX_B, - FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C, + FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C, /* IPSR14 */ - FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, + FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD, FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1, FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3, - FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C, - FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C, + FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C, + FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C, FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B, FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B, FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B, FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B, FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, - FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, + FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, - FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, + FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, /* IPSR15 */ FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, @@ -432,18 +433,18 @@ enum { /* MOD_SEL3 */ FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3, FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, - FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, - FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, - FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, - FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, + FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, + FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_MMC_0, FN_SEL_MMC_1, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, - FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, - FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, - FN_SEL_IIC1_4, - FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, + FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3, + FN_SEL_I2C1_4, + FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, /* MOD_SEL4 */ FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3, @@ -481,22 +482,23 @@ enum { D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK, D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK, - A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, SCL0_C_MARK, PWM2_B_MARK, + A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, I2C0_SCL_C_MARK, + PWM2_B_MARK, A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK, A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK, A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK, /* IPSR1 */ - A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, SCL0_MARK, - A9_MARK, MSIOF1_SS2_MARK, SDA0_MARK, + A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, I2C0_SCL_MARK, + A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK, A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK, - A11_MARK, MSIOF1_RXD_MARK, SCL3_D_MARK, MSIOF1_RXD_D_MARK, - A12_MARK, FMCLK_MARK, SDA3_D_MARK, MSIOF1_SCK_D_MARK, + A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK, + A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK, A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK, A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK, A15_MARK, BPFCLK_C_MARK, A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK, - A17_MARK, DACK2_B_MARK, SDA0_C_MARK, + A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK, A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK, /* IPSR2 */ @@ -509,8 +511,8 @@ enum { A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK, A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK, RX1_MARK, SCIFA1_RXD_MARK, - CS0_N_MARK, ATAG0_N_B_MARK, SCL1_MARK, - CS1_N_A26_MARK, ATADIR0_N_B_MARK, SDA1_MARK, + CS0_N_MARK, ATAG0_N_B_MARK, I2C1_SCL_MARK, + CS1_N_A26_MARK, ATADIR0_N_B_MARK, I2C1_SDA_MARK, EX_CS1_N_MARK, MSIOF2_SCK_MARK, EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK, EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK, @@ -537,14 +539,15 @@ enum { SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK, /* IPSR4 */ - SSI_SDATA0_MARK, SCL0_B_MARK, SCL7_B_MARK, MSIOF2_SCK_C_MARK, - SSI_SCK1_MARK, SDA0_B_MARK, SDA7_B_MARK, + SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK, + SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK, MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK, - SSI_WS1_MARK, SCL1_B_MARK, SCL8_B_MARK, + SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK, MSIOF2_TXD_C_MARK, GLO_I1_D_MARK, - SSI_SDATA1_MARK, SDA1_B_MARK, SDA8_B_MARK, MSIOF2_RXD_C_MARK, - SSI_SCK2_MARK, SCL2_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, HSCK1_E_MARK, - SSI_WS2_MARK, SDA2_MARK, GPS_SIGN_B_MARK, RX2_E_MARK, + SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK, + SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, + HSCK1_E_MARK, + SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK, GLO_Q1_D_MARK, HCTS1_N_E_MARK, SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK, SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK, @@ -580,12 +583,12 @@ enum { IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK, IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK, IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK, - IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK, - IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK, + IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK, + IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK, MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK, - IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK, + IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK, IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK, - SDA1_E_MARK, MSIOF2_SYNC_E_MARK, + I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK, IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK, GPS_CLK_C_MARK, GPS_CLK_D_MARK, IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK, @@ -632,17 +635,17 @@ enum { DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK, /* IPSR9 */ - DU1_DB6_MARK, LCDOUT22_MARK, SCL3_C_MARK, RX3_MARK, SCIFA3_RXD_MARK, - DU1_DB7_MARK, LCDOUT23_MARK, SDA3_C_MARK, + DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK, + DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK, SCIF3_SCK_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK, DU1_DOTCLKOUT0_MARK, QCLK_MARK, DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK, - TX3_B_MARK, SCL2_B_MARK, PWM4_MARK, + TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, - CAN0_RX_MARK, RX3_B_MARK, SDA2_B_MARK, + CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK, DU1_DISP_MARK, QPOLA_MARK, DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK, VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK, @@ -650,15 +653,15 @@ enum { VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK, VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK, VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK, - VI0_G0_MARK, SCL8_MARK, STP_IVCXO27_0_C_MARK, SCL4_MARK, + VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK, HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK, /* IPSR10 */ - VI0_G1_MARK, SDA8_MARK, STP_ISCLK_0_C_MARK, SDA4_MARK, + VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK, HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK, - VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, SCL3_B_MARK, + VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK, HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK, - VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, SDA3_B_MARK, + VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK, HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK, VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK, HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK, @@ -672,13 +675,15 @@ enum { TS_SCK0_C_MARK, ATAG1_N_MARK, VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK, VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK, - VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, SCL1_D_MARK, + VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, + I2C1_SCL_D_MARK, /* IPSR11 */ - VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK, - VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK, + VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, + I2C1_SDA_D_MARK, + VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK, VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK, - SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK, + I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK, VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK, TX4_B_MARK, SCIFA4_TXD_B_MARK, VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK, @@ -690,16 +695,16 @@ enum { VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK, VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK, VI1_DATA7_MARK, AVB_MDC_MARK, - ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK, - ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK, + ETH_MDIO_MARK, AVB_RX_CLK_MARK, I2C2_SCL_C_MARK, + ETH_CRS_DV_MARK, AVB_LINK_MARK, I2C2_SDA_C_MARK, /* IPSR12 */ - ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK, - ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK, + ETH_RX_ER_MARK, AVB_CRS_MARK, I2C3_SCL_MARK, IIC0_SCL_MARK, + ETH_RXD0_MARK, AVB_PHY_INT_MARK, I2C3_SDA_MARK, IIC0_SDA_MARK, ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK, - SCL2_D_MARK, MSIOF1_RXD_E_MARK, + I2C2_SCL_D_MARK, MSIOF1_RXD_E_MARK, ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK, - SDA2_D_MARK, MSIOF1_SCK_E_MARK, + I2C2_SDA_D_MARK, MSIOF1_SCK_E_MARK, ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK, CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK, ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK, @@ -730,15 +735,17 @@ enum { SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK, SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK, SD1_DATA3_MARK, IERX_B_MARK, - SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK, + SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK, /* IPSR14 */ - SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK, + SD1_WP_MARK, PWM1_B_MARK, I2C1_SDA_C_MARK, SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK, SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK, SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK, - SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK, - SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK, + SD2_CD_MARK, MMC_D4_MARK, IIC1_SCL_C_MARK, TX5_B_MARK, + SCIFA5_TXD_C_MARK, + SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK, + SCIFA5_RXD_C_MARK, MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK, VI1_CLK_C_MARK, VI1_G0_B_MARK, MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK, @@ -746,9 +753,9 @@ enum { MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK, MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK, MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK, - VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK, + VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK, MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK, - VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK, + VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK, /* IPSR15 */ SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK, @@ -822,7 +829,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP0_18_16, A0), PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2), PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1), - PINMUX_IPSR_MSEL(IP0_18_16, SCL0_C, SEL_IIC0_2), + PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2), PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B), PINMUX_IPSR_GPSR(IP0_20_19, A1), PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1), @@ -842,20 +849,20 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0), PINMUX_IPSR_GPSR(IP1_3_2, A8), PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0), - PINMUX_IPSR_MSEL(IP1_3_2, SCL0, SEL_IIC0_0), + PINMUX_IPSR_MSEL(IP1_3_2, I2C0_SCL, SEL_I2C0_0), PINMUX_IPSR_GPSR(IP1_5_4, A9), PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0), - PINMUX_IPSR_MSEL(IP1_5_4, SDA0, SEL_IIC0_0), + PINMUX_IPSR_MSEL(IP1_5_4, I2C0_SDA, SEL_I2C0_0), PINMUX_IPSR_GPSR(IP1_7_6, A10), PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0), PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3), PINMUX_IPSR_GPSR(IP1_10_8, A11), PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0), - PINMUX_IPSR_MSEL(IP1_10_8, SCL3_D, SEL_IIC3_3), + PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3), PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3), PINMUX_IPSR_GPSR(IP1_13_11, A12), PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0), - PINMUX_IPSR_MSEL(IP1_13_11, SDA3_D, SEL_IIC3_3), + PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3), PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3), PINMUX_IPSR_GPSR(IP1_16_14, A13), PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2), @@ -874,7 +881,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1), PINMUX_IPSR_GPSR(IP1_28_26, A17), PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1), - PINMUX_IPSR_MSEL(IP1_28_26, SDA0_C, SEL_IIC0_2), + PINMUX_IPSR_MSEL(IP1_28_26, I2C0_SDA_C, SEL_I2C0_2), PINMUX_IPSR_GPSR(IP1_31_29, A18), PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0), PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2), @@ -914,10 +921,10 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0), PINMUX_IPSR_GPSR(IP2_20_19, CS0_N), PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1), - PINMUX_IPSR_MSEL(IP2_20_19, SCL1, SEL_IIC1_0), + PINMUX_IPSR_MSEL(IP2_20_19, I2C1_SCL, SEL_I2C1_0), PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26), PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1), - PINMUX_IPSR_MSEL(IP2_22_21, SDA1, SEL_IIC1_0), + PINMUX_IPSR_MSEL(IP2_22_21, I2C1_SDA, SEL_I2C1_0), PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N), PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0), PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N), @@ -989,30 +996,30 @@ static const u16 pinmux_data[] = { /* IPSR4 */ PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0), - PINMUX_IPSR_MSEL(IP4_1_0, SCL0_B, SEL_IIC0_1), - PINMUX_IPSR_MSEL(IP4_1_0, SCL7_B, SEL_IIC7_1), + PINMUX_IPSR_MSEL(IP4_1_0, I2C0_SCL_B, SEL_I2C0_1), + PINMUX_IPSR_MSEL(IP4_1_0, IIC0_SCL_B, SEL_IIC0_1), PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2), PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0), - PINMUX_IPSR_MSEL(IP4_4_2, SDA0_B, SEL_IIC0_1), - PINMUX_IPSR_MSEL(IP4_4_2, SDA7_B, SEL_IIC7_1), + PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1), + PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1), PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2), PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3), PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0), - PINMUX_IPSR_MSEL(IP4_7_5, SCL1_B, SEL_IIC1_1), - PINMUX_IPSR_MSEL(IP4_7_5, SCL8_B, SEL_IIC8_1), + PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1), + PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1), PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2), PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3), PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0), - PINMUX_IPSR_MSEL(IP4_9_8, SDA1_B, SEL_IIC1_1), - PINMUX_IPSR_MSEL(IP4_9_8, SDA8_B, SEL_IIC8_1), + PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1), + PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1), PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2), PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2), - PINMUX_IPSR_MSEL(IP4_12_10, SCL2, SEL_IIC2_0), + PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1), PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3), PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4), PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2), - PINMUX_IPSR_MSEL(IP4_15_13, SDA2, SEL_IIC2_0), + PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0), PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1), PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4), PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3), @@ -1115,22 +1122,22 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3), PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N), PINMUX_IPSR_GPSR(IP6_15_14, IRQ3), - PINMUX_IPSR_MSEL(IP6_15_14, SCL4_C, SEL_IIC4_2), + PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2), PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4), PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N), PINMUX_IPSR_GPSR(IP6_18_16, IRQ4), PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2), - PINMUX_IPSR_MSEL(IP6_18_16, SDA4_C, SEL_IIC4_2), + PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2), PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4), PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N), PINMUX_IPSR_GPSR(IP6_20_19, IRQ5), PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2), - PINMUX_IPSR_MSEL(IP6_20_19, SCL1_E, SEL_IIC1_4), + PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4), PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4), PINMUX_IPSR_GPSR(IP6_23_21, IRQ6), PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2), PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1), - PINMUX_IPSR_MSEL(IP6_23_21, SDA1_E, SEL_IIC1_4), + PINMUX_IPSR_MSEL(IP6_23_21, I2C1_SDA_E, SEL_I2C1_4), PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4), PINMUX_IPSR_GPSR(IP6_26_24, IRQ7), PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2), @@ -1260,12 +1267,12 @@ static const u16 pinmux_data[] = { /* IPSR9 */ PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6), PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22), - PINMUX_IPSR_MSEL(IP9_2_0, SCL3_C, SEL_IIC3_2), + PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2), PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0), PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0), PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7), PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23), - PINMUX_IPSR_MSEL(IP9_5_3, SDA3_C, SEL_IIC3_2), + PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2), PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0), PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0), PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0), @@ -1276,7 +1283,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE), PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0), PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1), - PINMUX_IPSR_MSEL(IP9_10_8, SCL2_B, SEL_IIC2_1), + PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1), PINMUX_IPSR_GPSR(IP9_10_8, PWM4), PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC), PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS), @@ -1286,7 +1293,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE), PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0), PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1), - PINMUX_IPSR_MSEL(IP9_15_13, SDA2_B, SEL_IIC2_1), + PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1), PINMUX_IPSR_GPSR(IP9_16, DU1_DISP), PINMUX_IPSR_GPSR(IP9_16, QPOLA), PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE), @@ -1312,32 +1319,32 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1), PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1), PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0), - PINMUX_IPSR_MSEL(IP9_31_29, SCL8, SEL_IIC8_0), + PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0), PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2), - PINMUX_IPSR_MSEL(IP9_31_29, SCL4, SEL_IIC4_0), + PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0), PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0), PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N), /* IPSR10 */ PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1), - PINMUX_IPSR_MSEL(IP10_2_0, SDA8, SEL_IIC8_0), + PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0), PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2), - PINMUX_IPSR_MSEL(IP10_2_0, SDA4, SEL_IIC4_0), + PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0), PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0), PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N), PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2), PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N), PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2), - PINMUX_IPSR_MSEL(IP10_5_3, SCL3_B, SEL_IIC3_1), + PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1), PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0), PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N), PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3), PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N), PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2), - PINMUX_IPSR_MSEL(IP10_8_6, SDA3_B, SEL_IIC3_1), + PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1), PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0), PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N), @@ -1382,24 +1389,24 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5), PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1), PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2), - PINMUX_IPSR_MSEL(IP10_31_29, SCL1_D, SEL_IIC1_3), + PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3), /* IPSR11 */ PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5), PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6), PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1), PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2), - PINMUX_IPSR_MSEL(IP11_2_0, SDA1_D, SEL_IIC1_3), + PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3), PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6), PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7), PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1), PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2), - PINMUX_IPSR_MSEL(IP11_5_3, SCL4_B, SEL_IIC4_1), + PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1), PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7), PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1), PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2), PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4), - PINMUX_IPSR_MSEL(IP11_8_6, SDA4_B, SEL_IIC4_1), + PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1), PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3), PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3), PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0), @@ -1438,29 +1445,29 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP11_27, AVB_MDC), PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO), PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK), - PINMUX_IPSR_MSEL(IP11_29_28, SCL2_C, SEL_IIC2_2), + PINMUX_IPSR_MSEL(IP11_29_28, I2C2_SCL_C, SEL_I2C2_2), PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV), PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK), - PINMUX_IPSR_MSEL(IP11_31_30, SDA2_C, SEL_IIC2_2), + PINMUX_IPSR_MSEL(IP11_31_30, I2C2_SDA_C, SEL_I2C2_2), /* IPSR12 */ PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER), PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS), - PINMUX_IPSR_MSEL(IP12_1_0, SCL3, SEL_IIC3_0), - PINMUX_IPSR_MSEL(IP12_1_0, SCL7, SEL_IIC7_0), + PINMUX_IPSR_MSEL(IP12_1_0, I2C3_SCL, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP12_1_0, IIC0_SCL, SEL_IIC0_0), PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0), PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT), - PINMUX_IPSR_MSEL(IP12_3_2, SDA3, SEL_IIC3_0), - PINMUX_IPSR_MSEL(IP12_3_2, SDA7, SEL_IIC7_0), + PINMUX_IPSR_MSEL(IP12_3_2, I2C3_SDA, SEL_I2C3_0), + PINMUX_IPSR_MSEL(IP12_3_2, IIC0_SDA, SEL_IIC0_0), PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1), PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK), PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2), - PINMUX_IPSR_MSEL(IP12_6_4, SCL2_D, SEL_IIC2_3), + PINMUX_IPSR_MSEL(IP12_6_4, I2C2_SCL_D, SEL_I2C2_3), PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4), PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK), PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0), PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2), - PINMUX_IPSR_MSEL(IP12_9_7, SDA2_D, SEL_IIC2_3), + PINMUX_IPSR_MSEL(IP12_9_7, I2C2_SDA_D, SEL_I2C2_3), PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4), PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK), PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1), @@ -1552,12 +1559,12 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD), PINMUX_IPSR_GPSR(IP13_30_28, PWM0), PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0), - PINMUX_IPSR_MSEL(IP13_30_28, SCL1_C, SEL_IIC1_2), + PINMUX_IPSR_MSEL(IP13_30_28, I2C1_SCL_C, SEL_I2C1_2), /* IPSR14 */ PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP), PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B), - PINMUX_IPSR_MSEL(IP14_1_0, SDA1_C, SEL_IIC1_2), + PINMUX_IPSR_MSEL(IP14_1_0, I2C1_SDA_C, SEL_I2C1_2), PINMUX_IPSR_GPSR(IP14_2, SD2_CLK), PINMUX_IPSR_GPSR(IP14_2, MMC_CLK), PINMUX_IPSR_GPSR(IP14_3, SD2_CMD), @@ -1572,12 +1579,12 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP14_7, MMC_D3), PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD), PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4), - PINMUX_IPSR_MSEL(IP14_10_8, SCL8_C, SEL_IIC8_2), + PINMUX_IPSR_MSEL(IP14_10_8, IIC1_SCL_C, SEL_IIC1_2), PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1), PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2), PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP), PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5), - PINMUX_IPSR_MSEL(IP14_13_11, SDA8_C, SEL_IIC8_2), + PINMUX_IPSR_MSEL(IP14_13_11, IIC1_SDA_C, SEL_IIC1_2), PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1), PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2), PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0), @@ -1603,14 +1610,14 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0), PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4), PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2), - PINMUX_IPSR_MSEL(IP14_28_26, SCL7_C, SEL_IIC7_2), + PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2), PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B), PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0), PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0), PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0), PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4), PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2), - PINMUX_IPSR_MSEL(IP14_31_29, SDA7_C, SEL_IIC7_2), + PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2), PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B), /* IPSR15 */ @@ -2343,21 +2350,21 @@ static const unsigned int i2c0_pins[] = { RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), }; static const unsigned int i2c0_mux[] = { - SCL0_MARK, SDA0_MARK, + I2C0_SCL_MARK, I2C0_SDA_MARK, }; static const unsigned int i2c0_b_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), }; static const unsigned int i2c0_b_mux[] = { - SCL0_B_MARK, SDA0_B_MARK, + I2C0_SCL_B_MARK, I2C0_SDA_B_MARK, }; static const unsigned int i2c0_c_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1), }; static const unsigned int i2c0_c_mux[] = { - SCL0_C_MARK, SDA0_C_MARK, + I2C0_SCL_C_MARK, I2C0_SDA_C_MARK, }; /* - I2C1 ------------------------------------------------------------------- */ static const unsigned int i2c1_pins[] = { @@ -2365,35 +2372,35 @@ static const unsigned int i2c1_pins[] = { RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11), }; static const unsigned int i2c1_mux[] = { - SCL1_MARK, SDA1_MARK, + I2C1_SCL_MARK, I2C1_SDA_MARK, }; static const unsigned int i2c1_b_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), }; static const unsigned int i2c1_b_mux[] = { - SCL1_B_MARK, SDA1_B_MARK, + I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, }; static const unsigned int i2c1_c_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), }; static const unsigned int i2c1_c_mux[] = { - SCL1_C_MARK, SDA1_C_MARK, + I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, }; static const unsigned int i2c1_d_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26), }; static const unsigned int i2c1_d_mux[] = { - SCL1_D_MARK, SDA1_D_MARK, + I2C1_SCL_D_MARK, I2C1_SDA_D_MARK, }; static const unsigned int i2c1_e_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16), }; static const unsigned int i2c1_e_mux[] = { - SCL1_E_MARK, SDA1_E_MARK, + I2C1_SCL_E_MARK, I2C1_SDA_E_MARK, }; /* - I2C2 ------------------------------------------------------------------- */ static const unsigned int i2c2_pins[] = { @@ -2401,28 +2408,28 @@ static const unsigned int i2c2_pins[] = { RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7), }; static const unsigned int i2c2_mux[] = { - SCL2_MARK, SDA2_MARK, + I2C2_SCL_MARK, I2C2_SDA_MARK, }; static const unsigned int i2c2_b_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29), }; static const unsigned int i2c2_b_mux[] = { - SCL2_B_MARK, SDA2_B_MARK, + I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, }; static const unsigned int i2c2_c_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), }; static const unsigned int i2c2_c_mux[] = { - SCL2_C_MARK, SDA2_C_MARK, + I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, }; static const unsigned int i2c2_d_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), }; static const unsigned int i2c2_d_mux[] = { - SCL2_D_MARK, SDA2_D_MARK, + I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, }; /* - I2C3 ------------------------------------------------------------------- */ static const unsigned int i2c3_pins[] = { @@ -2430,28 +2437,28 @@ static const unsigned int i2c3_pins[] = { RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), }; static const unsigned int i2c3_mux[] = { - SCL3_MARK, SDA3_MARK, + I2C3_SCL_MARK, I2C3_SDA_MARK, }; static const unsigned int i2c3_b_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), }; static const unsigned int i2c3_b_mux[] = { - SCL3_B_MARK, SDA3_B_MARK, + I2C3_SCL_B_MARK, I2C3_SDA_B_MARK, }; static const unsigned int i2c3_c_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), }; static const unsigned int i2c3_c_mux[] = { - SCL3_C_MARK, SDA3_C_MARK, + I2C3_SCL_C_MARK, I2C3_SDA_C_MARK, }; static const unsigned int i2c3_d_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), }; static const unsigned int i2c3_d_mux[] = { - SCL3_D_MARK, SDA3_D_MARK, + I2C3_SCL_D_MARK, I2C3_SDA_D_MARK, }; /* - I2C4 ------------------------------------------------------------------- */ static const unsigned int i2c4_pins[] = { @@ -2459,21 +2466,21 @@ static const unsigned int i2c4_pins[] = { RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), }; static const unsigned int i2c4_mux[] = { - SCL4_MARK, SDA4_MARK, + I2C4_SCL_MARK, I2C4_SDA_MARK, }; static const unsigned int i2c4_b_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28), }; static const unsigned int i2c4_b_mux[] = { - SCL4_B_MARK, SDA4_B_MARK, + I2C4_SCL_B_MARK, I2C4_SDA_B_MARK, }; static const unsigned int i2c4_c_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14), }; static const unsigned int i2c4_c_mux[] = { - SCL4_C_MARK, SDA4_C_MARK, + I2C4_SCL_C_MARK, I2C4_SDA_C_MARK, }; /* - I2C7 ------------------------------------------------------------------- */ static const unsigned int i2c7_pins[] = { @@ -2481,21 +2488,21 @@ static const unsigned int i2c7_pins[] = { RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), }; static const unsigned int i2c7_mux[] = { - SCL7_MARK, SDA7_MARK, + IIC0_SCL_MARK, IIC0_SDA_MARK, }; static const unsigned int i2c7_b_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), }; static const unsigned int i2c7_b_mux[] = { - SCL7_B_MARK, SDA7_B_MARK, + IIC0_SCL_B_MARK, IIC0_SDA_B_MARK, }; static const unsigned int i2c7_c_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), }; static const unsigned int i2c7_c_mux[] = { - SCL7_C_MARK, SDA7_C_MARK, + IIC0_SCL_C_MARK, IIC0_SDA_C_MARK, }; /* - I2C8 ------------------------------------------------------------------- */ static const unsigned int i2c8_pins[] = { @@ -2503,21 +2510,21 @@ static const unsigned int i2c8_pins[] = { RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), }; static const unsigned int i2c8_mux[] = { - SCL8_MARK, SDA8_MARK, + IIC1_SCL_MARK, IIC1_SDA_MARK, }; static const unsigned int i2c8_b_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), }; static const unsigned int i2c8_b_mux[] = { - SCL8_B_MARK, SDA8_B_MARK, + IIC1_SCL_B_MARK, IIC1_SDA_B_MARK, }; static const unsigned int i2c8_c_pins[] = { /* SCL, SDA */ RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23), }; static const unsigned int i2c8_c_mux[] = { - SCL8_C_MARK, SDA8_C_MARK, + IIC1_SCL_C_MARK, IIC1_SDA_C_MARK, }; /* - INTC ------------------------------------------------------------------- */ static const unsigned int intc_irq0_pins[] = { @@ -4412,357 +4419,364 @@ static const unsigned int vin2_clk_mux[] = { VI2_CLK_MARK, }; -static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(adi_common), - SH_PFC_PIN_GROUP(adi_chsel0), - SH_PFC_PIN_GROUP(adi_chsel1), - SH_PFC_PIN_GROUP(adi_chsel2), - SH_PFC_PIN_GROUP(adi_common_b), - SH_PFC_PIN_GROUP(adi_chsel0_b), - SH_PFC_PIN_GROUP(adi_chsel1_b), - SH_PFC_PIN_GROUP(adi_chsel2_b), - SH_PFC_PIN_GROUP(audio_clk_a), - SH_PFC_PIN_GROUP(audio_clk_b), - SH_PFC_PIN_GROUP(audio_clk_b_b), - SH_PFC_PIN_GROUP(audio_clk_c), - SH_PFC_PIN_GROUP(audio_clkout), - SH_PFC_PIN_GROUP(avb_link), - SH_PFC_PIN_GROUP(avb_magic), - SH_PFC_PIN_GROUP(avb_phy_int), - SH_PFC_PIN_GROUP(avb_mdio), - SH_PFC_PIN_GROUP(avb_mii), - SH_PFC_PIN_GROUP(avb_gmii), - SH_PFC_PIN_GROUP(can0_data), - SH_PFC_PIN_GROUP(can0_data_b), - SH_PFC_PIN_GROUP(can0_data_c), - SH_PFC_PIN_GROUP(can0_data_d), - SH_PFC_PIN_GROUP(can0_data_e), - SH_PFC_PIN_GROUP(can0_data_f), - SH_PFC_PIN_GROUP(can1_data), - SH_PFC_PIN_GROUP(can1_data_b), - SH_PFC_PIN_GROUP(can1_data_c), - SH_PFC_PIN_GROUP(can1_data_d), - SH_PFC_PIN_GROUP(can_clk), - SH_PFC_PIN_GROUP(can_clk_b), - SH_PFC_PIN_GROUP(can_clk_c), - SH_PFC_PIN_GROUP(can_clk_d), - SH_PFC_PIN_GROUP(du_rgb666), - SH_PFC_PIN_GROUP(du_rgb888), - SH_PFC_PIN_GROUP(du_clk_out_0), - SH_PFC_PIN_GROUP(du_clk_out_1), - SH_PFC_PIN_GROUP(du_sync), - SH_PFC_PIN_GROUP(du_oddf), - SH_PFC_PIN_GROUP(du_cde), - SH_PFC_PIN_GROUP(du_disp), - SH_PFC_PIN_GROUP(du0_clk_in), - SH_PFC_PIN_GROUP(du1_clk_in), - SH_PFC_PIN_GROUP(du1_clk_in_b), - SH_PFC_PIN_GROUP(du1_clk_in_c), - SH_PFC_PIN_GROUP(eth_link), - SH_PFC_PIN_GROUP(eth_magic), - SH_PFC_PIN_GROUP(eth_mdio), - SH_PFC_PIN_GROUP(eth_rmii), - SH_PFC_PIN_GROUP(hscif0_data), - SH_PFC_PIN_GROUP(hscif0_clk), - SH_PFC_PIN_GROUP(hscif0_ctrl), - SH_PFC_PIN_GROUP(hscif0_data_b), - SH_PFC_PIN_GROUP(hscif0_ctrl_b), - SH_PFC_PIN_GROUP(hscif0_data_c), - SH_PFC_PIN_GROUP(hscif0_clk_c), - SH_PFC_PIN_GROUP(hscif1_data), - SH_PFC_PIN_GROUP(hscif1_clk), - SH_PFC_PIN_GROUP(hscif1_ctrl), - SH_PFC_PIN_GROUP(hscif1_data_b), - SH_PFC_PIN_GROUP(hscif1_data_c), - SH_PFC_PIN_GROUP(hscif1_clk_c), - SH_PFC_PIN_GROUP(hscif1_ctrl_c), - SH_PFC_PIN_GROUP(hscif1_data_d), - SH_PFC_PIN_GROUP(hscif1_data_e), - SH_PFC_PIN_GROUP(hscif1_clk_e), - SH_PFC_PIN_GROUP(hscif1_ctrl_e), - SH_PFC_PIN_GROUP(hscif2_data), - SH_PFC_PIN_GROUP(hscif2_clk), - SH_PFC_PIN_GROUP(hscif2_ctrl), - SH_PFC_PIN_GROUP(hscif2_data_b), - SH_PFC_PIN_GROUP(hscif2_ctrl_b), - SH_PFC_PIN_GROUP(hscif2_data_c), - SH_PFC_PIN_GROUP(hscif2_clk_c), - SH_PFC_PIN_GROUP(hscif2_data_d), - SH_PFC_PIN_GROUP(i2c0), - SH_PFC_PIN_GROUP(i2c0_b), - SH_PFC_PIN_GROUP(i2c0_c), - SH_PFC_PIN_GROUP(i2c1), - SH_PFC_PIN_GROUP(i2c1_b), - SH_PFC_PIN_GROUP(i2c1_c), - SH_PFC_PIN_GROUP(i2c1_d), - SH_PFC_PIN_GROUP(i2c1_e), - SH_PFC_PIN_GROUP(i2c2), - SH_PFC_PIN_GROUP(i2c2_b), - SH_PFC_PIN_GROUP(i2c2_c), - SH_PFC_PIN_GROUP(i2c2_d), - SH_PFC_PIN_GROUP(i2c3), - SH_PFC_PIN_GROUP(i2c3_b), - SH_PFC_PIN_GROUP(i2c3_c), - SH_PFC_PIN_GROUP(i2c3_d), - SH_PFC_PIN_GROUP(i2c4), - SH_PFC_PIN_GROUP(i2c4_b), - SH_PFC_PIN_GROUP(i2c4_c), - SH_PFC_PIN_GROUP(i2c7), - SH_PFC_PIN_GROUP(i2c7_b), - SH_PFC_PIN_GROUP(i2c7_c), - SH_PFC_PIN_GROUP(i2c8), - SH_PFC_PIN_GROUP(i2c8_b), - SH_PFC_PIN_GROUP(i2c8_c), - SH_PFC_PIN_GROUP(intc_irq0), - SH_PFC_PIN_GROUP(intc_irq1), - SH_PFC_PIN_GROUP(intc_irq2), - SH_PFC_PIN_GROUP(intc_irq3), - SH_PFC_PIN_GROUP(mlb_3pin), - SH_PFC_PIN_GROUP(mmc_data1), - SH_PFC_PIN_GROUP(mmc_data4), - SH_PFC_PIN_GROUP(mmc_data8), - SH_PFC_PIN_GROUP(mmc_ctrl), - SH_PFC_PIN_GROUP(msiof0_clk), - SH_PFC_PIN_GROUP(msiof0_sync), - SH_PFC_PIN_GROUP(msiof0_ss1), - SH_PFC_PIN_GROUP(msiof0_ss2), - SH_PFC_PIN_GROUP(msiof0_rx), - SH_PFC_PIN_GROUP(msiof0_tx), - SH_PFC_PIN_GROUP(msiof0_clk_b), - SH_PFC_PIN_GROUP(msiof0_sync_b), - SH_PFC_PIN_GROUP(msiof0_ss1_b), - SH_PFC_PIN_GROUP(msiof0_ss2_b), - SH_PFC_PIN_GROUP(msiof0_rx_b), - SH_PFC_PIN_GROUP(msiof0_tx_b), - SH_PFC_PIN_GROUP(msiof0_clk_c), - SH_PFC_PIN_GROUP(msiof0_sync_c), - SH_PFC_PIN_GROUP(msiof0_ss1_c), - SH_PFC_PIN_GROUP(msiof0_ss2_c), - SH_PFC_PIN_GROUP(msiof0_rx_c), - SH_PFC_PIN_GROUP(msiof0_tx_c), - SH_PFC_PIN_GROUP(msiof1_clk), - SH_PFC_PIN_GROUP(msiof1_sync), - SH_PFC_PIN_GROUP(msiof1_ss1), - SH_PFC_PIN_GROUP(msiof1_ss2), - SH_PFC_PIN_GROUP(msiof1_rx), - SH_PFC_PIN_GROUP(msiof1_tx), - SH_PFC_PIN_GROUP(msiof1_clk_b), - SH_PFC_PIN_GROUP(msiof1_sync_b), - SH_PFC_PIN_GROUP(msiof1_ss1_b), - SH_PFC_PIN_GROUP(msiof1_ss2_b), - SH_PFC_PIN_GROUP(msiof1_rx_b), - SH_PFC_PIN_GROUP(msiof1_tx_b), - SH_PFC_PIN_GROUP(msiof1_clk_c), - SH_PFC_PIN_GROUP(msiof1_sync_c), - SH_PFC_PIN_GROUP(msiof1_rx_c), - SH_PFC_PIN_GROUP(msiof1_tx_c), - SH_PFC_PIN_GROUP(msiof1_clk_d), - SH_PFC_PIN_GROUP(msiof1_sync_d), - SH_PFC_PIN_GROUP(msiof1_ss1_d), - SH_PFC_PIN_GROUP(msiof1_rx_d), - SH_PFC_PIN_GROUP(msiof1_tx_d), - SH_PFC_PIN_GROUP(msiof1_clk_e), - SH_PFC_PIN_GROUP(msiof1_sync_e), - SH_PFC_PIN_GROUP(msiof1_rx_e), - SH_PFC_PIN_GROUP(msiof1_tx_e), - SH_PFC_PIN_GROUP(msiof2_clk), - SH_PFC_PIN_GROUP(msiof2_sync), - SH_PFC_PIN_GROUP(msiof2_ss1), - SH_PFC_PIN_GROUP(msiof2_ss2), - SH_PFC_PIN_GROUP(msiof2_rx), - SH_PFC_PIN_GROUP(msiof2_tx), - SH_PFC_PIN_GROUP(msiof2_clk_b), - SH_PFC_PIN_GROUP(msiof2_sync_b), - SH_PFC_PIN_GROUP(msiof2_ss1_b), - SH_PFC_PIN_GROUP(msiof2_ss2_b), - SH_PFC_PIN_GROUP(msiof2_rx_b), - SH_PFC_PIN_GROUP(msiof2_tx_b), - SH_PFC_PIN_GROUP(msiof2_clk_c), - SH_PFC_PIN_GROUP(msiof2_sync_c), - SH_PFC_PIN_GROUP(msiof2_rx_c), - SH_PFC_PIN_GROUP(msiof2_tx_c), - SH_PFC_PIN_GROUP(msiof2_clk_d), - SH_PFC_PIN_GROUP(msiof2_sync_d), - SH_PFC_PIN_GROUP(msiof2_ss1_d), - SH_PFC_PIN_GROUP(msiof2_ss2_d), - SH_PFC_PIN_GROUP(msiof2_rx_d), - SH_PFC_PIN_GROUP(msiof2_tx_d), - SH_PFC_PIN_GROUP(msiof2_clk_e), - SH_PFC_PIN_GROUP(msiof2_sync_e), - SH_PFC_PIN_GROUP(msiof2_rx_e), - SH_PFC_PIN_GROUP(msiof2_tx_e), - SH_PFC_PIN_GROUP(pwm0), - SH_PFC_PIN_GROUP(pwm0_b), - SH_PFC_PIN_GROUP(pwm1), - SH_PFC_PIN_GROUP(pwm1_b), - SH_PFC_PIN_GROUP(pwm2), - SH_PFC_PIN_GROUP(pwm2_b), - SH_PFC_PIN_GROUP(pwm3), - SH_PFC_PIN_GROUP(pwm4), - SH_PFC_PIN_GROUP(pwm4_b), - SH_PFC_PIN_GROUP(pwm5), - SH_PFC_PIN_GROUP(pwm5_b), - SH_PFC_PIN_GROUP(pwm6), - SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), - SH_PFC_PIN_GROUP(qspi_ctrl_b), - SH_PFC_PIN_GROUP(qspi_data2_b), - SH_PFC_PIN_GROUP(qspi_data4_b), - SH_PFC_PIN_GROUP(scif0_data), - SH_PFC_PIN_GROUP(scif0_data_b), - SH_PFC_PIN_GROUP(scif0_data_c), - SH_PFC_PIN_GROUP(scif0_data_d), - SH_PFC_PIN_GROUP(scif0_data_e), - SH_PFC_PIN_GROUP(scif1_data), - SH_PFC_PIN_GROUP(scif1_data_b), - SH_PFC_PIN_GROUP(scif1_clk_b), - SH_PFC_PIN_GROUP(scif1_data_c), - SH_PFC_PIN_GROUP(scif1_data_d), - SH_PFC_PIN_GROUP(scif2_data), - SH_PFC_PIN_GROUP(scif2_data_b), - SH_PFC_PIN_GROUP(scif2_clk_b), - SH_PFC_PIN_GROUP(scif2_data_c), - SH_PFC_PIN_GROUP(scif2_data_e), - SH_PFC_PIN_GROUP(scif3_data), - SH_PFC_PIN_GROUP(scif3_clk), - SH_PFC_PIN_GROUP(scif3_data_b), - SH_PFC_PIN_GROUP(scif3_clk_b), - SH_PFC_PIN_GROUP(scif3_data_c), - SH_PFC_PIN_GROUP(scif3_data_d), - SH_PFC_PIN_GROUP(scif4_data), - SH_PFC_PIN_GROUP(scif4_data_b), - SH_PFC_PIN_GROUP(scif4_data_c), - SH_PFC_PIN_GROUP(scif5_data), - SH_PFC_PIN_GROUP(scif5_data_b), - SH_PFC_PIN_GROUP(scifa0_data), - SH_PFC_PIN_GROUP(scifa0_data_b), - SH_PFC_PIN_GROUP(scifa1_data), - SH_PFC_PIN_GROUP(scifa1_clk), - SH_PFC_PIN_GROUP(scifa1_data_b), - SH_PFC_PIN_GROUP(scifa1_clk_b), - SH_PFC_PIN_GROUP(scifa1_data_c), - SH_PFC_PIN_GROUP(scifa2_data), - SH_PFC_PIN_GROUP(scifa2_clk), - SH_PFC_PIN_GROUP(scifa2_data_b), - SH_PFC_PIN_GROUP(scifa3_data), - SH_PFC_PIN_GROUP(scifa3_clk), - SH_PFC_PIN_GROUP(scifa3_data_b), - SH_PFC_PIN_GROUP(scifa3_clk_b), - SH_PFC_PIN_GROUP(scifa3_data_c), - SH_PFC_PIN_GROUP(scifa3_clk_c), - SH_PFC_PIN_GROUP(scifa4_data), - SH_PFC_PIN_GROUP(scifa4_data_b), - SH_PFC_PIN_GROUP(scifa4_data_c), - SH_PFC_PIN_GROUP(scifa5_data), - SH_PFC_PIN_GROUP(scifa5_data_b), - SH_PFC_PIN_GROUP(scifa5_data_c), - SH_PFC_PIN_GROUP(scifb0_data), - SH_PFC_PIN_GROUP(scifb0_clk), - SH_PFC_PIN_GROUP(scifb0_ctrl), - SH_PFC_PIN_GROUP(scifb0_data_b), - SH_PFC_PIN_GROUP(scifb0_clk_b), - SH_PFC_PIN_GROUP(scifb0_ctrl_b), - SH_PFC_PIN_GROUP(scifb0_data_c), - SH_PFC_PIN_GROUP(scifb0_clk_c), - SH_PFC_PIN_GROUP(scifb0_data_d), - SH_PFC_PIN_GROUP(scifb0_clk_d), - SH_PFC_PIN_GROUP(scifb1_data), - SH_PFC_PIN_GROUP(scifb1_clk), - SH_PFC_PIN_GROUP(scifb1_ctrl), - SH_PFC_PIN_GROUP(scifb1_data_b), - SH_PFC_PIN_GROUP(scifb1_clk_b), - SH_PFC_PIN_GROUP(scifb1_data_c), - SH_PFC_PIN_GROUP(scifb1_clk_c), - SH_PFC_PIN_GROUP(scifb1_data_d), - SH_PFC_PIN_GROUP(scifb2_data), - SH_PFC_PIN_GROUP(scifb2_clk), - SH_PFC_PIN_GROUP(scifb2_ctrl), - SH_PFC_PIN_GROUP(scifb2_data_b), - SH_PFC_PIN_GROUP(scifb2_clk_b), - SH_PFC_PIN_GROUP(scifb2_ctrl_b), - SH_PFC_PIN_GROUP(scifb2_data_c), - SH_PFC_PIN_GROUP(scifb2_clk_c), - SH_PFC_PIN_GROUP(scifb2_data_d), - SH_PFC_PIN_GROUP(scif_clk), - SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), - SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_cd), - SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi1_cd), - SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_ctrl), - SH_PFC_PIN_GROUP(sdhi2_cd), - SH_PFC_PIN_GROUP(sdhi2_wp), - SH_PFC_PIN_GROUP(ssi0_data), - SH_PFC_PIN_GROUP(ssi0_data_b), - SH_PFC_PIN_GROUP(ssi0129_ctrl), - SH_PFC_PIN_GROUP(ssi0129_ctrl_b), - SH_PFC_PIN_GROUP(ssi1_data), - SH_PFC_PIN_GROUP(ssi1_data_b), - SH_PFC_PIN_GROUP(ssi1_ctrl), - SH_PFC_PIN_GROUP(ssi1_ctrl_b), - SH_PFC_PIN_GROUP(ssi2_data), - SH_PFC_PIN_GROUP(ssi2_ctrl), - SH_PFC_PIN_GROUP(ssi3_data), - SH_PFC_PIN_GROUP(ssi34_ctrl), - SH_PFC_PIN_GROUP(ssi4_data), - SH_PFC_PIN_GROUP(ssi4_ctrl), - SH_PFC_PIN_GROUP(ssi5_data), - SH_PFC_PIN_GROUP(ssi5_ctrl), - SH_PFC_PIN_GROUP(ssi6_data), - SH_PFC_PIN_GROUP(ssi6_ctrl), - SH_PFC_PIN_GROUP(ssi7_data), - SH_PFC_PIN_GROUP(ssi7_data_b), - SH_PFC_PIN_GROUP(ssi78_ctrl), - SH_PFC_PIN_GROUP(ssi78_ctrl_b), - SH_PFC_PIN_GROUP(ssi8_data), - SH_PFC_PIN_GROUP(ssi8_data_b), - SH_PFC_PIN_GROUP(ssi9_data), - SH_PFC_PIN_GROUP(ssi9_data_b), - SH_PFC_PIN_GROUP(ssi9_ctrl), - SH_PFC_PIN_GROUP(ssi9_ctrl_b), - SH_PFC_PIN_GROUP(usb0), - SH_PFC_PIN_GROUP(usb1), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), - SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), - SH_PFC_PIN_GROUP(vin0_sync), - SH_PFC_PIN_GROUP(vin0_field), - SH_PFC_PIN_GROUP(vin0_clkenb), - SH_PFC_PIN_GROUP(vin0_clk), - SH_PFC_PIN_GROUP(vin1_data8), - SH_PFC_PIN_GROUP(vin1_sync), - SH_PFC_PIN_GROUP(vin1_field), - SH_PFC_PIN_GROUP(vin1_clkenb), - SH_PFC_PIN_GROUP(vin1_clk), - VIN_DATA_PIN_GROUP(vin1_b_data, 24), - VIN_DATA_PIN_GROUP(vin1_b_data, 20), - SH_PFC_PIN_GROUP(vin1_b_data18), - VIN_DATA_PIN_GROUP(vin1_b_data, 16), - VIN_DATA_PIN_GROUP(vin1_b_data, 12), - VIN_DATA_PIN_GROUP(vin1_b_data, 10), - VIN_DATA_PIN_GROUP(vin1_b_data, 8), - SH_PFC_PIN_GROUP(vin1_b_sync), - SH_PFC_PIN_GROUP(vin1_b_field), - SH_PFC_PIN_GROUP(vin1_b_clkenb), - SH_PFC_PIN_GROUP(vin1_b_clk), - SH_PFC_PIN_GROUP(vin2_data8), - SH_PFC_PIN_GROUP(vin2_sync), - SH_PFC_PIN_GROUP(vin2_field), - SH_PFC_PIN_GROUP(vin2_clkenb), - SH_PFC_PIN_GROUP(vin2_clk), +static const struct { + struct sh_pfc_pin_group common[341]; + struct sh_pfc_pin_group r8a779x[9]; +} pinmux_groups = { + .common = { + SH_PFC_PIN_GROUP(audio_clk_a), + SH_PFC_PIN_GROUP(audio_clk_b), + SH_PFC_PIN_GROUP(audio_clk_b_b), + SH_PFC_PIN_GROUP(audio_clk_c), + SH_PFC_PIN_GROUP(audio_clkout), + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP(avb_mdio), + SH_PFC_PIN_GROUP(avb_mii), + SH_PFC_PIN_GROUP(avb_gmii), + SH_PFC_PIN_GROUP(can0_data), + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can0_data_c), + SH_PFC_PIN_GROUP(can0_data_d), + SH_PFC_PIN_GROUP(can0_data_e), + SH_PFC_PIN_GROUP(can0_data_f), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can1_data_b), + SH_PFC_PIN_GROUP(can1_data_c), + SH_PFC_PIN_GROUP(can1_data_d), + SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(can_clk_b), + SH_PFC_PIN_GROUP(can_clk_c), + SH_PFC_PIN_GROUP(can_clk_d), + SH_PFC_PIN_GROUP(du_rgb666), + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out_0), + SH_PFC_PIN_GROUP(du_clk_out_1), + SH_PFC_PIN_GROUP(du_sync), + SH_PFC_PIN_GROUP(du_oddf), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(du0_clk_in), + SH_PFC_PIN_GROUP(du1_clk_in), + SH_PFC_PIN_GROUP(du1_clk_in_b), + SH_PFC_PIN_GROUP(du1_clk_in_c), + SH_PFC_PIN_GROUP(eth_link), + SH_PFC_PIN_GROUP(eth_magic), + SH_PFC_PIN_GROUP(eth_mdio), + SH_PFC_PIN_GROUP(eth_rmii), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_ctrl_b), + SH_PFC_PIN_GROUP(hscif0_data_c), + SH_PFC_PIN_GROUP(hscif0_clk_c), + SH_PFC_PIN_GROUP(hscif1_data), + SH_PFC_PIN_GROUP(hscif1_clk), + SH_PFC_PIN_GROUP(hscif1_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_data_c), + SH_PFC_PIN_GROUP(hscif1_clk_c), + SH_PFC_PIN_GROUP(hscif1_ctrl_c), + SH_PFC_PIN_GROUP(hscif1_data_d), + SH_PFC_PIN_GROUP(hscif1_data_e), + SH_PFC_PIN_GROUP(hscif1_clk_e), + SH_PFC_PIN_GROUP(hscif1_ctrl_e), + SH_PFC_PIN_GROUP(hscif2_data), + SH_PFC_PIN_GROUP(hscif2_clk), + SH_PFC_PIN_GROUP(hscif2_ctrl), + SH_PFC_PIN_GROUP(hscif2_data_b), + SH_PFC_PIN_GROUP(hscif2_ctrl_b), + SH_PFC_PIN_GROUP(hscif2_data_c), + SH_PFC_PIN_GROUP(hscif2_clk_c), + SH_PFC_PIN_GROUP(hscif2_data_d), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c0_b), + SH_PFC_PIN_GROUP(i2c0_c), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c1_c), + SH_PFC_PIN_GROUP(i2c1_d), + SH_PFC_PIN_GROUP(i2c1_e), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c2_d), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(i2c3_b), + SH_PFC_PIN_GROUP(i2c3_c), + SH_PFC_PIN_GROUP(i2c3_d), + SH_PFC_PIN_GROUP(i2c4), + SH_PFC_PIN_GROUP(i2c4_b), + SH_PFC_PIN_GROUP(i2c4_c), + SH_PFC_PIN_GROUP(i2c7), + SH_PFC_PIN_GROUP(i2c7_b), + SH_PFC_PIN_GROUP(i2c7_c), + SH_PFC_PIN_GROUP(i2c8), + SH_PFC_PIN_GROUP(i2c8_b), + SH_PFC_PIN_GROUP(i2c8_c), + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(mmc_data1), + SH_PFC_PIN_GROUP(mmc_data4), + SH_PFC_PIN_GROUP(mmc_data8), + SH_PFC_PIN_GROUP(mmc_ctrl), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_rx), + SH_PFC_PIN_GROUP(msiof0_tx), + SH_PFC_PIN_GROUP(msiof0_clk_b), + SH_PFC_PIN_GROUP(msiof0_sync_b), + SH_PFC_PIN_GROUP(msiof0_ss1_b), + SH_PFC_PIN_GROUP(msiof0_ss2_b), + SH_PFC_PIN_GROUP(msiof0_rx_b), + SH_PFC_PIN_GROUP(msiof0_tx_b), + SH_PFC_PIN_GROUP(msiof0_clk_c), + SH_PFC_PIN_GROUP(msiof0_sync_c), + SH_PFC_PIN_GROUP(msiof0_ss1_c), + SH_PFC_PIN_GROUP(msiof0_ss2_c), + SH_PFC_PIN_GROUP(msiof0_rx_c), + SH_PFC_PIN_GROUP(msiof0_tx_c), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_rx), + SH_PFC_PIN_GROUP(msiof1_tx), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_sync_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_rx_b), + SH_PFC_PIN_GROUP(msiof1_tx_b), + SH_PFC_PIN_GROUP(msiof1_clk_c), + SH_PFC_PIN_GROUP(msiof1_sync_c), + SH_PFC_PIN_GROUP(msiof1_rx_c), + SH_PFC_PIN_GROUP(msiof1_tx_c), + SH_PFC_PIN_GROUP(msiof1_clk_d), + SH_PFC_PIN_GROUP(msiof1_sync_d), + SH_PFC_PIN_GROUP(msiof1_ss1_d), + SH_PFC_PIN_GROUP(msiof1_rx_d), + SH_PFC_PIN_GROUP(msiof1_tx_d), + SH_PFC_PIN_GROUP(msiof1_clk_e), + SH_PFC_PIN_GROUP(msiof1_sync_e), + SH_PFC_PIN_GROUP(msiof1_rx_e), + SH_PFC_PIN_GROUP(msiof1_tx_e), + SH_PFC_PIN_GROUP(msiof2_clk), + SH_PFC_PIN_GROUP(msiof2_sync), + SH_PFC_PIN_GROUP(msiof2_ss1), + SH_PFC_PIN_GROUP(msiof2_ss2), + SH_PFC_PIN_GROUP(msiof2_rx), + SH_PFC_PIN_GROUP(msiof2_tx), + SH_PFC_PIN_GROUP(msiof2_clk_b), + SH_PFC_PIN_GROUP(msiof2_sync_b), + SH_PFC_PIN_GROUP(msiof2_ss1_b), + SH_PFC_PIN_GROUP(msiof2_ss2_b), + SH_PFC_PIN_GROUP(msiof2_rx_b), + SH_PFC_PIN_GROUP(msiof2_tx_b), + SH_PFC_PIN_GROUP(msiof2_clk_c), + SH_PFC_PIN_GROUP(msiof2_sync_c), + SH_PFC_PIN_GROUP(msiof2_rx_c), + SH_PFC_PIN_GROUP(msiof2_tx_c), + SH_PFC_PIN_GROUP(msiof2_clk_d), + SH_PFC_PIN_GROUP(msiof2_sync_d), + SH_PFC_PIN_GROUP(msiof2_ss1_d), + SH_PFC_PIN_GROUP(msiof2_ss2_d), + SH_PFC_PIN_GROUP(msiof2_rx_d), + SH_PFC_PIN_GROUP(msiof2_tx_d), + SH_PFC_PIN_GROUP(msiof2_clk_e), + SH_PFC_PIN_GROUP(msiof2_sync_e), + SH_PFC_PIN_GROUP(msiof2_rx_e), + SH_PFC_PIN_GROUP(msiof2_tx_e), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm1), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm3), + SH_PFC_PIN_GROUP(pwm4), + SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(pwm5), + SH_PFC_PIN_GROUP(pwm5_b), + SH_PFC_PIN_GROUP(pwm6), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), + SH_PFC_PIN_GROUP(qspi_ctrl_b), + SH_PFC_PIN_GROUP(qspi_data2_b), + SH_PFC_PIN_GROUP(qspi_data4_b), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif0_data_c), + SH_PFC_PIN_GROUP(scif0_data_d), + SH_PFC_PIN_GROUP(scif0_data_e), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_clk_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_data_d), + SH_PFC_PIN_GROUP(scif2_data), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scif2_clk_b), + SH_PFC_PIN_GROUP(scif2_data_c), + SH_PFC_PIN_GROUP(scif2_data_e), + SH_PFC_PIN_GROUP(scif3_data), + SH_PFC_PIN_GROUP(scif3_clk), + SH_PFC_PIN_GROUP(scif3_data_b), + SH_PFC_PIN_GROUP(scif3_clk_b), + SH_PFC_PIN_GROUP(scif3_data_c), + SH_PFC_PIN_GROUP(scif3_data_d), + SH_PFC_PIN_GROUP(scif4_data), + SH_PFC_PIN_GROUP(scif4_data_b), + SH_PFC_PIN_GROUP(scif4_data_c), + SH_PFC_PIN_GROUP(scif5_data), + SH_PFC_PIN_GROUP(scif5_data_b), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_data_b), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_data_b), + SH_PFC_PIN_GROUP(scifa1_clk_b), + SH_PFC_PIN_GROUP(scifa1_data_c), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk), + SH_PFC_PIN_GROUP(scifa2_data_b), + SH_PFC_PIN_GROUP(scifa3_data), + SH_PFC_PIN_GROUP(scifa3_clk), + SH_PFC_PIN_GROUP(scifa3_data_b), + SH_PFC_PIN_GROUP(scifa3_clk_b), + SH_PFC_PIN_GROUP(scifa3_data_c), + SH_PFC_PIN_GROUP(scifa3_clk_c), + SH_PFC_PIN_GROUP(scifa4_data), + SH_PFC_PIN_GROUP(scifa4_data_b), + SH_PFC_PIN_GROUP(scifa4_data_c), + SH_PFC_PIN_GROUP(scifa5_data), + SH_PFC_PIN_GROUP(scifa5_data_b), + SH_PFC_PIN_GROUP(scifa5_data_c), + SH_PFC_PIN_GROUP(scifb0_data), + SH_PFC_PIN_GROUP(scifb0_clk), + SH_PFC_PIN_GROUP(scifb0_ctrl), + SH_PFC_PIN_GROUP(scifb0_data_b), + SH_PFC_PIN_GROUP(scifb0_clk_b), + SH_PFC_PIN_GROUP(scifb0_ctrl_b), + SH_PFC_PIN_GROUP(scifb0_data_c), + SH_PFC_PIN_GROUP(scifb0_clk_c), + SH_PFC_PIN_GROUP(scifb0_data_d), + SH_PFC_PIN_GROUP(scifb0_clk_d), + SH_PFC_PIN_GROUP(scifb1_data), + SH_PFC_PIN_GROUP(scifb1_clk), + SH_PFC_PIN_GROUP(scifb1_ctrl), + SH_PFC_PIN_GROUP(scifb1_data_b), + SH_PFC_PIN_GROUP(scifb1_clk_b), + SH_PFC_PIN_GROUP(scifb1_data_c), + SH_PFC_PIN_GROUP(scifb1_clk_c), + SH_PFC_PIN_GROUP(scifb1_data_d), + SH_PFC_PIN_GROUP(scifb2_data), + SH_PFC_PIN_GROUP(scifb2_clk), + SH_PFC_PIN_GROUP(scifb2_ctrl), + SH_PFC_PIN_GROUP(scifb2_data_b), + SH_PFC_PIN_GROUP(scifb2_clk_b), + SH_PFC_PIN_GROUP(scifb2_ctrl_b), + SH_PFC_PIN_GROUP(scifb2_data_c), + SH_PFC_PIN_GROUP(scifb2_clk_c), + SH_PFC_PIN_GROUP(scifb2_data_d), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi0_data_b), + SH_PFC_PIN_GROUP(ssi0129_ctrl), + SH_PFC_PIN_GROUP(ssi0129_ctrl_b), + SH_PFC_PIN_GROUP(ssi1_data), + SH_PFC_PIN_GROUP(ssi1_data_b), + SH_PFC_PIN_GROUP(ssi1_ctrl), + SH_PFC_PIN_GROUP(ssi1_ctrl_b), + SH_PFC_PIN_GROUP(ssi2_data), + SH_PFC_PIN_GROUP(ssi2_ctrl), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi34_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5_data), + SH_PFC_PIN_GROUP(ssi5_ctrl), + SH_PFC_PIN_GROUP(ssi6_data), + SH_PFC_PIN_GROUP(ssi6_ctrl), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi7_data_b), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi78_ctrl_b), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi8_data_b), + SH_PFC_PIN_GROUP(ssi9_data), + SH_PFC_PIN_GROUP(ssi9_data_b), + SH_PFC_PIN_GROUP(ssi9_ctrl), + SH_PFC_PIN_GROUP(ssi9_ctrl_b), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb1), + VIN_DATA_PIN_GROUP(vin0_data, 24), + VIN_DATA_PIN_GROUP(vin0_data, 20), + SH_PFC_PIN_GROUP(vin0_data18), + VIN_DATA_PIN_GROUP(vin0_data, 16), + VIN_DATA_PIN_GROUP(vin0_data, 12), + VIN_DATA_PIN_GROUP(vin0_data, 10), + VIN_DATA_PIN_GROUP(vin0_data, 8), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin0_field), + SH_PFC_PIN_GROUP(vin0_clkenb), + SH_PFC_PIN_GROUP(vin0_clk), + SH_PFC_PIN_GROUP(vin1_data8), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_clkenb), + SH_PFC_PIN_GROUP(vin1_clk), + VIN_DATA_PIN_GROUP(vin1_b_data, 24), + VIN_DATA_PIN_GROUP(vin1_b_data, 20), + SH_PFC_PIN_GROUP(vin1_b_data18), + VIN_DATA_PIN_GROUP(vin1_b_data, 16), + VIN_DATA_PIN_GROUP(vin1_b_data, 12), + VIN_DATA_PIN_GROUP(vin1_b_data, 10), + VIN_DATA_PIN_GROUP(vin1_b_data, 8), + SH_PFC_PIN_GROUP(vin1_b_sync), + SH_PFC_PIN_GROUP(vin1_b_field), + SH_PFC_PIN_GROUP(vin1_b_clkenb), + SH_PFC_PIN_GROUP(vin1_b_clk), + SH_PFC_PIN_GROUP(vin2_data8), + SH_PFC_PIN_GROUP(vin2_sync), + SH_PFC_PIN_GROUP(vin2_field), + SH_PFC_PIN_GROUP(vin2_clkenb), + SH_PFC_PIN_GROUP(vin2_clk), + }, + .r8a779x = { + SH_PFC_PIN_GROUP(adi_common), + SH_PFC_PIN_GROUP(adi_chsel0), + SH_PFC_PIN_GROUP(adi_chsel1), + SH_PFC_PIN_GROUP(adi_chsel2), + SH_PFC_PIN_GROUP(adi_common_b), + SH_PFC_PIN_GROUP(adi_chsel0_b), + SH_PFC_PIN_GROUP(adi_chsel1_b), + SH_PFC_PIN_GROUP(adi_chsel2_b), + SH_PFC_PIN_GROUP(mlb_3pin), + } }; static const char * const adi_groups[] = { @@ -5280,65 +5294,72 @@ static const char * const vin2_groups[] = { "vin2_clk", }; -static const struct sh_pfc_function pinmux_functions[] = { - SH_PFC_FUNCTION(adi), - SH_PFC_FUNCTION(audio_clk), - SH_PFC_FUNCTION(avb), - SH_PFC_FUNCTION(can0), - SH_PFC_FUNCTION(can1), - SH_PFC_FUNCTION(du), - SH_PFC_FUNCTION(du0), - SH_PFC_FUNCTION(du1), - SH_PFC_FUNCTION(eth), - SH_PFC_FUNCTION(hscif0), - SH_PFC_FUNCTION(hscif1), - SH_PFC_FUNCTION(hscif2), - SH_PFC_FUNCTION(i2c0), - SH_PFC_FUNCTION(i2c1), - SH_PFC_FUNCTION(i2c2), - SH_PFC_FUNCTION(i2c3), - SH_PFC_FUNCTION(i2c4), - SH_PFC_FUNCTION(i2c7), - SH_PFC_FUNCTION(i2c8), - SH_PFC_FUNCTION(intc), - SH_PFC_FUNCTION(mlb), - SH_PFC_FUNCTION(mmc), - SH_PFC_FUNCTION(msiof0), - SH_PFC_FUNCTION(msiof1), - SH_PFC_FUNCTION(msiof2), - SH_PFC_FUNCTION(pwm0), - SH_PFC_FUNCTION(pwm1), - SH_PFC_FUNCTION(pwm2), - SH_PFC_FUNCTION(pwm3), - SH_PFC_FUNCTION(pwm4), - SH_PFC_FUNCTION(pwm5), - SH_PFC_FUNCTION(pwm6), - SH_PFC_FUNCTION(qspi), - SH_PFC_FUNCTION(scif0), - SH_PFC_FUNCTION(scif1), - SH_PFC_FUNCTION(scif2), - SH_PFC_FUNCTION(scif3), - SH_PFC_FUNCTION(scif4), - SH_PFC_FUNCTION(scif5), - SH_PFC_FUNCTION(scifa0), - SH_PFC_FUNCTION(scifa1), - SH_PFC_FUNCTION(scifa2), - SH_PFC_FUNCTION(scifa3), - SH_PFC_FUNCTION(scifa4), - SH_PFC_FUNCTION(scifa5), - SH_PFC_FUNCTION(scifb0), - SH_PFC_FUNCTION(scifb1), - SH_PFC_FUNCTION(scifb2), - SH_PFC_FUNCTION(scif_clk), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), - SH_PFC_FUNCTION(ssi), - SH_PFC_FUNCTION(usb0), - SH_PFC_FUNCTION(usb1), - SH_PFC_FUNCTION(vin0), - SH_PFC_FUNCTION(vin1), - SH_PFC_FUNCTION(vin2), +static const struct { + struct sh_pfc_function common[56]; + struct sh_pfc_function r8a779x[2]; +} pinmux_functions = { + .common = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(du0), + SH_PFC_FUNCTION(du1), + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(hscif2), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(i2c4), + SH_PFC_FUNCTION(i2c7), + SH_PFC_FUNCTION(i2c8), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(mmc), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scif3), + SH_PFC_FUNCTION(scif4), + SH_PFC_FUNCTION(scif5), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifa3), + SH_PFC_FUNCTION(scifa4), + SH_PFC_FUNCTION(scifa5), + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), + SH_PFC_FUNCTION(vin2), + }, + .r8a779x = { + SH_PFC_FUNCTION(adi), + SH_PFC_FUNCTION(mlb), + } }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -5638,7 +5659,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_A1, FN_MSIOF0_SYNC_B, 0, 0, /* IP0_18_16 [3] */ - FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B, + FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B, 0, 0, 0, /* IP0_15 [1] */ FN_D15, 0, @@ -5679,7 +5700,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C, 0, 0, 0, /* IP1_28_26 [3] */ - FN_A17, FN_DACK2_B, 0, FN_SDA0_C, + FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C, 0, 0, 0, 0, /* IP1_25_23 [3] */ FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B, @@ -5694,17 +5715,17 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D, 0, 0, 0, 0, /* IP1_13_11 [3] */ - FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D, + FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D, 0, 0, 0, 0, /* IP1_10_8 [3] */ - FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D, + FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D, 0, 0, 0, 0, /* IP1_7_6 [2] */ FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D, /* IP1_5_4 [2] */ - FN_A9, FN_MSIOF1_SS2, FN_SDA0, 0, + FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0, /* IP1_3_2 [2] */ - FN_A8, FN_MSIOF1_SS1, FN_SCL0, 0, + FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0, /* IP1_1_0 [2] */ FN_A7, FN_MSIOF1_SYNC, 0, 0, } @@ -5722,9 +5743,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP2_24_23 [2] */ FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0, /* IP2_22_21 [2] */ - FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, 0, + FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0, /* IP2_20_19 [2] */ - FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, 0, + FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0, /* IP2_18_16 [3] */ FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD, 0, 0, @@ -5807,23 +5828,23 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E, 0, 0, 0, 0, /* IP4_15_13 [3] */ - FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E, + FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E, FN_GLO_Q1_D, FN_HCTS1_N_E, 0, 0, /* IP4_12_10 [3] */ - FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E, + FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E, 0, 0, 0, /* IP4_9_8 [2] */ - FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C, + FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C, /* IP4_7_5 [3] */ - FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D, - 0, 0, 0, + FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, + FN_GLO_I1_D, 0, 0, 0, /* IP4_4_2 [3] */ - FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, + FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C, FN_GLO_I0_D, 0, 0, 0, /* IP4_1_0 [2] */ - FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, } + FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C, } }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) { @@ -5877,15 +5898,15 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* IP6_23_21 [3] */ FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, - FN_SDA1_E, FN_MSIOF2_SYNC_E, + FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E, 0, 0, 0, /* IP6_20_19 [2] */ - FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E, + FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E, /* IP6_18_16 [3] */ - FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N, - 0, 0, 0, + FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, + FN_INTC_IRQ4_N, 0, 0, 0, /* IP6_15_14 [2] */ - FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, + FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N, /* IP6_13_12 [2] */ FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0, /* IP6_11_10 [2] */ @@ -5990,7 +6011,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) { /* IP9_31_29 [3] */ - FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4, + FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL, FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0, /* IP9_28_27 [2] */ FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0, @@ -6008,7 +6029,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_DU1_DISP, FN_QPOLA, /* IP9_15_13 [3] */ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE, - FN_CAN0_RX, FN_RX3_B, FN_SDA2_B, + FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B, 0, 0, 0, /* IP9_12 [1] */ FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE, @@ -6016,24 +6037,24 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS, /* IP9_10_8 [3] */ FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX, - FN_TX3_B, FN_SCL2_B, FN_PWM4, + FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4, 0, 0, /* IP9_7 [1] */ FN_DU1_DOTCLKOUT0, FN_QCLK, /* IP9_6 [1] */ FN_DU1_DOTCLKIN, FN_QSTVA_QVS, /* IP9_5_3 [3] */ - FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, + FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK, 0, 0, 0, /* IP9_2_0 [3] */ - FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD, + FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD, 0, 0, 0, } }, { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) { /* IP10_31_29 [3] */ - FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D, + FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D, 0, 0, 0, /* IP10_28_27 [2] */ FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C, @@ -6058,22 +6079,22 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D, 0, 0, /* IP10_8_6 [3] */ - FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B, + FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B, FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0, /* IP10_5_3 [3] */ - FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B, + FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B, FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0, /* IP10_2_0 [3] */ - FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4, + FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA, FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, } }, { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 3, 3, 3, 3, 3) { /* IP11_31_30 [2] */ - FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0, + FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0, /* IP11_29_28 [2] */ - FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0, + FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0, /* IP11_27 [1] */ FN_VI1_DATA7, FN_AVB_MDC, /* IP11_26 [1] */ @@ -6106,13 +6127,13 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* IP11_8_6 [3] */ FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E, - FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0, + FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0, /* IP11_5_3 [3] */ - FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B, + FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B, 0, 0, 0, /* IP11_2_0 [3] */ - FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D, - 0, 0, 0, } + FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, + FN_I2C1_SDA_D, 0, 0, 0, } }, { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) { @@ -6144,16 +6165,16 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, /* IP12_9_7 [3] */ FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, - FN_SDA2_D, FN_MSIOF1_SCK_E, + FN_I2C2_SDA_D, FN_MSIOF1_SCK_E, 0, 0, 0, /* IP12_6_4 [3] */ FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C, - FN_SCL2_D, FN_MSIOF1_RXD_E, + FN_I2C2_SCL_D, FN_MSIOF1_RXD_E, 0, 0, 0, /* IP12_3_2 [2] */ - FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7, + FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA, /* IP12_1_0 [2] */ - FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, } + FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, } }, { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1, @@ -6161,7 +6182,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP13_31 [1] */ 0, 0, /* IP13_30_28 [3] */ - FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C, + FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C, 0, 0, 0, 0, /* IP13_27 [1] */ FN_SD1_DATA3, FN_IERX_B, @@ -6210,10 +6231,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) { /* IP14_31_29 [3] */ FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E, - FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0, + FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0, /* IP14_28_26 [3] */ FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E, - FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0, + FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0, /* IP14_25_23 [3] */ FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B, 0, 0, 0, @@ -6229,10 +6250,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_VI1_CLK_C, FN_VI1_G0_B, 0, 0, /* IP14_13_11 [3] */ - FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C, + FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C, 0, 0, 0, /* IP14_10_8 [3] */ - FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C, + FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C, 0, 0, 0, /* IP14_7 [1] */ FN_SD2_DATA3, FN_MMC_D3, @@ -6247,7 +6268,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP14_2 [1] */ FN_SD2_CLK, FN_MMC_CLK, /* IP14_1_0 [2] */ - FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, } + FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, } }, { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) { @@ -6424,14 +6445,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_CANCLK [2] */ FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3, - /* SEL_IIC8 [2] */ - FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0, - /* SEL_IIC7 [2] */ - FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0, - /* SEL_IIC4 [2] */ - FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0, - /* SEL_IIC3 [2] */ - FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3, + /* SEL_IIC1 [2] */ + FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, + /* SEL_IIC0 [2] */ + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, + /* SEL_I2C4 [2] */ + FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0, + /* SEL_I2C3 [2] */ + FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3, /* SEL_SCIF3 [2] */ FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, /* SEL_IEB [2] */ @@ -6442,14 +6463,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, /* RESERVED [2] */ 0, 0, 0, 0, - /* SEL_IIC2 [2] */ - FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, - /* SEL_IIC1 [3] */ - FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3, - FN_SEL_IIC1_4, + /* SEL_I2C2 [2] */ + FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, + /* SEL_I2C1 [3] */ + FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3, + FN_SEL_I2C1_4, 0, 0, 0, - /* SEL_IIC0 [2] */ - FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0, + /* SEL_I2C0 [2] */ + FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0, /* RESERVED [2] */ 0, 0, 0, 0, /* RESERVED [2] */ @@ -6520,6 +6541,28 @@ static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = { .pin_to_pocctrl = r8a7791_pin_to_pocctrl, }; +#ifdef CONFIG_PINCTRL_PFC_R8A7743 +const struct sh_pfc_soc_info r8a7743_pinmux_info = { + .name = "r8a77430_pfc", + .ops = &r8a7791_pinmux_ops, + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common), + + .cfg_regs = pinmux_config_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; +#endif + #ifdef CONFIG_PINCTRL_PFC_R8A7791 const struct sh_pfc_soc_info r8a7791_pinmux_info = { .name = "r8a77910_pfc", @@ -6530,10 +6573,12 @@ const struct sh_pfc_soc_info r8a7791_pinmux_info = { .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common) + + ARRAY_SIZE(pinmux_groups.r8a779x), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common) + + ARRAY_SIZE(pinmux_functions.r8a779x), .cfg_regs = pinmux_config_regs, @@ -6552,10 +6597,12 @@ const struct sh_pfc_soc_info r8a7793_pinmux_info = { .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common) + + ARRAY_SIZE(pinmux_groups.r8a779x), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common) + + ARRAY_SIZE(pinmux_functions.r8a779x), .cfg_regs = pinmux_config_regs, diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c index 21badb6166b9..cc3597f66605 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7792.c @@ -1137,6 +1137,43 @@ static const unsigned int scif0_ctrl_pins[] = { static const unsigned int scif0_ctrl_mux[] = { RTS0_N_MARK, CTS0_N_MARK, }; +/* - SCIF1 ------------------------------------------------------------------ */ +static const unsigned int scif1_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(10, 19), RCAR_GP_PIN(10, 18), +}; +static const unsigned int scif1_data_mux[] = { + RX1_MARK, TX1_MARK, +}; +static const unsigned int scif1_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(10, 15), +}; +static const unsigned int scif1_clk_mux[] = { + SCK1_MARK, +}; +static const unsigned int scif1_ctrl_pins[] = { + /* RTS, CTS */ + RCAR_GP_PIN(10, 17), RCAR_GP_PIN(10, 16), +}; +static const unsigned int scif1_ctrl_mux[] = { + RTS1_N_MARK, CTS1_N_MARK, +}; +/* - SCIF2 ------------------------------------------------------------------ */ +static const unsigned int scif2_data_pins[] = { + /* RX, TX */ + RCAR_GP_PIN(10, 22), RCAR_GP_PIN(10, 21), +}; +static const unsigned int scif2_data_mux[] = { + RX2_MARK, TX2_MARK, +}; +static const unsigned int scif2_clk_pins[] = { + /* SCK */ + RCAR_GP_PIN(10, 20), +}; +static const unsigned int scif2_clk_mux[] = { + SCK2_MARK, +}; /* - SCIF3 ------------------------------------------------------------------ */ static const unsigned int scif3_data_pins[] = { /* RX, TX */ @@ -1680,6 +1717,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif2_data), + SH_PFC_PIN_GROUP(scif2_clk), SH_PFC_PIN_GROUP(scif3_data), SH_PFC_PIN_GROUP(scif3_clk), SH_PFC_PIN_GROUP(sdhi0_data1), @@ -1826,6 +1868,17 @@ static const char * const scif0_groups[] = { "scif0_ctrl", }; +static const char * const scif1_groups[] = { + "scif1_data", + "scif1_clk", + "scif1_ctrl", +}; + +static const char * const scif2_groups[] = { + "scif2_data", + "scif2_clk", +}; + static const char * const scif3_groups[] = { "scif3_data", "scif3_clk", @@ -1924,6 +1977,8 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(qspi), SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), SH_PFC_FUNCTION(scif3), SH_PFC_FUNCTION(sdhi0), SH_PFC_FUNCTION(vin0), diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index ef093ac0cf2f..a0ed220071f5 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c @@ -1,9 +1,9 @@ /* - * r8a7794 processor support - PFC hardware block. + * r8a7794/r8a7745 processor support - PFC hardware block. * * Copyright (C) 2014-2015 Renesas Electronics Corporation * Copyright (C) 2015 Renesas Solutions Corp. - * Copyright (C) 2015-2016 Cogent Embedded, Inc., <source@cogentembedded.com> + * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 @@ -105,235 +105,279 @@ enum { FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, /* IPSR1 */ - FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, FN_D7, FN_IRQ3, FN_TCLK1, - FN_PWM6_B, FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, FN_D9, FN_HSCIF2_HTX, - FN_I2C1_SDA_B, FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, - FN_PWM5_C, FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D, - FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, FN_D13, - FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, FN_D14, FN_SCIFA1_RXD, - FN_IIC0_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, FN_A0, - FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD, FN_A3, FN_SCIFB0_SCK, - FN_A4, FN_SCIFB0_TXD, FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C, + FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, + FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B, + FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, + FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, + FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C, + FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D, + FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, + FN_D13, FN_SCIFA1_SCK, FN_PWM2_C, FN_TCLK2_B, + FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, + FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, + FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, + FN_A1, FN_SCIFB1_TXD, + FN_A3, FN_SCIFB0_SCK, + FN_A4, FN_SCIFB0_TXD, + FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C, FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C, /* IPSR2 */ - FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, FN_A8, FN_MSIOF1_RXD, - FN_SCIFA0_RXD_B, FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, FN_A10, - FN_MSIOF1_SCK, FN_IIC1_SCL_B, FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, - FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, FN_A13, FN_MSIOF1_SS2, - FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N, - FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, FN_A16, - FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_VSP, FN_CAN_CLK_C, - FN_TPUTO2_B, FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, - FN_AVB_AVTP_CAPTURE_B, FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, - FN_CAN1_TX_B, FN_AVB_AVTP_MATCH_B, FN_A19, FN_MSIOF2_SS2, FN_PWM4, - FN_TPUTO2, FN_MOUT0, FN_A20, FN_SPCLK, FN_MOUT1, + FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, + FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, + FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, + FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, + FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, + FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, + FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, + FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N, + FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, + FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C, + FN_TPUTO2_B, + FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, + FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B, + FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2, + FN_A20, FN_SPCLK, /* IPSR3 */ - FN_A21, FN_MOSI_IO0, FN_MOUT2, FN_A22, FN_MISO_IO1, FN_MOUT5, - FN_ATADIR1_N, FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, FN_A24, FN_IO3, - FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N, FN_CS0_N, FN_VI1_DATA8, - FN_CS1_N_A26, FN_VI1_DATA9, FN_EX_CS0_N, FN_VI1_DATA10, FN_EX_CS1_N, - FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, FN_EX_CS2_N, FN_PWM0, - FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, - FN_SDATA_B, FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, - FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, FN_EX_CS4_N, - FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_RIF0_D0, FN_FMCLK, - FN_SCIFB2_CTS_N, FN_SCKZ_B, FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, - FN_TS_SPSYNC_B, FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B, - FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, FN_MTS_N_B, - FN_RD_N, FN_ATACS11_N, FN_RD_WR_N, FN_ATAG1_N, + FN_A21, FN_MOSI_IO0, + FN_A22, FN_MISO_IO1, FN_ATADIR1_N, + FN_A23, FN_IO2, FN_ATAWR1_N, + FN_A24, FN_IO3, FN_EX_WAIT2, + FN_A25, FN_SSL, FN_ATARD1_N, + FN_CS0_N, FN_VI1_DATA8, + FN_CS1_N_A26, FN_VI1_DATA9, + FN_EX_CS0_N, FN_VI1_DATA10, + FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, + FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3, + FN_SCIFB2_TXD, + FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK, + FN_SCIFB2_SCK, + FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK, + FN_SCIFB2_CTS_N, + FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN, + FN_SCIFB2_RTS_N, + FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, + FN_RD_N, FN_ATACS11_N, + FN_RD_WR_N, FN_ATAG1_N, /* IPSR4 */ - FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, FN_DU0_DR0, - FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, FN_CC50_STATE0, - FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, FN_CC50_STATE1, - FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, FN_DU0_DR3, FN_LCDOUT19, - FN_CC50_STATE3, FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, FN_DU0_DR5, - FN_LCDOUT21, FN_CC50_STATE5, FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, - FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, FN_DU0_DG0, FN_LCDOUT8, - FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, FN_CC50_STATE8, FN_DU0_DG1, FN_LCDOUT9, - FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, FN_CC50_STATE9, FN_DU0_DG2, FN_LCDOUT10, - FN_CC50_STATE10, FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, FN_DU0_DG4, - FN_LCDOUT12, FN_CC50_STATE12, + FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, + FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, + FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, + FN_DU0_DR2, FN_LCDOUT18, + FN_DU0_DR3, FN_LCDOUT19, + FN_DU0_DR4, FN_LCDOUT20, + FN_DU0_DR5, FN_LCDOUT21, + FN_DU0_DR6, FN_LCDOUT22, + FN_DU0_DR7, FN_LCDOUT23, + FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, + FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, + FN_DU0_DG2, FN_LCDOUT10, + FN_DU0_DG3, FN_LCDOUT11, + FN_DU0_DG4, FN_LCDOUT12, /* IPSR5 */ - FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, FN_DU0_DG6, FN_LCDOUT14, - FN_CC50_STATE14, FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, FN_DU0_DB0, - FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C, - FN_CC50_STATE16, FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, - FN_CAN0_TX_C, FN_CC50_STATE17, FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, - FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, FN_DU0_DB4, FN_LCDOUT4, - FN_CC50_STATE20, FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, FN_DU0_DB6, - FN_LCDOUT6, FN_CC50_STATE22, FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, - FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, FN_DU0_DOTCLKOUT0, - FN_QCLK, FN_CC50_STATE25, FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, - FN_CC50_STATE26, FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, + FN_DU0_DG5, FN_LCDOUT13, + FN_DU0_DG6, FN_LCDOUT14, + FN_DU0_DG7, FN_LCDOUT15, + FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C, + FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C, + FN_DU0_DB2, FN_LCDOUT2, + FN_DU0_DB3, FN_LCDOUT3, + FN_DU0_DB4, FN_LCDOUT4, + FN_DU0_DB5, FN_LCDOUT5, + FN_DU0_DB6, FN_LCDOUT6, + FN_DU0_DB7, FN_LCDOUT7, + FN_DU0_DOTCLKIN, FN_QSTVA_QVS, + FN_DU0_DOTCLKOUT0, FN_QCLK, + FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, + FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, /* IPSR6 */ - FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, - FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, - FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB, - FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0, - FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2, - FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4, - FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6, - FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB, - FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD, - FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N, - FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N, - FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, - FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK, - FN_ADIDATA, FN_AD_DI, + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, + FN_DU0_DISP, FN_QPOLA, + FN_DU0_CDE, FN_QPOLB, + FN_VI0_CLK, FN_AVB_RX_CLK, + FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV, + FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, + FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1, + FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, + FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3, + FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, + FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5, + FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, + FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, + FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, + FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, + FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, + FN_AVB_TX_EN, + FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK, + FN_ADIDATA, /* IPSR7 */ - FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0, - FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, - FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3, - FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, + FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0, + FN_ADICS_SAMP, + FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1, + FN_ADICLK, + FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, + FN_ADICHS0, FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3, - FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, - FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, - FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, - FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0, - FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B, + FN_ADICHS1, + FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4, + FN_ADICHS2, + FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B, + FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6, + FN_SSI_WS5_B, + FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7, + FN_SSI_SDATA5_B, FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B, FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK, - FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD, + FN_SSI_WS6_B, + FN_DREQ0_N, FN_SCIFB1_RXD, /* IPSR8 */ FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC, - FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, - FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX, - FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B, + FN_SSI_SDATA6_B, + FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, FN_AVB_MDIO, + FN_SSI_SCK78_B, + FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, + FN_SSI_WS78_B, FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, - FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7, - FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B, + FN_AVB_MAGIC, FN_SSI_SDATA7_B, + FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E, + FN_AVB_PHY_INT, FN_SSI_SDATA8_B, FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK, - FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, - FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD, - FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, - FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B, - FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, - FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, + FN_CAN1_RX_D, FN_TPUTO0_B, + FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE, + FN_CAN1_TX_D, + FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D, + FN_TPUTO1_B, + FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D, + FN_BPFCLK_C, + FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D, + FN_FMCLK_C, /* IPSR9 */ - FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_RIF1_D1_B, - FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, FN_MSIOF0_SCK, FN_IRQ0, - FN_TS_SDATA, FN_DU1_DR4, FN_RIF1_SYNC, FN_TPUTO1_C, FN_MSIOF0_SYNC, - FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_RIF1_CLK, FN_BPFCLK_B, FN_MSIOF0_SS1, - FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_RIF1_D0, FN_FMCLK_B, - FN_RDS_CLK_B, FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, - FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, FN_HSCIF1_HRX, FN_I2C4_SCL, - FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, + FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D, + FN_FMIN_C, + FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C, + FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B, + FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B, + FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B, + FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0, + FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B, - FN_SPEEDIN_B, FN_VSP_B, FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, - FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, + FN_SPEEDIN_B, + FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B, FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B, - FN_CAN_STEP0, FN_CC50_STATE33, FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, - FN_DU1_DG5, FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, + FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B, /* IPSR10 */ - FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0, - FN_CC50_STATE35, FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B, - FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC1_SCL, - FN_DU1_DB0, FN_SSI_SDATA2_B, FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, - FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, - FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, FN_SCIF2_SCK, FN_IRQ1, - FN_DU1_DB2, FN_SSI_WS9_B, FN_USB0_IDIN, FN_CAN_DEBUGOUT4, - FN_CC50_STATE39, FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, - FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT, + FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, + FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B, + FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B, + FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, + FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B, + FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B, FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C, - FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, FN_SCIF3_TXD, - FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B, - FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, - FN_AUDIO_CLKC_C, FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, FN_I2C2_SDA, - FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, FN_CAN_DEBUGOUT9, - FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10, + FN_SSI_SCK4_B, + FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, + FN_SSI_WS4_B, + FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C, + FN_SSI_SDATA4_B, + FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, + FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, /* IPSR11 */ FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, - FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, - FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B, - FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6, - FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC, - FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, - FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78, - FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78, - FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7, - FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N, + FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1, + FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, + FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC, + FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, + FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP, + FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE, + FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, - FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, - FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, - FN_ADICLK_B, FN_AD_CLK_B, + FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B, + FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, /* IPSR12 */ FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, - FN_AD_NCS_N_B, FN_DREQ1_N_B, FN_SSI_WS34, FN_MSIOF1_SS1_B, - FN_SCIFA1_RXD_C, FN_ADICHS1_B, FN_CAN1_RX_C, FN_DACK1_B, FN_SSI_SDATA3, - FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, FN_CAN1_TX_C, - FN_DREQ2_N, FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, FN_SSI_WS4, - FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, FN_SSI_SDATA4, FN_MLB_DAT, - FN_IERX_B, FN_IRD_SCK, FN_SSI_SDATA8, FN_SCIF1_SCK_B, - FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1, - FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D, - FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B, - FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, - FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1, - FN_ATAWR0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, - FN_MDATA, FN_ATAG0_N, FN_ETH_RXD1_B, + FN_DREQ1_N_B, + FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B, + FN_CAN1_RX_C, FN_DACK1_B, + FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, + FN_CAN1_TX_C, FN_DREQ2_N, + FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, + FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, + FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON, + FN_DACK2, FN_ETH_MDIO_B, + FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D, + FN_ETH_CRS_DV_B, + FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, + FN_ETH_RX_ER_B, + FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_ATAWR0_N, + FN_ETH_RXD0_B, + FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_ATAG0_N, FN_ETH_RXD1_B, /* IPSR13 */ - FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ, - FN_ATACS00_N, FN_ETH_LINK_B, FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, - FN_SCIFA0_TXD_D, FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, - FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_MTS_N, - FN_EX_WAIT1, FN_ETH_TXD1_B, FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, - FN_VI1_DATA6, FN_ATARD0_N, FN_ETH_TX_EN_B, FN_SSI_SDATA9, - FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N, - FN_ETH_MAGIC_B, FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, - FN_VI1_CLKENB, FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, + FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, + FN_ATACS00_N, FN_ETH_LINK_B, + FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4, + FN_ATACS10_N, FN_ETH_REFCLK_B, + FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_EX_WAIT1, + FN_ETH_TXD1_B, + FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N, + FN_ETH_TX_EN_B, + FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, + FN_ATADIR0_N, FN_ETH_MAGIC_B, + FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB, + FN_TS_SDATA_C, FN_ETH_TXD0_B, FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, - FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, FN_AUDIO_CLKC, - FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, FN_TS_SDEN_C, - FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, - FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, FN_TS_SPSYNC_C, FN_RIF0_D1_B, - FN_FMIN_E, FN_RDS_DATA_D, + FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B, + FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, + FN_TS_SDEN_C, FN_FMCLK_E, + FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, + FN_TS_SPSYNC_C, FN_FMIN_E, /* MOD_SEL */ FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, - FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1, - FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1, - FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0, - FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1, - FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0, - FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, - FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1, - FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0, - FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4, + FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, + FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, + FN_SEL_DARC_4, + FN_SEL_ETH_0, FN_SEL_ETH_1, + FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, + FN_SEL_I2C00_4, + FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, + FN_SEL_I2C01_4, + FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, + FN_SEL_I2C02_4, FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, - FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, - FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1, - FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1, + FN_SEL_I2C03_4, + FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, + FN_SEL_I2C04_4, + FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3, /* MOD_SEL2 */ - FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0, - FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0, - FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0, - FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0, - FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0, - FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0, - FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, - FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, - FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, - FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1, - FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, - FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1, - FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1, - FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, - FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1, - FN_SEL_RDS_2, FN_SEL_RDS_3, + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3, + FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, + FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, + FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, + FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, + FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, + FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, + FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, + FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, + FN_SEL_TMU_0, FN_SEL_TMU_1, + FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, + FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, + FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, /* MOD_SEL3 */ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, @@ -372,117 +416,141 @@ enum { SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK, /* IPSR1 */ - D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK, D7_MARK, IRQ3_MARK, - TCLK1_MARK, PWM6_B_MARK, D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK, - D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK, D10_MARK, - HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK, + D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK, + D7_MARK, IRQ3_MARK, TCLK1_MARK, PWM6_B_MARK, + D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK, + D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK, + D10_MARK, HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK, D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK, D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK, - D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK, PWM2_C_MARK, TCLK2_B_MARK, - D14_MARK, SCIFA1_RXD_MARK, IIC0_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK, - IIC0_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK, - SCIFB1_TXD_MARK, A3_MARK, SCIFB0_SCK_MARK, A4_MARK, SCIFB0_TXD_MARK, - A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, A6_MARK, - SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK, + D13_MARK, SCIFA1_SCK_MARK, PWM2_C_MARK, TCLK2_B_MARK, + D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK, + D15_MARK, SCIFA1_TXD_MARK, I2C5_SDA_B_MARK, + A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, + A1_MARK, SCIFB1_TXD_MARK, + A3_MARK, SCIFB0_SCK_MARK, + A4_MARK, SCIFB0_TXD_MARK, + A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, + A6_MARK, SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK, /* IPSR2 */ - A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, A8_MARK, MSIOF1_RXD_MARK, - SCIFA0_RXD_B_MARK, A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK, - A10_MARK, MSIOF1_SCK_MARK, IIC1_SCL_B_MARK, A11_MARK, MSIOF1_SYNC_MARK, - IIC1_SDA_B_MARK, A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK, - A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK, - HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK, - HSCIF0_HTX_B_MARK, DACK1_MARK, A16_MARK, MSIOF2_SCK_MARK, - HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, VSP_MARK, CAN_CLK_C_MARK, - TPUTO2_B_MARK, A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, - CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_B_MARK, A18_MARK, MSIOF2_SS1_MARK, - SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, AVB_AVTP_MATCH_B_MARK, A19_MARK, - MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, MOUT0_MARK, A20_MARK, - SPCLK_MARK, MOUT1_MARK, + A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, + A8_MARK, MSIOF1_RXD_MARK, SCIFA0_RXD_B_MARK, + A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK, + A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK, + A11_MARK, MSIOF1_SYNC_MARK, IIC0_SDA_B_MARK, + A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK, + A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, + A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK, + A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK, + A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, + CAN_CLK_C_MARK, TPUTO2_B_MARK, + A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK, + A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, + A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, + A20_MARK, SPCLK_MARK, /* IPSR3 */ - A21_MARK, MOSI_IO0_MARK, MOUT2_MARK, A22_MARK, MISO_IO1_MARK, - MOUT5_MARK, ATADIR1_N_MARK, A23_MARK, IO2_MARK, MOUT6_MARK, - ATAWR1_N_MARK, A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK, - ATARD1_N_MARK, CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK, - VI1_DATA9_MARK, EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK, - TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, EX_CS2_N_MARK, - PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, RIF0_SYNC_MARK, - TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK, EX_CS3_N_MARK, - SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, RIF0_CLK_MARK, - BPFCLK_MARK, SCIFB2_SCK_MARK, MDATA_B_MARK, EX_CS4_N_MARK, - SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, RIF0_D0_MARK, - FMCLK_MARK, SCIFB2_CTS_N_MARK, SCKZ_B_MARK, EX_CS5_N_MARK, - SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, RIF0_D1_MARK, - FMIN_MARK, SCIFB2_RTS_N_MARK, STM_N_B_MARK, BS_N_MARK, DRACK0_MARK, - PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK, RD_N_MARK, - ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK, + A21_MARK, MOSI_IO0_MARK, + A22_MARK, MISO_IO1_MARK, ATADIR1_N_MARK, + A23_MARK, IO2_MARK, ATAWR1_N_MARK, + A24_MARK, IO3_MARK, EX_WAIT2_MARK, + A25_MARK, SSL_MARK, ATARD1_N_MARK, + CS0_N_MARK, VI1_DATA8_MARK, + CS1_N_A26_MARK, VI1_DATA9_MARK, + EX_CS0_N_MARK, VI1_DATA10_MARK, + EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, + EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, + TPUTO3_MARK, SCIFB2_TXD_MARK, + EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, + BPFCLK_MARK, SCIFB2_SCK_MARK, + EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, + FMCLK_MARK, SCIFB2_CTS_N_MARK, + EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, + FMIN_MARK, SCIFB2_RTS_N_MARK, + BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, + RD_N_MARK, ATACS11_N_MARK, + RD_WR_N_MARK, ATAG1_N_MARK, /* IPSR4 */ - EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, PWMFSW0_MARK, + EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK, - CC50_STATE0_MARK, DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, - I2C2_SDA_D_MARK, CC50_STATE1_MARK, DU0_DR2_MARK, LCDOUT18_MARK, - CC50_STATE2_MARK, DU0_DR3_MARK, LCDOUT19_MARK, CC50_STATE3_MARK, - DU0_DR4_MARK, LCDOUT20_MARK, CC50_STATE4_MARK, DU0_DR5_MARK, - LCDOUT21_MARK, CC50_STATE5_MARK, DU0_DR6_MARK, LCDOUT22_MARK, - CC50_STATE6_MARK, DU0_DR7_MARK, LCDOUT23_MARK, CC50_STATE7_MARK, + DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK, + DU0_DR2_MARK, LCDOUT18_MARK, + DU0_DR3_MARK, LCDOUT19_MARK, + DU0_DR4_MARK, LCDOUT20_MARK, + DU0_DR5_MARK, LCDOUT21_MARK, + DU0_DR6_MARK, LCDOUT22_MARK, + DU0_DR7_MARK, LCDOUT23_MARK, DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK, - CC50_STATE8_MARK, DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, - I2C3_SDA_D_MARK, CC50_STATE9_MARK, DU0_DG2_MARK, LCDOUT10_MARK, - CC50_STATE10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, CC50_STATE11_MARK, - DU0_DG4_MARK, LCDOUT12_MARK, CC50_STATE12_MARK, + DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK, + DU0_DG2_MARK, LCDOUT10_MARK, + DU0_DG3_MARK, LCDOUT11_MARK, + DU0_DG4_MARK, LCDOUT12_MARK, /* IPSR5 */ - DU0_DG5_MARK, LCDOUT13_MARK, CC50_STATE13_MARK, DU0_DG6_MARK, - LCDOUT14_MARK, CC50_STATE14_MARK, DU0_DG7_MARK, LCDOUT15_MARK, - CC50_STATE15_MARK, DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, - I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK, DU0_DB1_MARK, - LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, CAN0_TX_C_MARK, - CC50_STATE17_MARK, DU0_DB2_MARK, LCDOUT2_MARK, CC50_STATE18_MARK, - DU0_DB3_MARK, LCDOUT3_MARK, CC50_STATE19_MARK, DU0_DB4_MARK, - LCDOUT4_MARK, CC50_STATE20_MARK, DU0_DB5_MARK, LCDOUT5_MARK, - CC50_STATE21_MARK, DU0_DB6_MARK, LCDOUT6_MARK, CC50_STATE22_MARK, - DU0_DB7_MARK, LCDOUT7_MARK, CC50_STATE23_MARK, DU0_DOTCLKIN_MARK, - QSTVA_QVS_MARK, CC50_STATE24_MARK, DU0_DOTCLKOUT0_MARK, - QCLK_MARK, CC50_STATE25_MARK, DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, - CC50_STATE26_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK, - CC50_STATE27_MARK, + DU0_DG5_MARK, LCDOUT13_MARK, + DU0_DG6_MARK, LCDOUT14_MARK, + DU0_DG7_MARK, LCDOUT15_MARK, + DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK, + CAN0_RX_C_MARK, + DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, + CAN0_TX_C_MARK, + DU0_DB2_MARK, LCDOUT2_MARK, + DU0_DB3_MARK, LCDOUT3_MARK, + DU0_DB4_MARK, LCDOUT4_MARK, + DU0_DB5_MARK, LCDOUT5_MARK, + DU0_DB6_MARK, LCDOUT6_MARK, + DU0_DB7_MARK, LCDOUT7_MARK, + DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK, + DU0_DOTCLKOUT0_MARK, QCLK_MARK, + DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, + DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK, /* IPSR6 */ - DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK, - DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK, - DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK, - CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, - AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK, - VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK, - AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK, - VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK, - AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK, - I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK, + DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, + DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, + DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK, + VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK, + VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK, + VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, + VI0_DATA3_VI0_B3_MARK, AVB_RXD2_MARK, + VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK, + VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, + VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK, + VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, + VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, + AVB_RXD7_MARK, VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK, - AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, - IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, - I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK, - VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK, - ADIDATA_MARK, AD_DI_MARK, + AVB_RX_ER_MARK, + VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK, + AVB_COL_MARK, + VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK, + AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, + ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK, + AVB_TX_CLK_MARK, ADIDATA_MARK, /* IPSR7 */ - ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK, - AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK, - MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK, - AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, - CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK, + ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK, + AVB_TXD0_MARK, ADICS_SAMP_MARK, + ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, + AVB_TXD1_MARK, ADICLK_MARK, + ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK, + AVB_TXD2_MARK, ADICHS0_MARK, ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK, - AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK, - MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK, + AVB_TXD3_MARK, ADICHS1_MARK, + ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, + AVB_TXD4_MARK, ADICHS2_MARK, ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK, - SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, - IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK, - VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK, - SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, - AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK, - SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK, + SSI_SCK5_B_MARK, + ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK, + AVB_TXD6_MARK, SSI_WS5_B_MARK, + ETH_TX_EN_MARK, VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK, + AVB_TXD7_MARK, SSI_SDATA5_B_MARK, + ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, AVB_TX_ER_MARK, + SSI_SCK6_B_MARK, + ETH_TXD0_MARK, VI0_R2_MARK, SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, + AVB_GTX_CLK_MARK, SSI_WS6_B_MARK, DREQ0_N_MARK, SCIFB1_RXD_MARK, /* IPSR8 */ @@ -498,103 +566,107 @@ enum { I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK, AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK, SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK, - CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, - DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK, - I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK, - TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK, - I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK, - FMCLK_C_MARK, RDS_CLK_MARK, + CAN1_TX_D_MARK, + I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK, + TS_SDATA_D_MARK, TPUTO1_B_MARK, + I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, TS_SCK_D_MARK, + BPFCLK_C_MARK, + MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK, + TS_SDEN_D_MARK, FMCLK_C_MARK, /* IPSR9 */ MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK, - RIF1_D1_B_MARK, TS_SPSYNC_D_MARK, FMIN_C_MARK, RDS_DATA_MARK, - MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, RIF1_SYNC_MARK, - TPUTO1_C_MARK, MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, - RIF1_CLK_MARK, BPFCLK_B_MARK, MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, - TS_SDEN_MARK, DU1_DR6_MARK, RIF1_D0_MARK, FMCLK_B_MARK, RDS_CLK_B_MARK, + TS_SPSYNC_D_MARK, FMIN_C_MARK, + MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK, + MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK, + MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK, + FMCLK_B_MARK, MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK, - RIF1_D1_MARK, FMIN_B_MARK, RDS_DATA_B_MARK, HSCIF1_HRX_MARK, - I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, HSCIF1_HTX_MARK, - I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, HSCIF1_HSCK_MARK, - PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, SPEEDIN_B_MARK, - VSP_B_MARK, HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, - DU1_DG3_MARK, SSI_SCK1_B_MARK, CAN_DEBUG_HW_TRIGGER_MARK, - CC50_STATE32_MARK, HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, - DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK, CC50_STATE33_MARK, + FMIN_B_MARK, + HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, + HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, + HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, + SPEEDIN_B_MARK, + HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK, + SSI_SCK1_B_MARK, + HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK, + SSI_WS1_B_MARK, SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK, - CAN_TXCLK_MARK, CC50_STATE34_MARK, + CAN_TXCLK_MARK, /* IPSR10 */ - SCIF1_RXD_MARK, IIC0_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK, - CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, IIC0_SDA_MARK, - DU1_DG7_MARK, SSI_WS2_B_MARK, CAN_DEBUGOUT1_MARK, CC50_STATE36_MARK, - SCIF2_RXD_MARK, IIC1_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK, - USB0_EXTLP_MARK, CAN_DEBUGOUT2_MARK, CC50_STATE37_MARK, SCIF2_TXD_MARK, - IIC1_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK, - CAN_DEBUGOUT3_MARK, CC50_STATE38_MARK, SCIF2_SCK_MARK, IRQ1_MARK, - DU1_DB2_MARK, SSI_WS9_B_MARK, USB0_IDIN_MARK, CAN_DEBUGOUT4_MARK, - CC50_STATE39_MARK, SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, - DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK, CAN_DEBUGOUT5_MARK, - CC50_OSCOUT_MARK, SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, - DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, CAN_DEBUGOUT6_MARK, - RDS_CLK_C_MARK, SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, - DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, CAN_DEBUGOUT7_MARK, - RDS_DATA_C_MARK, I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, - AUDIO_CLKC_C_MARK, SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK, I2C2_SDA_MARK, - SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, CAN_DEBUGOUT9_MARK, - SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, CAN_DEBUGOUT10_MARK, + SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK, + SCIF1_TXD_MARK, I2C5_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK, + SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK, + SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, + SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK, + SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK, + SSI_SDATA9_B_MARK, + SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK, + AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, + SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK, + AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, + I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK, + SSI_SDATA4_B_MARK, + I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, + SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, /* IPSR11 */ SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK, - CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, - DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK, - SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK, + SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK, + SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK, - DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK, - SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, - CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK, - DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK, - DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, - AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK, - MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK, - PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, - ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, - PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK, + DU1_EXVSYNC_DU1_VSYNC_MARK, + SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, + DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, + SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, DU1_DISP_MARK, + SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK, + SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK, + CAN_CLK_D_MARK, + SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, + SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK, + SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK, /* IPSR12 */ SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK, - AD_NCS_N_B_MARK, DREQ1_N_B_MARK, SSI_WS34_MARK, MSIOF1_SS1_B_MARK, - SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, CAN1_RX_C_MARK, DACK1_B_MARK, + DREQ1_N_B_MARK, + SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, + CAN1_RX_C_MARK, DACK1_B_MARK, SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK, - CAN1_TX_C_MARK, DREQ2_N_MARK, SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK, - IRD_TX_MARK, SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, IRD_RX_MARK, - SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, IRD_SCK_MARK, + CAN1_TX_C_MARK, DREQ2_N_MARK, + SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK, + SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, + SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK, - DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK, - IIC1_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK, - ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK, - VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK, - SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK, - ATAWR0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, - VI1_DATA2_MARK, MDATA_MARK, ATAG0_N_MARK, ETH_RXD1_B_MARK, + DACK2_MARK, ETH_MDIO_B_MARK, + SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK, + CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK, + SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK, + CAN0_TX_D_MARK, ETH_RX_ER_B_MARK, + SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, ATAWR0_N_MARK, + ETH_RXD0_B_MARK, + SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK, ATAG0_N_MARK, + ETH_RXD1_B_MARK, /* IPSR13 */ SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK, - SCKZ_MARK, ATACS00_N_MARK, ETH_LINK_B_MARK, SSI_SDATA2_MARK, - HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, VI1_DATA4_MARK, STM_N_MARK, - ATACS10_N_MARK, ETH_REFCLK_B_MARK, SSI_SCK9_MARK, SCIF2_SCK_B_MARK, - PWM2_B_MARK, VI1_DATA5_MARK, MTS_N_MARK, EX_WAIT1_MARK, - ETH_TXD1_B_MARK, SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, - VI1_DATA6_MARK, ATARD0_N_MARK, ETH_TX_EN_B_MARK, SSI_SDATA9_MARK, - SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, ATADIR0_N_MARK, - ETH_MAGIC_B_MARK, AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, - VI1_CLKENB_MARK, TS_SDATA_C_MARK, RIF0_SYNC_B_MARK, ETH_TXD0_B_MARK, + ATACS00_N_MARK, ETH_LINK_B_MARK, + SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, + VI1_DATA4_MARK, ATACS10_N_MARK, ETH_REFCLK_B_MARK, + SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK, + EX_WAIT1_MARK, ETH_TXD1_B_MARK, + SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK, + ATARD0_N_MARK, ETH_TX_EN_B_MARK, + SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, + ATADIR0_N_MARK, ETH_MAGIC_B_MARK, + AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK, + TS_SDATA_C_MARK, ETH_TXD0_B_MARK, AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK, - TS_SCK_C_MARK, RIF0_CLK_B_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK, + TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK, AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK, - TS_SDEN_C_MARK, RIF0_D0_B_MARK, FMCLK_E_MARK, RDS_CLK_D_MARK, + TS_SDEN_C_MARK, FMCLK_E_MARK, AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK, - TS_SPSYNC_C_MARK, RIF0_D1_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, + TS_SPSYNC_C_MARK, FMIN_E_MARK, PINMUX_MARK_END, }; @@ -700,15 +772,14 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3), PINMUX_IPSR_GPSR(IP1_17_15, D13), PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0), - PINMUX_IPSR_GPSR(IP1_17_15, TANS1), PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C), PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1), PINMUX_IPSR_GPSR(IP1_19_18, D14), PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0), - PINMUX_IPSR_MSEL(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1), + PINMUX_IPSR_MSEL(IP1_19_18, I2C5_SCL_B, SEL_I2C05_1), PINMUX_IPSR_GPSR(IP1_21_20, D15), PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0), - PINMUX_IPSR_MSEL(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1), + PINMUX_IPSR_MSEL(IP1_21_20, I2C5_SDA_B, SEL_I2C05_1), PINMUX_IPSR_GPSR(IP1_23_22, A0), PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK), PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B), @@ -739,10 +810,10 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1), PINMUX_IPSR_GPSR(IP2_7_6, A10), PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0), - PINMUX_IPSR_MSEL(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1), + PINMUX_IPSR_MSEL(IP2_7_6, IIC0_SCL_B, SEL_IIC0_1), PINMUX_IPSR_GPSR(IP2_9_8, A11), PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0), - PINMUX_IPSR_MSEL(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1), + PINMUX_IPSR_MSEL(IP2_9_8, IIC0_SDA_B, SEL_IIC0_1), PINMUX_IPSR_GPSR(IP2_11_10, A12), PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0), PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1), @@ -761,39 +832,31 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0), PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1), PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0), - PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0), PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2), PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B), PINMUX_IPSR_GPSR(IP2_23_21, A17), PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0), PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4), PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1), - PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1), PINMUX_IPSR_GPSR(IP2_26_24, A18), PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0), PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4), PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1), - PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1), PINMUX_IPSR_GPSR(IP2_29_27, A19), PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0), PINMUX_IPSR_GPSR(IP2_29_27, PWM4), PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2), - PINMUX_IPSR_GPSR(IP2_29_27, MOUT0), PINMUX_IPSR_GPSR(IP2_31_30, A20), PINMUX_IPSR_GPSR(IP2_31_30, SPCLK), - PINMUX_IPSR_GPSR(IP2_29_27, MOUT1), /* IPSR3 */ PINMUX_IPSR_GPSR(IP3_1_0, A21), PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0), - PINMUX_IPSR_GPSR(IP3_1_0, MOUT2), PINMUX_IPSR_GPSR(IP3_3_2, A22), PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1), - PINMUX_IPSR_GPSR(IP3_3_2, MOUT5), PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N), PINMUX_IPSR_GPSR(IP3_5_4, A23), PINMUX_IPSR_GPSR(IP3_5_4, IO2), - PINMUX_IPSR_GPSR(IP3_5_4, MOUT6), PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N), PINMUX_IPSR_GPSR(IP3_7_6, A24), PINMUX_IPSR_GPSR(IP3_7_6, IO3), @@ -815,40 +878,31 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP3_17_15, PWM0), PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2), PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1), - PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0), PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3), PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD), - PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1), PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N), PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0), PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2), PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1), - PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0), PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0), PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK), - PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1), PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N), PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0), PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4), PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1), - PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0), PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0), PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N), - PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1), PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N), PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0), PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4), PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1), - PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0), PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0), PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N), - PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1), PINMUX_IPSR_GPSR(IP3_29_27, BS_N), PINMUX_IPSR_GPSR(IP3_29_27, DRACK0), PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C), PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C), PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N), - PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1), PINMUX_IPSR_GPSR(IP3_30, RD_N), PINMUX_IPSR_GPSR(IP3_30, ATACS11_N), PINMUX_IPSR_GPSR(IP3_31, RD_WR_N), @@ -858,121 +912,88 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0), PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1), PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0), - PINMUX_IPSR_GPSR(IP4_1_0, PWMFSW0), PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0), PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16), PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2), PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3), - PINMUX_IPSR_GPSR(IP4_4_2, CC50_STATE0), PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1), PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17), PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2), PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3), - PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE1), PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2), PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18), - PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE2), PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3), PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19), - PINMUX_IPSR_GPSR(IP4_11_10, CC50_STATE3), PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4), PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20), - PINMUX_IPSR_GPSR(IP4_13_12, CC50_STATE4), PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5), PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21), - PINMUX_IPSR_GPSR(IP4_15_14, CC50_STATE5), PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6), PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22), - PINMUX_IPSR_GPSR(IP4_17_16, CC50_STATE6), PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7), PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23), - PINMUX_IPSR_GPSR(IP4_19_18, CC50_STATE7), PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0), PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8), PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2), PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3), - PINMUX_IPSR_GPSR(IP4_22_20, CC50_STATE8), PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1), PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9), PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2), PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3), - PINMUX_IPSR_GPSR(IP4_25_23, CC50_STATE9), PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2), PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10), - PINMUX_IPSR_GPSR(IP4_27_26, CC50_STATE10), PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3), PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11), - PINMUX_IPSR_GPSR(IP4_29_28, CC50_STATE11), PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4), PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12), - PINMUX_IPSR_GPSR(IP4_31_30, CC50_STATE12), /* IPSR5 */ PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5), PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13), - PINMUX_IPSR_GPSR(IP5_1_0, CC50_STATE13), PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6), PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14), - PINMUX_IPSR_GPSR(IP5_3_2, CC50_STATE14), PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7), PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15), - PINMUX_IPSR_GPSR(IP5_5_4, CC50_STATE15), PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0), PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0), PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2), PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3), PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2), - PINMUX_IPSR_GPSR(IP5_8_6, CC50_STATE16), PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1), PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1), PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2), PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3), PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2), - PINMUX_IPSR_GPSR(IP5_11_9, CC50_STATE17), PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2), PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2), - PINMUX_IPSR_GPSR(IP5_13_12, CC50_STATE18), PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3), PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3), - PINMUX_IPSR_GPSR(IP5_15_14, CC50_STATE19), PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4), PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4), - PINMUX_IPSR_GPSR(IP5_17_16, CC50_STATE20), PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5), PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5), - PINMUX_IPSR_GPSR(IP5_19_18, CC50_STATE21), PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6), PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6), - PINMUX_IPSR_GPSR(IP5_21_20, CC50_STATE22), PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7), PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7), - PINMUX_IPSR_GPSR(IP5_23_22, CC50_STATE23), PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN), PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS), - PINMUX_IPSR_GPSR(IP5_25_24, CC50_STATE24), PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0), PINMUX_IPSR_GPSR(IP5_27_26, QCLK), - PINMUX_IPSR_GPSR(IP5_27_26, CC50_STATE25), PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1), PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE), - PINMUX_IPSR_GPSR(IP5_29_28, CC50_STATE26), PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC), PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS), - PINMUX_IPSR_GPSR(IP5_31_30, CC50_STATE27), /* IPSR6 */ PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC), PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE), - PINMUX_IPSR_GPSR(IP6_1_0, CC50_STATE28), PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE), PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE), - PINMUX_IPSR_GPSR(IP6_3_2, CC50_STATE29), PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP), PINMUX_IPSR_GPSR(IP6_5_4, QPOLA), - PINMUX_IPSR_GPSR(IP6_5_4, CC50_STATE30), PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE), PINMUX_IPSR_GPSR(IP6_7_6, QPOLB), - PINMUX_IPSR_GPSR(IP6_7_6, CC50_STATE31), PINMUX_IPSR_GPSR(IP6_8, VI0_CLK), PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK), PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0), @@ -1014,33 +1035,29 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0), PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0), PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), - PINMUX_IPSR_MSEL(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3), + PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3), PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK), PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0), - PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0), /* IPSR7 */ PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1), PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), - PINMUX_IPSR_MSEL(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3), + PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3), PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0), PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0), - PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0), PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0), PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2), PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1), PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0), - PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0), PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0), PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3), PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2), PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0), - PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0), PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0), PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4), PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), @@ -1061,13 +1078,13 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0), PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7), PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2), - PINMUX_IPSR_MSEL(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3), + PINMUX_IPSR_MSEL(IP7_20_18, IIC0_SCL_D, SEL_IIC0_3), PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6), PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1), PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0), PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0), PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2), - PINMUX_IPSR_MSEL(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3), + PINMUX_IPSR_MSEL(IP7_23_21, IIC0_SDA_D, SEL_IIC0_3), PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7), PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1), PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0), @@ -1136,60 +1153,48 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B), PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0), - PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1), PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B), PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0), PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), PINMUX_IPSR_GPSR(IP8_28_26, IRQ5), PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1), - PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1), PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2), PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD), PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2), - PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1), PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2), - PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0), /* IPSR9 */ PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD), PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0), PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2), PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3), - PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1), PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3), PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2), - PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0), PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK), PINMUX_IPSR_GPSR(IP9_5_3, IRQ0), PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0), PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4), - PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0), PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C), PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC), PINMUX_IPSR_GPSR(IP9_8_6, PWM1), PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0), PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5), - PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0), PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1), PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1), PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0), PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0), PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6), - PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0), PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1), - PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1), PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2), PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0), PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0), PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7), - PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0), PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1), - PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1), PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0), PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0), PINMUX_IPSR_GPSR(IP9_16_15, PWM6), @@ -1204,165 +1209,124 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2), PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1), PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1), - PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1), PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0), PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0), PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0), PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3), PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1), - PINMUX_IPSR_GPSR(IP9_24_22, CAN_DEBUG_HW_TRIGGER), - PINMUX_IPSR_GPSR(IP9_24_22, CC50_STATE32), PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0), PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0), PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0), PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4), PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1), - PINMUX_IPSR_GPSR(IP9_27_25, CAN_STEP0), - PINMUX_IPSR_GPSR(IP9_27_25, CC50_STATE33), PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0), PINMUX_IPSR_GPSR(IP9_30_28, PWM3), PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0), PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5), PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1), - PINMUX_IPSR_GPSR(IP9_30_28, CAN_TXCLK), - PINMUX_IPSR_GPSR(IP9_30_28, CC50_STATE34), /* IPSR10 */ PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0), - PINMUX_IPSR_MSEL(IP10_2_0, IIC0_SCL, SEL_IIC00_0), + PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0), PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6), PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1), - PINMUX_IPSR_GPSR(IP10_2_0, CAN_DEBUGOUT0), - PINMUX_IPSR_GPSR(IP10_2_0, CC50_STATE35), PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0), - PINMUX_IPSR_MSEL(IP10_5_3, IIC0_SDA, SEL_IIC00_0), + PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0), PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7), PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1), - PINMUX_IPSR_GPSR(IP10_5_3, CAN_DEBUGOUT1), - PINMUX_IPSR_GPSR(IP10_5_3, CC50_STATE36), PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0), - PINMUX_IPSR_MSEL(IP10_8_6, IIC1_SCL, SEL_IIC01_0), + PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0), PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0), PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1), - PINMUX_IPSR_GPSR(IP10_8_6, USB0_EXTLP), - PINMUX_IPSR_GPSR(IP10_8_6, CAN_DEBUGOUT2), - PINMUX_IPSR_GPSR(IP10_8_6, CC50_STATE37), PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0), - PINMUX_IPSR_MSEL(IP10_11_9, IIC1_SDA, SEL_IIC01_0), + PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0), PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1), PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1), - PINMUX_IPSR_GPSR(IP10_11_9, USB0_OVC1), - PINMUX_IPSR_GPSR(IP10_11_9, CAN_DEBUGOUT3), - PINMUX_IPSR_GPSR(IP10_11_9, CC50_STATE38), PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0), PINMUX_IPSR_GPSR(IP10_14_12, IRQ1), PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2), PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1), - PINMUX_IPSR_GPSR(IP10_14_12, USB0_IDIN), - PINMUX_IPSR_GPSR(IP10_14_12, CAN_DEBUGOUT4), - PINMUX_IPSR_GPSR(IP10_14_12, CC50_STATE39), PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0), PINMUX_IPSR_GPSR(IP10_17_15, IRQ2), PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3), PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3), PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1), - PINMUX_IPSR_GPSR(IP10_17_15, TANS2), - PINMUX_IPSR_GPSR(IP10_17_15, CAN_DEBUGOUT5), - PINMUX_IPSR_GPSR(IP10_17_15, CC50_OSCOUT), PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0), PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4), PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3), PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4), PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2), PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1), - PINMUX_IPSR_GPSR(IP10_20_18, CAN_DEBUGOUT6), - PINMUX_IPSR_MSEL(IP10_20_18, RDS_CLK_C, SEL_RDS_2), PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0), PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4), PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3), PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5), PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2), PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1), - PINMUX_IPSR_GPSR(IP10_23_21, CAN_DEBUGOUT7), - PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2), PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0), PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0), PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6), PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2), PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1), - PINMUX_IPSR_GPSR(IP10_26_24, CAN_DEBUGOUT8), PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0), PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0), PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7), PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2), - PINMUX_IPSR_GPSR(IP10_29_27, CAN_DEBUGOUT9), PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0), PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0), PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN), - PINMUX_IPSR_GPSR(IP10_31_30, CAN_DEBUGOUT10), /* IPSR11 */ PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0), PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0), - PINMUX_IPSR_GPSR(IP11_2_0, CAN_DEBUGOUT11), PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1), - PINMUX_IPSR_GPSR(IP11_5_3, CAN_DEBUGOUT12), PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0), PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC), - PINMUX_IPSR_GPSR(IP11_7_6, CAN_DEBUGOUT13), PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0), PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC), - PINMUX_IPSR_GPSR(IP11_10_8, CAN_DEBUGOUT14), PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE), - PINMUX_IPSR_GPSR(IP11_13_11, CAN_DEBUGOUT15), PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0), PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), - PINMUX_IPSR_MSEL(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2), + PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2), PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP), PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0), PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1), - PINMUX_IPSR_MSEL(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2), + PINMUX_IPSR_MSEL(IP11_17_16, I2C5_SCL_C, SEL_I2C05_2), PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE), PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0), PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1), PINMUX_IPSR_GPSR(IP11_20_18, IRQ8), PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3), - PINMUX_IPSR_GPSR(IP11_20_18, PCMOE_N), PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129), PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1), - PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1), - PINMUX_IPSR_GPSR(IP11_23_21, PCMWE_N), PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129), PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), - PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1), PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0), PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B), PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1), - PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1), /* IPSR12 */ PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34), PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1), PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2), PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1), - PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1), PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1), PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34), PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1), @@ -1379,15 +1343,12 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0), PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK), PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1), - PINMUX_IPSR_GPSR(IP12_10_9, IRD_TX), PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0), PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG), PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1), - PINMUX_IPSR_GPSR(IP12_12_11, IRD_RX), PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0), PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT), PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1), - PINMUX_IPSR_GPSR(IP12_14_13, IRD_SCK), PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0), PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1), PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B), @@ -1397,28 +1358,24 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1), PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0), PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1), - PINMUX_IPSR_MSEL(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2), + PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2), PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK), PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3), - PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0), PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1), PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0), PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1), - PINMUX_IPSR_MSEL(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2), + PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2), PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0), PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3), - PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0), PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1), PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0), PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1), PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1), - PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0), PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N), PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1), PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1), PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2), - PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0), PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N), PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1), @@ -1427,21 +1384,18 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3), PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3), - PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0), PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N), PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1), PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0), PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1), PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3), PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4), - PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0), PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N), PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1), PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0), PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1), PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B), PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5), - PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0), PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1), PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1), PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0), @@ -1461,14 +1415,12 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3), PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB), PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2), - PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1), PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1), PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0), PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1), PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3), PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD), PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2), - PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1), PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4), PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1), PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0), @@ -1476,17 +1428,13 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3), PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N), PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2), - PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1), PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4), - PINMUX_IPSR_MSEL(IP13_23_21, RDS_CLK_D, SEL_RDS_3), PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0), PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1), PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3), PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N), PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2), - PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1), PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4), - PINMUX_IPSR_MSEL(IP13_26_24, RDS_DATA_D, SEL_RDS_3), }; static const struct sh_pfc_pin pinmux_pins[] = { @@ -1660,30 +1608,6 @@ static const unsigned int avb_gmii_mux[] = { AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, AVB_COL_MARK, }; -static const unsigned int avb_avtp_capture_pins[] = { - RCAR_GP_PIN(5, 11), -}; -static const unsigned int avb_avtp_capture_mux[] = { - AVB_AVTP_CAPTURE_MARK, -}; -static const unsigned int avb_avtp_match_pins[] = { - RCAR_GP_PIN(5, 12), -}; -static const unsigned int avb_avtp_match_mux[] = { - AVB_AVTP_MATCH_MARK, -}; -static const unsigned int avb_avtp_capture_b_pins[] = { - RCAR_GP_PIN(1, 1), -}; -static const unsigned int avb_avtp_capture_b_mux[] = { - AVB_AVTP_CAPTURE_B_MARK, -}; -static const unsigned int avb_avtp_match_b_pins[] = { - RCAR_GP_PIN(1, 2), -}; -static const unsigned int avb_avtp_match_b_mux[] = { - AVB_AVTP_MATCH_B_MARK, -}; /* - DU --------------------------------------------------------------------- */ static const unsigned int du0_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -3535,10 +3459,6 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(avb_mdio), SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_gmii), - SH_PFC_PIN_GROUP(avb_avtp_capture), - SH_PFC_PIN_GROUP(avb_avtp_match), - SH_PFC_PIN_GROUP(avb_avtp_capture_b), - SH_PFC_PIN_GROUP(avb_avtp_match_b), SH_PFC_PIN_GROUP(du0_rgb666), SH_PFC_PIN_GROUP(du0_rgb888), SH_PFC_PIN_GROUP(du0_clk0_out), @@ -3809,10 +3729,6 @@ static const char * const avb_groups[] = { "avb_mdio", "avb_mii", "avb_gmii", - "avb_avtp_capture", - "avb_avtp_match", - "avb_avtp_capture_b", - "avb_avtp_match_b", }; static const char * const du0_groups[] = { @@ -4540,11 +4456,11 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP1_23_22 [2] */ FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0, /* IP1_21_20 [2] */ - FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, 0, + FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 0, /* IP1_19_18 [2] */ - FN_D14, FN_SCIFA1_RXD, FN_IIC0_SCL_B, 0, + FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0, /* IP1_17_15 [3] */ - FN_D13, FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, + FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0, /* IP1_14_13 [2] */ FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, @@ -4565,19 +4481,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, 2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) { /* IP2_31_30 [2] */ - FN_A20, FN_SPCLK, FN_MOUT1, 0, + FN_A20, FN_SPCLK, 0, 0, /* IP2_29_27 [3] */ FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2, - FN_MOUT0, 0, 0, 0, + 0, 0, 0, 0, /* IP2_26_24 [3] */ FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B, - FN_AVB_AVTP_MATCH_B, 0, 0, 0, + 0, 0, 0, 0, /* IP2_23_21 [3] */ FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B, - FN_AVB_AVTP_CAPTURE_B, 0, 0, 0, + 0, 0, 0, 0, /* IP2_20_18 [3] */ FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, - FN_VSP, FN_CAN_CLK_C, FN_TPUTO2_B, 0, + 0, FN_CAN_CLK_C, FN_TPUTO2_B, 0, /* IP2_17_16 [2] */ FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, /* IP2_15_14 [2] */ @@ -4587,9 +4503,9 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP2_11_10 [2] */ FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0, /* IP2_9_8 [2] */ - FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, 0, + FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 0, /* IP2_7_6 [2] */ - FN_A10, FN_MSIOF1_SCK, FN_IIC1_SCL_B, 0, + FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 0, /* IP2_5_4 [2] */ FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0, /* IP2_3_2 [2] */ @@ -4605,19 +4521,19 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_RD_N, FN_ATACS11_N, /* IP3_29_27 [3] */ FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, - FN_MTS_N_B, 0, 0, + 0, 0, 0, /* IP3_26_24 [3] */ FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, - FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B, + 0, FN_FMIN, FN_SCIFB2_RTS_N, 0, /* IP3_23_21 [3] */ FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, - FN_RIF0_D0, FN_FMCLK, FN_SCIFB2_CTS_N, FN_SCKZ_B, + 0, FN_FMCLK, FN_SCIFB2_CTS_N, 0, /* IP3_20_18 [3] */ FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, - FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, + 0, FN_BPFCLK, FN_SCIFB2_SCK, 0, /* IP3_17_15 [3] */ FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, - FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, FN_SDATA_B, + 0, FN_TPUTO3, FN_SCIFB2_TXD, 0, /* IP3_14_13 [2] */ FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, /* IP3_12 [1] */ @@ -4631,88 +4547,88 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP3_7_6 [2] */ FN_A24, FN_IO3, FN_EX_WAIT2, 0, /* IP3_5_4 [2] */ - FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, + FN_A23, FN_IO2, 0, FN_ATAWR1_N, /* IP3_3_2 [2] */ - FN_A22, FN_MISO_IO1, FN_MOUT5, FN_ATADIR1_N, + FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N, /* IP3_1_0 [2] */ - FN_A21, FN_MOSI_IO0, FN_MOUT2, 0, } + FN_A21, FN_MOSI_IO0, 0, 0, } }, { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) { /* IP4_31_30 [2] */ - FN_DU0_DG4, FN_LCDOUT12, FN_CC50_STATE12, 0, + FN_DU0_DG4, FN_LCDOUT12, 0, 0, /* IP4_29_28 [2] */ - FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, 0, + FN_DU0_DG3, FN_LCDOUT11, 0, 0, /* IP4_27_26 [2] */ - FN_DU0_DG2, FN_LCDOUT10, FN_CC50_STATE10, 0, + FN_DU0_DG2, FN_LCDOUT10, 0, 0, /* IP4_25_23 [3] */ FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, - FN_CC50_STATE9, 0, 0, 0, + 0, 0, 0, 0, /* IP4_22_20 [3] */ FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, - FN_CC50_STATE8, 0, 0, 0, + 0, 0, 0, 0, /* IP4_19_18 [2] */ - FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, 0, + FN_DU0_DR7, FN_LCDOUT23, 0, 0, /* IP4_17_16 [2] */ - FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, 0, + FN_DU0_DR6, FN_LCDOUT22, 0, 0, /* IP4_15_14 [2] */ - FN_DU0_DR5, FN_LCDOUT21, FN_CC50_STATE5, 0, + FN_DU0_DR5, FN_LCDOUT21, 0, 0, /* IP4_13_12 [2] */ - FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, 0, + FN_DU0_DR4, FN_LCDOUT20, 0, 0, /* IP4_11_10 [2] */ - FN_DU0_DR3, FN_LCDOUT19, FN_CC50_STATE3, 0, + FN_DU0_DR3, FN_LCDOUT19, 0, 0, /* IP4_9_8 [2] */ - FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, 0, + FN_DU0_DR2, FN_LCDOUT18, 0, 0, /* IP4_7_5 [3] */ FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, - FN_CC50_STATE1, 0, 0, 0, + 0, 0, 0, 0, /* IP4_4_2 [3] */ FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, - FN_CC50_STATE0, 0, 0, 0, + 0, 0, 0, 0, /* IP4_1_0 [2] */ - FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, } + FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, } }, { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) { /* IP5_31_30 [2] */ - FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, 0, + FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0, /* IP5_29_28 [2] */ - FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_CC50_STATE26, 0, + FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0, /* IP5_27_26 [2] */ - FN_DU0_DOTCLKOUT0, FN_QCLK, FN_CC50_STATE25, 0, + FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0, /* IP5_25_24 [2] */ - FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, 0, + FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0, /* IP5_23_22 [2] */ - FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, 0, + FN_DU0_DB7, FN_LCDOUT7, 0, 0, /* IP5_21_20 [2] */ - FN_DU0_DB6, FN_LCDOUT6, FN_CC50_STATE22, 0, + FN_DU0_DB6, FN_LCDOUT6, 0, 0, /* IP5_19_18 [2] */ - FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, 0, + FN_DU0_DB5, FN_LCDOUT5, 0, 0, /* IP5_17_16 [2] */ - FN_DU0_DB4, FN_LCDOUT4, FN_CC50_STATE20, 0, + FN_DU0_DB4, FN_LCDOUT4, 0, 0, /* IP5_15_14 [2] */ - FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, 0, + FN_DU0_DB3, FN_LCDOUT3, 0, 0, /* IP5_13_12 [2] */ - FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, 0, + FN_DU0_DB2, FN_LCDOUT2, 0, 0, /* IP5_11_9 [3] */ FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, - FN_CAN0_TX_C, FN_CC50_STATE17, 0, 0, + FN_CAN0_TX_C, 0, 0, 0, /* IP5_8_6 [3] */ FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, - FN_CAN0_RX_C, FN_CC50_STATE16, 0, 0, + FN_CAN0_RX_C, 0, 0, 0, /* IP5_5_4 [2] */ - FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, 0, + FN_DU0_DG7, FN_LCDOUT15, 0, 0, /* IP5_3_2 [2] */ - FN_DU0_DG6, FN_LCDOUT14, FN_CC50_STATE14, 0, + FN_DU0_DG6, FN_LCDOUT14, 0, 0, /* IP5_1_0 [2] */ - FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, 0, } + FN_DU0_DG5, FN_LCDOUT13, 0, 0, } }, { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2) { /* IP6_31_29 [3] */ - FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, - FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0, + FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, + FN_AVB_TX_CLK, FN_ADIDATA, 0, 0, /* IP6_28_26 [3] */ FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0, @@ -4744,14 +4660,14 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* IP6_8 [1] */ FN_VI0_CLK, FN_AVB_RX_CLK, /* IP6_7_6 [2] */ - FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0, + FN_DU0_CDE, FN_QPOLB, 0, 0, /* IP6_5_4 [2] */ - FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0, + FN_DU0_DISP, FN_QPOLA, 0, 0, /* IP6_3_2 [2] */ - FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, + FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, /* IP6_1_0 [2] */ - FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, } + FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, } }, { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { @@ -4766,10 +4682,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B, 0, 0, 0, /* IP7_23_21 [3] */ - FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D, + FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0, /* IP7_20_18 [3] */ - FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D, + FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0, /* IP7_17_15 [3] */ FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, @@ -4782,25 +4698,25 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_AVB_TXD3, FN_ADICHS1, 0, 0, /* IP7_8_6 [3] */ FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, - FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0, + FN_AVB_TXD2, FN_ADICHS0, 0, 0, /* IP7_5_3 [3] */ FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, - FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0, + FN_AVB_TXD1, FN_ADICLK, 0, 0, /* IP7_2_0 [3] */ - FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, - FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, } + FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, + FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, } }, { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) { /* IP8_31_29 [3] */ FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, - FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, + 0, FN_TS_SDEN_D, FN_FMCLK_C, 0, /* IP8_28_26 [3] */ FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, - FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0, + 0, FN_TS_SCK_D, FN_BPFCLK_C, 0, /* IP8_25_23 [3] */ FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, - FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0, + 0, FN_TS_SDATA_D, FN_TPUTO1_B, 0, /* IP8_22_20 [3] */ FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0, @@ -4831,70 +4747,70 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, /* IP9_30_28 [3] */ FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, - FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, 0, + FN_SSI_SDATA1_B, 0, 0, 0, /* IP9_27_25 [3] */ FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, - FN_SSI_WS1_B, FN_CAN_STEP0, FN_CC50_STATE33, 0, + FN_SSI_WS1_B, 0, 0, 0, /* IP9_24_22 [3] */ FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, - FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, 0, + FN_SSI_SCK1_B, 0, 0, 0, /* IP9_21_19 [3] */ FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, - FN_REMOCON_B, FN_SPEEDIN_B, FN_VSP_B, 0, + FN_REMOCON_B, FN_SPEEDIN_B, 0, 0, /* IP9_18_17 [2] */ FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1, /* IP9_16_15 [2] */ FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0, /* IP9_14_12 [3] */ FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, - FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, 0, + 0, FN_FMIN_B, 0, 0, /* IP9_11_9 [3] */ FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, - FN_RIF1_D0, FN_FMCLK_B, FN_RDS_CLK_B, 0, + 0, FN_FMCLK_B, 0, 0, /* IP9_8_6 [3] */ FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, - FN_RIF1_CLK, FN_BPFCLK_B, 0, 0, + 0, FN_BPFCLK_B, 0, 0, /* IP9_5_3 [3] */ FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, - FN_RIF1_SYNC, FN_TPUTO1_C, 0, 0, + 0, FN_TPUTO1_C, 0, 0, /* IP9_2_0 [3] */ FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, - FN_RIF1_D1_B, FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, } + 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, } }, { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { /* IP10_31_30 [2] */ - FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10, + FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0, /* IP10_29_27 [3] */ FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, - FN_CAN_DEBUGOUT9, 0, 0, 0, + 0, 0, 0, 0, /* IP10_26_24 [3] */ FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C, - FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, 0, 0, + FN_SSI_SDATA4_B, 0, 0, 0, /* IP10_23_21 [3] */ FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, - FN_AUDIO_CLKB_C, FN_SSI_WS4_B, FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, + FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0, /* IP10_20_18 [3] */ FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, - FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, + FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0, /* IP10_17_15 [3] */ FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, - FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT, + FN_SSI_SDATA9_B, 0, 0, 0, /* IP10_14_12 [3] */ FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B, - FN_USB0_IDIN, FN_CAN_DEBUGOUT4, FN_CC50_STATE39, 0, + 0, 0, 0, 0, /* IP10_11_9 [3] */ - FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, - FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, 0, + FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B, + 0, 0, 0, 0, /* IP10_8_6 [3] */ - FN_SCIF2_RXD, FN_IIC1_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B, - FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, FN_CC50_STATE37, 0, + FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B, + 0, 0, 0, 0, /* IP10_5_3 [3] */ - FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B, - FN_CAN_DEBUGOUT1, FN_CC50_STATE36, 0, 0, + FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B, + 0, 0, 0, 0, /* IP10_2_0 [3] */ - FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, - FN_CAN_DEBUGOUT0, FN_CC50_STATE35, 0, 0, } + FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, + 0, 0, 0, 0, } }, { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) { @@ -4902,61 +4818,60 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, 0, 0, /* IP11_29_27 [3] */ FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, - FN_AD_CLK_B, 0, 0, 0, + 0, 0, 0, 0, /* IP11_26_24 [3] */ FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B, - FN_AD_DO_B, 0, 0, 0, + 0, 0, 0, 0, /* IP11_23_21 [3] */ FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, - FN_AD_DI_B, FN_PCMWE_N, 0, 0, + 0, 0, 0, 0, /* IP11_20_18 [3] */ FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, - FN_CAN_CLK_D, FN_PCMOE_N, 0, 0, + FN_CAN_CLK_D, 0, 0, 0, /* IP11_17_16 [2] */ - FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, + FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE, /* IP11_15_14 [2] */ - FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, + FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP, /* IP11_13_11 [3] */ FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, - FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0, + FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0, /* IP11_10_8 [3] */ FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, - FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0, + FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0, /* IP11_7_6 [2] */ - FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, - FN_CAN_DEBUGOUT13, + FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0, /* IP11_5_3 [3] */ FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1, - FN_CAN_DEBUGOUT12, 0, 0, 0, + 0, 0, 0, 0, /* IP11_2_0 [3] */ FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, - FN_CAN_DEBUGOUT11, 0, 0, 0, } + 0, 0, 0, 0, } }, { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, 2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) { /* IP12_31_30 [2] */ 0, 0, 0, 0, /* IP12_29_27 [3] */ - FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA, + FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0, FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0, /* IP12_26_24 [3] */ - FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA, + FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0, FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0, /* IP12_23_21 [3] */ - FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0, - FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0, + FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, + FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0, /* IP12_20_18 [3] */ - FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, - FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, 0, + FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, + FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0, /* IP12_17_15 [3] */ FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0, /* IP12_14_13 [2] */ - FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, FN_IRD_SCK, + FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0, /* IP12_12_11 [2] */ - FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, + FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0, /* IP12_10_9 [2] */ - FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, + FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0, /* IP12_8_6 [3] */ FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, FN_CAN1_TX_C, FN_DREQ2_N, 0, 0, @@ -4965,7 +4880,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_CAN1_RX_C, FN_DACK1_B, 0, 0, /* IP12_2_0 [3] */ FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B, - FN_AD_NCS_N_B, FN_DREQ1_N_B, 0, 0, } + 0, FN_DREQ1_N_B, 0, 0, } }, { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) { @@ -4981,16 +4896,16 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 0, 0, /* IP13_26_24 [3] */ FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, - FN_TS_SPSYNC_C, FN_RIF0_D1_B, FN_FMIN_E, FN_RDS_DATA_D, + FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0, /* IP13_23_21 [3] */ FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, - FN_TS_SDEN_C, FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, + FN_TS_SDEN_C, 0, FN_FMCLK_E, 0, /* IP13_20_18 [3] */ FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD, - FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, + FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B, /* IP13_17_15 [3] */ FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB, - FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, 0, + FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0, /* IP13_14_12 [3] */ FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0, @@ -4999,38 +4914,32 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0, /* IP13_8_6 [3] */ FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, - FN_MTS_N, FN_EX_WAIT1, FN_ETH_TXD1_B, 0, + 0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0, /* IP13_5_3 [2] */ FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, - FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, 0, + FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0, /* IP13_2_0 [3] */ FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, - FN_SCKZ, FN_ATACS00_N, FN_ETH_LINK_B, 0, } + 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, } }, { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, - 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, + 2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1) { /* SEL_ADG [2] */ FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, - /* SEL_ADI [1] */ - FN_SEL_ADI_0, FN_SEL_ADI_1, + /* RESERVED [1] */ + 0, 0, /* SEL_CAN [2] */ FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, /* SEL_DARC [3] */ FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, 0, 0, 0, - /* SEL_DR0 [1] */ - FN_SEL_DR0_0, FN_SEL_DR0_1, - /* SEL_DR1 [1] */ - FN_SEL_DR1_0, FN_SEL_DR1_1, - /* SEL_DR2 [1] */ - FN_SEL_DR2_0, FN_SEL_DR2_1, - /* SEL_DR3 [1] */ - FN_SEL_DR3_0, FN_SEL_DR3_1, + /* RESERVED [4] */ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* SEL_ETH [1] */ FN_SEL_ETH_0, FN_SEL_ETH_1, - /* SLE_FSN [1] */ - FN_SEL_FSN_0, FN_SEL_FSN_1, + /* RESERVED [1] */ + 0, 0, /* SEL_IC200 [3] */ FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, FN_SEL_I2C00_4, 0, 0, 0, @@ -5046,10 +4955,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_I2C04 [3] */ FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, FN_SEL_I2C04_4, 0, 0, 0, - /* SEL_IIC00 [2] */ - FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3, - /* SEL_AVB [1] */ - FN_SEL_AVB_0, FN_SEL_AVB_1, } + /* SEL_I2C05 [2] */ + FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3, + /* RESERVED [1] */ + 0, 0, } }, { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, @@ -5057,7 +4966,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_IEB [2] */ FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, /* SEL_IIC0 [2] */ - FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, + FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3, /* SEL_LBS [1] */ FN_SEL_LBS_0, FN_SEL_LBS_1, /* SEL_MSI1 [1] */ @@ -5085,8 +4994,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SCIFA5 [2] */ FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, - /* SEL_SPDM [1] */ - FN_SEL_SPDM_0, FN_SEL_SPDM_1, + /* RESERVED [1] */ + 0, 0, /* SEL_TMU [1] */ FN_SEL_TMU_0, FN_SEL_TMU_1, /* SEL_TSIF0 [2] */ @@ -5099,8 +5008,8 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, /* SEL_HSCIF1 [1] */ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, - /* SEL_RDS [2] */ - FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, } + /* RESERVED [2] */ + 0, 0, 0, 0, } }, { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, @@ -5185,6 +5094,28 @@ static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = { .pin_to_pocctrl = r8a7794_pin_to_pocctrl, }; +#ifdef CONFIG_PINCTRL_PFC_R8A7745 +const struct sh_pfc_soc_info r8a7745_pinmux_info = { + .name = "r8a77450_pfc", + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups, + .nr_groups = ARRAY_SIZE(pinmux_groups), + .functions = pinmux_functions, + .nr_functions = ARRAY_SIZE(pinmux_functions), + + .cfg_regs = pinmux_config_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; +#endif + +#ifdef CONFIG_PINCTRL_PFC_R8A7794 const struct sh_pfc_soc_info r8a7794_pinmux_info = { .name = "r8a77940_pfc", .ops = &r8a7794_pinmux_ops, @@ -5204,3 +5135,4 @@ const struct sh_pfc_soc_info r8a7794_pinmux_info = { .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; +#endif diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c index 081efda9a280..95fd0994893a 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795-es1.c @@ -192,8 +192,8 @@ #define GPSR6_9 F_(SSI_WS4, IP14_27_24) #define GPSR6_8 F_(SSI_SCK4, IP14_23_20) #define GPSR6_7 F_(SSI_SDATA3, IP14_19_16) -#define GPSR6_6 F_(SSI_WS34, IP14_15_12) -#define GPSR6_5 F_(SSI_SCK34, IP14_11_8) +#define GPSR6_6 F_(SSI_WS349, IP14_15_12) +#define GPSR6_5 F_(SSI_SCK349, IP14_11_8) #define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4) #define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0) #define GPSR6_2 F_(SSI_SDATA0, IP13_31_28) @@ -328,8 +328,8 @@ #define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP14_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP14_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -1256,11 +1256,11 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0), PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1), - PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK34), + PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK349), PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), - PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS34), + PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS349), PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), @@ -3650,12 +3650,12 @@ static const unsigned int ssi3_data_pins[] = { static const unsigned int ssi3_data_mux[] = { SSI_SDATA3_MARK, }; -static const unsigned int ssi34_ctrl_pins[] = { +static const unsigned int ssi349_ctrl_pins[] = { /* SCK, WS */ RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), }; -static const unsigned int ssi34_ctrl_mux[] = { - SSI_SCK34_MARK, SSI_WS34_MARK, +static const unsigned int ssi349_ctrl_mux[] = { + SSI_SCK349_MARK, SSI_WS349_MARK, }; static const unsigned int ssi4_data_pins[] = { /* SDATA */ @@ -4063,7 +4063,7 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(ssi2_ctrl_a), SH_PFC_PIN_GROUP(ssi2_ctrl_b), SH_PFC_PIN_GROUP(ssi3_data), - SH_PFC_PIN_GROUP(ssi34_ctrl), + SH_PFC_PIN_GROUP(ssi349_ctrl), SH_PFC_PIN_GROUP(ssi4_data), SH_PFC_PIN_GROUP(ssi4_ctrl), SH_PFC_PIN_GROUP(ssi5_data), @@ -4509,7 +4509,7 @@ static const char * const ssi_groups[] = { "ssi2_ctrl_a", "ssi2_ctrl_b", "ssi3_data", - "ssi34_ctrl", + "ssi349_ctrl", "ssi4_data", "ssi4_ctrl", "ssi5_data", @@ -5356,8 +5356,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ - { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */ - { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */ + { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ + { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ } }, @@ -5604,8 +5604,8 @@ static const struct sh_pfc_bias_info bias_info[] = { { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ - { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */ - { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */ + { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */ + { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */ { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c index 0454f31c0831..1656295af2b0 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c @@ -193,8 +193,8 @@ #define GPSR6_9 F_(SSI_WS4, IP15_27_24) #define GPSR6_8 F_(SSI_SCK4, IP15_23_20) #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) -#define GPSR6_6 F_(SSI_WS34, IP15_15_12) -#define GPSR6_5 F_(SSI_SCK34, IP15_11_8) +#define GPSR6_6 F_(SSI_WS349, IP15_15_12) +#define GPSR6_5 F_(SSI_SCK349, IP15_11_8) #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) @@ -339,8 +339,8 @@ #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP15_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP15_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -1315,11 +1315,11 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0), PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1), - PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK34), + PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), - PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS34), + PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349), PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), @@ -1576,6 +1576,273 @@ static const struct sh_pfc_pin pinmux_pins[] = { SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), }; +/* - EtherAVB --------------------------------------------------------------- */ +static const unsigned int avb_link_pins[] = { + /* AVB_LINK */ + RCAR_GP_PIN(2, 12), +}; +static const unsigned int avb_link_mux[] = { + AVB_LINK_MARK, +}; +static const unsigned int avb_magic_pins[] = { + /* AVB_MAGIC_ */ + RCAR_GP_PIN(2, 10), +}; +static const unsigned int avb_magic_mux[] = { + AVB_MAGIC_MARK, +}; +static const unsigned int avb_phy_int_pins[] = { + /* AVB_PHY_INT */ + RCAR_GP_PIN(2, 11), +}; +static const unsigned int avb_phy_int_mux[] = { + AVB_PHY_INT_MARK, +}; +static const unsigned int avb_mdc_pins[] = { + /* AVB_MDC, AVB_MDIO */ + RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), +}; +static const unsigned int avb_mdc_mux[] = { + AVB_MDC_MARK, AVB_MDIO_MARK, +}; +static const unsigned int avb_mii_pins[] = { + /* + * AVB_TX_CTL, AVB_TXC, AVB_TD0, + * AVB_TD1, AVB_TD2, AVB_TD3, + * AVB_RX_CTL, AVB_RXC, AVB_RD0, + * AVB_RD1, AVB_RD2, AVB_RD3, + * AVB_TXCREFCLK + */ + PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18), + PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17), + PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13), + PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14), + PIN_NUMBER('A', 12), + +}; +static const unsigned int avb_mii_mux[] = { + AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, + AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, + AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, + AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, + AVB_TXCREFCLK_MARK, +}; +static const unsigned int avb_avtp_pps_pins[] = { + /* AVB_AVTP_PPS */ + RCAR_GP_PIN(2, 6), +}; +static const unsigned int avb_avtp_pps_mux[] = { + AVB_AVTP_PPS_MARK, +}; +static const unsigned int avb_avtp_match_a_pins[] = { + /* AVB_AVTP_MATCH_A */ + RCAR_GP_PIN(2, 13), +}; +static const unsigned int avb_avtp_match_a_mux[] = { + AVB_AVTP_MATCH_A_MARK, +}; +static const unsigned int avb_avtp_capture_a_pins[] = { + /* AVB_AVTP_CAPTURE_A */ + RCAR_GP_PIN(2, 14), +}; +static const unsigned int avb_avtp_capture_a_mux[] = { + AVB_AVTP_CAPTURE_A_MARK, +}; +static const unsigned int avb_avtp_match_b_pins[] = { + /* AVB_AVTP_MATCH_B */ + RCAR_GP_PIN(1, 8), +}; +static const unsigned int avb_avtp_match_b_mux[] = { + AVB_AVTP_MATCH_B_MARK, +}; +static const unsigned int avb_avtp_capture_b_pins[] = { + /* AVB_AVTP_CAPTURE_B */ + RCAR_GP_PIN(1, 11), +}; +static const unsigned int avb_avtp_capture_b_mux[] = { + AVB_AVTP_CAPTURE_B_MARK, +}; + +/* - DU --------------------------------------------------------------------- */ +static const unsigned int du_rgb666_pins[] = { + /* R[7:2], G[7:2], B[7:2] */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), +}; +static const unsigned int du_rgb666_mux[] = { + DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, + DU_DR3_MARK, DU_DR2_MARK, + DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, + DU_DG3_MARK, DU_DG2_MARK, + DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, + DU_DB3_MARK, DU_DB2_MARK, +}; +static const unsigned int du_rgb888_pins[] = { + /* R[7:0], G[7:0], B[7:0] */ + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), +}; +static const unsigned int du_rgb888_mux[] = { + DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, + DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, + DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, + DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, + DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, + DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, +}; +static const unsigned int du_clk_out_0_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(1, 27), +}; +static const unsigned int du_clk_out_0_mux[] = { + DU_DOTCLKOUT0_MARK +}; +static const unsigned int du_clk_out_1_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int du_clk_out_1_mux[] = { + DU_DOTCLKOUT1_MARK +}; +static const unsigned int du_sync_pins[] = { + /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), +}; +static const unsigned int du_sync_mux[] = { + DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK +}; +static const unsigned int du_oddf_pins[] = { + /* EXDISP/EXODDF/EXCDE */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int du_oddf_mux[] = { + DU_EXODDF_DU_ODDF_DISP_CDE_MARK, +}; +static const unsigned int du_cde_pins[] = { + /* CDE */ + RCAR_GP_PIN(2, 0), +}; +static const unsigned int du_cde_mux[] = { + DU_CDE_MARK, +}; +static const unsigned int du_disp_pins[] = { + /* DISP */ + RCAR_GP_PIN(2, 1), +}; +static const unsigned int du_disp_mux[] = { + DU_DISP_MARK, +}; + +/* - PWM0 --------------------------------------------------------------------*/ +static const unsigned int pwm0_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 6), +}; +static const unsigned int pwm0_mux[] = { + PWM0_MARK, +}; +/* - PWM1 --------------------------------------------------------------------*/ +static const unsigned int pwm1_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 7), +}; +static const unsigned int pwm1_a_mux[] = { + PWM1_A_MARK, +}; +static const unsigned int pwm1_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 8), +}; +static const unsigned int pwm1_b_mux[] = { + PWM1_B_MARK, +}; +/* - PWM2 --------------------------------------------------------------------*/ +static const unsigned int pwm2_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 8), +}; +static const unsigned int pwm2_a_mux[] = { + PWM2_A_MARK, +}; +static const unsigned int pwm2_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 11), +}; +static const unsigned int pwm2_b_mux[] = { + PWM2_B_MARK, +}; +/* - PWM3 --------------------------------------------------------------------*/ +static const unsigned int pwm3_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int pwm3_a_mux[] = { + PWM3_A_MARK, +}; +static const unsigned int pwm3_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int pwm3_b_mux[] = { + PWM3_B_MARK, +}; +/* - PWM4 --------------------------------------------------------------------*/ +static const unsigned int pwm4_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 1), +}; +static const unsigned int pwm4_a_mux[] = { + PWM4_A_MARK, +}; +static const unsigned int pwm4_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int pwm4_b_mux[] = { + PWM4_B_MARK, +}; +/* - PWM5 --------------------------------------------------------------------*/ +static const unsigned int pwm5_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 2), +}; +static const unsigned int pwm5_a_mux[] = { + PWM5_A_MARK, +}; +static const unsigned int pwm5_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 4), +}; +static const unsigned int pwm5_b_mux[] = { + PWM5_B_MARK, +}; +/* - PWM6 --------------------------------------------------------------------*/ +static const unsigned int pwm6_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 3), +}; +static const unsigned int pwm6_a_mux[] = { + PWM6_A_MARK, +}; +static const unsigned int pwm6_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int pwm6_b_mux[] = { + PWM6_B_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -1790,6 +2057,37 @@ static const unsigned int scif_clk_b_mux[] = { }; static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP(avb_mdc), + SH_PFC_PIN_GROUP(avb_mii), + SH_PFC_PIN_GROUP(avb_avtp_pps), + SH_PFC_PIN_GROUP(avb_avtp_match_a), + SH_PFC_PIN_GROUP(avb_avtp_capture_a), + SH_PFC_PIN_GROUP(avb_avtp_match_b), + SH_PFC_PIN_GROUP(avb_avtp_capture_b), + SH_PFC_PIN_GROUP(du_rgb666), + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out_0), + SH_PFC_PIN_GROUP(du_clk_out_1), + SH_PFC_PIN_GROUP(du_sync), + SH_PFC_PIN_GROUP(du_oddf), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du_disp), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm1_a), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2_a), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm3_a), + SH_PFC_PIN_GROUP(pwm3_b), + SH_PFC_PIN_GROUP(pwm4_a), + SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(pwm5_a), + SH_PFC_PIN_GROUP(pwm5_b), + SH_PFC_PIN_GROUP(pwm6_a), + SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -1821,6 +2119,64 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(scif_clk_b), }; +static const char * const avb_groups[] = { + "avb_link", + "avb_magic", + "avb_phy_int", + "avb_mdc", + "avb_mii", + "avb_avtp_pps", + "avb_avtp_match_a", + "avb_avtp_capture_a", + "avb_avtp_match_b", + "avb_avtp_capture_b", +}; + +static const char * const du_groups[] = { + "du_rgb666", + "du_rgb888", + "du_clk_out_0", + "du_clk_out_1", + "du_sync", + "du_oddf", + "du_cde", + "du_disp", +}; + +static const char * const pwm0_groups[] = { + "pwm0", +}; + +static const char * const pwm1_groups[] = { + "pwm1_a", + "pwm1_b", +}; + +static const char * const pwm2_groups[] = { + "pwm2_a", + "pwm2_b", +}; + +static const char * const pwm3_groups[] = { + "pwm3_a", + "pwm3_b", +}; + +static const char * const pwm4_groups[] = { + "pwm4_a", + "pwm4_b", +}; + +static const char * const pwm5_groups[] = { + "pwm5_a", + "pwm5_b", +}; + +static const char * const pwm6_groups[] = { + "pwm6_a", + "pwm6_b", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -1872,6 +2228,15 @@ static const char * const scif_clk_groups[] = { }; static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), @@ -2653,8 +3018,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ - { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */ - { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */ + { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ + { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ } }, @@ -2900,8 +3265,8 @@ static const struct sh_pfc_bias_info bias_info[] = { { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ - { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */ - { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */ + { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */ + { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */ { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c index b0362ae707e2..98bf5d0e078e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c @@ -199,13 +199,13 @@ #define GPSR6_9 F_(SSI_WS4, IP15_27_24) #define GPSR6_8 F_(SSI_SCK4, IP15_23_20) #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16) -#define GPSR6_6 F_(SSI_WS34, IP15_15_12) -#define GPSR6_5 F_(SSI_SCK34, IP15_11_8) +#define GPSR6_6 F_(SSI_WS349, IP15_15_12) +#define GPSR6_5 F_(SSI_SCK349, IP15_11_8) #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4) #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) -#define GPSR6_1 F_(SSI_WS0129, IP14_27_24) -#define GPSR6_0 F_(SSI_SCK0129, IP14_23_20) +#define GPSR6_1 F_(SSI_WS01239, IP14_27_24) +#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) /* GPSR7 */ #define GPSR7_3 FM(GP7_03) @@ -338,15 +338,15 @@ #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP14_23_20 FM(SSI_SCK0129) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP14_27_24 FM(SSI_WS0129) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */ #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP15_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP15_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) @@ -1304,10 +1304,10 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1), PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5), - PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK0129), + PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239), PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5), - PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS0129), + PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239), PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5), PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0), @@ -1319,11 +1319,11 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0), PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1), - PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK34), + PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349), PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0), PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0), - PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS34), + PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349), PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0), PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0), PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0), @@ -1582,6 +1582,128 @@ static const struct sh_pfc_pin pinmux_pins[] = { SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS), }; +/* - AUDIO CLOCK ------------------------------------------------------------ */ +static const unsigned int audio_clk_a_a_pins[] = { + /* CLK A */ + RCAR_GP_PIN(6, 22), +}; +static const unsigned int audio_clk_a_a_mux[] = { + AUDIO_CLKA_A_MARK, +}; +static const unsigned int audio_clk_a_b_pins[] = { + /* CLK A */ + RCAR_GP_PIN(5, 4), +}; +static const unsigned int audio_clk_a_b_mux[] = { + AUDIO_CLKA_B_MARK, +}; +static const unsigned int audio_clk_a_c_pins[] = { + /* CLK A */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int audio_clk_a_c_mux[] = { + AUDIO_CLKA_C_MARK, +}; +static const unsigned int audio_clk_b_a_pins[] = { + /* CLK B */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int audio_clk_b_a_mux[] = { + AUDIO_CLKB_A_MARK, +}; +static const unsigned int audio_clk_b_b_pins[] = { + /* CLK B */ + RCAR_GP_PIN(6, 23), +}; +static const unsigned int audio_clk_b_b_mux[] = { + AUDIO_CLKB_B_MARK, +}; +static const unsigned int audio_clk_c_a_pins[] = { + /* CLK C */ + RCAR_GP_PIN(5, 21), +}; +static const unsigned int audio_clk_c_a_mux[] = { + AUDIO_CLKC_A_MARK, +}; +static const unsigned int audio_clk_c_b_pins[] = { + /* CLK C */ + RCAR_GP_PIN(5, 0), +}; +static const unsigned int audio_clk_c_b_mux[] = { + AUDIO_CLKC_B_MARK, +}; +static const unsigned int audio_clkout_a_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(5, 18), +}; +static const unsigned int audio_clkout_a_mux[] = { + AUDIO_CLKOUT_A_MARK, +}; +static const unsigned int audio_clkout_b_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(6, 28), +}; +static const unsigned int audio_clkout_b_mux[] = { + AUDIO_CLKOUT_B_MARK, +}; +static const unsigned int audio_clkout_c_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(5, 3), +}; +static const unsigned int audio_clkout_c_mux[] = { + AUDIO_CLKOUT_C_MARK, +}; +static const unsigned int audio_clkout_d_pins[] = { + /* CLKOUT */ + RCAR_GP_PIN(5, 21), +}; +static const unsigned int audio_clkout_d_mux[] = { + AUDIO_CLKOUT_D_MARK, +}; +static const unsigned int audio_clkout1_a_pins[] = { + /* CLKOUT1 */ + RCAR_GP_PIN(5, 15), +}; +static const unsigned int audio_clkout1_a_mux[] = { + AUDIO_CLKOUT1_A_MARK, +}; +static const unsigned int audio_clkout1_b_pins[] = { + /* CLKOUT1 */ + RCAR_GP_PIN(6, 29), +}; +static const unsigned int audio_clkout1_b_mux[] = { + AUDIO_CLKOUT1_B_MARK, +}; +static const unsigned int audio_clkout2_a_pins[] = { + /* CLKOUT2 */ + RCAR_GP_PIN(5, 16), +}; +static const unsigned int audio_clkout2_a_mux[] = { + AUDIO_CLKOUT2_A_MARK, +}; +static const unsigned int audio_clkout2_b_pins[] = { + /* CLKOUT2 */ + RCAR_GP_PIN(6, 30), +}; +static const unsigned int audio_clkout2_b_mux[] = { + AUDIO_CLKOUT2_B_MARK, +}; + +static const unsigned int audio_clkout3_a_pins[] = { + /* CLKOUT3 */ + RCAR_GP_PIN(5, 19), +}; +static const unsigned int audio_clkout3_a_mux[] = { + AUDIO_CLKOUT3_A_MARK, +}; +static const unsigned int audio_clkout3_b_pins[] = { + /* CLKOUT3 */ + RCAR_GP_PIN(6, 31), +}; +static const unsigned int audio_clkout3_b_mux[] = { + AUDIO_CLKOUT3_B_MARK, +}; + /* - EtherAVB --------------------------------------------------------------- */ static const unsigned int avb_link_pins[] = { /* AVB_LINK */ @@ -1605,11 +1727,33 @@ static const unsigned int avb_phy_int_mux[] = { AVB_PHY_INT_MARK, }; static const unsigned int avb_mdc_pins[] = { - /* AVB_MDC */ - RCAR_GP_PIN(2, 9), + /* AVB_MDC, AVB_MDIO */ + RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9), }; static const unsigned int avb_mdc_mux[] = { - AVB_MDC_MARK, + AVB_MDC_MARK, AVB_MDIO_MARK, +}; +static const unsigned int avb_mii_pins[] = { + /* + * AVB_TX_CTL, AVB_TXC, AVB_TD0, + * AVB_TD1, AVB_TD2, AVB_TD3, + * AVB_RX_CTL, AVB_RXC, AVB_RD0, + * AVB_RD1, AVB_RD2, AVB_RD3, + * AVB_TXCREFCLK + */ + PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18), + PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17), + PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13), + PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14), + PIN_NUMBER('A', 12), + +}; +static const unsigned int avb_mii_mux[] = { + AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK, + AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK, + AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK, + AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK, + AVB_TXCREFCLK_MARK, }; static const unsigned int avb_avtp_pps_pins[] = { /* AVB_AVTP_PPS */ @@ -2955,6 +3099,105 @@ static const unsigned int msiof3_rxd_e_mux[] = { MSIOF3_RXD_E_MARK, }; +/* - PWM0 --------------------------------------------------------------------*/ +static const unsigned int pwm0_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 6), +}; +static const unsigned int pwm0_mux[] = { + PWM0_MARK, +}; +/* - PWM1 --------------------------------------------------------------------*/ +static const unsigned int pwm1_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 7), +}; +static const unsigned int pwm1_a_mux[] = { + PWM1_A_MARK, +}; +static const unsigned int pwm1_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 8), +}; +static const unsigned int pwm1_b_mux[] = { + PWM1_B_MARK, +}; +/* - PWM2 --------------------------------------------------------------------*/ +static const unsigned int pwm2_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 8), +}; +static const unsigned int pwm2_a_mux[] = { + PWM2_A_MARK, +}; +static const unsigned int pwm2_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 11), +}; +static const unsigned int pwm2_b_mux[] = { + PWM2_B_MARK, +}; +/* - PWM3 --------------------------------------------------------------------*/ +static const unsigned int pwm3_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 0), +}; +static const unsigned int pwm3_a_mux[] = { + PWM3_A_MARK, +}; +static const unsigned int pwm3_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 2), +}; +static const unsigned int pwm3_b_mux[] = { + PWM3_B_MARK, +}; +/* - PWM4 --------------------------------------------------------------------*/ +static const unsigned int pwm4_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 1), +}; +static const unsigned int pwm4_a_mux[] = { + PWM4_A_MARK, +}; +static const unsigned int pwm4_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 3), +}; +static const unsigned int pwm4_b_mux[] = { + PWM4_B_MARK, +}; +/* - PWM5 --------------------------------------------------------------------*/ +static const unsigned int pwm5_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 2), +}; +static const unsigned int pwm5_a_mux[] = { + PWM5_A_MARK, +}; +static const unsigned int pwm5_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 4), +}; +static const unsigned int pwm5_b_mux[] = { + PWM5_B_MARK, +}; +/* - PWM6 --------------------------------------------------------------------*/ +static const unsigned int pwm6_a_pins[] = { + /* PWM */ + RCAR_GP_PIN(1, 3), +}; +static const unsigned int pwm6_a_mux[] = { + PWM6_A_MARK, +}; +static const unsigned int pwm6_b_pins[] = { + /* PWM */ + RCAR_GP_PIN(2, 5), +}; +static const unsigned int pwm6_b_mux[] = { + PWM6_B_MARK, +}; + /* - SCIF0 ------------------------------------------------------------------ */ static const unsigned int scif0_data_pins[] = { /* RX, TX */ @@ -3376,11 +3619,206 @@ static const unsigned int sdhi3_ds_mux[] = { SD3_DS_MARK, }; +/* - SSI -------------------------------------------------------------------- */ +static const unsigned int ssi0_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 2), +}; +static const unsigned int ssi0_data_mux[] = { + SSI_SDATA0_MARK, +}; +static const unsigned int ssi01239_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), +}; +static const unsigned int ssi01239_ctrl_mux[] = { + SSI_SCK01239_MARK, SSI_WS01239_MARK, +}; +static const unsigned int ssi1_data_a_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 3), +}; +static const unsigned int ssi1_data_a_mux[] = { + SSI_SDATA1_A_MARK, +}; +static const unsigned int ssi1_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 12), +}; +static const unsigned int ssi1_data_b_mux[] = { + SSI_SDATA1_B_MARK, +}; +static const unsigned int ssi1_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), +}; +static const unsigned int ssi1_ctrl_a_mux[] = { + SSI_SCK1_A_MARK, SSI_WS1_A_MARK, +}; +static const unsigned int ssi1_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21), +}; +static const unsigned int ssi1_ctrl_b_mux[] = { + SSI_SCK1_B_MARK, SSI_WS1_B_MARK, +}; +static const unsigned int ssi2_data_a_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 4), +}; +static const unsigned int ssi2_data_a_mux[] = { + SSI_SDATA2_A_MARK, +}; +static const unsigned int ssi2_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 13), +}; +static const unsigned int ssi2_data_b_mux[] = { + SSI_SDATA2_B_MARK, +}; +static const unsigned int ssi2_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21), +}; +static const unsigned int ssi2_ctrl_a_mux[] = { + SSI_SCK2_A_MARK, SSI_WS2_A_MARK, +}; +static const unsigned int ssi2_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29), +}; +static const unsigned int ssi2_ctrl_b_mux[] = { + SSI_SCK2_B_MARK, SSI_WS2_B_MARK, +}; +static const unsigned int ssi3_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 7), +}; +static const unsigned int ssi3_data_mux[] = { + SSI_SDATA3_MARK, +}; +static const unsigned int ssi349_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6), +}; +static const unsigned int ssi349_ctrl_mux[] = { + SSI_SCK349_MARK, SSI_WS349_MARK, +}; +static const unsigned int ssi4_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 10), +}; +static const unsigned int ssi4_data_mux[] = { + SSI_SDATA4_MARK, +}; +static const unsigned int ssi4_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), +}; +static const unsigned int ssi4_ctrl_mux[] = { + SSI_SCK4_MARK, SSI_WS4_MARK, +}; +static const unsigned int ssi5_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 13), +}; +static const unsigned int ssi5_data_mux[] = { + SSI_SDATA5_MARK, +}; +static const unsigned int ssi5_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12), +}; +static const unsigned int ssi5_ctrl_mux[] = { + SSI_SCK5_MARK, SSI_WS5_MARK, +}; +static const unsigned int ssi6_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 16), +}; +static const unsigned int ssi6_data_mux[] = { + SSI_SDATA6_MARK, +}; +static const unsigned int ssi6_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), +}; +static const unsigned int ssi6_ctrl_mux[] = { + SSI_SCK6_MARK, SSI_WS6_MARK, +}; +static const unsigned int ssi7_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 19), +}; +static const unsigned int ssi7_data_mux[] = { + SSI_SDATA7_MARK, +}; +static const unsigned int ssi78_ctrl_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), +}; +static const unsigned int ssi78_ctrl_mux[] = { + SSI_SCK78_MARK, SSI_WS78_MARK, +}; +static const unsigned int ssi8_data_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 20), +}; +static const unsigned int ssi8_data_mux[] = { + SSI_SDATA8_MARK, +}; +static const unsigned int ssi9_data_a_pins[] = { + /* SDATA */ + RCAR_GP_PIN(6, 21), +}; +static const unsigned int ssi9_data_a_mux[] = { + SSI_SDATA9_A_MARK, +}; +static const unsigned int ssi9_data_b_pins[] = { + /* SDATA */ + RCAR_GP_PIN(5, 14), +}; +static const unsigned int ssi9_data_b_mux[] = { + SSI_SDATA9_B_MARK, +}; +static const unsigned int ssi9_ctrl_a_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16), +}; +static const unsigned int ssi9_ctrl_a_mux[] = { + SSI_SCK9_A_MARK, SSI_WS9_A_MARK, +}; +static const unsigned int ssi9_ctrl_b_pins[] = { + /* SCK, WS */ + RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31), +}; +static const unsigned int ssi9_ctrl_b_mux[] = { + SSI_SCK9_B_MARK, SSI_WS9_B_MARK, +}; + static const struct sh_pfc_pin_group pinmux_groups[] = { + SH_PFC_PIN_GROUP(audio_clk_a_a), + SH_PFC_PIN_GROUP(audio_clk_a_b), + SH_PFC_PIN_GROUP(audio_clk_a_c), + SH_PFC_PIN_GROUP(audio_clk_b_a), + SH_PFC_PIN_GROUP(audio_clk_b_b), + SH_PFC_PIN_GROUP(audio_clk_c_a), + SH_PFC_PIN_GROUP(audio_clk_c_b), + SH_PFC_PIN_GROUP(audio_clkout_a), + SH_PFC_PIN_GROUP(audio_clkout_b), + SH_PFC_PIN_GROUP(audio_clkout_c), + SH_PFC_PIN_GROUP(audio_clkout_d), + SH_PFC_PIN_GROUP(audio_clkout1_a), + SH_PFC_PIN_GROUP(audio_clkout1_b), + SH_PFC_PIN_GROUP(audio_clkout2_a), + SH_PFC_PIN_GROUP(audio_clkout2_b), + SH_PFC_PIN_GROUP(audio_clkout3_a), + SH_PFC_PIN_GROUP(audio_clkout3_b), SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), SH_PFC_PIN_GROUP(avb_mdc), + SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_avtp_pps), SH_PFC_PIN_GROUP(avb_avtp_match_a), SH_PFC_PIN_GROUP(avb_avtp_capture_a), @@ -3565,6 +4003,19 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(msiof3_ss2_e), SH_PFC_PIN_GROUP(msiof3_txd_e), SH_PFC_PIN_GROUP(msiof3_rxd_e), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm1_a), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2_a), + SH_PFC_PIN_GROUP(pwm2_b), + SH_PFC_PIN_GROUP(pwm3_a), + SH_PFC_PIN_GROUP(pwm3_b), + SH_PFC_PIN_GROUP(pwm4_a), + SH_PFC_PIN_GROUP(pwm4_b), + SH_PFC_PIN_GROUP(pwm5_a), + SH_PFC_PIN_GROUP(pwm5_b), + SH_PFC_PIN_GROUP(pwm6_a), + SH_PFC_PIN_GROUP(pwm6_b), SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_ctrl), @@ -3620,6 +4071,51 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { SH_PFC_PIN_GROUP(sdhi3_cd), SH_PFC_PIN_GROUP(sdhi3_wp), SH_PFC_PIN_GROUP(sdhi3_ds), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi01239_ctrl), + SH_PFC_PIN_GROUP(ssi1_data_a), + SH_PFC_PIN_GROUP(ssi1_data_b), + SH_PFC_PIN_GROUP(ssi1_ctrl_a), + SH_PFC_PIN_GROUP(ssi1_ctrl_b), + SH_PFC_PIN_GROUP(ssi2_data_a), + SH_PFC_PIN_GROUP(ssi2_data_b), + SH_PFC_PIN_GROUP(ssi2_ctrl_a), + SH_PFC_PIN_GROUP(ssi2_ctrl_b), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi349_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5_data), + SH_PFC_PIN_GROUP(ssi5_ctrl), + SH_PFC_PIN_GROUP(ssi6_data), + SH_PFC_PIN_GROUP(ssi6_ctrl), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi9_data_a), + SH_PFC_PIN_GROUP(ssi9_data_b), + SH_PFC_PIN_GROUP(ssi9_ctrl_a), + SH_PFC_PIN_GROUP(ssi9_ctrl_b), +}; + +static const char * const audio_clk_groups[] = { + "audio_clk_a_a", + "audio_clk_a_b", + "audio_clk_a_c", + "audio_clk_b_a", + "audio_clk_b_b", + "audio_clk_c_a", + "audio_clk_c_b", + "audio_clkout_a", + "audio_clkout_b", + "audio_clkout_c", + "audio_clkout_d", + "audio_clkout1_a", + "audio_clkout1_b", + "audio_clkout2_a", + "audio_clkout2_b", + "audio_clkout3_a", + "audio_clkout3_b", }; static const char * const avb_groups[] = { @@ -3627,6 +4123,7 @@ static const char * const avb_groups[] = { "avb_magic", "avb_phy_int", "avb_mdc", + "avb_mii", "avb_avtp_pps", "avb_avtp_match_a", "avb_avtp_capture_a", @@ -3879,6 +4376,40 @@ static const char * const msiof3_groups[] = { "msiof3_rxd_e", }; +static const char * const pwm0_groups[] = { + "pwm0", +}; + +static const char * const pwm1_groups[] = { + "pwm1_a", + "pwm1_b", +}; + +static const char * const pwm2_groups[] = { + "pwm2_a", + "pwm2_b", +}; + +static const char * const pwm3_groups[] = { + "pwm3_a", + "pwm3_b", +}; + +static const char * const pwm4_groups[] = { + "pwm4_a", + "pwm4_b", +}; + +static const char * const pwm5_groups[] = { + "pwm5_a", + "pwm5_b", +}; + +static const char * const pwm6_groups[] = { + "pwm6_a", + "pwm6_b", +}; + static const char * const scif0_groups[] = { "scif0_data", "scif0_clk", @@ -3967,7 +4498,36 @@ static const char * const sdhi3_groups[] = { "sdhi3_ds", }; +static const char * const ssi_groups[] = { + "ssi0_data", + "ssi01239_ctrl", + "ssi1_data_a", + "ssi1_data_b", + "ssi1_ctrl_a", + "ssi1_ctrl_b", + "ssi2_data_a", + "ssi2_data_b", + "ssi2_ctrl_a", + "ssi2_ctrl_b", + "ssi3_data", + "ssi349_ctrl", + "ssi4_data", + "ssi4_ctrl", + "ssi5_data", + "ssi5_ctrl", + "ssi6_data", + "ssi6_ctrl", + "ssi7_data", + "ssi78_ctrl", + "ssi8_data", + "ssi9_data_a", + "ssi9_data_b", + "ssi9_ctrl_a", + "ssi9_ctrl_b", +}; + static const struct sh_pfc_function pinmux_functions[] = { + SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(can0), SH_PFC_FUNCTION(can1), @@ -3991,6 +4551,13 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(msiof1), SH_PFC_FUNCTION(msiof2), SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), SH_PFC_FUNCTION(scif0), SH_PFC_FUNCTION(scif1), SH_PFC_FUNCTION(scif2), @@ -4002,6 +4569,7 @@ static const struct sh_pfc_function pinmux_functions[] = { SH_PFC_FUNCTION(sdhi1), SH_PFC_FUNCTION(sdhi2), SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(ssi), }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -4775,8 +5343,8 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = { { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ - { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */ - { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */ + { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ + { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ } }, @@ -5022,8 +5590,8 @@ static const struct sh_pfc_bias_info bias_info[] = { { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */ { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */ { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */ - { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */ - { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */ + { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */ + { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */ { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */ { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */ { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */ diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index f31eb6c1e87d..4376397123de 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -259,6 +259,8 @@ struct sh_pfc_soc_info { extern const struct sh_pfc_soc_info emev2_pinmux_info; extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; extern const struct sh_pfc_soc_info r8a7740_pinmux_info; +extern const struct sh_pfc_soc_info r8a7743_pinmux_info; +extern const struct sh_pfc_soc_info r8a7745_pinmux_info; extern const struct sh_pfc_soc_info r8a7778_pinmux_info; extern const struct sh_pfc_soc_info r8a7779_pinmux_info; extern const struct sh_pfc_soc_info r8a7790_pinmux_info; diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index 222b6685b09f..06431ff49ffb 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -209,6 +209,24 @@ static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) return irq_create_fwspec_mapping(&fwspec); } +static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) +{ + struct stm32_gpio_bank *bank = gpiochip_get_data(chip); + int pin = stm32_gpio_pin(offset); + int ret; + u32 mode, alt; + + stm32_pmx_get_mode(bank, pin, &mode, &alt); + if ((alt == 0) && (mode == 0)) + ret = 1; + else if ((alt == 0) && (mode == 1)) + ret = 0; + else + ret = -EINVAL; + + return ret; +} + static const struct gpio_chip stm32_gpio_template = { .request = stm32_gpio_request, .free = stm32_gpio_free, @@ -217,14 +235,44 @@ static const struct gpio_chip stm32_gpio_template = { .direction_input = stm32_gpio_direction_input, .direction_output = stm32_gpio_direction_output, .to_irq = stm32_gpio_to_irq, + .get_direction = stm32_gpio_get_direction, }; +static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) +{ + struct stm32_gpio_bank *bank = irq_data->domain->host_data; + struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); + int ret; + + ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); + if (ret) + return ret; + + ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); + if (ret) { + dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", + irq_data->hwirq); + return ret; + } + + return 0; +} + +static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) +{ + struct stm32_gpio_bank *bank = irq_data->domain->host_data; + + gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); +} + static struct irq_chip stm32_gpio_irq_chip = { .name = "stm32gpio", .irq_eoi = irq_chip_eoi_parent, .irq_mask = irq_chip_mask_parent, .irq_unmask = irq_chip_unmask_parent, .irq_set_type = irq_chip_set_type_parent, + .irq_request_resources = stm32_gpio_irq_request_resources, + .irq_release_resources = stm32_gpio_irq_release_resources, }; static int stm32_gpio_domain_translate(struct irq_domain *d, @@ -248,15 +296,6 @@ static void stm32_gpio_domain_activate(struct irq_domain *d, struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_nr); - gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); -} - -static void stm32_gpio_domain_deactivate(struct irq_domain *d, - struct irq_data *irq_data) -{ - struct stm32_gpio_bank *bank = d->host_data; - - gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); } static int stm32_gpio_domain_alloc(struct irq_domain *d, @@ -285,7 +324,6 @@ static const struct irq_domain_ops stm32_gpio_domain_ops = { .alloc = stm32_gpio_domain_alloc, .free = irq_domain_free_irqs_common, .activate = stm32_gpio_domain_activate, - .deactivate = stm32_gpio_domain_deactivate, }; /* Pinctrl functions */ @@ -411,11 +449,6 @@ static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, pin = STM32_GET_PIN_NO(pinfunc); func = STM32_GET_PIN_FUNC(pinfunc); - if (pin >= pctl->match_data->npins) { - dev_err(pctl->dev, "invalid pin number.\n"); - return -EINVAL; - } - if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { dev_err(pctl->dev, "invalid function.\n"); return -EINVAL; @@ -558,8 +591,8 @@ static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, clk_disable(bank->clk); } -static void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, - int pin, u32 *mode, u32 *alt) +void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, + u32 *alt) { u32 val; int alt_shift = (pin % 8) * 4; diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.h b/drivers/pinctrl/stm32/pinctrl-stm32.h index 35ebc94c01e4..8702a9992ce5 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.h +++ b/drivers/pinctrl/stm32/pinctrl-stm32.h @@ -45,7 +45,10 @@ struct stm32_pinctrl_match_data { const unsigned int npins; }; -int stm32_pctl_probe(struct platform_device *pdev); +struct stm32_gpio_bank; +int stm32_pctl_probe(struct platform_device *pdev); +void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, + int pin, u32 *mode, u32 *alt); #endif /* __PINCTRL_STM32_H */ diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 793e6f94fa0b..31f85ca92669 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -7,7 +7,7 @@ config PINCTRL_SUNXI select GPIOLIB config PINCTRL_SUN4I_A10 - def_bool MACH_SUN4I + def_bool MACH_SUN4I || MACH_SUN7I select PINCTRL_SUNXI config PINCTRL_SUN5I @@ -23,10 +23,6 @@ config PINCTRL_SUN6I_A31_R depends on RESET_CONTROLLER select PINCTRL_SUNXI -config PINCTRL_SUN7I_A20 - def_bool MACH_SUN7I - select PINCTRL_SUNXI - config PINCTRL_SUN8I_A23 def_bool MACH_SUN8I select PINCTRL_SUNXI @@ -39,6 +35,10 @@ config PINCTRL_SUN8I_A83T def_bool MACH_SUN8I select PINCTRL_SUNXI +config PINCTRL_SUN8I_A83T_R + def_bool MACH_SUN8I + select PINCTRL_SUNXI + config PINCTRL_SUN8I_A23_R def_bool MACH_SUN8I depends on RESET_CONTROLLER diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index df4ccd6cd44c..dc6c9619e41c 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -6,13 +6,13 @@ obj-$(CONFIG_PINCTRL_SUN4I_A10) += pinctrl-sun4i-a10.o obj-$(CONFIG_PINCTRL_SUN5I) += pinctrl-sun5i.o obj-$(CONFIG_PINCTRL_SUN6I_A31) += pinctrl-sun6i-a31.o obj-$(CONFIG_PINCTRL_SUN6I_A31_R) += pinctrl-sun6i-a31-r.o -obj-$(CONFIG_PINCTRL_SUN7I_A20) += pinctrl-sun7i-a20.o obj-$(CONFIG_PINCTRL_SUN8I_A23) += pinctrl-sun8i-a23.o obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o obj-$(CONFIG_PINCTRL_SUN50I_A64_R) += pinctrl-sun50i-a64-r.o obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o +obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c index fb30b86a97ee..159580c04b14 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c @@ -24,101 +24,147 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ - SUNXI_FUNCTION(0x4, "uart2")), /* RTS */ + SUNXI_FUNCTION(0x4, "uart2"), /* RTS */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD3 */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ - SUNXI_FUNCTION(0x4, "uart2")), /* CTS */ + SUNXI_FUNCTION(0x4, "uart2"), /* CTS */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD2 */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x4, "uart2")), /* TX */ + SUNXI_FUNCTION(0x4, "uart2"), /* TX */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD1 */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ - SUNXI_FUNCTION(0x4, "uart2")), /* RX */ + SUNXI_FUNCTION(0x4, "uart2"), /* RX */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD0 */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ - SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */ + SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD3 */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ - SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */ + SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD2 */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ - SUNXI_FUNCTION(0x3, "spi3")), /* CLK */ + SUNXI_FUNCTION(0x3, "spi3"), /* CLK */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD1 */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ - SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */ + SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD0 */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ - SUNXI_FUNCTION(0x3, "spi3")), /* MISO */ + SUNXI_FUNCTION(0x3, "spi3"), /* MISO */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXCK */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ - SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */ + SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ERXERR */ + PINCTRL_SUN7I_A20), + SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* MCLK */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ - SUNXI_FUNCTION(0x4, "uart1")), /* TX */ + SUNXI_FUNCTION(0x4, "uart1"), /* TX */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXDV */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ - SUNXI_FUNCTION(0x4, "uart1")), /* RX */ + SUNXI_FUNCTION(0x4, "uart1"), /* RX */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* EMDC */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ SUNXI_FUNCTION(0x3, "uart6"), /* TX */ - SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ + SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* EMDIO */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ SUNXI_FUNCTION(0x3, "uart6"), /* RX */ - SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ + SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXCTL / ETXEN */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ SUNXI_FUNCTION(0x3, "uart7"), /* TX */ - SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ + SUNXI_FUNCTION(0x4, "uart1"), /* DTR */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ETXCK */ + PINCTRL_SUN7I_A20), + SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* BCLK */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ SUNXI_FUNCTION(0x3, "uart7"), /* RX */ - SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ + SUNXI_FUNCTION(0x4, "uart1"), /* DSR */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXCK / ECRS */ + PINCTRL_SUN7I_A20), + SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* LRCK */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ SUNXI_FUNCTION(0x3, "can"), /* TX */ - SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ + SUNXI_FUNCTION(0x4, "uart1"), /* DCD */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GCLKIN / ECOL */ + PINCTRL_SUN7I_A20), + SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* DO */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ SUNXI_FUNCTION(0x3, "can"), /* RX */ - SUNXI_FUNCTION(0x4, "uart1")), /* RING */ + SUNXI_FUNCTION(0x4, "uart1"), /* RING */ + SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ETXERR */ + PINCTRL_SUN7I_A20), + SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* DI */ + PINCTRL_SUN7I_A20)), /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -150,47 +196,77 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */ + /* + * On A10 there's only one I2S controller and the pin group + * is simply named "i2s". On A20 there's two and thus it's + * renamed to "i2s0". Deal with these name here, in order + * to satisfy existing device trees. + */ + SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* MCLK */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* MCLK */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ + SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* BCLK */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* BCLK */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */ + SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* LRCK */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* LRCK */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */ + SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO0 */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO0 */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x3, "ac97")), /* DO */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */ + SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO1 */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO1 */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */ + SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO2 */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO2 */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */ + SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO3 */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO3 */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s"), /* DI */ + SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DI */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DI */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x3, "ac97"), /* DI */ - /* Undocumented mux function - See SPDIF MCLK above */ + /* Undocumented mux function on A10 - See SPDIF MCLK above */ SUNXI_FUNCTION(0x4, "spdif")), /* SPDIF IN */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ - /* Undocumented mux function - See SPDIF MCLK above */ + /* Undocumented mux function on A10 - See SPDIF MCLK above */ SUNXI_FUNCTION(0x4, "spdif")), /* SPDIF OUT */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -672,7 +748,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAA0 */ + PINCTRL_SUN4I_A10), SUNXI_FUNCTION(0x4, "uart3"), /* TX */ SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */ SUNXI_FUNCTION(0x7, "csi1")), /* D0 */ @@ -680,7 +757,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAA1 */ + PINCTRL_SUN4I_A10), SUNXI_FUNCTION(0x4, "uart3"), /* RX */ SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */ SUNXI_FUNCTION(0x7, "csi1")), /* D1 */ @@ -688,7 +766,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAA2 */ + PINCTRL_SUN4I_A10), SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */ SUNXI_FUNCTION(0x7, "csi1")), /* D2 */ @@ -696,7 +775,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIRQ */ + PINCTRL_SUN4I_A10), SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */ SUNXI_FUNCTION(0x7, "csi1")), /* D3 */ @@ -704,7 +784,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD0 */ + PINCTRL_SUN4I_A10), SUNXI_FUNCTION(0x4, "uart4"), /* TX */ SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */ SUNXI_FUNCTION(0x7, "csi1")), /* D4 */ @@ -712,7 +793,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD1 */ + PINCTRL_SUN4I_A10), SUNXI_FUNCTION(0x4, "uart4"), /* RX */ SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */ SUNXI_FUNCTION(0x7, "csi1")), /* D5 */ @@ -720,7 +802,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD2 */ + PINCTRL_SUN4I_A10), SUNXI_FUNCTION(0x4, "uart5"), /* TX */ SUNXI_FUNCTION(0x5, "ms"), /* BS */ SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */ @@ -729,7 +812,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD3 */ + PINCTRL_SUN4I_A10), SUNXI_FUNCTION(0x4, "uart5"), /* RX */ SUNXI_FUNCTION(0x5, "ms"), /* CLK */ SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */ @@ -738,7 +822,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD4 */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD3 */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */ SUNXI_FUNCTION(0x5, "ms"), /* D0 */ SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */ @@ -747,7 +834,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD5 */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD2 */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */ SUNXI_FUNCTION(0x5, "ms"), /* D1 */ SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */ @@ -756,7 +846,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD6 */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD1 */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */ SUNXI_FUNCTION(0x5, "ms"), /* D2 */ SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */ @@ -765,7 +858,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD7 */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD0 */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */ SUNXI_FUNCTION(0x5, "ms"), /* D3 */ SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */ @@ -774,7 +870,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD8 */ + PINCTRL_SUN4I_A10), SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */ SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */ SUNXI_FUNCTION(0x7, "csi1")), /* D12 */ @@ -782,7 +879,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD9 */ + PINCTRL_SUN4I_A10), SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */ SUNXI_FUNCTION(0x5, "sim"), /* RST */ SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */ @@ -791,7 +889,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD10 */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD3 */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */ SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */ SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */ @@ -800,7 +901,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD11 */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD2 */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */ SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */ SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */ @@ -809,7 +913,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD12 */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD1 */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */ SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */ SUNXI_FUNCTION(0x7, "csi1")), /* D16 */ @@ -817,7 +924,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD13 */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD0 */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */ SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */ SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */ @@ -826,7 +936,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD14 */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXCK */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */ SUNXI_FUNCTION(0x5, "sim"), /* SCK */ SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */ @@ -835,7 +948,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD15 */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXERR */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */ SUNXI_FUNCTION(0x5, "sim"), /* SDA */ SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */ @@ -844,7 +960,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAOE */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXDV */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "can"), /* TX */ SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */ SUNXI_FUNCTION(0x7, "csi1")), /* D20 */ @@ -852,7 +971,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATADREQ */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* EMDC */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "can"), /* RX */ SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */ SUNXI_FUNCTION(0x7, "csi1")), /* D21 */ @@ -860,7 +982,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATADACK */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* EMDIO */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */ SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */ SUNXI_FUNCTION(0x7, "csi1")), /* D22 */ @@ -868,7 +993,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */ - SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATACS0 */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXEN */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */ SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */ SUNXI_FUNCTION(0x7, "csi1")), /* D23 */ @@ -876,7 +1004,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */ - SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATACS1 */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXCK */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */ SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */ SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */ @@ -884,7 +1015,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* DE */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIORDY */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ECRS */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */ SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */ SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */ @@ -892,7 +1026,10 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIOR */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ECOL */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */ SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */ SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */ @@ -900,24 +1037,35 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */ - SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */ + SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIOW */ + PINCTRL_SUN4I_A10), + SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXERR */ + PINCTRL_SUN7I_A20), SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */ SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */ SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SCK */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SDA */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2), SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out")), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_VARIANT(0x3, "i2c4", /* SCK */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */ + SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */ + SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SDA */ + PINCTRL_SUN7I_A20)), SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -959,12 +1107,16 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ SUNXI_FUNCTION(0x3, "uart6"), /* TX */ + SUNXI_FUNCTION_VARIANT(0x4, "clk_out_a", + PINCTRL_SUN7I_A20), SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ SUNXI_FUNCTION(0x3, "uart6"), /* RX */ + SUNXI_FUNCTION_VARIANT(0x4, "clk_out_b", + PINCTRL_SUN7I_A20), SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -1027,12 +1179,21 @@ static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { static int sun4i_a10_pinctrl_probe(struct platform_device *pdev) { - return sunxi_pinctrl_init(pdev, - &sun4i_a10_pinctrl_data); + unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev); + + return sunxi_pinctrl_init_with_variant(pdev, &sun4i_a10_pinctrl_data, + variant); } static const struct of_device_id sun4i_a10_pinctrl_match[] = { - { .compatible = "allwinner,sun4i-a10-pinctrl", }, + { + .compatible = "allwinner,sun4i-a10-pinctrl", + .data = (void *)PINCTRL_SUN4I_A10 + }, + { + .compatible = "allwinner,sun7i-a20-pinctrl", + .data = (void *)PINCTRL_SUN7I_A20 + }, {} }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c deleted file mode 100644 index b6f4c68ffb39..000000000000 --- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c +++ /dev/null @@ -1,1056 +0,0 @@ -/* - * Allwinner A20 SoCs pinctrl driver. - * - * Copyright (C) 2014 Maxime Ripard - * - * Maxime Ripard <maxime.ripard@free-electrons.com> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/of.h> -#include <linux/of_device.h> -#include <linux/pinctrl/pinctrl.h> - -#include "pinctrl-sunxi.h" - -static const struct sunxi_desc_pin sun7i_a20_pins[] = { - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXD3 */ - SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */ - SUNXI_FUNCTION(0x4, "uart2"), /* RTS */ - SUNXI_FUNCTION(0x5, "gmac")), /* GRXD3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXD2 */ - SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ - SUNXI_FUNCTION(0x4, "uart2"), /* CTS */ - SUNXI_FUNCTION(0x5, "gmac")), /* GRXD2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXD1 */ - SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x4, "uart2"), /* TX */ - SUNXI_FUNCTION(0x5, "gmac")), /* GRXD1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXD0 */ - SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ - SUNXI_FUNCTION(0x4, "uart2"), /* RX */ - SUNXI_FUNCTION(0x5, "gmac")), /* GRXD0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */ - SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */ - SUNXI_FUNCTION(0x5, "gmac")), /* GTXD3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */ - SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */ - SUNXI_FUNCTION(0x5, "gmac")), /* GTXD2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */ - SUNXI_FUNCTION(0x3, "spi3"), /* CLK */ - SUNXI_FUNCTION(0x5, "gmac")), /* GTXD1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */ - SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */ - SUNXI_FUNCTION(0x5, "gmac")), /* GTXD0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */ - SUNXI_FUNCTION(0x3, "spi3"), /* MISO */ - SUNXI_FUNCTION(0x5, "gmac")), /* GRXCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */ - SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */ - SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ERXERR */ - SUNXI_FUNCTION(0x6, "i2s1")), /* MCLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */ - SUNXI_FUNCTION(0x4, "uart1"), /* TX */ - SUNXI_FUNCTION(0x5, "gmac")), /* GRXCTL / ERXDV */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* EMDC */ - SUNXI_FUNCTION(0x4, "uart1"), /* RX */ - SUNXI_FUNCTION(0x5, "gmac")), /* EMDC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* EMDIO */ - SUNXI_FUNCTION(0x3, "uart6"), /* TX */ - SUNXI_FUNCTION(0x4, "uart1"), /* RTS */ - SUNXI_FUNCTION(0x5, "gmac")), /* EMDIO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXEN */ - SUNXI_FUNCTION(0x3, "uart6"), /* RX */ - SUNXI_FUNCTION(0x4, "uart1"), /* CTS */ - SUNXI_FUNCTION(0x5, "gmac")), /* GTXCTL / ETXEN */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXCK */ - SUNXI_FUNCTION(0x3, "uart7"), /* TX */ - SUNXI_FUNCTION(0x4, "uart1"), /* DTR */ - SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXCK */ - SUNXI_FUNCTION(0x6, "i2s1")), /* BCLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ECRS */ - SUNXI_FUNCTION(0x3, "uart7"), /* RX */ - SUNXI_FUNCTION(0x4, "uart1"), /* DSR */ - SUNXI_FUNCTION(0x5, "gmac"), /* GTXCK / ECRS */ - SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ECOL */ - SUNXI_FUNCTION(0x3, "can"), /* TX */ - SUNXI_FUNCTION(0x4, "uart1"), /* DCD */ - SUNXI_FUNCTION(0x5, "gmac"), /* GCLKIN / ECOL */ - SUNXI_FUNCTION(0x6, "i2s1")), /* DO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "emac"), /* ETXERR */ - SUNXI_FUNCTION(0x3, "can"), /* RX */ - SUNXI_FUNCTION(0x4, "uart1"), /* RING */ - SUNXI_FUNCTION(0x5, "gmac"), /* GNULL / ETXERR */ - SUNXI_FUNCTION(0x6, "i2s1")), /* LRCK */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0"), /* TX */ - SUNXI_FUNCTION(0x4, "spdif")), /* MCLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ir0")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0"), /* MCLK */ - SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ - SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0"), /* LRCK */ - SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0"), /* DO0 */ - SUNXI_FUNCTION(0x3, "ac97")), /* DO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0")), /* DO1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0")), /* DO2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0")), /* DO3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2s0"), /* DI */ - SUNXI_FUNCTION(0x3, "ac97"), /* DI */ - SUNXI_FUNCTION(0x4, "spdif")), /* DI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* CS1 */ - SUNXI_FUNCTION(0x4, "spdif")), /* DO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */ - SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* CLK */ - SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */ - SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi2"), /* MISO */ - SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "uart0"), /* TX */ - SUNXI_FUNCTION(0x3, "ir1")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "uart0"), /* RX */ - SUNXI_FUNCTION(0x3, "ir1")), /* RX */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ - SUNXI_FUNCTION(0x3, "spi0")), /* MISO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ - SUNXI_FUNCTION(0x3, "spi0")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ - SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NWP */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */ - SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 20), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */ - SUNXI_FUNCTION(0x3, "spi2")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 21), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */ - SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 22), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */ - SUNXI_FUNCTION(0x3, "spi2")), /* MISO */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 23), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ - SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ - SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ - SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ - SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ - SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ - SUNXI_FUNCTION(0x3, "sim")), /* DET */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ - SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ - SUNXI_FUNCTION(0x3, "sim")), /* RST */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ - SUNXI_FUNCTION(0x3, "sim")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ - SUNXI_FUNCTION(0x3, "sim")), /* SDA */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* CLK */ - SUNXI_FUNCTION(0x3, "csi0")), /* PCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* ERR */ - SUNXI_FUNCTION(0x3, "csi0")), /* CK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */ - SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */ - SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D0 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D1 */ - SUNXI_FUNCTION(0x3, "csi0"), /* D1 */ - SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D2 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D3 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D4 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D5 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D6 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts0"), /* D7 */ - SUNXI_FUNCTION(0x3, "csi0")), /* D7 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ - SUNXI_FUNCTION(0x4, "jtag")), /* MSI */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ - SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ - SUNXI_FUNCTION(0x4, "uart0")), /* TX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ - SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ - SUNXI_FUNCTION(0x4, "uart0")), /* RX */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ - SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* CLK */ - SUNXI_FUNCTION(0x3, "csi1"), /* PCK */ - SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* ERR */ - SUNXI_FUNCTION(0x3, "csi1"), /* CK */ - SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */ - SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */ - SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */ - SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */ - SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D0 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D0 */ - SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */ - SUNXI_FUNCTION(0x5, "csi0")), /* D8 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D1 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D1 */ - SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */ - SUNXI_FUNCTION(0x5, "csi0")), /* D9 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D2 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D2 */ - SUNXI_FUNCTION(0x4, "uart3"), /* TX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D10 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D3 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D3 */ - SUNXI_FUNCTION(0x4, "uart3"), /* RX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D11 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D4 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D4 */ - SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ - SUNXI_FUNCTION(0x5, "csi0")), /* D12 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D5 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D5 */ - SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ - SUNXI_FUNCTION(0x5, "csi0")), /* D13 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D6 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D6 */ - SUNXI_FUNCTION(0x4, "uart4"), /* TX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D14 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ts1"), /* D7 */ - SUNXI_FUNCTION(0x3, "csi1"), /* D7 */ - SUNXI_FUNCTION(0x4, "uart4"), /* RX */ - SUNXI_FUNCTION(0x5, "csi0")), /* D15 */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */ - SUNXI_FUNCTION(0x4, "uart3"), /* TX */ - SUNXI_FUNCTION_IRQ(0x6, 0), /* EINT0 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */ - SUNXI_FUNCTION(0x4, "uart3"), /* RX */ - SUNXI_FUNCTION_IRQ(0x6, 1), /* EINT1 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */ - SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ - SUNXI_FUNCTION_IRQ(0x6, 2), /* EINT2 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */ - SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ - SUNXI_FUNCTION_IRQ(0x6, 3), /* EINT3 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */ - SUNXI_FUNCTION(0x4, "uart4"), /* TX */ - SUNXI_FUNCTION_IRQ(0x6, 4), /* EINT4 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D4 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */ - SUNXI_FUNCTION(0x4, "uart4"), /* RX */ - SUNXI_FUNCTION_IRQ(0x6, 5), /* EINT5 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D5 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */ - SUNXI_FUNCTION(0x4, "uart5"), /* TX */ - SUNXI_FUNCTION(0x5, "ms"), /* BS */ - SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D6 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */ - SUNXI_FUNCTION(0x4, "uart5"), /* RX */ - SUNXI_FUNCTION(0x5, "ms"), /* CLK */ - SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D7 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */ - SUNXI_FUNCTION(0x3, "emac"), /* ERXD3 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */ - SUNXI_FUNCTION(0x5, "ms"), /* D0 */ - SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D8 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */ - SUNXI_FUNCTION(0x3, "emac"), /* ERXD2 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */ - SUNXI_FUNCTION(0x5, "ms"), /* D1 */ - SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D9 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */ - SUNXI_FUNCTION(0x3, "emac"), /* ERXD1 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */ - SUNXI_FUNCTION(0x5, "ms"), /* D2 */ - SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D10 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */ - SUNXI_FUNCTION(0x3, "emac"), /* ERXD0 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */ - SUNXI_FUNCTION(0x5, "ms"), /* D3 */ - SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D11 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */ - SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */ - SUNXI_FUNCTION_IRQ(0x6, 12), /* EINT12 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D12 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */ - SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */ - SUNXI_FUNCTION(0x5, "sim"), /* RST */ - SUNXI_FUNCTION_IRQ(0x6, 13), /* EINT13 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D13 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */ - SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */ - SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */ - SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D14 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */ - SUNXI_FUNCTION(0x3, "emac"), /* ETXD3 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */ - SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */ - SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D15 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */ - SUNXI_FUNCTION(0x3, "emac"), /* ETXD2 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */ - SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D16 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */ - SUNXI_FUNCTION(0x3, "emac"), /* ETXD1 */ - SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */ - SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */ - SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D17 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */ - SUNXI_FUNCTION(0x3, "emac"), /* ETXD0 */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */ - SUNXI_FUNCTION(0x5, "sim"), /* SCK */ - SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D18 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */ - SUNXI_FUNCTION(0x3, "emac"), /* ERXERR */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */ - SUNXI_FUNCTION(0x5, "sim"), /* SDA */ - SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D19 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */ - SUNXI_FUNCTION(0x3, "emac"), /* ERXDV */ - SUNXI_FUNCTION(0x4, "can"), /* TX */ - SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D20 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */ - SUNXI_FUNCTION(0x3, "emac"), /* EMDC */ - SUNXI_FUNCTION(0x4, "can"), /* RX */ - SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */ - SUNXI_FUNCTION(0x7, "csi1")), /* D21 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 22), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */ - SUNXI_FUNCTION(0x3, "emac"), /* EMDIO */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */ - SUNXI_FUNCTION(0x7, "csi1")), /* D22 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 23), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */ - SUNXI_FUNCTION(0x3, "emac"), /* ETXEN */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */ - SUNXI_FUNCTION(0x7, "csi1")), /* D23 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 24), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */ - SUNXI_FUNCTION(0x3, "emac"), /* ETXCK */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */ - SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 25), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* DE */ - SUNXI_FUNCTION(0x3, "emac"), /* ECRS */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */ - SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 26), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */ - SUNXI_FUNCTION(0x3, "emac"), /* ECOL */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */ - SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 27), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */ - SUNXI_FUNCTION(0x3, "emac"), /* ETXERR */ - SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */ - SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */ - SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */ - /* Hole */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "i2c3")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "i2c3")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x3, "i2c4")), /* SCK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */ - SUNXI_FUNCTION(0x3, "i2c4")), /* SDA */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */ - SUNXI_FUNCTION(0x3, "uart5"), /* TX */ - SUNXI_FUNCTION_IRQ(0x6, 22)), /* EINT22 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* CLK */ - SUNXI_FUNCTION(0x3, "uart5"), /* RX */ - SUNXI_FUNCTION_IRQ(0x6, 23)), /* EINT23 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ - SUNXI_FUNCTION(0x3, "uart6"), /* TX */ - SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */ - SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ - SUNXI_FUNCTION(0x3, "uart6"), /* RX */ - SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */ - SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */ - SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */ - SUNXI_FUNCTION(0x4, "timer4"), /* TCLKIN0 */ - SUNXI_FUNCTION_IRQ(0x6, 26)), /* EINT26 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */ - SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */ - SUNXI_FUNCTION(0x4, "timer5"), /* TCLKIN1 */ - SUNXI_FUNCTION_IRQ(0x6, 27)), /* EINT27 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */ - SUNXI_FUNCTION(0x3, "uart2"), /* RTS */ - SUNXI_FUNCTION_IRQ(0x6, 28)), /* EINT28 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 17), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* CLK */ - SUNXI_FUNCTION(0x3, "uart2"), /* CTS */ - SUNXI_FUNCTION_IRQ(0x6, 29)), /* EINT29 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 18), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */ - SUNXI_FUNCTION(0x3, "uart2"), /* TX */ - SUNXI_FUNCTION_IRQ(0x6, 30)), /* EINT30 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 19), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "spi1"), /* MISO */ - SUNXI_FUNCTION(0x3, "uart2"), /* RX */ - SUNXI_FUNCTION_IRQ(0x6, 31)), /* EINT31 */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 20), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */ - SUNXI_FUNCTION(0x3, "uart7"), /* TX */ - SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */ - SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21), - SUNXI_FUNCTION(0x0, "gpio_in"), - SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */ - SUNXI_FUNCTION(0x3, "uart7"), /* RX */ - SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */ -}; - -static const struct sunxi_pinctrl_desc sun7i_a20_pinctrl_data = { - .pins = sun7i_a20_pins, - .npins = ARRAY_SIZE(sun7i_a20_pins), - .irq_banks = 1, -}; - -static int sun7i_a20_pinctrl_probe(struct platform_device *pdev) -{ - return sunxi_pinctrl_init(pdev, - &sun7i_a20_pinctrl_data); -} - -static const struct of_device_id sun7i_a20_pinctrl_match[] = { - { .compatible = "allwinner,sun7i-a20-pinctrl", }, - {} -}; - -static struct platform_driver sun7i_a20_pinctrl_driver = { - .probe = sun7i_a20_pinctrl_probe, - .driver = { - .name = "sun7i-a20-pinctrl", - .of_match_table = sun7i_a20_pinctrl_match, - }, -}; -builtin_platform_driver(sun7i_a20_pinctrl_driver); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c new file mode 100644 index 000000000000..6531cf67958e --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c @@ -0,0 +1,128 @@ +/* + * Allwinner A83T SoCs special pins pinctrl driver. + * + * Copyright (C) 2017 Chen-Yu Tsai + * Chen-Yu Tsai <wens@csie.org> + * + * Based on pinctrl-sun50i-a64-r.c + * + * Copyright (C) 2016 Icenowy Zheng + * Icenowy Zheng <icenowy@aosc.xyz> + * + * Copyright (C) 2014 Chen-Yu Tsai + * Chen-Yu Tsai <wens@csie.org> + * + * Copyright (C) 2014 Boris Brezillon + * Boris Brezillon <boris.brezillon@free-electrons.com> + * + * Copyright (C) 2014 Maxime Ripard + * Maxime Ripard <maxime.ripard@free-electrons.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> +#include <linux/reset.h> + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin sun8i_a83t_r_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */ + SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PL_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */ + SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PL_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_uart"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PL_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_uart"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PL_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PL_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PL_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PL_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PL_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PL_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PL_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_pwm"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PL_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_cir_rx"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PL_EINT12 */ +}; + +static const struct sunxi_pinctrl_desc sun8i_a83t_r_pinctrl_data = { + .pins = sun8i_a83t_r_pins, + .npins = ARRAY_SIZE(sun8i_a83t_r_pins), + .pin_base = PL_BASE, + .irq_banks = 1, +}; + +static int sun8i_a83t_r_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, + &sun8i_a83t_r_pinctrl_data); +} + +static const struct of_device_id sun8i_a83t_r_pinctrl_match[] = { + { .compatible = "allwinner,sun8i-a83t-r-pinctrl", }, + {} +}; + +static struct platform_driver sun8i_a83t_r_pinctrl_driver = { + .probe = sun8i_a83t_r_pinctrl_probe, + .driver = { + .name = "sun8i-a83t-r-pinctrl", + .of_match_table = sun8i_a83t_r_pinctrl_match, + }, +}; +builtin_platform_driver(sun8i_a83t_r_pinctrl_driver); diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 58774acfc814..0dfd7fa66c48 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -979,7 +979,7 @@ static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d, return 0; } -static struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = { +static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = { .xlate = sunxi_pinctrl_irq_of_xlate, }; diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index a9d315a1256c..1bfc0d8a55df 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -87,6 +87,9 @@ #define PINCTRL_SUN5I_GR8 BIT(3) #define PINCTRL_SUN6I_A31 BIT(4) #define PINCTRL_SUN6I_A31S BIT(5) +#define PINCTRL_SUN4I_A10 BIT(6) +#define PINCTRL_SUN7I_A20 BIT(7) +#define PINCTRL_SUN8I_R40 BIT(8) struct sunxi_desc_function { unsigned long variant; diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 277622b4b6fb..51716819129d 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -21,7 +21,6 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> -#include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pinctrl/machine.h> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra114.c b/drivers/pinctrl/tegra/pinctrl-tegra114.c index 952132ce5ea0..56b33fca1bfc 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra114.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra114.c @@ -1,6 +1,8 @@ /* * Pinctrl data for the NVIDIA Tegra114 pinmux * + * Author: Pritesh Raithatha <praithatha@nvidia.com> + * * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -13,7 +15,7 @@ * more details. */ -#include <linux/module.h> +#include <linux/init.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> @@ -1857,7 +1859,6 @@ static const struct of_device_id tegra114_pinctrl_of_match[] = { { .compatible = "nvidia,tegra114-pinmux", }, { }, }; -MODULE_DEVICE_TABLE(of, tegra114_pinctrl_of_match); static struct platform_driver tegra114_pinctrl_driver = { .driver = { @@ -1866,8 +1867,4 @@ static struct platform_driver tegra114_pinctrl_driver = { }, .probe = tegra114_pinctrl_probe, }; -module_platform_driver(tegra114_pinctrl_driver); - -MODULE_AUTHOR("Pritesh Raithatha <praithatha@nvidia.com>"); -MODULE_DESCRIPTION("NVIDIA Tegra114 pinctrl driver"); -MODULE_LICENSE("GPL v2"); +builtin_platform_driver(tegra114_pinctrl_driver); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra124.c b/drivers/pinctrl/tegra/pinctrl-tegra124.c index bca239e3ae50..7bc998ace0d5 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra124.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra124.c @@ -1,6 +1,8 @@ /* * Pinctrl data for the NVIDIA Tegra124 pinmux * + * Author: Ashwini Ghuge <aghuge@nvidia.com> + * * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -13,7 +15,7 @@ * more details. */ -#include <linux/module.h> +#include <linux/init.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> @@ -2069,7 +2071,6 @@ static const struct of_device_id tegra124_pinctrl_of_match[] = { { .compatible = "nvidia,tegra124-pinmux", }, { }, }; -MODULE_DEVICE_TABLE(of, tegra124_pinctrl_of_match); static struct platform_driver tegra124_pinctrl_driver = { .driver = { @@ -2078,8 +2079,4 @@ static struct platform_driver tegra124_pinctrl_driver = { }, .probe = tegra124_pinctrl_probe, }; -module_platform_driver(tegra124_pinctrl_driver); - -MODULE_AUTHOR("Ashwini Ghuge <aghuge@nvidia.com>"); -MODULE_DESCRIPTION("NVIDIA Tegra124 pinctrl driver"); -MODULE_LICENSE("GPL v2"); +builtin_platform_driver(tegra124_pinctrl_driver); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c index ad62451a5a9b..7e38ee9bae78 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra20.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c @@ -1,6 +1,8 @@ /* * Pinctrl data for the NVIDIA Tegra20 pinmux * + * Author: Stephen Warren <swarren@nvidia.com> + * * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * Derived from code: @@ -17,7 +19,7 @@ * more details. */ -#include <linux/module.h> +#include <linux/init.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> @@ -2246,9 +2248,4 @@ static struct platform_driver tegra20_pinctrl_driver = { }, .probe = tegra20_pinctrl_probe, }; -module_platform_driver(tegra20_pinctrl_driver); - -MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); -MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver"); -MODULE_LICENSE("GPL v2"); -MODULE_DEVICE_TABLE(of, tegra20_pinctrl_of_match); +builtin_platform_driver(tegra20_pinctrl_driver); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c index 2b70e93da9db..c244e5b17bd6 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra210.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c @@ -13,7 +13,7 @@ * more details. */ -#include <linux/module.h> +#include <linux/init.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> @@ -1573,7 +1573,6 @@ static const struct of_device_id tegra210_pinctrl_of_match[] = { { .compatible = "nvidia,tegra210-pinmux", }, { }, }; -MODULE_DEVICE_TABLE(of, tegra210_pinctrl_of_match); static struct platform_driver tegra210_pinctrl_driver = { .driver = { @@ -1582,8 +1581,4 @@ static struct platform_driver tegra210_pinctrl_driver = { }, .probe = tegra210_pinctrl_probe, }; -module_platform_driver(tegra210_pinctrl_driver); - -MODULE_AUTHOR("NVIDIA"); -MODULE_DESCRIPTION("NVIDIA Tegra210 pinctrl driver"); -MODULE_LICENSE("GPL v2"); +builtin_platform_driver(tegra210_pinctrl_driver); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra30.c b/drivers/pinctrl/tegra/pinctrl-tegra30.c index 474ac6daf513..1f180a20f2ab 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra30.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra30.c @@ -1,6 +1,8 @@ /* * Pinctrl data for the NVIDIA Tegra30 pinmux * + * Author: Stephen Warren <swarren@nvidia.com> + * * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -13,7 +15,7 @@ * more details. */ -#include <linux/module.h> +#include <linux/init.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pinctrl/pinctrl.h> @@ -2492,7 +2494,6 @@ static const struct of_device_id tegra30_pinctrl_of_match[] = { { .compatible = "nvidia,tegra30-pinmux", }, { }, }; -MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match); static struct platform_driver tegra30_pinctrl_driver = { .driver = { @@ -2501,8 +2502,4 @@ static struct platform_driver tegra30_pinctrl_driver = { }, .probe = tegra30_pinctrl_probe, }; -module_platform_driver(tegra30_pinctrl_driver); - -MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); -MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver"); -MODULE_LICENSE("GPL v2"); +builtin_platform_driver(tegra30_pinctrl_driver); diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c index 706effe0a492..ad73db8d067b 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c @@ -508,57 +508,71 @@ static const unsigned usb1_pins[] = {48, 49}; static const int usb1_muxvals[] = {0, 0}; static const unsigned usb2_pins[] = {50, 51}; static const int usb2_muxvals[] = {0, 0}; -static const unsigned port_range_pins[] = { +static const unsigned port_range0_pins[] = { 159, 160, 161, 162, 163, 164, 165, 166, /* PORT0x */ 0, 1, 2, 3, 4, 5, 6, 7, /* PORT1x */ 8, 9, 10, 11, 12, 13, 14, 15, /* PORT2x */ - 16, 17, 18, -1, -1, -1, -1, -1, /* PORT3x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT4x */ - -1, -1, -1, 46, 47, 48, 49, 50, /* PORT5x */ - 51, -1, -1, 54, 55, 56, 57, 58, /* PORT6x */ + 16, 17, 18, /* PORT30-32 */ +}; +static const int port_range0_muxvals[] = { + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */ + 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */ + 15, 15, 15, /* PORT30-32 */ +}; +static const unsigned port_range1_pins[] = { + 46, 47, 48, 49, 50, /* PORT53-57 */ + 51, /* PORT60 */ +}; +static const int port_range1_muxvals[] = { + 15, 15, 15, 15, 15, /* PORT53-57 */ + 15, /* PORT60 */ +}; +static const unsigned port_range2_pins[] = { + 54, 55, 56, 57, 58, /* PORT63-67 */ 59, 60, 69, 70, 71, 72, 73, 74, /* PORT7x */ 75, 76, 77, 78, 79, 80, 81, 82, /* PORT8x */ 83, 84, 85, 86, 87, 88, 89, 90, /* PORT9x */ 91, 92, 93, 94, 95, 96, 97, 98, /* PORT10x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT11x */ - 99, 100, 101, 102, 103, 104, 105, 106, /* PORT12x */ - 107, 108, 109, 110, 111, 112, 113, 114, /* PORT13x */ - 115, 116, 117, 118, 119, 120, 121, 122, /* PORT14x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT15x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT16x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT17x */ - 61, 62, 63, 64, 65, 66, 67, 68, /* PORT18x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT19x */ - 123, 124, 125, 126, 127, 128, 129, 130, /* PORT20x */ - 131, 132, 133, 134, 135, 136, 137, 138, /* PORT21x */ - 139, 140, 141, 142, -1, -1, -1, -1, /* PORT22x */ - 147, 148, 149, 150, 151, 152, 153, 154, /* PORT23x */ - 155, 156, 157, 143, 144, 145, 146, 158, /* PORT24x */ }; -static const int port_range_muxvals[] = { - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */ - 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */ - 15, 15, 15, -1, -1, -1, -1, -1, /* PORT3x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT4x */ - -1, -1, -1, 15, 15, 15, 15, 15, /* PORT5x */ - 15, -1, -1, 15, 15, 15, 15, 15, /* PORT6x */ +static const int port_range2_muxvals[] = { + 15, 15, 15, 15, 15, /* PORT63-67 */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT7x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT11x */ +}; +static const unsigned port_range3_pins[] = { + 99, 100, 101, 102, 103, 104, 105, 106, /* PORT12x */ + 107, 108, 109, 110, 111, 112, 113, 114, /* PORT13x */ + 115, 116, 117, 118, 119, 120, 121, 122, /* PORT14x */ +}; +static const int port_range3_muxvals[] = { 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT15x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT16x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT17x */ +}; +static const unsigned port_range4_pins[] = { + 61, 62, 63, 64, 65, 66, 67, 68, /* PORT18x */ +}; +static const int port_range4_muxvals[] = { 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT19x */ +}; +static const unsigned port_range5_pins[] = { + 123, 124, 125, 126, 127, 128, 129, 130, /* PORT20x */ + 131, 132, 133, 134, 135, 136, 137, 138, /* PORT21x */ + 139, 140, 141, 142, /* PORT220-223 */ +}; +static const int port_range5_muxvals[] = { 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */ - 15, 15, 15, 15, -1, -1, -1, -1, /* PORT22x */ + 15, 15, 15, 15, /* PORT220-223 */ +}; +static const unsigned port_range6_pins[] = { + 147, 148, 149, 150, 151, 152, 153, 154, /* PORT23x */ + 155, 156, 157, 143, 144, 145, 146, 158, /* PORT24x */ +}; +static const int port_range6_muxvals[] = { 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */ }; @@ -607,147 +621,153 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = { UNIPHIER_PINCTRL_GROUP(usb0), UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range2), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range3), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range4), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range5), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range6), UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq), UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives), - UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range, 43), - UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range, 44), - UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range, 45), - UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range, 46), - UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range, 47), - UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range, 48), - UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range, 51), - UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range, 52), - UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range, 53), - UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range, 54), - UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range, 55), - UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range, 56), - UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range, 57), - UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range, 58), - UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range, 59), - UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range, 60), - UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range, 61), - UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range, 62), - UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range, 63), - UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range, 64), - UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range, 65), - UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range, 66), - UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range, 67), - UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range, 68), - UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range, 69), - UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range, 70), - UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range, 71), - UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range, 72), - UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range, 73), - UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range, 74), - UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range, 75), - UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range, 76), - UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range, 77), - UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range, 78), - UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range, 79), - UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range, 80), - UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range, 81), - UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range, 82), - UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range, 83), - UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range, 84), - UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range, 85), - UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range, 86), - UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range, 87), - UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range, 96), - UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range, 97), - UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range, 98), - UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range, 99), - UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range, 100), - UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range, 101), - UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range, 102), - UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range, 103), - UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range, 104), - UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range, 105), - UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range, 106), - UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range, 107), - UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range, 108), - UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range, 109), - UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range, 110), - UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range, 111), - UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range, 112), - UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range, 113), - UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range, 114), - UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range, 115), - UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range, 116), - UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range, 117), - UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range, 118), - UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range, 119), - UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range, 144), - UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range, 145), - UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range, 146), - UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range, 147), - UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range, 148), - UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range, 149), - UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range, 150), - UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range, 151), - UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range, 160), - UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range, 161), - UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range, 162), - UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range, 163), - UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range, 164), - UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range, 165), - UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range, 166), - UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range, 167), - UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range, 168), - UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range, 169), - UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range, 170), - UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range, 171), - UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range, 172), - UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range, 173), - UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range, 174), - UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range, 175), - UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range, 176), - UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range, 177), - UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range, 178), - UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range, 179), - UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range, 184), - UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range, 185), - UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range, 186), - UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range, 187), - UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range, 188), - UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range, 189), - UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range, 190), - UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range, 191), - UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range, 192), - UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range, 193), - UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range, 194), - UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range, 195), - UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range, 196), - UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range, 197), - UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range, 198), - UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range, 199), + UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23), + UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24), + UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25), + UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26), + UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range1, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range1, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range1, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range1, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range1, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range1, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range2, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range2, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range2, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range2, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range2, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range2, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range2, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range2, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range2, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range2, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range2, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range2, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range2, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range2, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range2, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range2, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range2, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range2, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range2, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range2, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range2, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range2, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range2, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range2, 23), + UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range2, 24), + UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range2, 25), + UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range2, 26), + UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range2, 27), + UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range2, 28), + UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range2, 29), + UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range2, 30), + UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range2, 31), + UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range2, 32), + UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range2, 33), + UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range2, 34), + UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range2, 35), + UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range2, 36), + UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range3, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range3, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range3, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range3, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range3, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range3, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range3, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range3, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range3, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range3, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range3, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range3, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range3, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range3, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range3, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range3, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range3, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range3, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range3, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range3, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range3, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range3, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range3, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range3, 23), + UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range4, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range4, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range4, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range4, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range4, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range4, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range4, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range4, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range5, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range5, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range5, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range5, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range5, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range5, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range5, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range5, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range5, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range5, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range5, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range5, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range5, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range5, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range5, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range5, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range5, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range5, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range5, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range5, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range6, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range6, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range6, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range6, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range6, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range6, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range6, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range6, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range6, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range6, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range6, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range6, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range6, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range6, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range6, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range6, 15), UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0), UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1), UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2), diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index c8d18a2d3a88..93006626028d 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -597,7 +597,7 @@ static const unsigned usb2_pins[] = {50, 51}; static const int usb2_muxvals[] = {0, 0}; static const unsigned usb3_pins[] = {52, 53}; static const int usb3_muxvals[] = {0, 0}; -static const unsigned port_range_pins[] = { +static const unsigned port_range0_pins[] = { 168, 169, 170, 171, 172, 173, 174, 175, /* PORT0x */ 0, 1, 2, 3, 4, 5, 6, 7, /* PORT1x */ 8, 9, 10, 11, 12, 13, 14, 15, /* PORT2x */ @@ -609,23 +609,8 @@ static const unsigned port_range_pins[] = { 75, 76, 77, 78, 79, 80, 81, 82, /* PORT8x */ 83, 84, 85, 86, 87, 88, 89, 90, /* PORT9x */ 91, 92, 93, 94, 95, 96, 97, 98, /* PORT10x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT11x */ - 99, 100, 101, 102, 103, 104, 105, 106, /* PORT12x */ - 107, 108, 109, 110, 111, 112, 113, 114, /* PORT13x */ - 115, 116, 117, 118, 119, 120, 121, 122, /* PORT14x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT15x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT16x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT17x */ - 61, 62, 63, 64, 65, 66, 67, 68, /* PORT18x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT19x */ - 123, 124, 125, 126, 127, 128, 129, 130, /* PORT20x */ - 131, 132, 133, 134, 135, 136, 137, 138, /* PORT21x */ - 139, 140, 141, 142, 143, 144, 145, 146, /* PORT22x */ - 147, 148, 149, 150, 151, 152, 153, 154, /* PORT23x */ - 155, 156, 157, 158, 159, 160, 161, 162, /* PORT24x */ - 163, 164, 165, 166, 167, /* PORT25x */ }; -static const int port_range_muxvals[] = { +static const int port_range0_muxvals[] = { 15, 15, 15, 15, 15, 15, 15, 15, /* PORT0x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT1x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT2x */ @@ -637,21 +622,38 @@ static const int port_range_muxvals[] = { 15, 15, 15, 15, 15, 15, 15, 15, /* PORT8x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT9x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT10x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT11x */ +}; +static const unsigned port_range1_pins[] = { + 99, 100, 101, 102, 103, 104, 105, 106, /* PORT12x */ + 107, 108, 109, 110, 111, 112, 113, 114, /* PORT13x */ + 115, 116, 117, 118, 119, 120, 121, 122, /* PORT14x */ +}; +static const int port_range1_muxvals[] = { 15, 15, 15, 15, 15, 15, 15, 15, /* PORT12x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT13x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT14x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT15x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT16x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT17x */ +}; +static const unsigned port_range2_pins[] = { + 61, 62, 63, 64, 65, 66, 67, 68, /* PORT18x */ +}; +static const int port_range2_muxvals[] = { 15, 15, 15, 15, 15, 15, 15, 15, /* PORT18x */ - -1, -1, -1, -1, -1, -1, -1, -1, /* PORT19x */ +}; +static const unsigned port_range3_pins[] = { + 123, 124, 125, 126, 127, 128, 129, 130, /* PORT20x */ + 131, 132, 133, 134, 135, 136, 137, 138, /* PORT21x */ + 139, 140, 141, 142, 143, 144, 145, 146, /* PORT22x */ + 147, 148, 149, 150, 151, 152, 153, 154, /* PORT23x */ + 155, 156, 157, 158, 159, 160, 161, 162, /* PORT24x */ + 163, 164, 165, 166, 167, /* PORT250-254 */ +}; +static const int port_range3_muxvals[] = { 15, 15, 15, 15, 15, 15, 15, 15, /* PORT20x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT21x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT22x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT23x */ 15, 15, 15, 15, 15, 15, 15, 15, /* PORT24x */ - 15, 15, 15, 15, 15, /* PORT25x */ + 15, 15, 15, 15, 15, /* PORT250-254 */ }; static const unsigned xirq_pins[] = { 149, 150, 151, 152, 153, 154, 155, 156, /* XIRQ0-7 */ @@ -695,174 +697,177 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = { UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), UNIPHIER_PINCTRL_GROUP(usb3), - UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range0), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range1), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range2), + UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_PORT(port_range3), UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq), UNIPHIER_PINCTRL_GROUP_GPIO_RANGE_IRQ(xirq_alternatives), - UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range, 0), - UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range, 1), - UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range, 2), - UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range, 3), - UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range, 4), - UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range, 5), - UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range, 6), - UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range, 7), - UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range, 8), - UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range, 9), - UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range, 10), - UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range, 11), - UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range, 12), - UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range, 13), - UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range, 14), - UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range, 15), - UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range, 16), - UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range, 17), - UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range, 18), - UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range, 19), - UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range, 20), - UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range, 21), - UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range, 22), - UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range, 23), - UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range, 24), - UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range, 25), - UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range, 26), - UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range, 27), - UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range, 28), - UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range, 29), - UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range, 30), - UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range, 31), - UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range, 32), - UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range, 33), - UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range, 34), - UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range, 35), - UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range, 36), - UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range, 37), - UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range, 38), - UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range, 39), - UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range, 40), - UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range, 41), - UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range, 42), - UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range, 43), - UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range, 44), - UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range, 45), - UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range, 46), - UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range, 47), - UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range, 48), - UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range, 49), - UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range, 50), - UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range, 51), - UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range, 52), - UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range, 53), - UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range, 54), - UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range, 55), - UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range, 56), - UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range, 57), - UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range, 58), - UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range, 59), - UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range, 60), - UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range, 61), - UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range, 62), - UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range, 63), - UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range, 64), - UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range, 65), - UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range, 66), - UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range, 67), - UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range, 68), - UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range, 69), - UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range, 70), - UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range, 71), - UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range, 72), - UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range, 73), - UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range, 74), - UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range, 75), - UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range, 76), - UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range, 77), - UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range, 78), - UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range, 79), - UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range, 80), - UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range, 81), - UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range, 82), - UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range, 83), - UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range, 84), - UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range, 85), - UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range, 86), - UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range, 87), - UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range, 96), - UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range, 97), - UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range, 98), - UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range, 99), - UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range, 100), - UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range, 101), - UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range, 102), - UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range, 103), - UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range, 104), - UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range, 105), - UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range, 106), - UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range, 107), - UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range, 108), - UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range, 109), - UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range, 110), - UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range, 111), - UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range, 112), - UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range, 113), - UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range, 114), - UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range, 115), - UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range, 116), - UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range, 117), - UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range, 118), - UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range, 119), - UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range, 144), - UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range, 145), - UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range, 146), - UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range, 147), - UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range, 148), - UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range, 149), - UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range, 150), - UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range, 151), - UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range, 160), - UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range, 161), - UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range, 162), - UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range, 163), - UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range, 164), - UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range, 165), - UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range, 166), - UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range, 167), - UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range, 168), - UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range, 169), - UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range, 170), - UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range, 171), - UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range, 172), - UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range, 173), - UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range, 174), - UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range, 175), - UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range, 176), - UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range, 177), - UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range, 178), - UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range, 179), - UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range, 180), - UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range, 181), - UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range, 182), - UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range, 183), - UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range, 184), - UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range, 185), - UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range, 186), - UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range, 187), - UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range, 188), - UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range, 189), - UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range, 190), - UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range, 191), - UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range, 192), - UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range, 193), - UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range, 194), - UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range, 195), - UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range, 196), - UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range, 197), - UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range, 198), - UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range, 199), - UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range, 200), - UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range, 201), - UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range, 202), - UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range, 203), - UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range, 204), + UNIPHIER_PINCTRL_GROUP_SINGLE(port00, port_range0, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port01, port_range0, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port02, port_range0, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port03, port_range0, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port04, port_range0, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port05, port_range0, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port06, port_range0, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port07, port_range0, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port10, port_range0, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port11, port_range0, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port12, port_range0, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port13, port_range0, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port14, port_range0, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port15, port_range0, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port16, port_range0, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port17, port_range0, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port20, port_range0, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port21, port_range0, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port22, port_range0, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port23, port_range0, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port24, port_range0, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(port25, port_range0, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(port26, port_range0, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(port27, port_range0, 23), + UNIPHIER_PINCTRL_GROUP_SINGLE(port30, port_range0, 24), + UNIPHIER_PINCTRL_GROUP_SINGLE(port31, port_range0, 25), + UNIPHIER_PINCTRL_GROUP_SINGLE(port32, port_range0, 26), + UNIPHIER_PINCTRL_GROUP_SINGLE(port33, port_range0, 27), + UNIPHIER_PINCTRL_GROUP_SINGLE(port34, port_range0, 28), + UNIPHIER_PINCTRL_GROUP_SINGLE(port35, port_range0, 29), + UNIPHIER_PINCTRL_GROUP_SINGLE(port36, port_range0, 30), + UNIPHIER_PINCTRL_GROUP_SINGLE(port37, port_range0, 31), + UNIPHIER_PINCTRL_GROUP_SINGLE(port40, port_range0, 32), + UNIPHIER_PINCTRL_GROUP_SINGLE(port41, port_range0, 33), + UNIPHIER_PINCTRL_GROUP_SINGLE(port42, port_range0, 34), + UNIPHIER_PINCTRL_GROUP_SINGLE(port43, port_range0, 35), + UNIPHIER_PINCTRL_GROUP_SINGLE(port44, port_range0, 36), + UNIPHIER_PINCTRL_GROUP_SINGLE(port45, port_range0, 37), + UNIPHIER_PINCTRL_GROUP_SINGLE(port46, port_range0, 38), + UNIPHIER_PINCTRL_GROUP_SINGLE(port47, port_range0, 39), + UNIPHIER_PINCTRL_GROUP_SINGLE(port50, port_range0, 40), + UNIPHIER_PINCTRL_GROUP_SINGLE(port51, port_range0, 41), + UNIPHIER_PINCTRL_GROUP_SINGLE(port52, port_range0, 42), + UNIPHIER_PINCTRL_GROUP_SINGLE(port53, port_range0, 43), + UNIPHIER_PINCTRL_GROUP_SINGLE(port54, port_range0, 44), + UNIPHIER_PINCTRL_GROUP_SINGLE(port55, port_range0, 45), + UNIPHIER_PINCTRL_GROUP_SINGLE(port56, port_range0, 46), + UNIPHIER_PINCTRL_GROUP_SINGLE(port57, port_range0, 47), + UNIPHIER_PINCTRL_GROUP_SINGLE(port60, port_range0, 48), + UNIPHIER_PINCTRL_GROUP_SINGLE(port61, port_range0, 49), + UNIPHIER_PINCTRL_GROUP_SINGLE(port62, port_range0, 50), + UNIPHIER_PINCTRL_GROUP_SINGLE(port63, port_range0, 51), + UNIPHIER_PINCTRL_GROUP_SINGLE(port64, port_range0, 52), + UNIPHIER_PINCTRL_GROUP_SINGLE(port65, port_range0, 53), + UNIPHIER_PINCTRL_GROUP_SINGLE(port66, port_range0, 54), + UNIPHIER_PINCTRL_GROUP_SINGLE(port67, port_range0, 55), + UNIPHIER_PINCTRL_GROUP_SINGLE(port70, port_range0, 56), + UNIPHIER_PINCTRL_GROUP_SINGLE(port71, port_range0, 57), + UNIPHIER_PINCTRL_GROUP_SINGLE(port72, port_range0, 58), + UNIPHIER_PINCTRL_GROUP_SINGLE(port73, port_range0, 59), + UNIPHIER_PINCTRL_GROUP_SINGLE(port74, port_range0, 60), + UNIPHIER_PINCTRL_GROUP_SINGLE(port75, port_range0, 61), + UNIPHIER_PINCTRL_GROUP_SINGLE(port76, port_range0, 62), + UNIPHIER_PINCTRL_GROUP_SINGLE(port77, port_range0, 63), + UNIPHIER_PINCTRL_GROUP_SINGLE(port80, port_range0, 64), + UNIPHIER_PINCTRL_GROUP_SINGLE(port81, port_range0, 65), + UNIPHIER_PINCTRL_GROUP_SINGLE(port82, port_range0, 66), + UNIPHIER_PINCTRL_GROUP_SINGLE(port83, port_range0, 67), + UNIPHIER_PINCTRL_GROUP_SINGLE(port84, port_range0, 68), + UNIPHIER_PINCTRL_GROUP_SINGLE(port85, port_range0, 69), + UNIPHIER_PINCTRL_GROUP_SINGLE(port86, port_range0, 70), + UNIPHIER_PINCTRL_GROUP_SINGLE(port87, port_range0, 71), + UNIPHIER_PINCTRL_GROUP_SINGLE(port90, port_range0, 72), + UNIPHIER_PINCTRL_GROUP_SINGLE(port91, port_range0, 73), + UNIPHIER_PINCTRL_GROUP_SINGLE(port92, port_range0, 74), + UNIPHIER_PINCTRL_GROUP_SINGLE(port93, port_range0, 75), + UNIPHIER_PINCTRL_GROUP_SINGLE(port94, port_range0, 76), + UNIPHIER_PINCTRL_GROUP_SINGLE(port95, port_range0, 77), + UNIPHIER_PINCTRL_GROUP_SINGLE(port96, port_range0, 78), + UNIPHIER_PINCTRL_GROUP_SINGLE(port97, port_range0, 79), + UNIPHIER_PINCTRL_GROUP_SINGLE(port100, port_range0, 80), + UNIPHIER_PINCTRL_GROUP_SINGLE(port101, port_range0, 81), + UNIPHIER_PINCTRL_GROUP_SINGLE(port102, port_range0, 82), + UNIPHIER_PINCTRL_GROUP_SINGLE(port103, port_range0, 83), + UNIPHIER_PINCTRL_GROUP_SINGLE(port104, port_range0, 84), + UNIPHIER_PINCTRL_GROUP_SINGLE(port105, port_range0, 85), + UNIPHIER_PINCTRL_GROUP_SINGLE(port106, port_range0, 86), + UNIPHIER_PINCTRL_GROUP_SINGLE(port107, port_range0, 87), + UNIPHIER_PINCTRL_GROUP_SINGLE(port120, port_range1, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port121, port_range1, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port122, port_range1, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port123, port_range1, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port124, port_range1, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port125, port_range1, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port126, port_range1, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port127, port_range1, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port130, port_range1, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port131, port_range1, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port132, port_range1, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port133, port_range1, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port134, port_range1, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port135, port_range1, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port136, port_range1, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port137, port_range1, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port140, port_range1, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port141, port_range1, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port142, port_range1, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port143, port_range1, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port144, port_range1, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(port145, port_range1, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(port146, port_range1, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(port147, port_range1, 23), + UNIPHIER_PINCTRL_GROUP_SINGLE(port180, port_range2, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port181, port_range2, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port182, port_range2, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port183, port_range2, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port184, port_range2, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port185, port_range2, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port186, port_range2, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port187, port_range2, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port200, port_range3, 0), + UNIPHIER_PINCTRL_GROUP_SINGLE(port201, port_range3, 1), + UNIPHIER_PINCTRL_GROUP_SINGLE(port202, port_range3, 2), + UNIPHIER_PINCTRL_GROUP_SINGLE(port203, port_range3, 3), + UNIPHIER_PINCTRL_GROUP_SINGLE(port204, port_range3, 4), + UNIPHIER_PINCTRL_GROUP_SINGLE(port205, port_range3, 5), + UNIPHIER_PINCTRL_GROUP_SINGLE(port206, port_range3, 6), + UNIPHIER_PINCTRL_GROUP_SINGLE(port207, port_range3, 7), + UNIPHIER_PINCTRL_GROUP_SINGLE(port210, port_range3, 8), + UNIPHIER_PINCTRL_GROUP_SINGLE(port211, port_range3, 9), + UNIPHIER_PINCTRL_GROUP_SINGLE(port212, port_range3, 10), + UNIPHIER_PINCTRL_GROUP_SINGLE(port213, port_range3, 11), + UNIPHIER_PINCTRL_GROUP_SINGLE(port214, port_range3, 12), + UNIPHIER_PINCTRL_GROUP_SINGLE(port215, port_range3, 13), + UNIPHIER_PINCTRL_GROUP_SINGLE(port216, port_range3, 14), + UNIPHIER_PINCTRL_GROUP_SINGLE(port217, port_range3, 15), + UNIPHIER_PINCTRL_GROUP_SINGLE(port220, port_range3, 16), + UNIPHIER_PINCTRL_GROUP_SINGLE(port221, port_range3, 17), + UNIPHIER_PINCTRL_GROUP_SINGLE(port222, port_range3, 18), + UNIPHIER_PINCTRL_GROUP_SINGLE(port223, port_range3, 19), + UNIPHIER_PINCTRL_GROUP_SINGLE(port224, port_range3, 20), + UNIPHIER_PINCTRL_GROUP_SINGLE(port225, port_range3, 21), + UNIPHIER_PINCTRL_GROUP_SINGLE(port226, port_range3, 22), + UNIPHIER_PINCTRL_GROUP_SINGLE(port227, port_range3, 23), + UNIPHIER_PINCTRL_GROUP_SINGLE(port230, port_range3, 24), + UNIPHIER_PINCTRL_GROUP_SINGLE(port231, port_range3, 25), + UNIPHIER_PINCTRL_GROUP_SINGLE(port232, port_range3, 26), + UNIPHIER_PINCTRL_GROUP_SINGLE(port233, port_range3, 27), + UNIPHIER_PINCTRL_GROUP_SINGLE(port234, port_range3, 28), + UNIPHIER_PINCTRL_GROUP_SINGLE(port235, port_range3, 29), + UNIPHIER_PINCTRL_GROUP_SINGLE(port236, port_range3, 30), + UNIPHIER_PINCTRL_GROUP_SINGLE(port237, port_range3, 31), + UNIPHIER_PINCTRL_GROUP_SINGLE(port240, port_range3, 32), + UNIPHIER_PINCTRL_GROUP_SINGLE(port241, port_range3, 33), + UNIPHIER_PINCTRL_GROUP_SINGLE(port242, port_range3, 34), + UNIPHIER_PINCTRL_GROUP_SINGLE(port243, port_range3, 35), + UNIPHIER_PINCTRL_GROUP_SINGLE(port244, port_range3, 36), + UNIPHIER_PINCTRL_GROUP_SINGLE(port245, port_range3, 37), + UNIPHIER_PINCTRL_GROUP_SINGLE(port246, port_range3, 38), + UNIPHIER_PINCTRL_GROUP_SINGLE(port247, port_range3, 39), + UNIPHIER_PINCTRL_GROUP_SINGLE(port250, port_range3, 40), + UNIPHIER_PINCTRL_GROUP_SINGLE(port251, port_range3, 41), + UNIPHIER_PINCTRL_GROUP_SINGLE(port252, port_range3, 42), + UNIPHIER_PINCTRL_GROUP_SINGLE(port253, port_range3, 43), + UNIPHIER_PINCTRL_GROUP_SINGLE(port254, port_range3, 44), UNIPHIER_PINCTRL_GROUP_SINGLE(xirq0, xirq, 0), UNIPHIER_PINCTRL_GROUP_SINGLE(xirq1, xirq, 1), UNIPHIER_PINCTRL_GROUP_SINGLE(xirq2, xirq, 2), diff --git a/drivers/pinctrl/zte/Kconfig b/drivers/pinctrl/zte/Kconfig new file mode 100644 index 000000000000..0d97352a24ec --- /dev/null +++ b/drivers/pinctrl/zte/Kconfig @@ -0,0 +1,13 @@ +config PINCTRL_ZX + bool + select PINMUX + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + +config PINCTRL_ZX296718 + bool "ZTE ZX296718 pinctrl driver" + depends on OF && ARCH_ZX + select PINCTRL_ZX + help + Say Y here to enable the ZX296718 pinctrl driver diff --git a/drivers/pinctrl/zte/Makefile b/drivers/pinctrl/zte/Makefile new file mode 100644 index 000000000000..c42e651d7a73 --- /dev/null +++ b/drivers/pinctrl/zte/Makefile @@ -0,0 +1,2 @@ +obj-$(CONFIG_PINCTRL_ZX) += pinctrl-zx.o +obj-$(CONFIG_PINCTRL_ZX296718) += pinctrl-zx296718.o diff --git a/drivers/pinctrl/zte/pinctrl-zx.c b/drivers/pinctrl/zte/pinctrl-zx.c new file mode 100644 index 000000000000..787e3967bd5c --- /dev/null +++ b/drivers/pinctrl/zte/pinctrl-zx.c @@ -0,0 +1,445 @@ +/* + * Copyright (C) 2017 Sanechips Technology Co., Ltd. + * Copyright 2017 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinconf-generic.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "../core.h" +#include "../pinctrl-utils.h" +#include "../pinmux.h" +#include "pinctrl-zx.h" + +#define ZX_PULL_DOWN BIT(0) +#define ZX_PULL_UP BIT(1) +#define ZX_INPUT_ENABLE BIT(3) +#define ZX_DS_SHIFT 4 +#define ZX_DS_MASK (0x7 << ZX_DS_SHIFT) +#define ZX_DS_VALUE(x) (((x) << ZX_DS_SHIFT) & ZX_DS_MASK) +#define ZX_SLEW BIT(8) + +struct zx_pinctrl { + struct pinctrl_dev *pctldev; + struct device *dev; + void __iomem *base; + void __iomem *aux_base; + spinlock_t lock; + struct zx_pinctrl_soc_info *info; +}; + +static int zx_dt_node_to_map(struct pinctrl_dev *pctldev, + struct device_node *np_config, + struct pinctrl_map **map, u32 *num_maps) +{ + return pinconf_generic_dt_node_to_map(pctldev, np_config, map, + num_maps, PIN_MAP_TYPE_INVALID); +} + +static const struct pinctrl_ops zx_pinctrl_ops = { + .dt_node_to_map = zx_dt_node_to_map, + .dt_free_map = pinctrl_utils_free_map, + .get_groups_count = pinctrl_generic_get_group_count, + .get_group_name = pinctrl_generic_get_group_name, + .get_group_pins = pinctrl_generic_get_group_pins, +}; + +#define NONAON_MVAL 2 + +static int zx_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, + unsigned int group_selector) +{ + struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev); + struct zx_pinctrl_soc_info *info = zpctl->info; + const struct pinctrl_pin_desc *pindesc = info->pins + group_selector; + struct zx_pin_data *data = pindesc->drv_data; + struct zx_mux_desc *mux = data->muxes; + u32 mask = (1 << data->width) - 1; + u32 offset = data->offset; + u32 bitpos = data->bitpos; + struct function_desc *func; + unsigned long flags; + u32 val, mval; + + /* Skip reserved pin */ + if (!data) + return -EINVAL; + + func = pinmux_generic_get_function(pctldev, func_selector); + if (!func) + return -EINVAL; + + while (mux->name) { + if (strcmp(mux->name, func->name) == 0) + break; + mux++; + } + + /* Found mux value to be written */ + mval = mux->muxval; + + spin_lock_irqsave(&zpctl->lock, flags); + + if (data->aon_pin) { + /* + * It's an AON pin, whose mux register offset and bit position + * can be caluculated from pin number. Each register covers 16 + * pins, and each pin occupies 2 bits. + */ + u16 aoffset = pindesc->number / 16 * 4; + u16 abitpos = (pindesc->number % 16) * 2; + + if (mval & AON_MUX_FLAG) { + /* + * This is a mux value that needs to be written into + * AON pinmux register. Write it and then we're done. + */ + val = readl(zpctl->aux_base + aoffset); + val &= ~(0x3 << abitpos); + val |= (mval & 0x3) << abitpos; + writel(val, zpctl->aux_base + aoffset); + } else { + /* + * It's a mux value that needs to be written into TOP + * pinmux register. + */ + val = readl(zpctl->base + offset); + val &= ~(mask << bitpos); + val |= (mval & mask) << bitpos; + writel(val, zpctl->base + offset); + + /* + * In this case, the AON pinmux register needs to be + * set up to select non-AON function. + */ + val = readl(zpctl->aux_base + aoffset); + val &= ~(0x3 << abitpos); + val |= NONAON_MVAL << abitpos; + writel(val, zpctl->aux_base + aoffset); + } + + } else { + /* + * This is a TOP pin, and we only need to set up TOP pinmux + * register and then we're done with it. + */ + val = readl(zpctl->base + offset); + val &= ~(mask << bitpos); + val |= (mval & mask) << bitpos; + writel(val, zpctl->base + offset); + } + + spin_unlock_irqrestore(&zpctl->lock, flags); + + return 0; +} + +static const struct pinmux_ops zx_pinmux_ops = { + .get_functions_count = pinmux_generic_get_function_count, + .get_function_name = pinmux_generic_get_function_name, + .get_function_groups = pinmux_generic_get_function_groups, + .set_mux = zx_set_mux, +}; + +static int zx_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *config) +{ + struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev); + struct zx_pinctrl_soc_info *info = zpctl->info; + const struct pinctrl_pin_desc *pindesc = info->pins + pin; + struct zx_pin_data *data = pindesc->drv_data; + enum pin_config_param param = pinconf_to_config_param(*config); + u32 val; + + /* Skip reserved pin */ + if (!data) + return -EINVAL; + + val = readl(zpctl->aux_base + data->coffset); + val = val >> data->cbitpos; + + switch (param) { + case PIN_CONFIG_BIAS_PULL_DOWN: + val &= ZX_PULL_DOWN; + val = !!val; + if (val == 0) + return -EINVAL; + break; + case PIN_CONFIG_BIAS_PULL_UP: + val &= ZX_PULL_UP; + val = !!val; + if (val == 0) + return -EINVAL; + break; + case PIN_CONFIG_INPUT_ENABLE: + val &= ZX_INPUT_ENABLE; + val = !!val; + if (val == 0) + return -EINVAL; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + val &= ZX_DS_MASK; + val = val >> ZX_DS_SHIFT; + break; + case PIN_CONFIG_SLEW_RATE: + val &= ZX_SLEW; + val = !!val; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, val); + + return 0; +} + +static int zx_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin, + unsigned long *configs, unsigned int num_configs) +{ + struct zx_pinctrl *zpctl = pinctrl_dev_get_drvdata(pctldev); + struct zx_pinctrl_soc_info *info = zpctl->info; + const struct pinctrl_pin_desc *pindesc = info->pins + pin; + struct zx_pin_data *data = pindesc->drv_data; + enum pin_config_param param; + u32 val, arg; + int i; + + /* Skip reserved pin */ + if (!data) + return -EINVAL; + + val = readl(zpctl->aux_base + data->coffset); + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_PULL_DOWN: + val |= ZX_PULL_DOWN << data->cbitpos; + break; + case PIN_CONFIG_BIAS_PULL_UP: + val |= ZX_PULL_UP << data->cbitpos; + break; + case PIN_CONFIG_INPUT_ENABLE: + val |= ZX_INPUT_ENABLE << data->cbitpos; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + val &= ~(ZX_DS_MASK << data->cbitpos); + val |= ZX_DS_VALUE(arg) << data->cbitpos; + break; + case PIN_CONFIG_SLEW_RATE: + if (arg) + val |= ZX_SLEW << data->cbitpos; + else + val &= ~ZX_SLEW << data->cbitpos; + break; + default: + return -ENOTSUPP; + } + } + + writel(val, zpctl->aux_base + data->coffset); + return 0; +} + +static const struct pinconf_ops zx_pinconf_ops = { + .pin_config_set = zx_pin_config_set, + .pin_config_get = zx_pin_config_get, + .is_generic = true, +}; + +static int zx_pinctrl_build_state(struct platform_device *pdev) +{ + struct zx_pinctrl *zpctl = platform_get_drvdata(pdev); + struct zx_pinctrl_soc_info *info = zpctl->info; + struct pinctrl_dev *pctldev = zpctl->pctldev; + struct function_desc *functions; + int nfunctions; + struct group_desc *groups; + int ngroups; + int i; + + /* Every single pin composes a group */ + ngroups = info->npins; + groups = devm_kzalloc(&pdev->dev, ngroups * sizeof(*groups), + GFP_KERNEL); + if (!groups) + return -ENOMEM; + + for (i = 0; i < ngroups; i++) { + const struct pinctrl_pin_desc *pindesc = info->pins + i; + struct group_desc *group = groups + i; + + group->name = pindesc->name; + group->pins = (int *) &pindesc->number; + group->num_pins = 1; + radix_tree_insert(&pctldev->pin_group_tree, i, group); + } + + pctldev->num_groups = ngroups; + + /* Build function list from pin mux functions */ + functions = devm_kzalloc(&pdev->dev, info->npins * sizeof(*functions), + GFP_KERNEL); + if (!functions) + return -ENOMEM; + + nfunctions = 0; + for (i = 0; i < info->npins; i++) { + const struct pinctrl_pin_desc *pindesc = info->pins + i; + struct zx_pin_data *data = pindesc->drv_data; + struct zx_mux_desc *mux; + + /* Reserved pins do not have a drv_data at all */ + if (!data) + continue; + + /* Loop over all muxes for the pin */ + mux = data->muxes; + while (mux->name) { + struct function_desc *func = functions; + + /* Search function list for given mux */ + while (func->name) { + if (strcmp(mux->name, func->name) == 0) { + /* Function exists */ + func->num_group_names++; + break; + } + func++; + } + + if (!func->name) { + /* New function */ + func->name = mux->name; + func->num_group_names = 1; + radix_tree_insert(&pctldev->pin_function_tree, + nfunctions++, func); + } + + mux++; + } + } + + pctldev->num_functions = nfunctions; + functions = krealloc(functions, nfunctions * sizeof(*functions), + GFP_KERNEL); + + /* Find pin groups for every single function */ + for (i = 0; i < info->npins; i++) { + const struct pinctrl_pin_desc *pindesc = info->pins + i; + struct zx_pin_data *data = pindesc->drv_data; + struct zx_mux_desc *mux; + + if (!data) + continue; + + mux = data->muxes; + while (mux->name) { + struct function_desc *func; + const char **group; + int j; + + /* Find function for given mux */ + for (j = 0; j < nfunctions; j++) + if (strcmp(functions[j].name, mux->name) == 0) + break; + + func = functions + j; + if (!func->group_names) { + func->group_names = devm_kzalloc(&pdev->dev, + func->num_group_names * + sizeof(*func->group_names), + GFP_KERNEL); + if (!func->group_names) + return -ENOMEM; + } + + group = func->group_names; + while (*group) + group++; + *group = pindesc->name; + + mux++; + } + } + + return 0; +} + +int zx_pinctrl_init(struct platform_device *pdev, + struct zx_pinctrl_soc_info *info) +{ + struct pinctrl_desc *pctldesc; + struct zx_pinctrl *zpctl; + struct device_node *np; + struct resource *res; + int ret; + + zpctl = devm_kzalloc(&pdev->dev, sizeof(*zpctl), GFP_KERNEL); + if (!zpctl) + return -ENOMEM; + + spin_lock_init(&zpctl->lock); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + zpctl->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(zpctl->base)) + return PTR_ERR(zpctl->base); + + np = of_parse_phandle(pdev->dev.of_node, "zte,auxiliary-controller", 0); + if (!np) { + dev_err(&pdev->dev, "failed to find auxiliary controller\n"); + return -ENODEV; + } + + zpctl->aux_base = of_iomap(np, 0); + if (!zpctl->aux_base) + return -ENOMEM; + + zpctl->dev = &pdev->dev; + zpctl->info = info; + + pctldesc = devm_kzalloc(&pdev->dev, sizeof(*pctldesc), GFP_KERNEL); + if (!pctldesc) + return -ENOMEM; + + pctldesc->name = dev_name(&pdev->dev); + pctldesc->owner = THIS_MODULE; + pctldesc->pins = info->pins; + pctldesc->npins = info->npins; + pctldesc->pctlops = &zx_pinctrl_ops; + pctldesc->pmxops = &zx_pinmux_ops; + pctldesc->confops = &zx_pinconf_ops; + + zpctl->pctldev = devm_pinctrl_register(&pdev->dev, pctldesc, zpctl); + if (IS_ERR(zpctl->pctldev)) { + ret = PTR_ERR(zpctl->pctldev); + dev_err(&pdev->dev, "failed to register pinctrl: %d\n", ret); + return ret; + } + + platform_set_drvdata(pdev, zpctl); + + ret = zx_pinctrl_build_state(pdev); + if (ret) { + dev_err(&pdev->dev, "failed to build state: %d\n", ret); + return ret; + } + + dev_info(&pdev->dev, "initialized pinctrl driver\n"); + return 0; +} diff --git a/drivers/pinctrl/zte/pinctrl-zx.h b/drivers/pinctrl/zte/pinctrl-zx.h new file mode 100644 index 000000000000..bc67e2be0503 --- /dev/null +++ b/drivers/pinctrl/zte/pinctrl-zx.h @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2017 Sanechips Technology Co., Ltd. + * Copyright 2017 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __PINCTRL_ZX_H +#define __PINCTRL_ZX_H + +/** + * struct zx_mux_desc - hardware mux descriptor + * @name: mux function name + * @muxval: mux register bit value + */ +struct zx_mux_desc { + const char *name; + u8 muxval; +}; + +/** + * struct zx_pin_data - hardware per-pin data + * @aon_pin: whether it's an AON pin + * @offset: register offset within TOP pinmux controller + * @bitpos: bit position within TOP pinmux register + * @width: bit width within TOP pinmux register + * @coffset: pinconf register offset within AON controller + * @cbitpos: pinconf bit position within AON register + * @muxes: available mux function names and corresponding register values + * + * Unlike TOP pinmux and AON pinconf registers which are arranged pretty + * arbitrarily, AON pinmux register bits are well organized per pin id, and + * each pin occupies two bits, so that we can calculate the AON register offset + * and bit position from pin id. Thus, we only need to define TOP pinmux and + * AON pinconf register data for the pin. + */ +struct zx_pin_data { + bool aon_pin; + u16 offset; + u16 bitpos; + u16 width; + u16 coffset; + u16 cbitpos; + struct zx_mux_desc *muxes; +}; + +struct zx_pinctrl_soc_info { + const struct pinctrl_pin_desc *pins; + unsigned int npins; +}; + +#define TOP_PIN(pin, off, bp, wd, coff, cbp, ...) { \ + .number = pin, \ + .name = #pin, \ + .drv_data = &(struct zx_pin_data) { \ + .aon_pin = false, \ + .offset = off, \ + .bitpos = bp, \ + .width = wd, \ + .coffset = coff, \ + .cbitpos = cbp, \ + .muxes = (struct zx_mux_desc[]) { \ + __VA_ARGS__, { } }, \ + }, \ +} + +#define AON_PIN(pin, off, bp, wd, coff, cbp, ...) { \ + .number = pin, \ + .name = #pin, \ + .drv_data = &(struct zx_pin_data) { \ + .aon_pin = true, \ + .offset = off, \ + .bitpos = bp, \ + .width = wd, \ + .coffset = coff, \ + .cbitpos = cbp, \ + .muxes = (struct zx_mux_desc[]) { \ + __VA_ARGS__, { } }, \ + }, \ +} + +#define ZX_RESERVED(pin) PINCTRL_PIN(pin, #pin) + +#define TOP_MUX(_val, _name) { \ + .name = _name, \ + .muxval = _val, \ +} + +/* + * When the flag is set, it's a mux configuration for an AON pin that sits in + * AON register. Otherwise, it's one for AON pin but sitting in TOP register. + */ +#define AON_MUX_FLAG BIT(7) + +#define AON_MUX(_val, _name) { \ + .name = _name, \ + .muxval = _val | AON_MUX_FLAG, \ +} + +int zx_pinctrl_init(struct platform_device *pdev, + struct zx_pinctrl_soc_info *info); + +#endif /* __PINCTRL_ZX_H */ diff --git a/drivers/pinctrl/zte/pinctrl-zx296718.c b/drivers/pinctrl/zte/pinctrl-zx296718.c new file mode 100644 index 000000000000..71efec17ee7e --- /dev/null +++ b/drivers/pinctrl/zte/pinctrl-zx296718.c @@ -0,0 +1,1027 @@ +/* + * Copyright (C) 2017 Sanechips Technology Co., Ltd. + * Copyright 2017 Linaro Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/platform_device.h> + +#include "pinctrl-zx.h" + +#define TOP_REG0 0x00 +#define TOP_REG1 0x04 +#define TOP_REG2 0x08 +#define TOP_REG3 0x0c +#define TOP_REG4 0x10 +#define TOP_REG5 0x14 +#define TOP_REG6 0x18 +#define TOP_REG7 0x1c +#define TOP_REG8 0x20 + +/* + * The pin numbering starts from AON pins with reserved ones included, + * so that register data like offset and bit position for AON pins can + * be calculated from pin number. + */ +enum zx296718_pin { + /* aon_pmm_reg_0 */ + I2C3_SCL = 0, + I2C3_SDA = 1, + AON_RESERVED0 = 2, + AON_RESERVED1 = 3, + SEC_EN = 4, + UART0_RXD = 5, + UART0_TXD = 6, + IR_IN = 7, + SPI0_CLK = 8, + SPI0_CS = 9, + SPI0_TXD = 10, + SPI0_RXD = 11, + KEY_COL0 = 12, + KEY_COL1 = 13, + KEY_COL2 = 14, + KEY_ROW0 = 15, + + /* aon_pmm_reg_1 */ + KEY_ROW1 = 16, + KEY_ROW2 = 17, + HDMI_SCL = 18, + HDMI_SDA = 19, + JTAG_TCK = 20, + JTAG_TRSTN = 21, + JTAG_TMS = 22, + JTAG_TDI = 23, + JTAG_TDO = 24, + I2C0_SCL = 25, + I2C0_SDA = 26, + I2C1_SCL = 27, + I2C1_SDA = 28, + AON_RESERVED2 = 29, + AON_RESERVED3 = 30, + AON_RESERVED4 = 31, + + /* aon_pmm_reg_2 */ + SPI1_CLK = 32, + SPI1_CS = 33, + SPI1_TXD = 34, + SPI1_RXD = 35, + AON_RESERVED5 = 36, + AON_RESERVED6 = 37, + AUDIO_DET = 38, + SPDIF_OUT = 39, + HDMI_CEC = 40, + HDMI_HPD = 41, + GMAC_25M_OUT = 42, + BOOT_SEL0 = 43, + BOOT_SEL1 = 44, + BOOT_SEL2 = 45, + DEEP_SLEEP_OUT_N = 46, + AON_RESERVED7 = 47, + + /* top_pmm_reg_0 */ + GMII_GTX_CLK = 48, + GMII_TX_CLK = 49, + GMII_TXD0 = 50, + GMII_TXD1 = 51, + GMII_TXD2 = 52, + GMII_TXD3 = 53, + GMII_TXD4 = 54, + GMII_TXD5 = 55, + GMII_TXD6 = 56, + GMII_TXD7 = 57, + GMII_TX_ER = 58, + GMII_TX_EN = 59, + GMII_RX_CLK = 60, + GMII_RXD0 = 61, + GMII_RXD1 = 62, + GMII_RXD2 = 63, + + /* top_pmm_reg_1 */ + GMII_RXD3 = 64, + GMII_RXD4 = 65, + GMII_RXD5 = 66, + GMII_RXD6 = 67, + GMII_RXD7 = 68, + GMII_RX_ER = 69, + GMII_RX_DV = 70, + GMII_COL = 71, + GMII_CRS = 72, + GMII_MDC = 73, + GMII_MDIO = 74, + SDIO1_CLK = 75, + SDIO1_CMD = 76, + SDIO1_DATA0 = 77, + SDIO1_DATA1 = 78, + SDIO1_DATA2 = 79, + + /* top_pmm_reg_2 */ + SDIO1_DATA3 = 80, + SDIO1_CD = 81, + SDIO1_WP = 82, + USIM1_CD = 83, + USIM1_CLK = 84, + USIM1_RST = 85, + + /* top_pmm_reg_3 */ + USIM1_DATA = 86, + SDIO0_CLK = 87, + SDIO0_CMD = 88, + SDIO0_DATA0 = 89, + SDIO0_DATA1 = 90, + SDIO0_DATA2 = 91, + SDIO0_DATA3 = 92, + SDIO0_CD = 93, + SDIO0_WP = 94, + + /* top_pmm_reg_4 */ + TSI0_DATA0 = 95, + SPINOR_CLK = 96, + TSI2_DATA = 97, + TSI2_CLK = 98, + TSI2_SYNC = 99, + TSI2_VALID = 100, + SPINOR_CS = 101, + SPINOR_DQ0 = 102, + SPINOR_DQ1 = 103, + SPINOR_DQ2 = 104, + SPINOR_DQ3 = 105, + VGA_HS = 106, + VGA_VS = 107, + TSI3_DATA = 108, + + /* top_pmm_reg_5 */ + TSI3_CLK = 109, + TSI3_SYNC = 110, + TSI3_VALID = 111, + I2S1_WS = 112, + I2S1_BCLK = 113, + I2S1_MCLK = 114, + I2S1_DIN0 = 115, + I2S1_DOUT0 = 116, + SPI3_CLK = 117, + SPI3_CS = 118, + SPI3_TXD = 119, + NAND_LDO_MS18_SEL = 120, + + /* top_pmm_reg_6 */ + SPI3_RXD = 121, + I2S0_MCLK = 122, + I2S0_BCLK = 123, + I2S0_WS = 124, + I2S0_DIN0 = 125, + I2S0_DOUT0 = 126, + I2C5_SCL = 127, + I2C5_SDA = 128, + SPI2_CLK = 129, + SPI2_CS = 130, + SPI2_TXD = 131, + + /* top_pmm_reg_7 */ + SPI2_RXD = 132, + NAND_WP_N = 133, + NAND_PAGE_SIZE0 = 134, + NAND_PAGE_SIZE1 = 135, + NAND_ADDR_CYCLE = 136, + NAND_RB0 = 137, + NAND_RB1 = 138, + NAND_RB2 = 139, + NAND_RB3 = 140, + + /* top_pmm_reg_8 */ + GMAC_125M_IN = 141, + GMAC_50M_OUT = 142, + SPINOR_SSCLK_LOOPBACK = 143, + SPINOR_SDIO1CLK_LOOPBACK = 144, +}; + +static const struct pinctrl_pin_desc zx296718_pins[] = { + /* aon_pmm_reg_0 */ + AON_PIN(I2C3_SCL, TOP_REG2, 18, 2, 0x48, 0, + AON_MUX(0x0, "ANMI"), /* anmi */ + AON_MUX(0x1, "AGPIO"), /* agpio29 */ + AON_MUX(0x2, "nonAON"), /* pin0 */ + AON_MUX(0x3, "EXT_INT"), /* int4 */ + TOP_MUX(0x0, "I2C3"), /* scl */ + TOP_MUX(0x1, "SPI2"), /* txd */ + TOP_MUX(0x2, "I2S1")), /* din0 */ + AON_PIN(I2C3_SDA, TOP_REG2, 20, 2, 0x48, 9, + AON_MUX(0x0, "WD"), /* rst_b */ + AON_MUX(0x1, "AGPIO"), /* agpio30 */ + AON_MUX(0x2, "nonAON"), /* pin1 */ + AON_MUX(0x3, "EXT_INT"), /* int5 */ + TOP_MUX(0x0, "I2C3"), /* sda */ + TOP_MUX(0x1, "SPI2"), /* rxd */ + TOP_MUX(0x2, "I2S0")), /* mclk */ + ZX_RESERVED(AON_RESERVED0), + ZX_RESERVED(AON_RESERVED1), + AON_PIN(SEC_EN, TOP_REG3, 5, 1, 0x50, 0, + AON_MUX(0x0, "SEC"), /* en */ + AON_MUX(0x1, "AGPIO"), /* agpio28 */ + AON_MUX(0x2, "nonAON"), /* pin3 */ + AON_MUX(0x3, "EXT_INT"), /* int7 */ + TOP_MUX(0x0, "I2C2"), /* sda */ + TOP_MUX(0x1, "SPI2")), /* cs */ + AON_PIN(UART0_RXD, 0, 0, 0, 0x50, 9, + AON_MUX(0x0, "UART0"), /* rxd */ + AON_MUX(0x1, "AGPIO"), /* agpio20 */ + AON_MUX(0x2, "nonAON")), /* pin34 */ + AON_PIN(UART0_TXD, 0, 0, 0, 0x50, 18, + AON_MUX(0x0, "UART0"), /* txd */ + AON_MUX(0x1, "AGPIO"), /* agpio21 */ + AON_MUX(0x2, "nonAON")), /* pin32 */ + AON_PIN(IR_IN, 0, 0, 0, 0x64, 0, + AON_MUX(0x0, "IR"), /* in */ + AON_MUX(0x1, "AGPIO"), /* agpio0 */ + AON_MUX(0x2, "nonAON")), /* pin27 */ + AON_PIN(SPI0_CLK, TOP_REG3, 16, 1, 0x64, 9, + AON_MUX(0x0, "EXT_INT"), /* int0 */ + AON_MUX(0x1, "AGPIO"), /* agpio23 */ + AON_MUX(0x2, "nonAON"), /* pin5 */ + AON_MUX(0x3, "PCU"), /* test6 */ + TOP_MUX(0x0, "SPI0"), /* clk */ + TOP_MUX(0x1, "ISP")), /* flash_trig */ + AON_PIN(SPI0_CS, TOP_REG3, 17, 1, 0x64, 18, + AON_MUX(0x0, "EXT_INT"), /* int1 */ + AON_MUX(0x1, "AGPIO"), /* agpio24 */ + AON_MUX(0x2, "nonAON"), /* pin6 */ + AON_MUX(0x3, "PCU"), /* test0 */ + TOP_MUX(0x0, "SPI0"), /* cs */ + TOP_MUX(0x1, "ISP")), /* prelight_trig */ + AON_PIN(SPI0_TXD, TOP_REG3, 18, 1, 0x68, 0, + AON_MUX(0x0, "EXT_INT"), /* int2 */ + AON_MUX(0x1, "AGPIO"), /* agpio25 */ + AON_MUX(0x2, "nonAON"), /* pin7 */ + AON_MUX(0x3, "PCU"), /* test1 */ + TOP_MUX(0x0, "SPI0"), /* txd */ + TOP_MUX(0x1, "ISP")), /* shutter_trig */ + AON_PIN(SPI0_RXD, TOP_REG3, 19, 1, 0x68, 9, + AON_MUX(0x0, "EXT_INT"), /* int3 */ + AON_MUX(0x1, "AGPIO"), /* agpio26 */ + AON_MUX(0x2, "nonAON"), /* pin8 */ + AON_MUX(0x3, "PCU"), /* test2 */ + TOP_MUX(0x0, "SPI0"), /* rxd */ + TOP_MUX(0x1, "ISP")), /* shutter_open */ + AON_PIN(KEY_COL0, TOP_REG3, 20, 1, 0x68, 18, + AON_MUX(0x0, "KEY"), /* col0 */ + AON_MUX(0x1, "AGPIO"), /* agpio5 */ + AON_MUX(0x2, "nonAON"), /* pin9 */ + AON_MUX(0x3, "PCU"), /* test3 */ + TOP_MUX(0x0, "UART3"), /* rxd */ + TOP_MUX(0x1, "I2S0")), /* din1 */ + AON_PIN(KEY_COL1, TOP_REG3, 21, 2, 0x6c, 0, + AON_MUX(0x0, "KEY"), /* col1 */ + AON_MUX(0x1, "AGPIO"), /* agpio6 */ + AON_MUX(0x2, "nonAON"), /* pin10 */ + TOP_MUX(0x0, "UART3"), /* txd */ + TOP_MUX(0x1, "I2S0"), /* din2 */ + TOP_MUX(0x2, "VGA")), /* scl */ + AON_PIN(KEY_COL2, TOP_REG3, 23, 2, 0x6c, 9, + AON_MUX(0x0, "KEY"), /* col2 */ + AON_MUX(0x1, "AGPIO"), /* agpio7 */ + AON_MUX(0x2, "nonAON"), /* pin11 */ + TOP_MUX(0x0, "PWM"), /* out1 */ + TOP_MUX(0x1, "I2S0"), /* din3 */ + TOP_MUX(0x2, "VGA")), /* sda */ + AON_PIN(KEY_ROW0, 0, 0, 0, 0x6c, 18, + AON_MUX(0x0, "KEY"), /* row0 */ + AON_MUX(0x1, "AGPIO"), /* agpio8 */ + AON_MUX(0x2, "nonAON"), /* pin33 */ + AON_MUX(0x3, "WD")), /* rst_b */ + + /* aon_pmm_reg_1 */ + AON_PIN(KEY_ROW1, TOP_REG3, 25, 2, 0x70, 0, + AON_MUX(0x0, "KEY"), /* row1 */ + AON_MUX(0x1, "AGPIO"), /* agpio9 */ + AON_MUX(0x2, "nonAON"), /* pin12 */ + TOP_MUX(0x0, "LCD"), /* port0 lcd_te */ + TOP_MUX(0x1, "I2S0"), /* dout2 */ + TOP_MUX(0x2, "PWM"), /* out2 */ + TOP_MUX(0x3, "VGA")), /* hs1 */ + AON_PIN(KEY_ROW2, TOP_REG3, 27, 2, 0x70, 9, + AON_MUX(0x0, "KEY"), /* row2 */ + AON_MUX(0x1, "AGPIO"), /* agpio10 */ + AON_MUX(0x2, "nonAON"), /* pin13 */ + TOP_MUX(0x0, "LCD"), /* port1 lcd_te */ + TOP_MUX(0x1, "I2S0"), /* dout3 */ + TOP_MUX(0x2, "PWM"), /* out3 */ + TOP_MUX(0x3, "VGA")), /* vs1 */ + AON_PIN(HDMI_SCL, TOP_REG3, 29, 1, 0x70, 18, + AON_MUX(0x0, "PCU"), /* test7 */ + AON_MUX(0x1, "AGPIO"), /* agpio3 */ + AON_MUX(0x2, "nonAON"), /* pin14 */ + TOP_MUX(0x0, "HDMI"), /* scl */ + TOP_MUX(0x1, "UART3")), /* rxd */ + AON_PIN(HDMI_SDA, TOP_REG3, 30, 1, 0x74, 0, + AON_MUX(0x0, "PCU"), /* test8 */ + AON_MUX(0x1, "AGPIO"), /* agpio4 */ + AON_MUX(0x2, "nonAON"), /* pin15 */ + TOP_MUX(0x0, "HDMI"), /* sda */ + TOP_MUX(0x1, "UART3")), /* txd */ + AON_PIN(JTAG_TCK, TOP_REG7, 3, 1, 0x78, 18, + AON_MUX(0x0, "JTAG"), /* tck */ + AON_MUX(0x1, "AGPIO"), /* agpio11 */ + AON_MUX(0x2, "nonAON"), /* pin22 */ + AON_MUX(0x3, "EXT_INT"), /* int4 */ + TOP_MUX(0x0, "SPI4"), /* clk */ + TOP_MUX(0x1, "UART1")), /* rxd */ + AON_PIN(JTAG_TRSTN, TOP_REG7, 4, 1, 0xac, 0, + AON_MUX(0x0, "JTAG"), /* trstn */ + AON_MUX(0x1, "AGPIO"), /* agpio12 */ + AON_MUX(0x2, "nonAON"), /* pin23 */ + AON_MUX(0x3, "EXT_INT"), /* int5 */ + TOP_MUX(0x0, "SPI4"), /* cs */ + TOP_MUX(0x1, "UART1")), /* txd */ + AON_PIN(JTAG_TMS, TOP_REG7, 5, 1, 0xac, 9, + AON_MUX(0x0, "JTAG"), /* tms */ + AON_MUX(0x1, "AGPIO"), /* agpio13 */ + AON_MUX(0x2, "nonAON"), /* pin24 */ + AON_MUX(0x3, "EXT_INT"), /* int6 */ + TOP_MUX(0x0, "SPI4"), /* txd */ + TOP_MUX(0x1, "UART2")), /* rxd */ + AON_PIN(JTAG_TDI, TOP_REG7, 6, 1, 0xac, 18, + AON_MUX(0x0, "JTAG"), /* tdi */ + AON_MUX(0x1, "AGPIO"), /* agpio14 */ + AON_MUX(0x2, "nonAON"), /* pin25 */ + AON_MUX(0x3, "EXT_INT"), /* int7 */ + TOP_MUX(0x0, "SPI4"), /* rxd */ + TOP_MUX(0x1, "UART2")), /* txd */ + AON_PIN(JTAG_TDO, 0, 0, 0, 0xb0, 0, + AON_MUX(0x0, "JTAG"), /* tdo */ + AON_MUX(0x1, "AGPIO"), /* agpio15 */ + AON_MUX(0x2, "nonAON")), /* pin26 */ + AON_PIN(I2C0_SCL, 0, 0, 0, 0xb0, 9, + AON_MUX(0x0, "I2C0"), /* scl */ + AON_MUX(0x1, "AGPIO"), /* agpio16 */ + AON_MUX(0x2, "nonAON")), /* pin28 */ + AON_PIN(I2C0_SDA, 0, 0, 0, 0xb0, 18, + AON_MUX(0x0, "I2C0"), /* sda */ + AON_MUX(0x1, "AGPIO"), /* agpio17 */ + AON_MUX(0x2, "nonAON")), /* pin29 */ + AON_PIN(I2C1_SCL, TOP_REG8, 4, 1, 0xb4, 0, + AON_MUX(0x0, "I2C1"), /* scl */ + AON_MUX(0x1, "AGPIO"), /* agpio18 */ + AON_MUX(0x2, "nonAON"), /* pin30 */ + TOP_MUX(0x0, "LCD")), /* port0 lcd_te */ + AON_PIN(I2C1_SDA, TOP_REG8, 5, 1, 0xb4, 9, + AON_MUX(0x0, "I2C1"), /* sda */ + AON_MUX(0x1, "AGPIO"), /* agpio19 */ + AON_MUX(0x2, "nonAON"), /* pin31 */ + TOP_MUX(0x0, "LCD")), /* port1 lcd_te */ + ZX_RESERVED(AON_RESERVED2), + ZX_RESERVED(AON_RESERVED3), + ZX_RESERVED(AON_RESERVED4), + + /* aon_pmm_reg_2 */ + AON_PIN(SPI1_CLK, TOP_REG2, 6, 3, 0x40, 9, + AON_MUX(0x0, "EXT_INT"), /* int0 */ + AON_MUX(0x1, "PCU"), /* test12 */ + AON_MUX(0x2, "nonAON"), /* pin39 */ + TOP_MUX(0x0, "SPI1"), /* clk */ + TOP_MUX(0x1, "PCM"), /* clk */ + TOP_MUX(0x2, "BGPIO"), /* gpio35 */ + TOP_MUX(0x3, "I2C4"), /* scl */ + TOP_MUX(0x4, "I2S1"), /* mclk */ + TOP_MUX(0x5, "ISP")), /* flash_trig */ + AON_PIN(SPI1_CS, TOP_REG2, 9, 3, 0x40, 18, + AON_MUX(0x0, "EXT_INT"), /* int1 */ + AON_MUX(0x1, "PCU"), /* test13 */ + AON_MUX(0x2, "nonAON"), /* pin40 */ + TOP_MUX(0x0, "SPI1"), /* cs */ + TOP_MUX(0x1, "PCM"), /* fs */ + TOP_MUX(0x2, "BGPIO"), /* gpio36 */ + TOP_MUX(0x3, "I2C4"), /* sda */ + TOP_MUX(0x4, "I2S1"), /* bclk */ + TOP_MUX(0x5, "ISP")), /* prelight_trig */ + AON_PIN(SPI1_TXD, TOP_REG2, 12, 3, 0x44, 0, + AON_MUX(0x0, "EXT_INT"), /* int2 */ + AON_MUX(0x1, "PCU"), /* test14 */ + AON_MUX(0x2, "nonAON"), /* pin41 */ + TOP_MUX(0x0, "SPI1"), /* txd */ + TOP_MUX(0x1, "PCM"), /* txd */ + TOP_MUX(0x2, "BGPIO"), /* gpio37 */ + TOP_MUX(0x3, "UART5"), /* rxd */ + TOP_MUX(0x4, "I2S1"), /* ws */ + TOP_MUX(0x5, "ISP")), /* shutter_trig */ + AON_PIN(SPI1_RXD, TOP_REG2, 15, 3, 0x44, 9, + AON_MUX(0x0, "EXT_INT"), /* int3 */ + AON_MUX(0x1, "PCU"), /* test15 */ + AON_MUX(0x2, "nonAON"), /* pin42 */ + TOP_MUX(0x0, "SPI1"), /* rxd */ + TOP_MUX(0x1, "PCM"), /* rxd */ + TOP_MUX(0x2, "BGPIO"), /* gpio38 */ + TOP_MUX(0x3, "UART5"), /* txd */ + TOP_MUX(0x4, "I2S1"), /* dout0 */ + TOP_MUX(0x5, "ISP")), /* shutter_open */ + ZX_RESERVED(AON_RESERVED5), + ZX_RESERVED(AON_RESERVED6), + AON_PIN(AUDIO_DET, TOP_REG3, 3, 2, 0x48, 18, + AON_MUX(0x0, "PCU"), /* test4 */ + AON_MUX(0x1, "AGPIO"), /* agpio27 */ + AON_MUX(0x2, "nonAON"), /* pin2 */ + AON_MUX(0x3, "EXT_INT"), /* int16 */ + TOP_MUX(0x0, "AUDIO"), /* detect */ + TOP_MUX(0x1, "I2C2"), /* scl */ + TOP_MUX(0x2, "SPI2")), /* clk */ + AON_PIN(SPDIF_OUT, TOP_REG3, 14, 2, 0x78, 9, + AON_MUX(0x0, "PCU"), /* test5 */ + AON_MUX(0x1, "AGPIO"), /* agpio22 */ + AON_MUX(0x2, "nonAON"), /* pin4 */ + TOP_MUX(0x0, "SPDIF"), /* out */ + TOP_MUX(0x1, "PWM"), /* out0 */ + TOP_MUX(0x2, "ISP")), /* fl_trig */ + AON_PIN(HDMI_CEC, 0, 0, 0, 0x74, 9, + AON_MUX(0x0, "PCU"), /* test9 */ + AON_MUX(0x1, "AGPIO"), /* agpio1 */ + AON_MUX(0x2, "nonAON")), /* pin16 */ + AON_PIN(HDMI_HPD, 0, 0, 0, 0x74, 18, + AON_MUX(0x0, "PCU"), /* test10 */ + AON_MUX(0x1, "AGPIO"), /* agpio2 */ + AON_MUX(0x2, "nonAON")), /* pin17 */ + AON_PIN(GMAC_25M_OUT, 0, 0, 0, 0x78, 0, + AON_MUX(0x0, "PCU"), /* test11 */ + AON_MUX(0x1, "AGPIO"), /* agpio31 */ + AON_MUX(0x2, "nonAON")), /* pin43 */ + AON_PIN(BOOT_SEL0, 0, 0, 0, 0xc0, 9, + AON_MUX(0x0, "BOOT"), /* sel0 */ + AON_MUX(0x1, "AGPIO"), /* agpio18 */ + AON_MUX(0x2, "nonAON")), /* pin18 */ + AON_PIN(BOOT_SEL1, 0, 0, 0, 0xc0, 18, + AON_MUX(0x0, "BOOT"), /* sel1 */ + AON_MUX(0x1, "AGPIO"), /* agpio19 */ + AON_MUX(0x2, "nonAON")), /* pin19 */ + AON_PIN(BOOT_SEL2, 0, 0, 0, 0xc4, 0, + AON_MUX(0x0, "BOOT"), /* sel2 */ + AON_MUX(0x1, "AGPIO"), /* agpio20 */ + AON_MUX(0x2, "nonAON")), /* pin20 */ + AON_PIN(DEEP_SLEEP_OUT_N, 0, 0, 0, 0xc4, 9, + AON_MUX(0x0, "DEEPSLP"), /* deep sleep out_n */ + AON_MUX(0x1, "AGPIO"), /* agpio21 */ + AON_MUX(0x2, "nonAON")), /* pin21 */ + ZX_RESERVED(AON_RESERVED7), + + /* top_pmm_reg_0 */ + TOP_PIN(GMII_GTX_CLK, TOP_REG0, 0, 2, 0x10, 0, + TOP_MUX(0x0, "GMII"), /* gtx_clk */ + TOP_MUX(0x1, "DVI0"), /* clk */ + TOP_MUX(0x2, "BGPIO")), /* gpio0 */ + TOP_PIN(GMII_TX_CLK, TOP_REG0, 2, 2, 0x10, 9, + TOP_MUX(0x0, "GMII"), /* tx_clk */ + TOP_MUX(0x1, "DVI0"), /* vs */ + TOP_MUX(0x2, "BGPIO")), /* gpio1 */ + TOP_PIN(GMII_TXD0, TOP_REG0, 4, 2, 0x10, 18, + TOP_MUX(0x0, "GMII"), /* txd0 */ + TOP_MUX(0x1, "DVI0"), /* hs */ + TOP_MUX(0x2, "BGPIO")), /* gpio2 */ + TOP_PIN(GMII_TXD1, TOP_REG0, 6, 2, 0x14, 0, + TOP_MUX(0x0, "GMII"), /* txd1 */ + TOP_MUX(0x1, "DVI0"), /* d0 */ + TOP_MUX(0x2, "BGPIO")), /* gpio3 */ + TOP_PIN(GMII_TXD2, TOP_REG0, 8, 2, 0x14, 9, + TOP_MUX(0x0, "GMII"), /* txd2 */ + TOP_MUX(0x1, "DVI0"), /* d1 */ + TOP_MUX(0x2, "BGPIO")), /* gpio4 */ + TOP_PIN(GMII_TXD3, TOP_REG0, 10, 2, 0x14, 18, + TOP_MUX(0x0, "GMII"), /* txd3 */ + TOP_MUX(0x1, "DVI0"), /* d2 */ + TOP_MUX(0x2, "BGPIO")), /* gpio5 */ + TOP_PIN(GMII_TXD4, TOP_REG0, 12, 2, 0x18, 0, + TOP_MUX(0x0, "GMII"), /* txd4 */ + TOP_MUX(0x1, "DVI0"), /* d3 */ + TOP_MUX(0x2, "BGPIO")), /* gpio6 */ + TOP_PIN(GMII_TXD5, TOP_REG0, 14, 2, 0x18, 9, + TOP_MUX(0x0, "GMII"), /* txd5 */ + TOP_MUX(0x1, "DVI0"), /* d4 */ + TOP_MUX(0x2, "BGPIO")), /* gpio7 */ + TOP_PIN(GMII_TXD6, TOP_REG0, 16, 2, 0x18, 18, + TOP_MUX(0x0, "GMII"), /* txd6 */ + TOP_MUX(0x1, "DVI0"), /* d5 */ + TOP_MUX(0x2, "BGPIO")), /* gpio8 */ + TOP_PIN(GMII_TXD7, TOP_REG0, 18, 2, 0x1c, 0, + TOP_MUX(0x0, "GMII"), /* txd7 */ + TOP_MUX(0x1, "DVI0"), /* d6 */ + TOP_MUX(0x2, "BGPIO")), /* gpio9 */ + TOP_PIN(GMII_TX_ER, TOP_REG0, 20, 2, 0x1c, 9, + TOP_MUX(0x0, "GMII"), /* tx_er */ + TOP_MUX(0x1, "DVI0"), /* d7 */ + TOP_MUX(0x2, "BGPIO")), /* gpio10 */ + TOP_PIN(GMII_TX_EN, TOP_REG0, 22, 2, 0x1c, 18, + TOP_MUX(0x0, "GMII"), /* tx_en */ + TOP_MUX(0x1, "DVI0"), /* d8 */ + TOP_MUX(0x3, "BGPIO")), /* gpio11 */ + TOP_PIN(GMII_RX_CLK, TOP_REG0, 24, 2, 0x20, 0, + TOP_MUX(0x0, "GMII"), /* rx_clk */ + TOP_MUX(0x1, "DVI0"), /* d9 */ + TOP_MUX(0x3, "BGPIO")), /* gpio12 */ + TOP_PIN(GMII_RXD0, TOP_REG0, 26, 2, 0x20, 9, + TOP_MUX(0x0, "GMII"), /* rxd0 */ + TOP_MUX(0x1, "DVI0"), /* d10 */ + TOP_MUX(0x3, "BGPIO")), /* gpio13 */ + TOP_PIN(GMII_RXD1, TOP_REG0, 28, 2, 0x20, 18, + TOP_MUX(0x0, "GMII"), /* rxd1 */ + TOP_MUX(0x1, "DVI0"), /* d11 */ + TOP_MUX(0x2, "BGPIO")), /* gpio14 */ + TOP_PIN(GMII_RXD2, TOP_REG0, 30, 2, 0x24, 0, + TOP_MUX(0x0, "GMII"), /* rxd2 */ + TOP_MUX(0x1, "DVI1"), /* clk */ + TOP_MUX(0x2, "BGPIO")), /* gpio15 */ + + /* top_pmm_reg_1 */ + TOP_PIN(GMII_RXD3, TOP_REG1, 0, 2, 0x24, 9, + TOP_MUX(0x0, "GMII"), /* rxd3 */ + TOP_MUX(0x1, "DVI1"), /* hs */ + TOP_MUX(0x2, "BGPIO")), /* gpio16 */ + TOP_PIN(GMII_RXD4, TOP_REG1, 2, 2, 0x24, 18, + TOP_MUX(0x0, "GMII"), /* rxd4 */ + TOP_MUX(0x1, "DVI1"), /* vs */ + TOP_MUX(0x2, "BGPIO")), /* gpio17 */ + TOP_PIN(GMII_RXD5, TOP_REG1, 4, 2, 0x28, 0, + TOP_MUX(0x0, "GMII"), /* rxd5 */ + TOP_MUX(0x1, "DVI1"), /* d0 */ + TOP_MUX(0x2, "BGPIO"), /* gpio18 */ + TOP_MUX(0x3, "TSI0")), /* dat0 */ + TOP_PIN(GMII_RXD6, TOP_REG1, 6, 2, 0x28, 9, + TOP_MUX(0x0, "GMII"), /* rxd6 */ + TOP_MUX(0x1, "DVI1"), /* d1 */ + TOP_MUX(0x2, "BGPIO"), /* gpio19 */ + TOP_MUX(0x3, "TSI0")), /* clk */ + TOP_PIN(GMII_RXD7, TOP_REG1, 8, 2, 0x28, 18, + TOP_MUX(0x0, "GMII"), /* rxd7 */ + TOP_MUX(0x1, "DVI1"), /* d2 */ + TOP_MUX(0x2, "BGPIO"), /* gpio20 */ + TOP_MUX(0x3, "TSI0")), /* sync */ + TOP_PIN(GMII_RX_ER, TOP_REG1, 10, 2, 0x2c, 0, + TOP_MUX(0x0, "GMII"), /* rx_er */ + TOP_MUX(0x1, "DVI1"), /* d3 */ + TOP_MUX(0x2, "BGPIO"), /* gpio21 */ + TOP_MUX(0x3, "TSI0")), /* valid */ + TOP_PIN(GMII_RX_DV, TOP_REG1, 12, 2, 0x2c, 9, + TOP_MUX(0x0, "GMII"), /* rx_dv */ + TOP_MUX(0x1, "DVI1"), /* d4 */ + TOP_MUX(0x2, "BGPIO"), /* gpio22 */ + TOP_MUX(0x3, "TSI1")), /* dat0 */ + TOP_PIN(GMII_COL, TOP_REG1, 14, 2, 0x2c, 18, + TOP_MUX(0x0, "GMII"), /* col */ + TOP_MUX(0x1, "DVI1"), /* d5 */ + TOP_MUX(0x2, "BGPIO"), /* gpio23 */ + TOP_MUX(0x3, "TSI1")), /* clk */ + TOP_PIN(GMII_CRS, TOP_REG1, 16, 2, 0x30, 0, + TOP_MUX(0x0, "GMII"), /* crs */ + TOP_MUX(0x1, "DVI1"), /* d6 */ + TOP_MUX(0x2, "BGPIO"), /* gpio24 */ + TOP_MUX(0x3, "TSI1")), /* sync */ + TOP_PIN(GMII_MDC, TOP_REG1, 18, 2, 0x30, 9, + TOP_MUX(0x0, "GMII"), /* mdc */ + TOP_MUX(0x1, "DVI1"), /* d7 */ + TOP_MUX(0x2, "BGPIO"), /* gpio25 */ + TOP_MUX(0x3, "TSI1")), /* valid */ + TOP_PIN(GMII_MDIO, TOP_REG1, 20, 1, 0x30, 18, + TOP_MUX(0x0, "GMII"), /* mdio */ + TOP_MUX(0x2, "BGPIO")), /* gpio26 */ + TOP_PIN(SDIO1_CLK, TOP_REG1, 21, 2, 0x34, 18, + TOP_MUX(0x0, "SDIO1"), /* clk */ + TOP_MUX(0x1, "USIM0"), /* clk */ + TOP_MUX(0x2, "BGPIO"), /* gpio27 */ + TOP_MUX(0x3, "SPINOR")), /* clk */ + TOP_PIN(SDIO1_CMD, TOP_REG1, 23, 2, 0x38, 0, + TOP_MUX(0x0, "SDIO1"), /* cmd */ + TOP_MUX(0x1, "USIM0"), /* cd */ + TOP_MUX(0x2, "BGPIO"), /* gpio28 */ + TOP_MUX(0x3, "SPINOR")), /* cs */ + TOP_PIN(SDIO1_DATA0, TOP_REG1, 25, 2, 0x38, 9, + TOP_MUX(0x0, "SDIO1"), /* dat0 */ + TOP_MUX(0x1, "USIM0"), /* rst */ + TOP_MUX(0x2, "BGPIO"), /* gpio29 */ + TOP_MUX(0x3, "SPINOR")), /* dq0 */ + TOP_PIN(SDIO1_DATA1, TOP_REG1, 27, 2, 0x38, 18, + TOP_MUX(0x0, "SDIO1"), /* dat1 */ + TOP_MUX(0x1, "USIM0"), /* data */ + TOP_MUX(0x2, "BGPIO"), /* gpio30 */ + TOP_MUX(0x3, "SPINOR")), /* dq1 */ + TOP_PIN(SDIO1_DATA2, TOP_REG1, 29, 2, 0x3c, 0, + TOP_MUX(0x0, "SDIO1"), /* dat2 */ + TOP_MUX(0x1, "BGPIO"), /* gpio31 */ + TOP_MUX(0x2, "SPINOR")), /* dq2 */ + + /* top_pmm_reg_2 */ + TOP_PIN(SDIO1_DATA3, TOP_REG2, 0, 2, 0x3c, 9, + TOP_MUX(0x0, "SDIO1"), /* dat3 */ + TOP_MUX(0x1, "BGPIO"), /* gpio32 */ + TOP_MUX(0x2, "SPINOR")), /* dq3 */ + TOP_PIN(SDIO1_CD, TOP_REG2, 2, 2, 0x3c, 18, + TOP_MUX(0x0, "SDIO1"), /* cd */ + TOP_MUX(0x1, "BGPIO"), /* gpio33 */ + TOP_MUX(0x2, "ISP")), /* fl_trig */ + TOP_PIN(SDIO1_WP, TOP_REG2, 4, 2, 0x40, 0, + TOP_MUX(0x0, "SDIO1"), /* wp */ + TOP_MUX(0x1, "BGPIO"), /* gpio34 */ + TOP_MUX(0x2, "ISP")), /* ref_clk */ + TOP_PIN(USIM1_CD, TOP_REG2, 22, 3, 0x44, 18, + TOP_MUX(0x0, "USIM1"), /* cd */ + TOP_MUX(0x1, "UART4"), /* rxd */ + TOP_MUX(0x2, "BGPIO"), /* gpio39 */ + TOP_MUX(0x3, "SPI3"), /* clk */ + TOP_MUX(0x4, "I2S0"), /* bclk */ + TOP_MUX(0x5, "B_DVI0")), /* d8 */ + TOP_PIN(USIM1_CLK, TOP_REG2, 25, 3, 0x4c, 18, + TOP_MUX(0x0, "USIM1"), /* clk */ + TOP_MUX(0x1, "UART4"), /* txd */ + TOP_MUX(0x2, "BGPIO"), /* gpio40 */ + TOP_MUX(0x3, "SPI3"), /* cs */ + TOP_MUX(0x4, "I2S0"), /* ws */ + TOP_MUX(0x5, "B_DVI0")), /* d9 */ + TOP_PIN(USIM1_RST, TOP_REG2, 28, 3, 0x4c, 0, + TOP_MUX(0x0, "USIM1"), /* rst */ + TOP_MUX(0x1, "UART4"), /* cts */ + TOP_MUX(0x2, "BGPIO"), /* gpio41 */ + TOP_MUX(0x3, "SPI3"), /* txd */ + TOP_MUX(0x4, "I2S0"), /* dout0 */ + TOP_MUX(0x5, "B_DVI0")), /* d10 */ + + /* top_pmm_reg_3 */ + TOP_PIN(USIM1_DATA, TOP_REG3, 0, 3, 0x4c, 9, + TOP_MUX(0x0, "USIM1"), /* dat */ + TOP_MUX(0x1, "UART4"), /* rst */ + TOP_MUX(0x2, "BGPIO"), /* gpio42 */ + TOP_MUX(0x3, "SPI3"), /* rxd */ + TOP_MUX(0x4, "I2S0"), /* din0 */ + TOP_MUX(0x5, "B_DVI0")), /* d11 */ + TOP_PIN(SDIO0_CLK, TOP_REG3, 6, 1, 0x58, 0, + TOP_MUX(0x0, "SDIO0"), /* clk */ + TOP_MUX(0x1, "GPIO")), /* gpio43 */ + TOP_PIN(SDIO0_CMD, TOP_REG3, 7, 1, 0x58, 9, + TOP_MUX(0x0, "SDIO0"), /* cmd */ + TOP_MUX(0x1, "GPIO")), /* gpio44 */ + TOP_PIN(SDIO0_DATA0, TOP_REG3, 8, 1, 0x58, 18, + TOP_MUX(0x0, "SDIO0"), /* dat0 */ + TOP_MUX(0x1, "GPIO")), /* gpio45 */ + TOP_PIN(SDIO0_DATA1, TOP_REG3, 9, 1, 0x5c, 0, + TOP_MUX(0x0, "SDIO0"), /* dat1 */ + TOP_MUX(0x1, "GPIO")), /* gpio46 */ + TOP_PIN(SDIO0_DATA2, TOP_REG3, 10, 1, 0x5c, 9, + TOP_MUX(0x0, "SDIO0"), /* dat2 */ + TOP_MUX(0x1, "GPIO")), /* gpio47 */ + TOP_PIN(SDIO0_DATA3, TOP_REG3, 11, 1, 0x5c, 18, + TOP_MUX(0x0, "SDIO0"), /* dat3 */ + TOP_MUX(0x1, "GPIO")), /* gpio48 */ + TOP_PIN(SDIO0_CD, TOP_REG3, 12, 1, 0x60, 0, + TOP_MUX(0x0, "SDIO0"), /* cd */ + TOP_MUX(0x1, "GPIO")), /* gpio49 */ + TOP_PIN(SDIO0_WP, TOP_REG3, 13, 1, 0x60, 9, + TOP_MUX(0x0, "SDIO0"), /* wp */ + TOP_MUX(0x1, "GPIO")), /* gpio50 */ + + /* top_pmm_reg_4 */ + TOP_PIN(TSI0_DATA0, TOP_REG4, 0, 2, 0x60, 18, + TOP_MUX(0x0, "TSI0"), /* dat0 */ + TOP_MUX(0x1, "LCD"), /* clk */ + TOP_MUX(0x2, "BGPIO")), /* gpio51 */ + TOP_PIN(SPINOR_CLK, TOP_REG4, 2, 2, 0xa8, 18, + TOP_MUX(0x0, "SPINOR"), /* clk */ + TOP_MUX(0x1, "TSI0"), /* dat1 */ + TOP_MUX(0x2, "LCD"), /* dat0 */ + TOP_MUX(0x3, "BGPIO")), /* gpio52 */ + TOP_PIN(TSI2_DATA, TOP_REG4, 4, 2, 0x7c, 0, + TOP_MUX(0x0, "TSI2"), /* dat */ + TOP_MUX(0x1, "TSI0"), /* dat2 */ + TOP_MUX(0x2, "LCD"), /* dat1 */ + TOP_MUX(0x3, "BGPIO")), /* gpio53 */ + TOP_PIN(TSI2_CLK, TOP_REG4, 6, 2, 0x7c, 9, + TOP_MUX(0x0, "TSI2"), /* clk */ + TOP_MUX(0x1, "TSI0"), /* dat3 */ + TOP_MUX(0x2, "LCD"), /* dat2 */ + TOP_MUX(0x3, "BGPIO")), /* gpio54 */ + TOP_PIN(TSI2_SYNC, TOP_REG4, 8, 2, 0x7c, 18, + TOP_MUX(0x0, "TSI2"), /* sync */ + TOP_MUX(0x1, "TSI0"), /* dat4 */ + TOP_MUX(0x2, "LCD"), /* dat3 */ + TOP_MUX(0x3, "BGPIO")), /* gpio55 */ + TOP_PIN(TSI2_VALID, TOP_REG4, 10, 2, 0x80, 0, + TOP_MUX(0x0, "TSI2"), /* valid */ + TOP_MUX(0x1, "TSI0"), /* dat5 */ + TOP_MUX(0x2, "LCD"), /* dat4 */ + TOP_MUX(0x3, "BGPIO")), /* gpio56 */ + TOP_PIN(SPINOR_CS, TOP_REG4, 12, 2, 0x80, 9, + TOP_MUX(0x0, "SPINOR"), /* cs */ + TOP_MUX(0x1, "TSI0"), /* dat6 */ + TOP_MUX(0x2, "LCD"), /* dat5 */ + TOP_MUX(0x3, "BGPIO")), /* gpio57 */ + TOP_PIN(SPINOR_DQ0, TOP_REG4, 14, 2, 0x80, 18, + TOP_MUX(0x0, "SPINOR"), /* dq0 */ + TOP_MUX(0x1, "TSI0"), /* dat7 */ + TOP_MUX(0x2, "LCD"), /* dat6 */ + TOP_MUX(0x3, "BGPIO")), /* gpio58 */ + TOP_PIN(SPINOR_DQ1, TOP_REG4, 16, 2, 0x84, 0, + TOP_MUX(0x0, "SPINOR"), /* dq1 */ + TOP_MUX(0x1, "TSI0"), /* clk */ + TOP_MUX(0x2, "LCD"), /* dat7 */ + TOP_MUX(0x3, "BGPIO")), /* gpio59 */ + TOP_PIN(SPINOR_DQ2, TOP_REG4, 18, 2, 0x84, 9, + TOP_MUX(0x0, "SPINOR"), /* dq2 */ + TOP_MUX(0x1, "TSI0"), /* sync */ + TOP_MUX(0x2, "LCD"), /* dat8 */ + TOP_MUX(0x3, "BGPIO")), /* gpio60 */ + TOP_PIN(SPINOR_DQ3, TOP_REG4, 20, 2, 0x84, 18, + TOP_MUX(0x0, "SPINOR"), /* dq3 */ + TOP_MUX(0x1, "TSI0"), /* valid */ + TOP_MUX(0x2, "LCD"), /* dat9 */ + TOP_MUX(0x3, "BGPIO")), /* gpio61 */ + TOP_PIN(VGA_HS, TOP_REG4, 22, 3, 0x88, 0, + TOP_MUX(0x0, "VGA"), /* hs */ + TOP_MUX(0x1, "TSI1"), /* dat0 */ + TOP_MUX(0x2, "LCD"), /* dat10 */ + TOP_MUX(0x3, "BGPIO"), /* gpio62 */ + TOP_MUX(0x4, "I2S1"), /* din1 */ + TOP_MUX(0x5, "B_DVI0")), /* clk */ + TOP_PIN(VGA_VS, TOP_REG4, 25, 3, 0x88, 9, + TOP_MUX(0x0, "VGA"), /* vs0 */ + TOP_MUX(0x1, "TSI1"), /* dat1 */ + TOP_MUX(0x2, "LCD"), /* dat11 */ + TOP_MUX(0x3, "BGPIO"), /* gpio63 */ + TOP_MUX(0x4, "I2S1"), /* din2 */ + TOP_MUX(0x5, "B_DVI0")), /* vs */ + TOP_PIN(TSI3_DATA, TOP_REG4, 28, 3, 0x88, 18, + TOP_MUX(0x0, "TSI3"), /* dat */ + TOP_MUX(0x1, "TSI1"), /* dat2 */ + TOP_MUX(0x2, "LCD"), /* dat12 */ + TOP_MUX(0x3, "BGPIO"), /* gpio64 */ + TOP_MUX(0x4, "I2S1"), /* din3 */ + TOP_MUX(0x5, "B_DVI0")), /* hs */ + + /* top_pmm_reg_5 */ + TOP_PIN(TSI3_CLK, TOP_REG5, 0, 3, 0x8c, 0, + TOP_MUX(0x0, "TSI3"), /* clk */ + TOP_MUX(0x1, "TSI1"), /* dat3 */ + TOP_MUX(0x2, "LCD"), /* dat13 */ + TOP_MUX(0x3, "BGPIO"), /* gpio65 */ + TOP_MUX(0x4, "I2S1"), /* dout1 */ + TOP_MUX(0x5, "B_DVI0")), /* d0 */ + TOP_PIN(TSI3_SYNC, TOP_REG5, 3, 3, 0x8c, 9, + TOP_MUX(0x0, "TSI3"), /* sync */ + TOP_MUX(0x1, "TSI1"), /* dat4 */ + TOP_MUX(0x2, "LCD"), /* dat14 */ + TOP_MUX(0x3, "BGPIO"), /* gpio66 */ + TOP_MUX(0x4, "I2S1"), /* dout2 */ + TOP_MUX(0x5, "B_DVI0")), /* d1 */ + TOP_PIN(TSI3_VALID, TOP_REG5, 6, 3, 0x8c, 18, + TOP_MUX(0x0, "TSI3"), /* valid */ + TOP_MUX(0x1, "TSI1"), /* dat5 */ + TOP_MUX(0x2, "LCD"), /* dat15 */ + TOP_MUX(0x3, "BGPIO"), /* gpio67 */ + TOP_MUX(0x4, "I2S1"), /* dout3 */ + TOP_MUX(0x5, "B_DVI0")), /* d2 */ + TOP_PIN(I2S1_WS, TOP_REG5, 9, 3, 0x90, 0, + TOP_MUX(0x0, "I2S1"), /* ws */ + TOP_MUX(0x1, "TSI1"), /* dat6 */ + TOP_MUX(0x2, "LCD"), /* dat16 */ + TOP_MUX(0x3, "BGPIO"), /* gpio68 */ + TOP_MUX(0x4, "VGA"), /* scl */ + TOP_MUX(0x5, "B_DVI0")), /* d3 */ + TOP_PIN(I2S1_BCLK, TOP_REG5, 12, 3, 0x90, 9, + TOP_MUX(0x0, "I2S1"), /* bclk */ + TOP_MUX(0x1, "TSI1"), /* dat7 */ + TOP_MUX(0x2, "LCD"), /* dat17 */ + TOP_MUX(0x3, "BGPIO"), /* gpio69 */ + TOP_MUX(0x4, "VGA"), /* sda */ + TOP_MUX(0x5, "B_DVI0")), /* d4 */ + TOP_PIN(I2S1_MCLK, TOP_REG5, 15, 2, 0x90, 18, + TOP_MUX(0x0, "I2S1"), /* mclk */ + TOP_MUX(0x1, "TSI1"), /* clk */ + TOP_MUX(0x2, "LCD"), /* dat18 */ + TOP_MUX(0x3, "BGPIO")), /* gpio70 */ + TOP_PIN(I2S1_DIN0, TOP_REG5, 17, 2, 0x94, 0, + TOP_MUX(0x0, "I2S1"), /* din0 */ + TOP_MUX(0x1, "TSI1"), /* sync */ + TOP_MUX(0x2, "LCD"), /* dat19 */ + TOP_MUX(0x3, "BGPIO")), /* gpio71 */ + TOP_PIN(I2S1_DOUT0, TOP_REG5, 19, 2, 0x94, 9, + TOP_MUX(0x0, "I2S1"), /* dout0 */ + TOP_MUX(0x1, "TSI1"), /* valid */ + TOP_MUX(0x2, "LCD"), /* dat20 */ + TOP_MUX(0x3, "BGPIO")), /* gpio72 */ + TOP_PIN(SPI3_CLK, TOP_REG5, 21, 3, 0x94, 18, + TOP_MUX(0x0, "SPI3"), /* clk */ + TOP_MUX(0x1, "TSO1"), /* clk */ + TOP_MUX(0x2, "LCD"), /* dat21 */ + TOP_MUX(0x3, "BGPIO"), /* gpio73 */ + TOP_MUX(0x4, "UART5"), /* rxd */ + TOP_MUX(0x5, "PCM"), /* fs */ + TOP_MUX(0x6, "I2S0"), /* din1 */ + TOP_MUX(0x7, "B_DVI0")), /* d5 */ + TOP_PIN(SPI3_CS, TOP_REG5, 24, 3, 0x98, 0, + TOP_MUX(0x0, "SPI3"), /* cs */ + TOP_MUX(0x1, "TSO1"), /* dat0 */ + TOP_MUX(0x2, "LCD"), /* dat22 */ + TOP_MUX(0x3, "BGPIO"), /* gpio74 */ + TOP_MUX(0x4, "UART5"), /* txd */ + TOP_MUX(0x5, "PCM"), /* clk */ + TOP_MUX(0x6, "I2S0"), /* din2 */ + TOP_MUX(0x7, "B_DVI0")), /* d6 */ + TOP_PIN(SPI3_TXD, TOP_REG5, 27, 3, 0x98, 9, + TOP_MUX(0x0, "SPI3"), /* txd */ + TOP_MUX(0x1, "TSO1"), /* dat1 */ + TOP_MUX(0x2, "LCD"), /* dat23 */ + TOP_MUX(0x3, "BGPIO"), /* gpio75 */ + TOP_MUX(0x4, "UART5"), /* cts */ + TOP_MUX(0x5, "PCM"), /* txd */ + TOP_MUX(0x6, "I2S0"), /* din3 */ + TOP_MUX(0x7, "B_DVI0")), /* d7 */ + TOP_PIN(NAND_LDO_MS18_SEL, TOP_REG5, 30, 1, 0xe4, 0, + TOP_MUX(0x0, "NAND"), /* ldo_ms18_sel */ + TOP_MUX(0x1, "BGPIO")), /* gpio99 */ + + /* top_pmm_reg_6 */ + TOP_PIN(SPI3_RXD, TOP_REG6, 0, 3, 0x98, 18, + TOP_MUX(0x0, "SPI3"), /* rxd */ + TOP_MUX(0x1, "TSO1"), /* dat2 */ + TOP_MUX(0x2, "LCD"), /* stvu_vsync */ + TOP_MUX(0x3, "BGPIO"), /* gpio76 */ + TOP_MUX(0x4, "UART5"), /* rts */ + TOP_MUX(0x5, "PCM"), /* rxd */ + TOP_MUX(0x6, "I2S0"), /* dout1 */ + TOP_MUX(0x7, "B_DVI1")), /* clk */ + TOP_PIN(I2S0_MCLK, TOP_REG6, 3, 3, 0x9c, 0, + TOP_MUX(0x0, "I2S0"), /* mclk */ + TOP_MUX(0x1, "TSO1"), /* dat3 */ + TOP_MUX(0x2, "LCD"), /* stvd */ + TOP_MUX(0x3, "BGPIO"), /* gpio77 */ + TOP_MUX(0x4, "USIM0"), /* cd */ + TOP_MUX(0x5, "B_DVI1")), /* vs */ + TOP_PIN(I2S0_BCLK, TOP_REG6, 6, 3, 0x9c, 9, + TOP_MUX(0x0, "I2S0"), /* bclk */ + TOP_MUX(0x1, "TSO1"), /* dat4 */ + TOP_MUX(0x2, "LCD"), /* sthl_hsync */ + TOP_MUX(0x3, "BGPIO"), /* gpio78 */ + TOP_MUX(0x4, "USIM0"), /* clk */ + TOP_MUX(0x5, "B_DVI1")), /* hs */ + TOP_PIN(I2S0_WS, TOP_REG6, 9, 3, 0x9c, 18, + TOP_MUX(0x0, "I2S0"), /* ws */ + TOP_MUX(0x1, "TSO1"), /* dat5 */ + TOP_MUX(0x2, "LCD"), /* sthr */ + TOP_MUX(0x3, "BGPIO"), /* gpio79 */ + TOP_MUX(0x4, "USIM0"), /* rst */ + TOP_MUX(0x5, "B_DVI1")), /* d0 */ + TOP_PIN(I2S0_DIN0, TOP_REG6, 12, 3, 0xa0, 0, + TOP_MUX(0x0, "I2S0"), /* din0 */ + TOP_MUX(0x1, "TSO1"), /* dat6 */ + TOP_MUX(0x2, "LCD"), /* oev_dataen */ + TOP_MUX(0x3, "BGPIO"), /* gpio80 */ + TOP_MUX(0x4, "USIM0"), /* dat */ + TOP_MUX(0x5, "B_DVI1")), /* d1 */ + TOP_PIN(I2S0_DOUT0, TOP_REG6, 15, 2, 0xa0, 9, + TOP_MUX(0x0, "I2S0"), /* dout0 */ + TOP_MUX(0x1, "TSO1"), /* dat7 */ + TOP_MUX(0x2, "LCD"), /* ckv */ + TOP_MUX(0x3, "BGPIO")), /* gpio81 */ + TOP_PIN(I2C5_SCL, TOP_REG6, 17, 3, 0xa0, 18, + TOP_MUX(0x0, "I2C5"), /* scl */ + TOP_MUX(0x1, "TSO1"), /* sync */ + TOP_MUX(0x2, "LCD"), /* ld */ + TOP_MUX(0x3, "BGPIO"), /* gpio82 */ + TOP_MUX(0x4, "PWM"), /* out2 */ + TOP_MUX(0x5, "I2S0"), /* dout2 */ + TOP_MUX(0x6, "B_DVI1")), /* d2 */ + TOP_PIN(I2C5_SDA, TOP_REG6, 20, 3, 0xa4, 0, + TOP_MUX(0x0, "I2C5"), /* sda */ + TOP_MUX(0x1, "TSO1"), /* vld */ + TOP_MUX(0x2, "LCD"), /* pol */ + TOP_MUX(0x3, "BGPIO"), /* gpio83 */ + TOP_MUX(0x4, "PWM"), /* out3 */ + TOP_MUX(0x5, "I2S0"), /* dout3 */ + TOP_MUX(0x6, "B_DVI1")), /* d3 */ + TOP_PIN(SPI2_CLK, TOP_REG6, 23, 3, 0xa4, 9, + TOP_MUX(0x0, "SPI2"), /* clk */ + TOP_MUX(0x1, "TSO0"), /* clk */ + TOP_MUX(0x2, "LCD"), /* degsl */ + TOP_MUX(0x3, "BGPIO"), /* gpio84 */ + TOP_MUX(0x4, "I2C4"), /* scl */ + TOP_MUX(0x5, "B_DVI1")), /* d4 */ + TOP_PIN(SPI2_CS, TOP_REG6, 26, 3, 0xa4, 18, + TOP_MUX(0x0, "SPI2"), /* cs */ + TOP_MUX(0x1, "TSO0"), /* data */ + TOP_MUX(0x2, "LCD"), /* rev */ + TOP_MUX(0x3, "BGPIO"), /* gpio85 */ + TOP_MUX(0x4, "I2C4"), /* sda */ + TOP_MUX(0x5, "B_DVI1")), /* d5 */ + TOP_PIN(SPI2_TXD, TOP_REG6, 29, 3, 0xa8, 0, + TOP_MUX(0x0, "SPI2"), /* txd */ + TOP_MUX(0x1, "TSO0"), /* sync */ + TOP_MUX(0x2, "LCD"), /* u_d */ + TOP_MUX(0x3, "BGPIO"), /* gpio86 */ + TOP_MUX(0x4, "I2C4"), /* scl */ + TOP_MUX(0x5, "B_DVI1")), /* d6 */ + + /* top_pmm_reg_7 */ + TOP_PIN(SPI2_RXD, TOP_REG7, 0, 3, 0xa8, 9, + TOP_MUX(0x0, "SPI2"), /* rxd */ + TOP_MUX(0x1, "TSO0"), /* vld */ + TOP_MUX(0x2, "LCD"), /* r_l */ + TOP_MUX(0x3, "BGPIO"), /* gpio87 */ + TOP_MUX(0x4, "I2C3"), /* sda */ + TOP_MUX(0x5, "B_DVI1")), /* d7 */ + TOP_PIN(NAND_WP_N, TOP_REG7, 7, 3, 0x54, 9, + TOP_MUX(0x0, "NAND"), /* wp */ + TOP_MUX(0x1, "PWM"), /* out2 */ + TOP_MUX(0x2, "SPI2"), /* clk */ + TOP_MUX(0x3, "BGPIO"), /* gpio88 */ + TOP_MUX(0x4, "TSI0"), /* dat0 */ + TOP_MUX(0x5, "I2S1")), /* din1 */ + TOP_PIN(NAND_PAGE_SIZE0, TOP_REG7, 10, 3, 0xb8, 0, + TOP_MUX(0x0, "NAND"), /* boot_pagesize0 */ + TOP_MUX(0x1, "PWM"), /* out3 */ + TOP_MUX(0x2, "SPI2"), /* cs */ + TOP_MUX(0x3, "BGPIO"), /* gpio89 */ + TOP_MUX(0x4, "TSI0"), /* clk */ + TOP_MUX(0x5, "I2S1")), /* din2 */ + TOP_PIN(NAND_PAGE_SIZE1, TOP_REG7, 13, 3, 0xb8, 9, + TOP_MUX(0x0, "NAND"), /* boot_pagesize1 */ + TOP_MUX(0x1, "I2C4"), /* scl */ + TOP_MUX(0x2, "SPI2"), /* txd */ + TOP_MUX(0x3, "BGPIO"), /* gpio90 */ + TOP_MUX(0x4, "TSI0"), /* sync */ + TOP_MUX(0x5, "I2S1")), /* din3 */ + TOP_PIN(NAND_ADDR_CYCLE, TOP_REG7, 16, 3, 0xb8, 18, + TOP_MUX(0x0, "NAND"), /* boot_addr_cycles */ + TOP_MUX(0x1, "I2C4"), /* sda */ + TOP_MUX(0x2, "SPI2"), /* rxd */ + TOP_MUX(0x3, "BGPIO"), /* gpio91 */ + TOP_MUX(0x4, "TSI0"), /* valid */ + TOP_MUX(0x5, "I2S1")), /* dout1 */ + TOP_PIN(NAND_RB0, TOP_REG7, 19, 3, 0xbc, 0, + TOP_MUX(0x0, "NAND"), /* rdy_busy0 */ + TOP_MUX(0x1, "I2C2"), /* scl */ + TOP_MUX(0x2, "USIM0"), /* cd */ + TOP_MUX(0x3, "BGPIO"), /* gpio92 */ + TOP_MUX(0x4, "TSI1")), /* data0 */ + TOP_PIN(NAND_RB1, TOP_REG7, 22, 3, 0xbc, 9, + TOP_MUX(0x0, "NAND"), /* rdy_busy1 */ + TOP_MUX(0x1, "I2C2"), /* sda */ + TOP_MUX(0x2, "USIM0"), /* clk */ + TOP_MUX(0x3, "BGPIO"), /* gpio93 */ + TOP_MUX(0x4, "TSI1")), /* clk */ + TOP_PIN(NAND_RB2, TOP_REG7, 25, 3, 0xbc, 18, + TOP_MUX(0x0, "NAND"), /* rdy_busy2 */ + TOP_MUX(0x1, "UART5"), /* rxd */ + TOP_MUX(0x2, "USIM0"), /* rst */ + TOP_MUX(0x3, "BGPIO"), /* gpio94 */ + TOP_MUX(0x4, "TSI1"), /* sync */ + TOP_MUX(0x4, "I2S1")), /* dout2 */ + TOP_PIN(NAND_RB3, TOP_REG7, 28, 3, 0x54, 18, + TOP_MUX(0x0, "NAND"), /* rdy_busy3 */ + TOP_MUX(0x1, "UART5"), /* txd */ + TOP_MUX(0x2, "USIM0"), /* dat */ + TOP_MUX(0x3, "BGPIO"), /* gpio95 */ + TOP_MUX(0x4, "TSI1"), /* valid */ + TOP_MUX(0x4, "I2S1")), /* dout3 */ + + /* top_pmm_reg_8 */ + TOP_PIN(GMAC_125M_IN, TOP_REG8, 0, 2, 0x34, 0, + TOP_MUX(0x0, "GMII"), /* 125m_in */ + TOP_MUX(0x1, "USB2"), /* 0_drvvbus */ + TOP_MUX(0x2, "ISP"), /* ref_clk */ + TOP_MUX(0x3, "BGPIO")), /* gpio96 */ + TOP_PIN(GMAC_50M_OUT, TOP_REG8, 2, 2, 0x34, 9, + TOP_MUX(0x0, "GMII"), /* 50m_out */ + TOP_MUX(0x1, "USB2"), /* 1_drvvbus */ + TOP_MUX(0x2, "BGPIO"), /* gpio97 */ + TOP_MUX(0x3, "USB2")), /* 0_drvvbus */ + TOP_PIN(SPINOR_SSCLK_LOOPBACK, TOP_REG8, 6, 1, 0xc8, 9, + TOP_MUX(0x0, "SPINOR")), /* sdio1_clk_i */ + TOP_PIN(SPINOR_SDIO1CLK_LOOPBACK, TOP_REG8, 7, 1, 0xc8, 18, + TOP_MUX(0x0, "SPINOR")), /* ssclk_i */ +}; + +static struct zx_pinctrl_soc_info zx296718_pinctrl_info = { + .pins = zx296718_pins, + .npins = ARRAY_SIZE(zx296718_pins), +}; + +static int zx296718_pinctrl_probe(struct platform_device *pdev) +{ + return zx_pinctrl_init(pdev, &zx296718_pinctrl_info); +} + +static const struct of_device_id zx296718_pinctrl_match[] = { + { .compatible = "zte,zx296718-pmm", }, + {} +}; +MODULE_DEVICE_TABLE(of, zx296718_pinctrl_match); + +static struct platform_driver zx296718_pinctrl_driver = { + .probe = zx296718_pinctrl_probe, + .driver = { + .name = "zx296718-pinctrl", + .of_match_table = zx296718_pinctrl_match, + }, +}; +builtin_platform_driver(zx296718_pinctrl_driver); + +MODULE_DESCRIPTION("ZTE ZX296718 pinctrl driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c index 76d13150283f..a75ff3622450 100644 --- a/drivers/pwm/pwm-jz4740.c +++ b/drivers/pwm/pwm-jz4740.c @@ -21,22 +21,10 @@ #include <linux/platform_device.h> #include <linux/pwm.h> -#include <asm/mach-jz4740/gpio.h> #include <asm/mach-jz4740/timer.h> #define NUM_PWM 8 -static const unsigned int jz4740_pwm_gpio_list[NUM_PWM] = { - JZ_GPIO_PWM0, - JZ_GPIO_PWM1, - JZ_GPIO_PWM2, - JZ_GPIO_PWM3, - JZ_GPIO_PWM4, - JZ_GPIO_PWM5, - JZ_GPIO_PWM6, - JZ_GPIO_PWM7, -}; - struct jz4740_pwm_chip { struct pwm_chip chip; struct clk *clk; @@ -49,9 +37,6 @@ static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip) static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) { - unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm]; - int ret; - /* * Timers 0 and 1 are used for system tasks, so they are unavailable * for use as PWMs. @@ -59,15 +44,6 @@ static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) if (pwm->hwpwm < 2) return -EBUSY; - ret = gpio_request(gpio, pwm->label); - if (ret) { - dev_err(chip->dev, "Failed to request GPIO#%u for PWM: %d\n", - gpio, ret); - return ret; - } - - jz_gpio_set_function(gpio, JZ_GPIO_FUNC_PWM); - jz4740_timer_start(pwm->hwpwm); return 0; @@ -75,13 +51,8 @@ static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) { - unsigned int gpio = jz4740_pwm_gpio_list[pwm->hwpwm]; - jz4740_timer_set_ctrl(pwm->hwpwm, 0); - jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE); - gpio_free(gpio); - jz4740_timer_stop(pwm->hwpwm); } diff --git a/drivers/video/fbdev/jz4740_fb.c b/drivers/video/fbdev/jz4740_fb.c index 87790e9644d0..b57df83fdbd3 100644 --- a/drivers/video/fbdev/jz4740_fb.c +++ b/drivers/video/fbdev/jz4740_fb.c @@ -17,6 +17,7 @@ #include <linux/module.h> #include <linux/mutex.h> #include <linux/platform_device.h> +#include <linux/pinctrl/consumer.h> #include <linux/clk.h> #include <linux/delay.h> @@ -27,7 +28,6 @@ #include <linux/dma-mapping.h> #include <asm/mach-jz4740/jz4740_fb.h> -#include <asm/mach-jz4740/gpio.h> #define JZ_REG_LCD_CFG 0x00 #define JZ_REG_LCD_VSYNC 0x04 @@ -146,93 +146,6 @@ static const struct fb_fix_screeninfo jzfb_fix = { .accel = FB_ACCEL_NONE, }; -static const struct jz_gpio_bulk_request jz_lcd_ctrl_pins[] = { - JZ_GPIO_BULK_PIN(LCD_PCLK), - JZ_GPIO_BULK_PIN(LCD_HSYNC), - JZ_GPIO_BULK_PIN(LCD_VSYNC), - JZ_GPIO_BULK_PIN(LCD_DE), - JZ_GPIO_BULK_PIN(LCD_PS), - JZ_GPIO_BULK_PIN(LCD_REV), - JZ_GPIO_BULK_PIN(LCD_CLS), - JZ_GPIO_BULK_PIN(LCD_SPL), -}; - -static const struct jz_gpio_bulk_request jz_lcd_data_pins[] = { - JZ_GPIO_BULK_PIN(LCD_DATA0), - JZ_GPIO_BULK_PIN(LCD_DATA1), - JZ_GPIO_BULK_PIN(LCD_DATA2), - JZ_GPIO_BULK_PIN(LCD_DATA3), - JZ_GPIO_BULK_PIN(LCD_DATA4), - JZ_GPIO_BULK_PIN(LCD_DATA5), - JZ_GPIO_BULK_PIN(LCD_DATA6), - JZ_GPIO_BULK_PIN(LCD_DATA7), - JZ_GPIO_BULK_PIN(LCD_DATA8), - JZ_GPIO_BULK_PIN(LCD_DATA9), - JZ_GPIO_BULK_PIN(LCD_DATA10), - JZ_GPIO_BULK_PIN(LCD_DATA11), - JZ_GPIO_BULK_PIN(LCD_DATA12), - JZ_GPIO_BULK_PIN(LCD_DATA13), - JZ_GPIO_BULK_PIN(LCD_DATA14), - JZ_GPIO_BULK_PIN(LCD_DATA15), - JZ_GPIO_BULK_PIN(LCD_DATA16), - JZ_GPIO_BULK_PIN(LCD_DATA17), -}; - -static unsigned int jzfb_num_ctrl_pins(struct jzfb *jzfb) -{ - unsigned int num; - - switch (jzfb->pdata->lcd_type) { - case JZ_LCD_TYPE_GENERIC_16_BIT: - num = 4; - break; - case JZ_LCD_TYPE_GENERIC_18_BIT: - num = 4; - break; - case JZ_LCD_TYPE_8BIT_SERIAL: - num = 3; - break; - case JZ_LCD_TYPE_SPECIAL_TFT_1: - case JZ_LCD_TYPE_SPECIAL_TFT_2: - case JZ_LCD_TYPE_SPECIAL_TFT_3: - num = 8; - break; - default: - num = 0; - break; - } - return num; -} - -static unsigned int jzfb_num_data_pins(struct jzfb *jzfb) -{ - unsigned int num; - - switch (jzfb->pdata->lcd_type) { - case JZ_LCD_TYPE_GENERIC_16_BIT: - num = 16; - break; - case JZ_LCD_TYPE_GENERIC_18_BIT: - num = 18; - break; - case JZ_LCD_TYPE_8BIT_SERIAL: - num = 8; - break; - case JZ_LCD_TYPE_SPECIAL_TFT_1: - case JZ_LCD_TYPE_SPECIAL_TFT_2: - case JZ_LCD_TYPE_SPECIAL_TFT_3: - if (jzfb->pdata->bpp == 18) - num = 18; - else - num = 16; - break; - default: - num = 0; - break; - } - return num; -} - /* Based on CNVT_TOHW macro from skeletonfb.c */ static inline uint32_t jzfb_convert_color_to_hw(unsigned val, struct fb_bitfield *bf) @@ -487,8 +400,7 @@ static void jzfb_enable(struct jzfb *jzfb) clk_prepare_enable(jzfb->ldclk); - jz_gpio_bulk_resume(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); - jz_gpio_bulk_resume(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); + pinctrl_pm_select_default_state(&jzfb->pdev->dev); writel(0, jzfb->base + JZ_REG_LCD_STATE); @@ -511,8 +423,7 @@ static void jzfb_disable(struct jzfb *jzfb) ctrl = readl(jzfb->base + JZ_REG_LCD_STATE); } while (!(ctrl & JZ_LCD_STATE_DISABLED)); - jz_gpio_bulk_suspend(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); - jz_gpio_bulk_suspend(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); + pinctrl_pm_select_sleep_state(&jzfb->pdev->dev); clk_disable_unprepare(jzfb->ldclk); } @@ -701,9 +612,6 @@ static int jzfb_probe(struct platform_device *pdev) fb->mode = NULL; jzfb_set_par(fb); - jz_gpio_bulk_request(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); - jz_gpio_bulk_request(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); - ret = register_framebuffer(fb); if (ret) { dev_err(&pdev->dev, "Failed to register framebuffer: %d\n", ret); @@ -715,9 +623,6 @@ static int jzfb_probe(struct platform_device *pdev) return 0; err_free_devmem: - jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); - jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); - fb_dealloc_cmap(&fb->cmap); jzfb_free_devmem(jzfb); err_framebuffer_release: @@ -731,9 +636,6 @@ static int jzfb_remove(struct platform_device *pdev) jzfb_blank(FB_BLANK_POWERDOWN, jzfb->fb); - jz_gpio_bulk_free(jz_lcd_ctrl_pins, jzfb_num_ctrl_pins(jzfb)); - jz_gpio_bulk_free(jz_lcd_data_pins, jzfb_num_data_pins(jzfb)); - fb_dealloc_cmap(&jzfb->fb->cmap); jzfb_free_devmem(jzfb); diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index 7620eb127cff..231d3075815a 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -73,10 +73,16 @@ * operation, if several modes of operation are supported these can be * passed in the argument on a custom form, else just use argument 1 * to indicate low power mode, argument 0 turns low power mode off. - * @PIN_CONFIG_OUTPUT: this will configure the pin as an output. Use argument - * 1 to indicate high level, argument 0 to indicate low level. (Please - * see Documentation/pinctrl.txt, section "GPIO mode pitfalls" for a - * discussion around this parameter.) + * @PIN_CONFIG_OUTPUT_ENABLE: this will enable the pin's output mode + * without driving a value there. For most platforms this reduces to + * enable the output buffers and then let the pin controller current + * configuration (eg. the currently selected mux function) drive values on + * the line. Use argument 1 to enable output mode, argument 0 to disable + * it. + * @PIN_CONFIG_OUTPUT: this will configure the pin as an output and drive a + * value on the line. Use argument 1 to indicate high level, argument 0 to + * indicate low level. (Please see Documentation/pinctrl.txt, section + * "GPIO mode pitfalls" for a discussion around this parameter.) * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power * supplies, the argument to this parameter (on a custom format) tells * the driver which alternative power source to use. @@ -105,6 +111,7 @@ enum pin_config_param { PIN_CONFIG_INPUT_SCHMITT, PIN_CONFIG_INPUT_SCHMITT_ENABLE, PIN_CONFIG_LOW_POWER_MODE, + PIN_CONFIG_OUTPUT_ENABLE, PIN_CONFIG_OUTPUT, PIN_CONFIG_POWER_SOURCE, PIN_CONFIG_SLEW_RATE, diff --git a/include/linux/spi/mcp23s08.h b/include/linux/spi/mcp23s08.h index aa07d7b32568..82d96a346e6f 100644 --- a/include/linux/spi/mcp23s08.h +++ b/include/linux/spi/mcp23s08.h @@ -1,11 +1,3 @@ - -/* FIXME driver should be able to handle IRQs... */ - -struct mcp23s08_chip_info { - bool is_present; /* true if populated */ - unsigned pullups; /* BIT(x) means enable pullup x */ -}; - struct mcp23s08_platform_data { /* For mcp23s08, up to 4 slaves (numbered 0..3) can share one SPI * chipselect, each providing 1 gpio_chip instance with 8 gpios. @@ -13,31 +5,13 @@ struct mcp23s08_platform_data { * chipselect, each providing 1 gpio_chip (port A + port B) with * 16 gpios. */ - struct mcp23s08_chip_info chip[8]; + u32 spi_present_mask; - /* "base" is the number of the first GPIO. Dynamic assignment is - * not currently supported, and even if there are gaps in chip - * addressing the GPIO numbers are sequential .. so for example - * if only slaves 0 and 3 are present, their GPIOs range from - * base to base+15 (or base+31 for s17 variant). + /* "base" is the number of the first GPIO or -1 for dynamic + * assignment. If there are gaps in chip addressing the GPIO + * numbers are sequential .. so for example if only slaves 0 + * and 3 are present, their GPIOs range from base to base+15 + * (or base+31 for s17 variant). */ unsigned base; - /* Marks the device as a interrupt controller. - * NOTE: The interrupt functionality is only supported for i2c - * versions of the chips. The spi chips can also do the interrupts, - * but this is not supported by the linux driver yet. - */ - bool irq_controller; - - /* Sets the mirror flag in the IOCON register. Devices - * with two interrupt outputs (these are the devices ending with 17 and - * those that have 16 IOs) have two IO banks: IO 0-7 form bank 1 and - * IO 8-15 are bank 2. These chips have two different interrupt outputs: - * One for bank 1 and another for bank 2. If irq-mirror is set, both - * interrupts are generated regardless of the bank that an input change - * occurred on. If it is not set, the interrupt are only generated for - * the bank they belong to. - * On devices with only one interrupt output this property is useless. - */ - bool mirror; }; |