diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2023-08-30 16:53:46 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-08-30 16:53:46 -0700 |
| commit | 0e72db77672ff4758a31fb5259c754a7bb229751 (patch) | |
| tree | 71afc69a3b476180115e6b9479e582b340828711 | |
| parent | a1c19328a160c80251868dbd80066dce23d07995 (diff) | |
| parent | 05c618f39089d977b0c3dc1105cb6cd5fc53cd01 (diff) | |
Merge tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM devicetree updates from Arnd Bergmann:
"These are the devicetree updates for Arm and RISC-V based SoCs, mainly
from Qualcomm, NXP/Freescale, Aspeed, TI, Rockchips, Samsung, ST and
Starfive.
Only a few new SoC got added:
- TI AM62P5, a variant of the existing Sitara AM62x family
- Intel Agilex5, an FPGFA platform that includes an Cortex-A76/A55
SoC.
- Qualcomm ipq5018 is used in wireless access points
- Qualcomm SM4450 (Snapdragon 4 Gen 2) is a new low-end mobile phone
platform.
In total, 29 machines get added, which is low because of the summer
break. These cover SoCs from Aspeed, Broadcom, NXP, Samsung, ST,
Allwinner, Amlogic, Intel, Qualcomm, Rockchip, TI and T-Head. Most of
these are development and reference boards.
Despite not adding a lot of new machines, there are over 700 patches
in total, most of which are cleanups and minor fixes"
* tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (735 commits)
arm64: dts: use capital "OR" for multiple licenses in SPDX
ARM: dts: use capital "OR" for multiple licenses in SPDX
arm64: dts: qcom: sdm845-db845c: Mark cont splash memory region as reserved
ARM: dts: qcom: apq8064: add support to gsbi4 uart
riscv: dts: change TH1520 files to dual license
riscv: dts: thead: add BeagleV Ahead board device tree
dt-bindings: riscv: Add BeagleV Ahead board compatibles
ARM: dts: stm32: add SCMI PMIC regulators on stm32mp135f-dk board
ARM: dts: stm32: STM32MP13x SoC exposes SCMI regulators
dt-bindings: rcc: stm32: add STM32MP13 SCMI regulators IDs
ARM: dts: stm32: support display on stm32f746-disco board
ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f746-disco
ARM: dts: stm32: add pin map for LTDC on stm32f7
ARM: dts: stm32: add ltdc support on stm32f746 MCU
arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sc8280xp: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sdm670: Add PDC
riscv: dts: starfive: fix jh7110 qspi sort order
...
923 files changed, 38455 insertions, 10235 deletions
diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index 08d59842655c..1c1094cd6b77 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -218,6 +218,14 @@ properties: - amlogic,aq222 - const: amlogic,s4 + - description: Boards with the Amlogic T7 A311D2 SoC + items: + - enum: + - amlogic,an400 + - khadas,vim4 + - const: amlogic,a311d2 + - const: amlogic,t7 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index e0eff4c05879..e17b3d66d6e5 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -79,9 +79,11 @@ properties: - facebook,elbert-bmc - facebook,fuji-bmc - facebook,greatlakes-bmc + - facebook,yosemite4-bmc - ibm,everest-bmc - ibm,rainier-bmc - ibm,tacoma-bmc + - inventec,starscream-bmc - inventec,transformer-bmc - jabil,rbp-bmc - qcom,dc-scm-v1-bmc diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index 5c3ac97e8728..4cc4e6754681 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -66,6 +66,7 @@ properties: - description: BCM47094 based boards items: - enum: + - asus,rt-ac3100 - asus,rt-ac88u - dlink,dir-885l - dlink,dir-890l diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm53573.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm53573.yaml new file mode 100644 index 000000000000..81b9a4a641c1 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm53573.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/bcm/brcm,bcm53573.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM53573 SoCs family + +description: + Broadcom BCM53573 / BCM47189 Wi-Fi SoCs derived from Northstar. + +maintainers: + - RafaÅ‚ MiÅ‚ecki <rafal@milecki.pl> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: BCM53573 based boards + items: + - enum: + - tenda,ac6-v1 + - tenda,w15e-v1 + - const: brcm,bcm53573 + + - description: BCM47189 based boards + items: + - enum: + - brcm,bcm947189acdbmr + - luxul,xap-810-v1 + - luxul,xap-1440-v1 + - tenda,ac9 + - const: brcm,bcm47189 + - const: brcm,bcm53573 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 2510eaa8906d..70e1e5394035 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -909,6 +909,7 @@ properties: - fsl,imx8mm-evk # i.MX8MM EVK Board - fsl,imx8mm-evkb # i.MX8MM EVKB Board - gateworks,imx8mm-gw7904 + - gateworks,imx8mm-gw7905-0x # i.MX8MM Gateworks Board - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit @@ -1031,10 +1032,11 @@ properties: - beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit - dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC - fsl,imx8mp-evk # i.MX8MP EVK Board + - gateworks,imx8mp-gw71xx-2x # i.MX8MP Gateworks Board + - gateworks,imx8mp-gw72xx-2x # i.MX8MP Gateworks Board + - gateworks,imx8mp-gw73xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board - gateworks,imx8mp-gw7905-2x # i.MX8MP Gateworks Board - - polyhex,imx8mp-debix # Polyhex Debix boards - - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules @@ -1068,6 +1070,20 @@ properties: - const: phytec,imx8mp-phycore-som # phyCORE-i.MX8MP SoM - const: fsl,imx8mp + - description: Polyhex DEBIX i.MX8MP based SBCs + items: + - enum: + - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board + - const: polyhex,imx8mp-debix # Polyhex i.MX8MP Debix SBCs + - const: fsl,imx8mp + + - description: Polyhex DEBIX i.MX8MP SOM A based boards + items: + - enum: + - polyhex,imx8mp-debix-som-a-bmb-08 # Polyhex Debix SOM A on SOM A I/O board + - const: polyhex,imx8mp-debix-som-a # Polyhex Debix SOM A + - const: fsl,imx8mp + - description: Toradex Boards with Verdin iMX8M Plus Modules items: - enum: @@ -1220,6 +1236,25 @@ properties: - const: fsl,imxrt1170 - description: + TQMa93xxLA and TQMa93xxCA are two series of feature compatible SOM + using NXP i.MX93 SOC in 11x11 mm package. + TQMa93xxLA is designed to be soldered on different carrier boards. + TQMa93xxCA is a compatible variant using board to board connectors. + All SOM and CPU variants use the same device tree hence only one + compatible is needed. Bootloader disables all features not present + in the assembled SOC. + MBa93xxCA mainboard can be used as starterkit for the SOM + soldered on an adapter board or for the connector variant + MBa93xxLA mainboard is a single board computer using the solderable + SOM variant + items: + - enum: + - tq,imx93-tqma9352-mba93xxca # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM on MBa93xxCA + - tq,imx93-tqma9352-mba93xxla # TQ-Systems GmbH i.MX93 TQMa93xxLA SOM on MBa93xxLA SBC + - const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM + - const: fsl,imx93 + + - description: Freescale Vybrid Platform Device Tree Bindings For the Vybrid SoC familiy all variants with DDR controller are supported, @@ -1289,6 +1324,16 @@ properties: - fsl,ls1021a-twr - const: fsl,ls1021a + - description: + TQ-Systems TQMLS102xA is a series of socketable SOM featuring + LS102x system-on-chip variants. MBLS102xA mainboard can be used as + starterkit. + items: + - enum: + - tq,ls1021a-tqmls1021a-mbls102xa + - const: tq,ls1021a-tqmls1021a + - const: fsl,ls1021a + - description: LS1028A based Boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml index 4b4dcf551eb6..2ee0c740eb56 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -21,6 +21,11 @@ properties: - intel,socfpga-agilex-n6000 - intel,socfpga-agilex-socdk - const: intel,socfpga-agilex + - description: Agilex5 boards + items: + - enum: + - intel,socfpga-agilex5-socdk + - const: intel,socfpga-agilex5 additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index fa8b31660cad..c863ec07cbbb 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt @@ -41,14 +41,6 @@ SoC Type (optional): SoC Families: -- OMAP2 generic - defaults to OMAP2420 - compatible = "ti,omap2" -- OMAP3 generic - compatible = "ti,omap3" -- OMAP4 generic - defaults to OMAP4430 - compatible = "ti,omap4" -- OMAP5 generic - defaults to OMAP5430 - compatible = "ti,omap5" - DRA7 generic - defaults to DRA742 compatible = "ti,dra7" - AM33x generic @@ -58,32 +50,6 @@ SoC Families: SoCs: -- OMAP2420 - compatible = "ti,omap2420", "ti,omap2" -- OMAP2430 - compatible = "ti,omap2430", "ti,omap2" - -- OMAP3430 - compatible = "ti,omap3430", "ti,omap3" - legacy: "ti,omap34xx" - please do not use any more -- AM3517 - compatible = "ti,am3517", "ti,omap3" -- OMAP3630 - compatible = "ti,omap3630", "ti,omap3" - legacy: "ti,omap36xx" - please do not use any more -- AM335x - compatible = "ti,am33xx" - -- OMAP4430 - compatible = "ti,omap4430", "ti,omap4" -- OMAP4460 - compatible = "ti,omap4460", "ti,omap4" - -- OMAP5430 - compatible = "ti,omap5430", "ti,omap5" -- OMAP5432 - compatible = "ti,omap5432", "ti,omap5" - - DRA762 compatible = "ti,dra762", "ti,dra7" @@ -116,65 +82,6 @@ SoCs: Boards (incomplete list of examples): -- OMAP3 BeagleBoard : Low cost community board - compatible = "ti,omap3-beagle", "ti,omap3430", "ti,omap3" - -- OMAP3 BeagleBoard A to B4 : Early BeagleBoard revisions A to B4 with a timer quirk - compatible = "ti,omap3-beagle-ab4", "ti,omap3-beagle", "ti,omap3430", "ti,omap3" - -- OMAP3 Tobi with Overo : Commercial expansion board with daughter board - compatible = "gumstix,omap3-overo-tobi", "gumstix,omap3-overo", "ti,omap3430", "ti,omap3" - -- OMAP4 SDP : Software Development Board - compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4" - -- OMAP4 PandaBoard : Low cost community board - compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4" - -- OMAP4 DuoVero with Parlor : Commercial expansion board with daughter board - compatible = "gumstix,omap4-duovero-parlor", "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; - -- OMAP4 VAR-STK-OM44 : Commercial dev kit with VAR-OM44CustomBoard and VAR-SOM-OM44 w/WLAN - compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; - -- OMAP4 VAR-DVK-OM44 : Commercial dev kit with VAR-OM44CustomBoard, VAR-SOM-OM44 w/WLAN and LCD touchscreen - compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; - -- OMAP3 EVM : Software Development Board for OMAP35x, AM/DM37x - compatible = "ti,omap3-evm", "ti,omap3630", "ti,omap3" - -- AM335X EVM : Software Development Board for AM335x - compatible = "ti,am335x-evm", "ti,am33xx" - -- AM335X Bone : Low cost community board - compatible = "ti,am335x-bone", "ti,am33xx" - -- AM3359 ICEv2 : Low cost Industrial Communication Engine EVM. - compatible = "ti,am3359-icev2", "ti,am33xx" - -- AM335X OrionLXm : Substation Automation Platform - compatible = "novatech,am335x-lxm", "ti,am33xx" - -- AM335X phyBOARD-WEGA: Single Board Computer dev kit - compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx" - -- AM335X CM-T335 : System On Module, built around the Sitara AM3352/4 - compatible = "compulab,cm-t335", "ti,am33xx" - -- AM335X SBC-T335 : single board computer, built around the Sitara AM3352/4 - compatible = "compulab,sbc-t335", "compulab,cm-t335", "ti,am33xx" - -- AM335X phyCORE-AM335x: Development kit - compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx" - -- AM335x phyBOARD-REGOR: Single Board Computer - compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx" - -- AM335X UC-8100-ME-T: Communication-centric industrial computing platform - compatible = "moxa,uc-8100-me-t", "ti,am33xx"; - -- OMAP5 EVM : Evaluation Module - compatible = "ti,omap5-evm", "ti,omap5" - AM437x CM-T43 compatible = "compulab,am437x-cm-t43", "ti,am4372", "ti,am43" @@ -217,9 +124,3 @@ Boards (incomplete list of examples): - DRA718 EVM: Software Development Board for DRA718 compatible = "ti,dra718-evm", "ti,dra718", "ti,dra722", "ti,dra72", "ti,dra7" - -- DM3730 Logic PD Torpedo + Wireless: Commercial System on Module with WiFi and Bluetooth - compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3" - -- DM3730 Logic PD SOM-LV: Commercial System on Module with WiFi and Bluetooth - compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3" diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml index e333ec4a9c5f..97621c92a1ab 100644 --- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml @@ -31,7 +31,7 @@ properties: compatible: oneOf: # Preferred naming style for compatibles of SoC components: - - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+-.*$" + - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|sa|sc|sdm|sdx|sm)[0-9]+(pro)?-.*$" - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$" # Legacy namings - variations of existing patterns/compatibles are OK, diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 450f616774e0..adbfaea32343 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -30,6 +30,7 @@ description: | apq8084 apq8096 ipq4018 + ipq5018 ipq5332 ipq6018 ipq8074 @@ -72,6 +73,7 @@ description: | sdx65 sdx75 sm4250 + sm4450 sm6115 sm6115p sm6125 @@ -104,6 +106,7 @@ description: | hk10-c2 idp liquid + rdp432-c2 mtp qrd rb2 @@ -186,6 +189,7 @@ properties: - items: - enum: + - samsung,a7 - sony,kanuti-tulip - square,apq8039-t2 - const: qcom,msm8939 @@ -341,6 +345,11 @@ properties: - items: - enum: + - qcom,ipq5018-rdp432-c2 + - const: qcom,ipq5018 + + - items: + - enum: - qcom,ipq5332-ap-mi01.2 - qcom,ipq5332-ap-mi01.3 - qcom,ipq5332-ap-mi01.6 @@ -904,6 +913,11 @@ properties: - items: - enum: + - qcom,sm4450-qrd + - const: qcom,sm4450 + + - items: + - enum: - fxtec,pro1x - const: qcom,sm6115 diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index ecdb72a519cb..ca5389862887 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -196,6 +196,11 @@ properties: - const: firefly,rk3566-roc-pc - const: rockchip,rk3566 + - description: Firefly Station P2 + items: + - const: firefly,rk3568-roc-pc + - const: rockchip,rk3568 + - description: FriendlyElec NanoPi R2 series boards items: - enum: @@ -222,6 +227,11 @@ properties: - friendlyarm,nanopi-r5s - const: rockchip,rk3568 + - description: FriendlyElec NanoPC T6 + items: + - const: friendlyarm,nanopc-t6 + - const: rockchip,rk3588 + - description: GeekBuying GeekBox items: - const: geekbuying,geekbox @@ -694,6 +704,11 @@ properties: - const: radxa,rock-4c-plus - const: rockchip,rk3399 + - description: Radxa ROCK 4SE + items: + - const: radxa,rock-4se + - const: rockchip,rk3399 + - description: Radxa ROCK Pi E items: - const: radxa,rockpi-e diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 4466b455bffa..4bf28e717a56 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -143,7 +143,9 @@ properties: - description: Octavo OSD32MP15x System-in-Package based boards items: - enum: - - lxa,stm32mp157c-mc1 # Linux Automation MC-1 + - lxa,stm32mp157c-mc1 # Linux Automation MC-1 + - lxa,stm32mp157c-tac-gen1 # Linux Automation TAC (Generation 1) + - lxa,stm32mp157c-tac-gen2 # Linux Automation TAC (Generation 2) - const: oct,stm32mp15xx-osd32 - enum: - st,stm32mp157 diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index ee8fdd2da869..58f322b9585f 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -997,4 +997,9 @@ properties: - const: xunlong,orangepi-zero2 - const: allwinner,sun50i-h616 + - description: Xunlong OrangePi Zero 3 + items: + - const: xunlong,orangepi-zero3 + - const: allwinner,sun50i-h618 + additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt deleted file mode 100644 index 5ae601e7f51f..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,nvec.txt +++ /dev/null @@ -1,21 +0,0 @@ -NVIDIA compliant embedded controller - -Required properties: -- compatible : should be "nvidia,nvec". -- reg : the iomem of the i2c slave controller -- interrupts : the interrupt line of the i2c slave controller -- clock-frequency : the frequency of the i2c bus -- gpios : the gpio used for ec request -- slave-addr: the i2c address of the slave controller -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - Tegra20/Tegra30: - - div-clk - - fast-clk - Tegra114: - - div-clk -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - i2c diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt deleted file mode 100644 index 9a4295b54539..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-ahb.txt +++ /dev/null @@ -1,17 +0,0 @@ -NVIDIA Tegra AHB - -Required properties: -- compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For - Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain - '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124, - tegra132, or tegra210. -- reg : Should contain 1 register ranges(address and length). For - Tegra20, Tegra30, and Tegra114 chips, the value must be <0x6000c004 - 0x10c>. For Tegra124, Tegra132 and Tegra210 chips, the value should - be be <0x6000c000 0x150>. - -Example (for a Tegra20 chip): - ahb: ahb@6000c004 { - compatible = "nvidia,tegra20-ahb"; - reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ - }; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt deleted file mode 100644 index a855c1bffc0f..000000000000 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-flowctrl.txt +++ /dev/null @@ -1,18 +0,0 @@ -NVIDIA Tegra Flow Controller - -Required properties: -- compatible: Should contain one of the following: - - "nvidia,tegra20-flowctrl": for Tegra20 - - "nvidia,tegra30-flowctrl": for Tegra30 - - "nvidia,tegra114-flowctrl": for Tegra114 - - "nvidia,tegra124-flowctrl": for Tegra124 - - "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl": for Tegra132 - - "nvidia,tegra210-flowctrl": for Tegra210 -- reg: Should contain one register range (address and length) - -Example: - - flow-controller@60007000 { - compatible = "nvidia,tegra20-flowctrl"; - reg = <0x60007000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 577eee95c893..03d2a0d79fb0 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -25,6 +25,12 @@ properties: - ti,am62a7-sk - const: ti,am62a7 + - description: K3 AM62P5 SoC and Boards + items: + - enum: + - ti,am62p5-sk + - const: ti,am62p5 + - description: K3 AM625 SoC PHYTEC phyBOARD-Lyra items: - const: phytec,am625-phyboard-lyra-rdk @@ -72,6 +78,13 @@ properties: - const: phytec,am64-phycore-som - const: ti,am642 + - description: K3 AM642 SoC on TQ-Systems TQMaX4XxL SoM + items: + - enum: + - tq,am642-tqma6442l-mbax4xxl # MBaX4XxL base board + - const: tq,am642-tqma6442l + - const: ti,am642 + - description: K3 AM654 SoC items: - enum: diff --git a/Documentation/devicetree/bindings/arm/ti/omap.yaml b/Documentation/devicetree/bindings/arm/ti/omap.yaml new file mode 100644 index 000000000000..b18fc046390a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ti/omap.yaml @@ -0,0 +1,176 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ti/omap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments OMAP SoC architecture + +maintainers: + - Tony Lindgren <tony@atomide.com> + +description: Platforms based on Texas Instruments OMAP SoC architecture. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + + - description: TI OMAP2420 SoC based platforms + items: + - enum: + - nokia,n800 + - nokia,n810 + - nokia,n810-wimax + - ti,omap2420-h4 + - const: ti,omap2420 + - const: ti,omap2 + + - description: TI OMAP2430 SoC based platforms + items: + - enum: + - ti,omap2430-sdp # TI OMAP2430 SDP + - const: ti,omap2430 + - const: ti,omap2 + + - description: TI OMAP3430 SoC based platforms + items: + - enum: + - compulab,omap3-cm-t3530 + - logicpd,dm3730-som-lv-devkit # LogicPD Zoom OMAP35xx SOM-LV Development Kit + - logicpd,dm3730-torpedo-devkit # LogicPD Zoom OMAP35xx Torpedo Development Kit + - nokia,omap3-n900 + - openpandora,omap3-pandora-600mhz + - ti,omap3430-sdp + - ti,omap3-beagle + - ti,omap3-evm # TI OMAP35XX EVM (TMDSEVM3530) + - ti,omap3-ldp # TI OMAP3430 LDP (Zoom1 Labrador) + - timll,omap3-devkit8000 + - const: ti,omap3430 + - const: ti,omap3 + + - description: Early BeagleBoard revisions A to B4 with a timer quirk + items: + - const: ti,omap3-beagle-ab4 + - const: ti,omap3-beagle + - const: ti,omap3430 + - const: ti,omap3 + + - description: Gumstix Overo TI OMAP 3430/3630 boards + expansion boards + items: + - enum: + - gumstix,omap3-overo-alto35 + - gumstix,omap3-overo-chestnut43 + - gumstix,omap3-overo-gallop43 + - gumstix,omap3-overo-palo35 + - gumstix,omap3-overo-palo43 + - gumstix,omap3-overo-summit + - gumstix,omap3-overo-tobi + - gumstix,omap3-overo-tobiduo + - const: gumstix,omap3-overo + - enum: + - ti,omap3430 + - ti,omap3630 + + - description: TI OMAP3630 SoC based platforms + items: + - enum: + - amazon,omap3-echo # Amazon Echo (first generation) + - compulab,omap3-cm-t3730 + - goldelico,gta04 + - lg,omap3-sniper # LG Optimus Black + - logicpd,dm3730-som-lv-devkit # LogicPD Zoom DM3730 SOM-LV Development Kit + - logicpd,dm3730-torpedo-devkit # LogicPD Zoom DM3730 Torpedo + Wireless Development Kit + - nokia,omap3-n9 + - nokia,omap3-n950 + - openpandora,omap3-pandora-1ghz + - ti,omap3-beagle-xm + - ti,omap3-evm-37xx # TI OMAP37XX EVM (TMDSEVM3730) + - ti,omap3-zoom3 + - const: ti,omap3630 + - const: ti,omap3 + + - description: TI AM35 SoC based platforms + items: + - enum: + - compulab,omap3-sbc-t3517 # CompuLab SBC-T3517 with CM-T3517 + - teejet,mt_ventoux + - ti,am3517-craneboard # TI AM3517 CraneBoard (TMDSEVM3517) + - ti,am3517-evm # TI AM3517 EVM (AM3517/05 TMDSEVM3517) + - const: ti,am3517 + - const: ti,omap3 + + - description: TI AM33 based platform + items: + - enum: + - compulab,cm-t335 + - moxa,uc-8100-me-t + - novatech,am335x-lxm + - ti,am335x-bone + - ti,am335x-evm + - ti,am3359-icev2 + - const: ti,am33xx + + - description: Compulab board variants based on TI AM33 + items: + - enum: + - compulab,sbc-t335 + - const: compulab,cm-t335 + - const: ti,am33xx + + - description: Phytec boards based on TI AM33 + items: + - enum: + - phytec,am335x-wega + - phytec,am335x-pcm-953 + - phytec,am335x-regor + - const: phytec,am335x-phycore-som + - const: ti,am33xx + + - description: TI OMAP4430 SoC based platforms + items: + - enum: + - amazon,omap4-kc1 # Amazon Kindle Fire (first generation) + - motorola,droid4 # Motorola Droid 4 XT894 + - motorola,droid-bionic # Motorola Droid Bionic XT875 + - ti,omap4-panda + - ti,omap4-sdp + - const: ti,omap4430 + - const: ti,omap4 + + - description: OMAP4 DuoVero with Parlor expansion board/daughter board + items: + - const: gumstix,omap4-duovero-parlor + - const: gumstix,omap4-duovero + - const: ti,omap4430 + - const: ti,omap4 + + - description: TI OMAP4460 SoC based platforms + items: + - enum: + - epson,embt2ws # Epson Moverio BT-200 + - ti,omap4-panda-es + - const: ti,omap4460 + - const: ti,omap4 + + - description: VAR-OM44 boards + items: + - enum: + - variscite,var-dvk-om44 + - variscite,var-stk-om44 + - const: variscite,var-som-om44 + - const: ti,omap4460 + - const: ti,omap4 + + - description: TI OMAP5 SoC based platforms + items: + - enum: + - compulab,omap5-cm-t54 + - isee,omap5-igep0050 + - ti,omap5-uevm + - const: ti,omap5 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml new file mode 100644 index 000000000000..d120b0da7f3d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/intel,agilex5-clkmgr.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/intel,agilex5-clkmgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA Agilex5 clock manager + +maintainers: + - Dinh Nguyen <dinguyen@kernel.org> + +description: + The Intel Agilex5 Clock Manager is an integrated clock controller, which + generates and supplies clock to all the modules. + +properties: + compatible: + const: intel,agilex5-clkmgr + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clkmgr: clock-controller@10d10000 { + compatible = "intel,agilex5-clkmgr"; + reg = <0x10d10000 0x1000>; + #clock-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml index 1b2181f6d440..a9ba21144a56 100644 --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml @@ -27,7 +27,9 @@ description: | properties: compatible: - const: nvidia,tegra124-car + enum: + - nvidia,tegra124-car + - nvidia,tegra132-car reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml new file mode 100644 index 000000000000..ef84a0c95f7e --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ5018 + +maintainers: + - Sricharan Ramabadhran <quic_srichara@quicinc.com> + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ5018 + + See also:: + include/dt-bindings/clock/qcom,ipq5018-gcc.h + include/dt-bindings/reset/qcom,ipq5018-gcc.h + +properties: + compatible: + const: qcom,gcc-ipq5018 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE20 PHY0 pipe clock source + - description: PCIE20 PHY1 pipe clock source + - description: USB3 PHY pipe clock source + - description: GEPHY RX clock source + - description: GEPHY TX clock source + - description: UNIPHY RX clock source + - description: UNIPHY TX clk source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,gcc-ipq5018"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, + <&pcie20_phy0_pipe_clk>, + <&pcie20_phy1_pipe_clk>, + <&usb3_phy0_pipe_clk>, + <&gephy_rx_clk>, + <&gephy_tx_clk>, + <&uniphy_rx_clk>, + <&uniphy_tx_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml new file mode 100644 index 000000000000..3b8b85be5cd0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator + +maintainers: + - Xingyu Wu <xingyu.wu@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-ispcrg + + reg: + maxItems: 1 + + clocks: + items: + - description: ISP Top core + - description: ISP Top Axi + - description: NOC ISP Bus + - description: external DVP + + clock-names: + items: + - const: isp_top_core + - const: isp_top_axi + - const: noc_bus_isp_axi + - const: dvp_clk + + resets: + items: + - description: ISP Top core + - description: ISP Top Axi + - description: NOC ISP Bus + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. + + power-domains: + maxItems: 1 + description: + ISP domain power + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - '#clock-cells' + - '#reset-cells' + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive,jh7110-crg.h> + #include <dt-bindings/power/starfive,jh7110-pmu.h> + #include <dt-bindings/reset/starfive,jh7110-crg.h> + + ispcrg: clock-controller@19810000 { + compatible = "starfive,jh7110-ispcrg"; + reg = <0x19810000 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, + <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, + <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, + <&dvp_clk>; + clock-names = "isp_top_core", "isp_top_axi", + "noc_bus_isp_axi", "dvp_clk"; + resets = <&syscrg JH7110_SYSRST_ISP_TOP>, + <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, + <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_ISP>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml new file mode 100644 index 000000000000..be8300ce86d0 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 PLL Clock Generator + +description: + These PLLs are high speed, low jitter frequency synthesizers in the JH7110. + Each PLL works in integer mode or fraction mode, with configuration + registers in the sys syscon. So the PLLs node should be a child of + SYS-SYSCON node. + The formula for calculating frequency is + Fvco = Fref * (NI + NF) / M / Q1 + +maintainers: + - Xingyu Wu <xingyu.wu@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-pll + + clocks: + maxItems: 1 + description: Main Oscillator (24 MHz) + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + +required: + - compatible + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml new file mode 100644 index 000000000000..b64ccd84200a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-stgcrg.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 System-Top-Group Clock and Reset Generator + +maintainers: + - Xingyu Wu <xingyu.wu@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-stgcrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: HIFI4 core + - description: STG AXI/AHB + - description: USB (125 MHz) + - description: CPU Bus + - description: HIFI4 Axi + - description: NOC STG Bus + - description: APB Bus + + clock-names: + items: + - const: osc + - const: hifi4_core + - const: stg_axiahb + - const: usb_125m + - const: cpu_bus + - const: hifi4_axi + - const: nocstg_bus + - const: apb_bus + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive,jh7110-crg.h> + + stgcrg: clock-controller@10230000 { + compatible = "starfive,jh7110-stgcrg"; + reg = <0x10230000 0x10000>; + clocks = <&osc>, + <&syscrg JH7110_SYSCLK_HIFI4_CORE>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_USB_125M>, + <&syscrg JH7110_SYSCLK_CPU_BUS>, + <&syscrg JH7110_SYSCLK_HIFI4_AXI>, + <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, + <&syscrg JH7110_SYSCLK_APB_BUS>; + clock-names = "osc", "hifi4_core", + "stg_axiahb", "usb_125m", + "cpu_bus", "hifi4_axi", + "nocstg_bus", "apb_bus"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml index 84373ae31644..5ba0a885aa80 100644 --- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml @@ -27,6 +27,9 @@ properties: - description: External I2S RX left/right channel clock - description: External TDM clock - description: External audio master clock + - description: PLL0 + - description: PLL1 + - description: PLL2 - items: - description: Main Oscillator (24 MHz) @@ -38,6 +41,9 @@ properties: - description: External I2S RX left/right channel clock - description: External TDM clock - description: External audio master clock + - description: PLL0 + - description: PLL1 + - description: PLL2 clock-names: oneOf: @@ -52,6 +58,9 @@ properties: - const: i2srx_lrck_ext - const: tdm_ext - const: mclk_ext + - const: pll0_out + - const: pll1_out + - const: pll2_out - items: - const: osc @@ -63,6 +72,9 @@ properties: - const: i2srx_lrck_ext - const: tdm_ext - const: mclk_ext + - const: pll0_out + - const: pll1_out + - const: pll2_out '#clock-cells': const: 1 @@ -93,12 +105,14 @@ examples: <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, - <&tdm_ext>, <&mclk_ext>; + <&tdm_ext>, <&mclk_ext>, + <&pllclk 0>, <&pllclk 1>, <&pllclk 2>; clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", - "tdm_ext", "mclk_ext"; + "tdm_ext", "mclk_ext", + "pll0_out", "pll1_out", "pll2_out"; #clock-cells = <1>; #reset-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml new file mode 100644 index 000000000000..af77bd8c86b1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Video-Output Clock and Reset Generator + +maintainers: + - Xingyu Wu <xingyu.wu@starfivetech.com> + +properties: + compatible: + const: starfive,jh7110-voutcrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Vout Top core + - description: Vout Top Ahb + - description: Vout Top Axi + - description: Vout Top HDMI MCLK + - description: I2STX0 BCLK + - description: external HDMI pixel + + clock-names: + items: + - const: vout_src + - const: vout_top_ahb + - const: vout_top_axi + - const: vout_top_hdmitx0_mclk + - const: i2stx0_bclk + - const: hdmitx0_pixelclk + + resets: + maxItems: 1 + description: Vout Top core + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices. + + power-domains: + maxItems: 1 + description: + Vout domain power + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - '#clock-cells' + - '#reset-cells' + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive,jh7110-crg.h> + #include <dt-bindings/power/starfive,jh7110-pmu.h> + #include <dt-bindings/reset/starfive,jh7110-crg.h> + + voutcrg: clock-controller@295C0000 { + compatible = "starfive,jh7110-voutcrg"; + reg = <0x295C0000 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, + <&hdmitx0_pixelclk>; + clock-names = "vout_src", "vout_top_ahb", + "vout_top_axi", "vout_top_hdmitx0_mclk", + "i2stx0_bclk", "hdmitx0_pixelclk"; + resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_VOUT>; + }; diff --git a/Documentation/devicetree/bindings/cpu/nvidia,tegra186-ccplex-cluster.yaml b/Documentation/devicetree/bindings/cpu/nvidia,tegra186-ccplex-cluster.yaml new file mode 100644 index 000000000000..16a448974561 --- /dev/null +++ b/Documentation/devicetree/bindings/cpu/nvidia,tegra186-ccplex-cluster.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpu/nvidia,tegra186-ccplex-cluster.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 CCPLEX Cluster + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + const: nvidia,tegra186-ccplex-cluster + + reg: + maxItems: 1 + + nvidia,bpmp: + description: phandle to the BPMP used to query CPU frequency tables + $ref: /schemas/types.yaml#/definitions/phandle + +additionalProperties: false + +required: + - compatible + - reg + - nvidia,bpmp + +examples: + - | + ccplex@e000000 { + compatible = "nvidia,tegra186-ccplex-cluster"; + reg = <0x0e000000 0x400000>; + nvidia,bpmp = <&bpmp>; + }; diff --git a/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml b/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml index 77ec8bc70bf7..f0ef7685550a 100644 --- a/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml +++ b/Documentation/devicetree/bindings/crypto/ti,sa2ul.yaml @@ -66,10 +66,22 @@ patternProperties: required: - compatible - reg - - power-domains - dmas - dma-names +allOf: + - if: + properties: + compatible: + contains: + const: ti,am62-sa3ul + then: + properties: + power-domains: false + else: + required: + - power-domains + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/eeprom/at24.yaml b/Documentation/devicetree/bindings/eeprom/at24.yaml index 84af0d5f52aa..2ec37c11286c 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.yaml +++ b/Documentation/devicetree/bindings/eeprom/at24.yaml @@ -102,6 +102,9 @@ properties: # These are special cases that don't conform to the above pattern. # Each requires a standard at24 model as fallback. - items: + - const: belling,bl24c16a + - const: atmel,24c16 + - items: - enum: - rohm,br24g01 - rohm,br24t01 diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml index 833c07f1685c..c43d17f6e96b 100644 --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml @@ -57,8 +57,11 @@ description: | "#address-cells" or "#size-cells" property. The shared memory area for the IPC TX and RX between CPU and BPMP are - predefined and work on top of sysram, which is an SRAM inside the - chip. See ".../sram/sram.yaml" for the bindings. + predefined and work on top of either sysram, which is an SRAM inside the + chip, or in normal SDRAM. + See ".../sram/sram.yaml" for the bindings for the SRAM case. + See "../reserved-memory/nvidia,tegra264-bpmp-shmem.yaml" for bindings for + the SDRAM case. properties: compatible: @@ -81,6 +84,11 @@ properties: minItems: 2 maxItems: 2 + memory-region: + description: phandle to reserved memory region used for IPC between + CPU-NS and BPMP. + maxItems: 1 + "#clock-cells": const: 1 @@ -115,10 +123,15 @@ properties: additionalProperties: false +oneOf: + - required: + - memory-region + - required: + - shmem + required: - compatible - mboxes - - shmem - "#clock-cells" - "#power-domain-cells" - "#reset-cells" @@ -165,8 +178,7 @@ examples: <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; interconnect-names = "read", "write", "dma-mem", "dma-write"; iommus = <&smmu TEGRA186_SID_BPMP>; - mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB - TEGRA_HSP_DB_MASTER_BPMP>; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>; #clock-cells = <1>; #power-domain-cells = <1>; @@ -184,3 +196,20 @@ examples: #thermal-sensor-cells = <1>; }; }; + + - | + #include <dt-bindings/mailbox/tegra186-hsp.h> + + bpmp { + compatible = "nvidia,tegra186-bpmp"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; + interconnect-names = "read", "write", "dma-mem", "dma-write"; + mboxes = <&hsp_top1 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; + memory-region = <&dram_cpu_bpmp_mail>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml index bb518c831f7b..f9ffb963d6b1 100644 --- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml +++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml @@ -126,7 +126,7 @@ required: - clock-names - bosch,mram-cfg -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml index e51be1ac0362..03b5567be389 100644 --- a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml +++ b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml @@ -49,6 +49,9 @@ properties: Set if the output SYNCLKO clock should be disabled. Do not mix with microchip,synclko-125. + interrupts: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml index fe603fb1b2cc..2162f661ed5a 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml @@ -20,12 +20,17 @@ description: |+ properties: compatible: - enum: - - samsung,s3c2410-pwm # 16-bit, S3C24xx - - samsung,s3c6400-pwm # 32-bit, S3C64xx - - samsung,s5p6440-pwm # 32-bit, S5P64x0 - - samsung,s5pc100-pwm # 32-bit, S5PC100, S5PV210, Exynos4210 rev0 SoCs - - samsung,exynos4210-pwm # 32-bit, Exynos + oneOf: + - enum: + - samsung,s3c2410-pwm # 16-bit, S3C24xx + - samsung,s3c6400-pwm # 32-bit, S3C64xx + - samsung,s5p6440-pwm # 32-bit, S5P64x0 + - samsung,s5pc100-pwm # 32-bit, S5PC100, S5PV210, Exynos4210 rev0 SoCs + - samsung,exynos4210-pwm # 32-bit, Exynos + - items: + - enum: + - samsung,exynosautov9-pwm + - const: samsung,exynos4210-pwm reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml new file mode 100644 index 000000000000..f9b2f0fdc282 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra CPU-NS - BPMP IPC reserved memory + +maintainers: + - Peter De Schrijver <pdeschrijver@nvidia.com> + +description: | + Define a memory region used for communication between CPU-NS and BPMP. + Typically this node is created by the bootloader as the physical address + has to be known to both CPU-NS and BPMP for correct IPC operation. + The memory region is defined using a child node under /reserved-memory. + The sub-node is named shmem@<address>. + +allOf: + - $ref: reserved-memory.yaml + +properties: + compatible: + const: nvidia,tegra264-bpmp-shmem + + reg: + description: The physical address and size of the shared SDRAM region + +unevaluatedProperties: false + +required: + - compatible + - reg + - no-map + +examples: + - | + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + dram_cpu_bpmp_mail: shmem@f1be0000 { + compatible = "nvidia,tegra264-bpmp-shmem"; + reg = <0x0 0xf1be0000 0x0 0x2000>; + no-map; + }; + }; +... diff --git a/Documentation/devicetree/bindings/riscv/thead.yaml b/Documentation/devicetree/bindings/riscv/thead.yaml index e62f6821372e..301912dcd290 100644 --- a/Documentation/devicetree/bindings/riscv/thead.yaml +++ b/Documentation/devicetree/bindings/riscv/thead.yaml @@ -17,6 +17,10 @@ properties: const: '/' compatible: oneOf: + - description: BeagleV Ahead single board computer + items: + - const: beagle,beaglev-ahead + - const: thead,th1520 - description: Sipeed Lichee Pi 4A board for the Sipeed Lichee Module 4A items: - enum: diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt deleted file mode 100644 index f709304036c2..000000000000 --- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt +++ /dev/null @@ -1,73 +0,0 @@ -NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver. - -Required properties: -- compatible : should be, - "nvidia,tegra20-hsuart" for Tegra20, - "nvidia,tegra30-hsuart" for Tegra30, - "nvidia,tegra186-hsuart" for Tegra186, - "nvidia,tegra194-hsuart" for Tegra194. - -- reg: Should contain UART controller registers location and length. -- interrupts: Should contain UART controller interrupts. -- clocks: Must contain one entry, for the module clock. - See ../clocks/clock-bindings.txt for details. -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - serial -- dmas : Must contain an entry for each entry in dma-names. - See ../dma/dma.txt for details. -- dma-names : Must include the following entries: - - rx - - tx - -Optional properties: -- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable - only if all 8 lines of UART controller are pinmuxed. -- nvidia,adjust-baud-rates: List of entries providing percentage of baud rate - adjustment within a range. - Each entry contains sets of 3 values. Range low/high and adjusted rate. - <range_low range_high adjusted_rate> - When baud rate set on controller falls within the range mentioned in this - field, baud rate will be adjusted by percentage mentioned here. - Ex: <9600 115200 200> - Increase baud rate by 2% when set baud rate falls within range 9600 to 115200 - -Baud Rate tolerance: - Standard UART devices are expected to have tolerance for baud rate error by - -4 to +4 %. All Tegra devices till Tegra210 had this support. However, - Tegra186 chip has a known hardware issue. UART Rx baud rate tolerance level - is 0% to +4% in 1-stop config. Otherwise, the received data will have - corruption/invalid framing errors. Parker errata suggests adjusting baud - rate to be higher than the deviations observed in Tx. - - Tx deviation of connected device can be captured over scope (or noted from - its spec) for valid range and Tegra baud rate has to be set above actual - Tx baud rate observed. To do this we use nvidia,adjust-baud-rates - - As an example, consider there is deviation observed in Tx for baud rates as - listed below. - 0 to 9600 has 1% deviation - 9600 to 115200 2% deviation - This slight deviation is expcted and Tegra UART is expected to handle it. Due - to the issue stated above, baud rate on Tegra UART should be set equal to or - above deviation observed for avoiding frame errors. - Property should be set like this - nvidia,adjust-baud-rates = <0 9600 100>, - <9600 115200 200>; - -Example: - -serial@70006000 { - compatible = "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart"; - reg = <0x70006000 0x40>; - reg-shift = <2>; - interrupts = <0 36 0x04>; - nvidia,enable-modem-interrupt; - clocks = <&tegra_car 6>; - resets = <&tegra_car 6>; - reset-names = "serial"; - dmas = <&apbdma 8>, <&apbdma 8>; - dma-names = "rx", "tx"; - nvidia,adjust-baud-rates = <1000000 4000000 136>; /* 1.36% shift */ -}; diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.yaml b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.yaml new file mode 100644 index 000000000000..04d55fecf47c --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nvidia,tegra20-hsuart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-hsuart + - nvidia,tegra30-hsuart + - nvidia,tegra186-hsuart + - nvidia,tegra194-hsuart + - items: + - const: nvidia,tegra124-hsuart + - const: nvidia,tegra30-hsuart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: module clock + + resets: + items: + - description: module reset + + reset-names: + items: + - const: serial + + dmas: + items: + - description: DMA channel used for reception + - description: DMA channel used for transmission + + dma-names: + items: + - const: rx + - const: tx + + nvidia,enable-modem-interrupt: + $ref: /schemas/types.yaml#/definitions/flag + description: Enable modem interrupts. Should be enable only if all 8 lines of UART controller + are pinmuxed. + + nvidia,adjust-baud-rates: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: | + List of entries providing percentage of baud rate adjustment within a range. Each entry + contains a set of 3 values: range low/high and adjusted rate. When the baud rate set on the + controller falls within the range mentioned in this field, the baud rate will be adjusted by + percentage mentioned here. + + Example: <9600 115200 200> + + Increase baud rate by 2% when set baud rate falls within range 9600 to 115200. + + Standard UART devices are expected to have tolerance for baud rate error by -4 to +4 %. All + Tegra devices till Tegra210 had this support. However, Tegra186 chip has a known hardware + issue. UART RX baud rate tolerance level is 0% to +4% in 1-stop config. Otherwise, the + received data will have corruption/invalid framing errors. Parker errata suggests adjusting + baud rate to be higher than the deviations observed in TX. + + TX deviation of connected device can be captured over scope (or noted from its spec) for + valid range and Tegra baud rate has to be set above actual TX baud rate observed. To do this + we use nvidia,adjust-baud-rates. + + As an example, consider there is deviation observed in TX for baud rates as listed below. 0 + to 9600 has 1% deviation 9600 to 115200 2% deviation. This slight deviation is expcted and + Tegra UART is expected to handle it. Due to the issue stated above, baud rate on Tegra UART + should be set equal to or above deviation observed for avoiding frame errors. Property + should be set like this: + + nvidia,adjust-baud-rates = <0 9600 100>, + <9600 115200 200>; + items: + items: + - description: range lower bound + - description: range upper bound + - description: adjustment (in permyriad, i.e. 0.01%) + +allOf: + - $ref: serial.yaml + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - reset-names + - dmas + - dma-names + +examples: + - | + #include <dt-bindings/clock/tegra30-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + serial@70006000 { + compatible = "nvidia,tegra30-hsuart"; + reg = <0x70006000 0x40>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + nvidia,enable-modem-interrupt; + clocks = <&tegra_car TEGRA30_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; + nvidia,adjust-baud-rates = <1000000 4000000 136>; /* 1.36% shift */ + }; diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml new file mode 100644 index 000000000000..0039319e91fe --- /dev/null +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 SoC system controller + +maintainers: + - William Qiu <william.qiu@starfivetech.com> + +description: + The StarFive JH7110 SoC system controller provides register information such + as offset, mask and shift to configure related modules such as MMC and PCIe. + +properties: + compatible: + oneOf: + - items: + - const: starfive,jh7110-sys-syscon + - const: syscon + - const: simple-mfd + - items: + - enum: + - starfive,jh7110-aon-syscon + - starfive,jh7110-stg-syscon + - const: syscon + + reg: + maxItems: 1 + + clock-controller: + $ref: /schemas/clock/starfive,jh7110-pll.yaml# + type: object + + "#power-domain-cells": + const: 1 + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: starfive,jh7110-sys-syscon + then: + required: + - clock-controller + else: + properties: + clock-controller: false + - if: + properties: + compatible: + contains: + const: starfive,jh7110-aon-syscon + then: + required: + - "#power-domain-cells" + else: + properties: + "#power-domain-cells": false + +additionalProperties: false + +examples: + - | + syscon@10240000 { + compatible = "starfive,jh7110-stg-syscon", "syscon"; + reg = <0x10240000 0x1000>; + }; + + syscon@13030000 { + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; + reg = <0x13030000 0x1000>; + + clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; + }; + + syscon@17010000 { + compatible = "starfive,jh7110-aon-syscon", "syscon"; + reg = <0x17010000 0x1000>; + #power-domain-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/soc/tegra/nvidia,nvec.yaml b/Documentation/devicetree/bindings/soc/tegra/nvidia,nvec.yaml new file mode 100644 index 000000000000..d5261ce3a619 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/tegra/nvidia,nvec.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/tegra/nvidia,nvec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA compliant embedded controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + const: nvidia,nvec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: divider clock + - description: fast clock + + clock-names: + minItems: 1 + items: + - const: div-clk + - const: fast-clk + + resets: + items: + - description: module reset + + reset-names: + items: + - const: i2c + + clock-frequency: true + + request-gpios: + description: phandle to the GPIO used for EC request + + slave-addr: + $ref: /schemas/types.yaml#/definitions/uint32 + description: I2C address of the slave controller + +additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + - clock-frequency + - request-gpios + - slave-addr + +examples: + - | + #include <dt-bindings/clock/tegra20-car.h> + #include <dt-bindings/gpio/tegra-gpio.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + i2c@7000c500 { + compatible = "nvidia,nvec"; + reg = <0x7000c500 0x100>; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <80000>; + request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; + slave-addr = <138>; + clocks = <&tegra_car TEGRA20_CLK_I2C3>, + <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; + clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + }; diff --git a/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-ahb.yaml b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-ahb.yaml new file mode 100644 index 000000000000..2f7269a26b8e --- /dev/null +++ b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-ahb.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-ahb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +title: NVIDIA Tegra AHB + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-ahb + - nvidia,tegra30-ahb + - items: + - enum: + - nvidia,tegra114-ahb + - nvidia,tegra124-ahb + - nvidia,tegra210-ahb + - const: nvidia,tegra30-ahb + + reg: + maxItems: 1 + +additionalProperties: false + +required: + - compatible + - reg + +examples: + - | + ahb@6000c004 { + compatible = "nvidia,tegra20-ahb"; + reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ + }; diff --git a/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-flowctrl.yaml b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-flowctrl.yaml new file mode 100644 index 000000000000..705544b7f98f --- /dev/null +++ b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-flowctrl.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-flowctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Flow Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + oneOf: + - enum: + - nvidia,tegra20-flowctrl + - nvidia,tegra30-flowctrl + - nvidia,tegra114-flowctrl + - nvidia,tegra124-flowctrl + - nvidia,tegra210-flowctrl + + - items: + - const: nvidia,tegra132-flowctrl + - const: nvidia,tegra124-flowctrl + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + flow-controller@60007000 { + compatible = "nvidia,tegra20-flowctrl"; + reg = <0x60007000 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml index 22cf9002fee7..a08959c6e072 100644 --- a/Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml +++ b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml @@ -34,18 +34,22 @@ properties: - const: ti,am654-navss-ringacc reg: + minItems: 4 items: - description: real time registers regions - description: fifos registers regions - description: proxy gcfg registers regions - description: proxy target registers regions + - description: configuration registers region reg-names: + minItems: 4 items: - const: rt - const: fifos - const: proxy_gcfg - const: proxy_target + - const: cfg msi-parent: true @@ -80,8 +84,9 @@ examples: reg = <0x0 0x3c000000 0x0 0x400000>, <0x0 0x38000000 0x0 0x400000>, <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x33000000 0x0 0x40000>, + <0x0 0x31080000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <818>; ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ ti,sci = <&dmsc>; diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt deleted file mode 100644 index aea4a2a178b9..000000000000 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.txt +++ /dev/null @@ -1,238 +0,0 @@ -Tegra124 SOCTHERM thermal management system - -The SOCTHERM IP block contains thermal sensors, support for polled -or interrupt-based thermal monitoring, CPU and GPU throttling based -on temperature trip points, and handling external overcurrent -notifications. It is also used to manage emergency shutdown in an -overheating situation. - -Required properties : -- compatible : For Tegra124, must contain "nvidia,tegra124-soctherm". - For Tegra132, must contain "nvidia,tegra132-soctherm". - For Tegra210, must contain "nvidia,tegra210-soctherm". -- reg : Should contain at least 2 entries for each entry in reg-names: - - SOCTHERM register set - - Tegra CAR register set: Required for Tegra124 and Tegra210. - - CCROC register set: Required for Tegra132. -- reg-names : Should contain at least 2 entries: - - soctherm-reg - - car-reg - - ccroc-reg -- interrupts : Defines the interrupt used by SOCTHERM -- clocks : Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entries: - - tsensor - - soctherm -- resets : Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names : Must include the following entries: - - soctherm -- #thermal-sensor-cells : Should be 1. For a description of this property, see - Documentation/devicetree/bindings/thermal/thermal-sensor.yaml. - See <dt-bindings/thermal/tegra124-soctherm.h> for a list of valid values - when referring to thermal sensors. -- throttle-cfgs: A sub-node which is a container of configuration for each - hardware throttle events. These events can be set as cooling devices. - * throttle events: Sub-nodes must be named as "light" or "heavy". - Properties: - - nvidia,priority: Each throttles has its own throttle settings, so the - SW need to set priorities for various throttle, the HW arbiter can select - the final throttle settings. - Bigger value indicates higher priority, In general, higher priority - translates to lower target frequency. SW needs to ensure that critical - thermal alarms are given higher priority, and ensure that there is - no race if priority of two vectors is set to the same value. - The range of this value is 1~100. - - nvidia,cpu-throt-percent: This property is for Tegra124 and Tegra210. - It is the throttling depth of pulse skippers, it's the percentage - throttling. - - nvidia,cpu-throt-level: This property is only for Tegra132, it is the - level of pulse skippers, which used to throttle clock frequencies. It - indicates cpu clock throttling depth, and the depth can be programmed. - Must set as following values: - TEGRA_SOCTHERM_THROT_LEVEL_LOW, TEGRA_SOCTHERM_THROT_LEVEL_MED - TEGRA_SOCTHERM_THROT_LEVEL_HIGH, TEGRA_SOCTHERM_THROT_LEVEL_NONE - - nvidia,gpu-throt-level: This property is for Tegra124 and Tegra210. - It is the level of pulse skippers, which used to throttle clock - frequencies. It indicates gpu clock throttling depth and can be - programmed to any of the following values which represent a throttling - percentage: - TEGRA_SOCTHERM_THROT_LEVEL_NONE (0%) - TEGRA_SOCTHERM_THROT_LEVEL_LOW (50%), - TEGRA_SOCTHERM_THROT_LEVEL_MED (75%), - TEGRA_SOCTHERM_THROT_LEVEL_HIGH (85%). - - #cooling-cells: Should be 1. This cooling device only support on/off state. - For a description of this property see: - Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml - - Optional properties: The following properties are T210 specific and - valid only for OCx throttle events. - - nvidia,count-threshold: Specifies the number of OC events that are - required for triggering an interrupt. Interrupts are not triggered if - the property is missing. A value of 0 will interrupt on every OC alarm. - - nvidia,polarity-active-low: Configures the polarity of the OC alaram - signal. If present, this means assert low, otherwise assert high. - - nvidia,alarm-filter: Number of clocks to filter event. When the filter - expires (which means the OC event has not occurred for a long time), - the counter is cleared and filter is rearmed. Default value is 0. - - nvidia,throttle-period-us: Specifies the number of uSec for which - throttling is engaged after the OC event is deasserted. Default value - is 0. - -Optional properties: -- nvidia,thermtrips : When present, this property specifies the temperature at - which the soctherm hardware will assert the thermal trigger signal to the - Power Management IC, which can be configured to reset or shutdown the device. - It is an array of pairs where each pair represents a tsensor id followed by a - temperature in milli Celcius. In the absence of this property the critical - trip point will be used for thermtrip temperature. - -Note: -- the "critical" type trip points will be used to set the temperature at which -the SOC_THERM hardware will assert a thermal trigger if the "nvidia,thermtrips" -property is missing. When the thermtrips property is present, the breach of a -critical trip point is reported back to the thermal framework to implement -software shutdown. - -- the "hot" type trip points will be set to SOC_THERM hardware as the throttle -temperature. Once the temperature of this thermal zone is higher -than it, it will trigger the HW throttle event. - -Example : - - soctherm@700e2000 { - compatible = "nvidia,tegra124-soctherm"; - reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ - 0x0 0x60006000 0x0 0x400 /* CAR reg_base */ - reg-names = "soctherm-reg", "car-reg"; - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, - <&tegra_car TEGRA124_CLK_SOC_THERM>; - clock-names = "tsensor", "soctherm"; - resets = <&tegra_car 78>; - reset-names = "soctherm"; - - #thermal-sensor-cells = <1>; - - nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500 - TEGRA124_SOCTHERM_SENSOR_GPU 103000>; - - throttle-cfgs { - /* - * When the "heavy" cooling device triggered, - * the HW will skip cpu clock's pulse in 85% depth, - * skip gpu clock's pulse in 85% level - */ - throttle_heavy: heavy { - nvidia,priority = <100>; - nvidia,cpu-throt-percent = <85>; - nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; - - #cooling-cells = <1>; - }; - - /* - * When the "light" cooling device triggered, - * the HW will skip cpu clock's pulse in 50% depth, - * skip gpu clock's pulse in 50% level - */ - throttle_light: light { - nvidia,priority = <80>; - nvidia,cpu-throt-percent = <50>; - nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_LOW>; - - #cooling-cells = <1>; - }; - - /* - * If these two devices are triggered in same time, the HW throttle - * arbiter will select the highest priority as the final throttle - * settings to skip cpu pulse. - */ - - throttle_oc1: oc1 { - nvidia,priority = <50>; - nvidia,polarity-active-low; - nvidia,count-threshold = <100>; - nvidia,alarm-filter = <5100000>; - nvidia,throttle-period-us = <0>; - nvidia,cpu-throt-percent = <75>; - nvidia,gpu-throt-level = - <TEGRA_SOCTHERM_THROT_LEVEL_MED>; - }; - }; - }; - -Example: referring to Tegra132's "reg", "reg-names" and "throttle-cfgs" : - - soctherm@700e2000 { - compatible = "nvidia,tegra132-soctherm"; - reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */ - 0x0 0x70040000 0x0 0x200>; /* CCROC reg_base */; - reg-names = "soctherm-reg", "ccroc-reg"; - - throttle-cfgs { - /* - * When the "heavy" cooling device triggered, - * the HW will skip cpu clock's pulse in HIGH level - */ - throttle_heavy: heavy { - nvidia,priority = <100>; - nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; - - #cooling-cells = <1>; - }; - - /* - * When the "light" cooling device triggered, - * the HW will skip cpu clock's pulse in MED level - */ - throttle_light: light { - nvidia,priority = <80>; - nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>; - - #cooling-cells = <1>; - }; - - /* - * If these two devices are triggered in same time, the HW throttle - * arbiter will select the highest priority as the final throttle - * settings to skip cpu pulse. - */ - - }; - }; - -Example: referring to thermal sensors : - - thermal-zones { - cpu { - polling-delay-passive = <1000>; - polling-delay = <1000>; - - thermal-sensors = - <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; - - trips { - cpu_shutdown_trip: shutdown-trip { - temperature = <102500>; - hysteresis = <1000>; - type = "critical"; - }; - - cpu_throttle_trip: throttle-trip { - temperature = <100000>; - hysteresis = <1000>; - type = "hot"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_throttle_trip>; - cooling-device = <&throttle_heavy 1 1>; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml new file mode 100644 index 000000000000..04a2ba1aa946 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml @@ -0,0 +1,380 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/nvidia,tegra124-soctherm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra124 SOCTHERM Thermal Management System + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +description: The SOCTHERM IP block contains thermal sensors, support for + polled or interrupt-based thermal monitoring, CPU and GPU throttling based + on temperature trip points, and handling external overcurrent notifications. + It is also used to manage emergency shutdown in an overheating situation. + +properties: + compatible: + enum: + - nvidia,tegra124-soctherm + - nvidia,tegra132-soctherm + - nvidia,tegra210-soctherm + + reg: + maxItems: 2 + + reg-names: + maxItems: 2 + + interrupts: + items: + - description: module interrupt + - description: EDP interrupt + + interrupt-names: + items: + - const: thermal + - const: edp + + clocks: + items: + - description: thermal sensor clock + - description: module clock + + clock-names: + items: + - const: tsensor + - const: soctherm + + resets: + items: + - description: module reset + + reset-names: + items: + - const: soctherm + + "#thermal-sensor-cells": + const: 1 + + throttle-cfgs: + $ref: thermal-cooling-devices.yaml + description: A sub-node which is a container of configuration for each + hardware throttle events. These events can be set as cooling devices. + Throttle event sub-nodes must be named as "light" or "heavy". + unevaluatedProperties: false + patternProperties: + "^(light|heavy|oc1)$": + type: object + properties: + nvidia,priority: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 100 + description: Each throttles has its own throttle settings, so the + SW need to set priorities for various throttle, the HW arbiter + can select the final throttle settings. Bigger value indicates + higher priority, In general, higher priority translates to lower + target frequency. SW needs to ensure that critical thermal + alarms are given higher priority, and ensure that there is no + race if priority of two vectors is set to the same value. + + nvidia,cpu-throt-percent: + description: This property is for Tegra124 and Tegra210. It is the + throttling depth of pulse skippers, it's the percentage + throttling. + minimum: 0 + maximum: 100 + + nvidia,cpu-throt-level: + $ref: /schemas/types.yaml#/definitions/uint32 + description: This property is only for Tegra132, it is the level + of pulse skippers, which used to throttle clock frequencies. It + indicates cpu clock throttling depth, and the depth can be + programmed. + enum: + # none (TEGRA_SOCTHERM_THROT_LEVEL_NONE) + - 0 + # low (TEGRA_SOCTHERM_THROT_LEVEL_LOW) + - 1 + # medium (TEGRA_SOCTHERM_THROT_LEVEL_MED) + - 2 + # high (TEGRA_SOCTHERM_THROT_LEVEL_HIGH) + - 3 + + nvidia,gpu-throt-level: + $ref: /schemas/types.yaml#/definitions/uint32 + description: This property is for Tegra124 and Tegra210. It is the + level of pulse skippers, which used to throttle clock + frequencies. It indicates gpu clock throttling depth and can be + programmed to any of the following values which represent a + throttling percentage. + enum: + # none (0%, TEGRA_SOCTHERM_THROT_LEVEL_NONE) + - 0 + # low (50%, TEGRA_SOCTHERM_THROT_LEVEL_LOW) + - 1 + # medium (75%, TEGRA_SOCTHERM_THROT_LEVEL_MED) + - 2 + # high (85%, TEGRA_SOCTHERM_THROT_LEVEL_HIGH) + - 3 + + # optional + # Tegra210 specific and valid only for OCx throttle events + nvidia,count-threshold: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Specifies the number of OC events that are required + for triggering an interrupt. Interrupts are not triggered if the + property is missing. A value of 0 will interrupt on every OC + alarm. + + nvidia,polarity-active-low: + $ref: /schemas/types.yaml#/definitions/flag + description: Configures the polarity of the OC alaram signal. If + present, this means assert low, otherwise assert high. + + nvidia,alarm-filter: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of clocks to filter event. When the filter + expires (which means the OC event has not occurred for a long + time), the counter is cleared and filter is rearmed. + default: 0 + + nvidia,throttle-period-us: + description: Specifies the number of microseconds for which + throttling is engaged after the OC event is deasserted. + default: 0 + + # optional + nvidia,thermtrips: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: | + When present, this property specifies the temperature at which the + SOCTHERM hardware will assert the thermal trigger signal to the Power + Management IC, which can be configured to reset or shutdown the device. + It is an array of pairs where each pair represents a tsensor ID followed + by a temperature in milli Celcius. In the absence of this property the + critical trip point will be used for thermtrip temperature. + + Note: + - the "critical" type trip points will be used to set the temperature at + which the SOCTHERM hardware will assert a thermal trigger if the + "nvidia,thermtrips" property is missing. When the thermtrips property + is present, the breach of a critical trip point is reported back to + the thermal framework to implement software shutdown. + + - the "hot" type trip points will be set to SOCTHERM hardware as the + throttle temperature. Once the temperature of this thermal zone is + higher than it, it will trigger the HW throttle event. + items: + items: + - description: sensor ID + oneOf: + - description: CPU sensor + const: 0 + - description: MEM sensor + const: 1 + - description: GPU sensor + const: 2 + - description: PLLX sensor + const: 3 + - description: temperature threshold (in millidegree Celsius) + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + - "#thermal-sensor-cells" + +allOf: + - $ref: thermal-sensor.yaml + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra124-soctherm + - nvidia,tegra210-soctherm + then: + properties: + reg: + items: + - description: SOCTHERM register set + - description: clock and reset controller registers + + reg-names: + items: + - const: soctherm-reg + - const: car-reg + + else: + properties: + reg: + items: + - description: SOCTHERM register set + - description: CCROC registers + + reg-names: + items: + - const: soctherm-reg + - const: ccroc-reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra124-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/thermal/tegra124-soctherm.h> + + soctherm@700e2000 { + compatible = "nvidia,tegra124-soctherm"; + reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */ + <0x60006000 0x400>; /* CAR reg_base */ + reg-names = "soctherm-reg", "car-reg"; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "thermal", "edp"; + clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, + <&tegra_car TEGRA124_CLK_SOC_THERM>; + clock-names = "tsensor", "soctherm"; + resets = <&tegra_car 78>; + reset-names = "soctherm"; + + #thermal-sensor-cells = <1>; + + nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500>, + <TEGRA124_SOCTHERM_SENSOR_GPU 103000>; + + throttle-cfgs { + /* + * When the "heavy" cooling device triggered, + * the HW will skip cpu clock's pulse in 85% depth, + * skip gpu clock's pulse in 85% level + */ + heavy { + nvidia,priority = <100>; + nvidia,cpu-throt-percent = <85>; + nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; + + #cooling-cells = <2>; + }; + + /* + * When the "light" cooling device triggered, + * the HW will skip cpu clock's pulse in 50% depth, + * skip gpu clock's pulse in 50% level + */ + light { + nvidia,priority = <80>; + nvidia,cpu-throt-percent = <50>; + nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_LOW>; + + #cooling-cells = <2>; + }; + + /* + * If these two devices are triggered in same time, the HW throttle + * arbiter will select the highest priority as the final throttle + * settings to skip cpu pulse. + */ + + oc1 { + nvidia,priority = <50>; + nvidia,polarity-active-low; + nvidia,count-threshold = <100>; + nvidia,alarm-filter = <5100000>; + nvidia,throttle-period-us = <0>; + nvidia,cpu-throt-percent = <75>; + nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>; + }; + }; + }; + + # referring to Tegra132's "reg", "reg-names" and "throttle-cfgs" + - | + thermal-sensor@700e2000 { + compatible = "nvidia,tegra132-soctherm"; + reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */ + <0x70040000 0x200>; /* CCROC reg_base */ + reg-names = "soctherm-reg", "ccroc-reg"; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "thermal", "edp"; + clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, + <&tegra_car TEGRA124_CLK_SOC_THERM>; + clock-names = "tsensor", "soctherm"; + resets = <&tegra_car 78>; + reset-names = "soctherm"; + #thermal-sensor-cells = <1>; + + throttle-cfgs { + /* + * When the "heavy" cooling device triggered, + * the HW will skip cpu clock's pulse in HIGH level + */ + heavy { + nvidia,priority = <100>; + nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; + + #cooling-cells = <2>; + }; + + /* + * When the "light" cooling device triggered, + * the HW will skip cpu clock's pulse in MED level + */ + light { + nvidia,priority = <80>; + nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>; + + #cooling-cells = <2>; + }; + + /* + * If these two devices are triggered in same time, the HW throttle + * arbiter will select the highest priority as the final throttle + * settings to skip cpu pulse. + */ + }; + }; + + # referring to thermal sensors + - | + thermal-zones { + cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; + + trips { + cpu_shutdown_trip: shutdown-trip { + temperature = <102500>; + hysteresis = <1000>; + type = "critical"; + }; + + cpu_throttle_trip: throttle-trip { + temperature = <100000>; + hysteresis = <1000>; + type = "hot"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_throttle_trip>; + cooling-device = <&throttle_heavy 1 1>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 1dfafc339ddd..a64876a5c3ea 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -190,6 +190,8 @@ patternProperties: description: Compass Electronics Group, LLC "^beagle,.*": description: BeagleBoard.org Foundation + "^belling,.*": + description: Shanghai Belling Co., Ltd. "^bhf,.*": description: Beckhoff Automation GmbH & Co. KG "^bitmain,.*": diff --git a/MAINTAINERS b/MAINTAINERS index 7118eeaa4ea5..cc2d478c4773 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20369,6 +20369,12 @@ S: Supported F: Documentation/devicetree/bindings/mmc/starfive* F: drivers/mmc/host/dw_mmc-starfive.c +STARFIVE JH7110 SYSCON +M: William Qiu <william.qiu@starfivetech.com> +M: Xingyu Wu <xingyu.wu@starfivetech.com> +S: Supported +F: Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml + STARFIVE JH7110 TDM DRIVER M: Walker Chen <walker.chen@starfivetech.com> S: Maintained @@ -20418,6 +20424,7 @@ STARFIVE SOC DRIVERS M: Conor Dooley <conor@kernel.org> S: Maintained T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ +F: Documentation/devicetree/bindings/soc/starfive/ F: drivers/soc/starfive/ STARFIVE TRNG DRIVER diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile index 589a1ce1120a..eebb5a0c873a 100644 --- a/arch/arm/boot/dts/allwinner/Makefile +++ b/arch/arm/boot/dts/allwinner/Makefile @@ -179,6 +179,25 @@ dtb-$(CONFIG_MACH_SUN7I) += \ sun7i-a20-pcduino3-nano.dtb \ sun7i-a20-wexler-tab7200.dtb \ sun7i-a20-wits-pro-a20-dkt.dtb + +# Enables support for device-tree overlays for all pis +DTC_FLAGS_sun8i-h3-orangepi-lite := -@ +DTC_FLAGS_sun8i-h3-bananapi-m2-plus := -@ +DTC_FLAGS_sun8i-h3-nanopi-m1-plus := -@ +DTC_FLAGS_sun8i-h3-nanopi-m1 := -@ +DTC_FLAGS_sun8i-h3-nanopi-duo2 := -@ +DTC_FLAGS_sun8i-h3-orangepi-plus2e := -@ +DTC_FLAGS_sun8i-h3-orangepi-one := -@ +DTC_FLAGS_sun8i-h3-orangepi-plus := -@ +DTC_FLAGS_sun8i-h3-orangepi-2 := -@ +DTC_FLAGS_sun8i-h3-orangepi-zero-plus2 := -@ +DTC_FLAGS_sun8i-h3-nanopi-neo-air := -@ +DTC_FLAGS_sun8i-h3-zeropi := -@ +DTC_FLAGS_sun8i-h3-nanopi-neo := -@ +DTC_FLAGS_sun8i-h3-nanopi-r1 := -@ +DTC_FLAGS_sun8i-h3-orangepi-pc := -@ +DTC_FLAGS_sun8i-h3-bananapi-m2-plus-v1.2 := -@ +DTC_FLAGS_sun8i-h3-orangepi-pc-plus := -@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a23-evb.dtb \ sun8i-a23-gt90h-v4.dtb \ diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts b/arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts index 94e24b5926dd..8b3a75383816 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s-mangopi-mq-r-t113.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) // Copyright (C) 2022 Arm Ltd. #include <dt-bindings/interrupt-controller/irq.h> diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi index 804aa197a24f..c7181308ae6f 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) // Copyright (C) 2022 Arm Ltd. #define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr diff --git a/arch/arm/boot/dts/allwinner/sunxi-d1s-t113-mangopi-mq-r.dtsi b/arch/arm/boot/dts/allwinner/sunxi-d1s-t113-mangopi-mq-r.dtsi index e9bc749488bb..a415c4a78a70 100644 --- a/arch/arm/boot/dts/allwinner/sunxi-d1s-t113-mangopi-mq-r.dtsi +++ b/arch/arm/boot/dts/allwinner/sunxi-d1s-t113-mangopi-mq-r.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) // Copyright (C) 2022 Arm Ltd. /* * Common peripherals and configurations for MangoPi MQ-R boards. diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile index c68984322a86..23cbc7203a8e 100644 --- a/arch/arm/boot/dts/aspeed/Makefile +++ b/arch/arm/boot/dts/aspeed/Makefile @@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-wedge400.dtb \ aspeed-bmc-facebook-yamp.dtb \ aspeed-bmc-facebook-yosemitev2.dtb \ + aspeed-bmc-facebook-yosemite4.dtb \ aspeed-bmc-ibm-bonnell.dtb \ aspeed-bmc-ibm-everest.dtb \ aspeed-bmc-ibm-rainier.dtb \ @@ -53,6 +54,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-quanta-q71l.dtb \ aspeed-bmc-quanta-s6q.dtb \ aspeed-bmc-supermicro-x11spi.dtb \ + aspeed-bmc-inventec-starscream.dtb \ aspeed-bmc-inventec-transformers.dtb \ aspeed-bmc-tyan-s7106.dtb \ aspeed-bmc-tyan-s8036.dtb \ diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts index 1e0e88465254..0715cb9ab30c 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ampere-mtmitchell.dts @@ -4,12 +4,18 @@ /dts-v1/; #include "aspeed-g6.dtsi" +#include <dt-bindings/i2c/i2c.h> #include <dt-bindings/gpio/aspeed-gpio.h> / { model = "Ampere Mt.Mitchell BMC"; compatible = "ampere,mtmitchell-bmc", "aspeed,ast2600"; + aliases { + serial7 = &uart8; + serial8 = &uart9; + }; + chosen { stdout-path = &uart5; }; @@ -61,174 +67,192 @@ adc0mux: adc0mux { compatible = "io-channel-mux"; - io-channels = <&adc0 0>; + io-channels = <&adc_i2c_0 0>; #io-channel-cells = <1>; io-channel-names = "parent"; mux-controls = <&gpioI5mux>; + settle-time-us = <10000>; channels = "s0", "s1"; }; adc1mux: adc1mux { compatible = "io-channel-mux"; - io-channels = <&adc0 1>; + io-channels = <&adc_i2c_0 1>; #io-channel-cells = <1>; io-channel-names = "parent"; mux-controls = <&gpioI5mux>; + settle-time-us = <10000>; channels = "s0", "s1"; }; adc2mux: adc2mux { compatible = "io-channel-mux"; - io-channels = <&adc0 2>; + io-channels = <&adc_i2c_0 2>; #io-channel-cells = <1>; io-channel-names = "parent"; mux-controls = <&gpioI5mux>; + settle-time-us = <10000>; channels = "s0", "s1"; }; adc3mux: adc3mux { compatible = "io-channel-mux"; - io-channels = <&adc0 3>; + io-channels = <&adc_i2c_0 3>; #io-channel-cells = <1>; io-channel-names = "parent"; mux-controls = <&gpioI5mux>; + settle-time-us = <10000>; channels = "s0", "s1"; }; adc4mux: adc4mux { compatible = "io-channel-mux"; - io-channels = <&adc0 4>; + io-channels = <&adc_i2c_0 4>; #io-channel-cells = <1>; io-channel-names = "parent"; mux-controls = <&gpioI5mux>; + settle-time-us = <10000>; channels = "s0", "s1"; }; adc5mux: adc5mux { compatible = "io-channel-mux"; - io-channels = <&adc0 5>; + io-channels = <&adc_i2c_0 5>; #io-channel-cells = <1>; io-channel-names = "parent"; mux-controls = <&gpioI5mux>; + settle-time-us = <10000>; channels = "s0", "s1"; }; adc6mux: adc6mux { compatible = "io-channel-mux"; - io-channels = <&adc0 6>; + io-channels = <&adc_i2c_0 6>; #io-channel-cells = <1>; io-channel-names = "parent"; mux-controls = <&gpioI5mux>; + settle-time-us = <10000>; channels = "s0", "s1"; }; adc7mux: adc7mux { compatible = "io-channel-mux"; - io-channels = <&adc0 7>; + io-channels = <&adc_i2c_0 7>; #io-channel-cells = <1>; io-channel-names = "parent"; mux-controls = <&gpioI5mux>; + settle-time-us = <10000>; channels = "s0", "s1"; }; adc8mux: adc8mux { compatible = "io-channel-mux"; - io-channels = <&adc1 0>; + io-channels = <&adc_i2c_0 8>; #io-channel-cells = <1>; io-channel-names = "parent"; mux-controls = <&gpioI5mux>; + settle-time-us = <10000>; channels = "s0", "s1"; }; adc9mux: adc9mux { compatible = "io-channel-mux"; - io-channels = <&adc1 1>; + io-channels = <&adc_i2c_0 9>; #io-channel-cells = <1>; io-channel-names = "parent"; mux-controls = <&gpioI5mux>; + settle-time-us = <10000>; channels = "s0", "s1"; }; adc10mux: adc10mux { compatible = "io-channel-mux"; - io-channels = <&adc1 2>; + io-channels = <&adc_i2c_0 10>; #io-channel-cells = <1>; io-channel-names = "parent"; mux-controls = <&gpioI5mux>; + settle-time-us = <10000>; channels = "s0", "s1"; }; adc11mux: adc11mux { compatible = "io-channel-mux"; - io-channels = <&adc1 3>; + io-channels = <&adc_i2c_0 11>; #io-channel-cells = <1>; io-channel-names = "parent"; mux-controls = <&gpioI5mux>; + settle-time-us = <10000>; channels = "s0", "s1"; }; adc12mux: adc12mux { compatible = "io-channel-mux"; - io-channels = <&adc1 4>; + io-channels = <&adc_i2c_0 12>; #io-channel-cells = <1>; io-channel-names = "parent"; mux-controls = <&gpioI5mux>; + settle-time-us = <10000>; channels = "s0", "s1"; }; adc13mux: adc13mux { compatible = "io-channel-mux"; - io-channels = <&adc1 5>; + io-channels = <&adc_i2c_0 13>; #io-channel-cells = <1>; io-channel-names = "parent"; mux-controls = <&gpioI5mux>; + settle-time-us = <10000>; channels = "s0", "s1"; }; adc14mux: adc14mux { compatible = "io-channel-mux"; - io-channels = <&adc1 6>; + io-channels = <&adc_i2c_0 14>; #io-channel-cells = <1>; io-channel-names = "parent"; mux-controls = <&gpioI5mux>; + settle-time-us = <10000>; channels = "s0", "s1"; }; adc15mux: adc15mux { compatible = "io-channel-mux"; - io-channels = <&adc1 7>; + io-channels = <&adc_i2c_0 15>; #io-channel-cells = <1>; io-channel-names = "parent"; mux-controls = <&gpioI5mux>; + settle-time-us = <10000>; channels = "s0", "s1"; }; iio-hwmon { compatible = "iio-hwmon"; - io-channels = <&adc0mux 0>, <&adc0mux 1>, - <&adc1mux 0>, <&adc1mux 1>, - <&adc2mux 0>, <&adc2mux 1>, - <&adc3mux 0>, <&adc3mux 1>, - <&adc4mux 0>, <&adc4mux 1>, - <&adc5mux 0>, <&adc5mux 1>, - <&adc6mux 0>, <&adc6mux 1>, - <&adc7mux 0>, <&adc7mux 1>, - <&adc8mux 0>, <&adc8mux 1>, - <&adc9mux 0>, <&adc9mux 1>, - <&adc10mux 0>, <&adc10mux 1>, - <&adc11mux 0>, <&adc11mux 1>, - <&adc12mux 0>, <&adc12mux 1>, - <&adc13mux 0>, <&adc13mux 1>, - <&adc14mux 0>, <&adc14mux 1>, - <&adc15mux 0>, <&adc15mux 1>, - <&adc_i2c 0>, <&adc_i2c 1>, - <&adc_i2c 2>, <&adc_i2c 3>, - <&adc_i2c 4>, <&adc_i2c 5>, - <&adc_i2c 6>, <&adc_i2c 7>, - <&adc_i2c 8>, <&adc_i2c 9>, - <&adc_i2c 10>, <&adc_i2c 11>, - <&adc_i2c 12>, <&adc_i2c 13>, - <&adc_i2c 14>, <&adc_i2c 15>; + io-channels = <&adc0mux 0>, <&adc0mux 1>, + <&adc1mux 0>, <&adc1mux 1>, + <&adc2mux 0>, <&adc2mux 1>, + <&adc3mux 0>, <&adc3mux 1>, + <&adc4mux 0>, <&adc4mux 1>, + <&adc5mux 0>, <&adc5mux 1>, + <&adc6mux 0>, <&adc6mux 1>, + <&adc7mux 0>, <&adc7mux 1>, + <&adc8mux 0>, <&adc8mux 1>, + <&adc9mux 0>, <&adc9mux 1>, + <&adc10mux 0>, <&adc10mux 1>, + <&adc11mux 0>, <&adc11mux 1>, + <&adc12mux 0>, <&adc12mux 1>, + <&adc13mux 0>, <&adc13mux 1>, + <&adc14mux 0>, <&adc14mux 1>, + <&adc15mux 0>, <&adc15mux 1>, + <&adc_i2c_1 0>, <&adc_i2c_1 1>, + <&adc_i2c_1 2>, <&adc_i2c_1 3>, + <&adc_i2c_1 4>, <&adc_i2c_1 5>, + <&adc_i2c_1 6>, <&adc_i2c_1 7>, + <&adc_i2c_1 8>, <&adc_i2c_1 9>, + <&adc_i2c_1 10>, <&adc_i2c_1 11>, + <&adc_i2c_1 12>, <&adc_i2c_1 13>, + <&adc_i2c_1 14>, <&adc_i2c_1 15>, + <&adc0 0>, <&adc0 1>, + <&adc0 2>; }; }; @@ -307,6 +331,14 @@ status = "okay"; }; +&uart8 { + status = "okay"; +}; + +&uart9 { + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -336,12 +368,27 @@ &i2c3 { status = "okay"; + bus-frequency = <1000000>; + multi-master; + mctp-controller; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; }; &i2c4 { status = "okay"; - adc_i2c: adc@16 { + adc_i2c_0: adc@14 { + compatible = "lltc,ltc2497"; + reg = <0x14>; + vref-supply = <&voltage_mon_reg>; + #io-channel-cells = <1>; + }; + + adc_i2c_1: adc@16 { compatible = "lltc,ltc2497"; reg = <0x16>; vref-supply = <&voltage_mon_reg>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-bytedance-g220a.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-bytedance-g220a.dts index f75cad41ae6f..3f03a198a1a8 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-bytedance-g220a.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-bytedance-g220a.dts @@ -424,7 +424,7 @@ &i2c3 { status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; @@ -471,7 +471,7 @@ &i2c6 { status = "okay"; - i2c-switch@72 { + i2c-mux@72 { compatible = "nxp,pca9548"; reg = <0x72>; #address-cells = <1>; @@ -524,7 +524,7 @@ }; }; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; @@ -533,7 +533,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9546"; reg = <0x71>; #address-cells = <1>; @@ -569,7 +569,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9546"; reg = <0x71>; #address-cells = <1>; @@ -605,7 +605,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9546"; reg = <0x71>; #address-cells = <1>; @@ -640,7 +640,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <3>; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9546"; reg = <0x71>; #address-cells = <1>; @@ -808,7 +808,7 @@ &i2c10 { status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; @@ -838,7 +838,7 @@ }; }; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9546"; reg = <0x71>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cloudripper.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cloudripper.dts index 5cd060029ea9..d49328fa487a 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cloudripper.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cloudripper.dts @@ -132,7 +132,7 @@ * PCA9548 (1-0070) provides 8 channels connecting to SMB (Switch * Main Board). */ - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -194,7 +194,7 @@ * PCA9548 (2-0070) provides 8 channels connecting to SCM (System * Controller Module). */ - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -256,7 +256,7 @@ * PCA9548 (3-0070) provides 8 channels connecting to SMB (Switch * Main Board). */ - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -423,7 +423,7 @@ * PCA9548 (8-0070) provides 8 channels connecting to PDB (Power * Delivery Board). */ - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -486,7 +486,7 @@ * PCA9548 (15-0076) provides 8 channels connecting to FCM (Fan * Controller Module). */ - i2c-switch@76 { + i2c-mux@76 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cmm.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cmm.dts index 90a3f485c67a..24153868cc00 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cmm.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-cmm.dts @@ -328,7 +328,7 @@ &i2c1 { status = "okay"; - i2c-switch@77 { + i2c-mux@77 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -341,7 +341,7 @@ #size-cells = <0>; reg = <0>; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -390,7 +390,7 @@ }; }; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -446,7 +446,7 @@ #size-cells = <0>; reg = <1>; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -495,7 +495,7 @@ }; }; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -551,7 +551,7 @@ #size-cells = <0>; reg = <2>; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -600,7 +600,7 @@ }; }; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -656,7 +656,7 @@ #size-cells = <0>; reg = <3>; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -705,7 +705,7 @@ }; }; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -761,7 +761,7 @@ #size-cells = <0>; reg = <4>; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -810,7 +810,7 @@ }; }; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -866,7 +866,7 @@ #size-cells = <0>; reg = <5>; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -915,7 +915,7 @@ }; }; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -971,7 +971,7 @@ #size-cells = <0>; reg = <6>; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1020,7 +1020,7 @@ }; }; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1076,7 +1076,7 @@ #size-cells = <0>; reg = <7>; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1125,7 +1125,7 @@ }; }; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1183,7 +1183,7 @@ &i2c2 { status = "okay"; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1281,7 +1281,7 @@ &i2c8 { status = "okay"; - i2c-switch@77 { + i2c-mux@77 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1294,7 +1294,7 @@ #size-cells = <0>; reg = <0>; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1350,7 +1350,7 @@ #size-cells = <0>; reg = <1>; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1406,7 +1406,7 @@ #size-cells = <0>; reg = <2>; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1462,7 +1462,7 @@ #size-cells = <0>; reg = <3>; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts index b5cd4c7800b0..74f3c67e0eff 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dts @@ -65,7 +65,7 @@ }; &i2c2 { - i2c-switch@75 { + i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -123,7 +123,7 @@ }; &i2c5 { - i2c-switch@75 { + i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts index 6b319f34a9b9..f23c26a3441d 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-fuji.dts @@ -233,7 +233,7 @@ * PCA9548 (2-0070) provides 8 channels connecting to SCM (System * Controller Module). */ - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -303,7 +303,7 @@ * PCA9548 (8-0070) provides 8 channels connecting to SMB (Switch * Main Board). */ - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -315,7 +315,7 @@ #size-cells = <0>; reg = <0>; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -481,7 +481,7 @@ #size-cells = <0>; reg = <1>; - i2c-switch@72 { + i2c-mux@72 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -544,7 +544,7 @@ #size-cells = <0>; reg = <2>; - i2c-switch@76 { + i2c-mux@76 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -615,7 +615,7 @@ #size-cells = <0>; reg = <3>; - i2c-switch@76 { + i2c-mux@76 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -715,7 +715,7 @@ * PCA9548 (11-0077) provides 8 channels connecting to SMB (Switch * Main Board). */ - i2c-switch@77 { + i2c-mux@77 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -727,7 +727,7 @@ #size-cells = <0>; reg = <0>; - i2c-switch@76 { + i2c-mux@76 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -790,7 +790,7 @@ #size-cells = <0>; reg = <1>; - i2c-switch@76 { + i2c-mux@76 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -853,7 +853,7 @@ #size-cells = <0>; reg = <2>; - i2c-switch@76 { + i2c-mux@76 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -916,7 +916,7 @@ #size-cells = <0>; reg = <3>; - i2c-switch@76 { + i2c-mux@76 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -979,7 +979,7 @@ #size-cells = <0>; reg = <4>; - i2c-switch@76 { + i2c-mux@76 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1042,7 +1042,7 @@ #size-cells = <0>; reg = <5>; - i2c-switch@76 { + i2c-mux@76 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1105,7 +1105,7 @@ #size-cells = <0>; reg = <6>; - i2c-switch@76 { + i2c-mux@76 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1168,7 +1168,7 @@ #size-cells = <0>; reg = <7>; - i2c-switch@76 { + i2c-mux@76 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minipack.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minipack.dts index 230d16cd9967..aafd1042b6e5 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minipack.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-minipack.dts @@ -344,7 +344,7 @@ * I2C Switch 2-0070 is connecting to SCM (System Controller * Module). */ - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -425,7 +425,7 @@ &i2c8 { status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -441,7 +441,7 @@ #size-cells = <0>; reg = <0>; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -507,7 +507,7 @@ #size-cells = <0>; reg = <1>; - i2c-switch@72 { + i2c-mux@72 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -573,7 +573,7 @@ #size-cells = <0>; reg = <2>; - i2c-switch@76 { + i2c-mux@76 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -639,7 +639,7 @@ #size-cells = <0>; reg = <3>; - i2c-switch@76 { + i2c-mux@76 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -729,7 +729,7 @@ * I2C Switch 9-0070 is connecting to MAC/PHY EEPROMs on SMB * (Switch Main Board). */ - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -793,7 +793,7 @@ &i2c11 { status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -809,7 +809,7 @@ #size-cells = <0>; reg = <0>; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -875,7 +875,7 @@ #size-cells = <0>; reg = <1>; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -941,7 +941,7 @@ #size-cells = <0>; reg = <2>; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1007,7 +1007,7 @@ #size-cells = <0>; reg = <3>; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1073,7 +1073,7 @@ #size-cells = <0>; reg = <4>; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1139,7 +1139,7 @@ #size-cells = <0>; reg = <5>; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1205,7 +1205,7 @@ #size-cells = <0>; reg = <6>; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -1271,7 +1271,7 @@ #size-cells = <0>; reg = <7>; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-tiogapass.dts index b6b16356f571..704ee684e0fb 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-tiogapass.dts @@ -211,7 +211,7 @@ &i2c1 { status = "okay"; //X24 Riser - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; @@ -243,7 +243,7 @@ pagesize = <32>; }; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9546"; #address-cells = <1>; #size-cells = <0>; @@ -303,7 +303,7 @@ pagesize = <32>; }; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9546"; #address-cells = <1>; #size-cells = <0>; @@ -363,7 +363,7 @@ pagesize = <32>; }; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9546"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge100.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge100.dts index 584efa528450..97cd11c3d9a5 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge100.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge100.dts @@ -44,7 +44,7 @@ }; &i2c7 { - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts index ed305948386f..a677c827e758 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-wedge400.dts @@ -59,7 +59,8 @@ ast-adc-hwmon { compatible = "iio-hwmon"; - io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>, + <&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>; }; /* @@ -138,7 +139,7 @@ &i2c2 { status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -218,7 +219,7 @@ &i2c8 { status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -287,7 +288,7 @@ &i2c11 { status = "okay"; - i2c-switch@76 { + i2c-mux@76 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -366,6 +367,7 @@ }; &sdhci1 { + max-frequency = <25000000>; /* * DMA mode needs to be disabled to avoid conflicts with UHCI * Controller in AST2500 SoC. diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yamp.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yamp.dts index 5e6105874217..98fe0d6c8188 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yamp.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yamp.dts @@ -57,7 +57,7 @@ &i2c2 { status = "okay"; - i2c-switch@75 { + i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts new file mode 100644 index 000000000000..64075cc41d92 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts @@ -0,0 +1,624 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2022 Facebook Inc. + +/dts-v1/; +#include "aspeed-g6.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/leds/leds-pca955x.h> +#include <dt-bindings/i2c/i2c.h> + +/ { + model = "Facebook Yosemite 4 BMC"; + compatible = "facebook,yosemite4-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + serial7 = &uart8; + serial8 = &uart9; + }; + + chosen { + stdout-path = "serial4:57600n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 0>, <&adc1 1>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&uart6 { + status = "okay"; +}; + +&uart7 { + status = "okay"; +}; + +&uart8 { + status = "okay"; +}; + +&uart9 { + status = "okay"; +}; + +&wdt1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; +}; + +&mac2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; + use-ncsi; + mlx,multi-host; +}; + +&mac3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + use-ncsi; + mlx,multi-host; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; + flash@1 { + status = "okay"; + m25p,fast-read; + label = "bmc2"; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + }; +}; + +&i2c0 { + status = "okay"; + mctp-controller; + bus-frequency = <400000>; + multi-master; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + power-sensor@40 { + compatible = "adi,adm1278"; + reg = <0x40>; + }; +}; + +&i2c1 { + status = "okay"; + mctp-controller; + bus-frequency = <400000>; + multi-master; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + power-sensor@40 { + compatible = "adi,adm1278"; + reg = <0x40>; + }; +}; + +&i2c2 { + status = "okay"; + mctp-controller; + bus-frequency = <400000>; + multi-master; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + power-sensor@40 { + compatible = "adi,adm1278"; + reg = <0x40>; + }; +}; + +&i2c3 { + status = "okay"; + mctp-controller; + bus-frequency = <400000>; + multi-master; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + power-sensor@40 { + compatible = "adi,adm1278"; + reg = <0x40>; + }; +}; + +&i2c4 { + status = "okay"; + mctp-controller; + bus-frequency = <400000>; + multi-master; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + power-sensor@40 { + compatible = "adi,adm1278"; + reg = <0x40>; + }; +}; + +&i2c5 { + status = "okay"; + mctp-controller; + bus-frequency = <400000>; + multi-master; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + power-sensor@40 { + compatible = "adi,adm1278"; + reg = <0x40>; + }; +}; + +&i2c6 { + status = "okay"; + mctp-controller; + bus-frequency = <400000>; + multi-master; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + power-sensor@40 { + compatible = "adi,adm1278"; + reg = <0x40>; + }; +}; + +&i2c7 { + status = "okay"; + mctp-controller; + bus-frequency = <400000>; + multi-master; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + power-sensor@40 { + compatible = "adi,adm1278"; + reg = <0x40>; + }; +}; + +&i2c8 { + status = "okay"; + bus-frequency = <400000>; + i2c-mux@70 { + compatible = "nxp,pca9544"; + idle-state = <0>; + i2c-mux-idle-disconnect; + reg = <0x70>; + }; +}; + +&i2c9 { + status = "okay"; + bus-frequency = <400000>; + i2c-mux@71 { + compatible = "nxp,pca9544"; + idle-state = <0>; + i2c-mux-idle-disconnect; + reg = <0x71>; + }; +}; + +&i2c10 { + status = "okay"; + bus-frequency = <400000>; +}; + +&i2c11 { + status = "okay"; + power-sensor@10 { + compatible = "adi, adm1272"; + reg = <0x10>; + }; + + power-sensor@12 { + compatible = "adi, adm1272"; + reg = <0x12>; + }; + + gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + + temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + + temperature-sensor@4a { + compatible = "ti,tmp75"; + reg = <0x4a>; + }; + + temperature-sensor@4b { + compatible = "ti,tmp75"; + reg = <0x4b>; + }; + + eeprom@54 { + compatible = "atmel,24c256"; + reg = <0x54>; + }; +}; + +&i2c12 { + status = "okay"; + bus-frequency = <400000>; + + temperature-sensor@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + rtc@6f { + compatible = "nuvoton,nct3018y"; + reg = <0x6f>; + }; +}; + +&i2c13 { + status = "okay"; + bus-frequency = <400000>; +}; + +&i2c14 { + status = "okay"; + bus-frequency = <400000>; + adc@1d { + compatible = "ti,adc128d818"; + reg = <0x1d>; + ti,mode = /bits/ 8 <2>; + }; + + adc@35 { + compatible = "ti,adc128d818"; + reg = <0x35>; + ti,mode = /bits/ 8 <2>; + }; + + adc@37 { + compatible = "ti,adc128d818"; + reg = <0x37>; + ti,mode = /bits/ 8 <2>; + }; + + power-sensor@40 { + compatible = "ti,ina230"; + reg = <0x40>; + }; + + power-sensor@41 { + compatible = "ti,ina230"; + reg = <0x41>; + }; + + power-sensor@42 { + compatible = "ti,ina230"; + reg = <0x42>; + }; + + power-sensor@43 { + compatible = "ti,ina230"; + reg = <0x43>; + }; + + power-sensor@44 { + compatible = "ti,ina230"; + reg = <0x44>; + }; + + temperature-sensor@4e { + compatible = "ti,tmp75"; + reg = <0x4e>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp75"; + reg = <0x4f>; + }; + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + + i2c-mux@71 { + compatible = "nxp,pca9846"; + #address-cells = <1>; + #size-cells = <0>; + + idle-state = <0>; + i2c-mux-idle-disconnect; + reg = <0x71>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + adc@1f { + compatible = "ti,adc128d818"; + reg = <0x1f>; + ti,mode = /bits/ 8 <2>; + }; + + pwm@20{ + compatible = "max31790"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + }; + + gpio@22{ + compatible = "ti,tca6424"; + reg = <0x22>; + }; + + pwm@23{ + compatible = "max31790"; + reg = <0x23>; + #address-cells = <1>; + #size-cells = <0>; + }; + + adc@33 { + compatible = "maxim,max11615"; + reg = <0x33>; + }; + + eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + }; + + gpio@61 { + compatible = "nxp,pca9552"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + adc@1f { + compatible = "ti,adc128d818"; + reg = <0x1f>; + ti,mode = /bits/ 8 <2>; + }; + + pwm@20{ + compatible = "max31790"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + }; + + gpio@22{ + compatible = "ti,tca6424"; + reg = <0x22>; + }; + + pwm@23{ + compatible = "max31790"; + reg = <0x23>; + #address-cells = <1>; + #size-cells = <0>; + }; + + adc@33 { + compatible = "maxim,max11615"; + reg = <0x33>; + }; + + eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + }; + + gpio@61 { + compatible = "nxp,pca9552"; + reg = <0x61>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; + + i2c-mux@73 { + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + + idle-state = <0>; + i2c-mux-idle-disconnect; + reg = <0x73>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + adc@35 { + compatible = "maxim,max11617"; + reg = <0x35>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + adc@35 { + compatible = "maxim,max11617"; + reg = <0x35>; + }; + }; + }; +}; + +&i2c15 { + status = "okay"; + mctp-controller; + multi-master; + bus-frequency = <400000>; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + i2c-mux@72 { + compatible = "nxp,pca9544"; + idle-state = <0>; + i2c-mux-idle-disconnect; + reg = <0x72>; + }; +}; + +&adc0 { + ref_voltage = <2500>; + status = "okay"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + ref_voltage = <2500>; + status = "okay"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default>; +}; + + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts index 81902cbe662c..d47ce4edc67c 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-bonnell.dts @@ -12,38 +12,11 @@ compatible = "ibm,bonnell-bmc", "aspeed,ast2600"; aliases { - i2c100 = &cfam0_i2c0; - i2c101 = &cfam0_i2c1; - i2c110 = &cfam0_i2c10; - i2c111 = &cfam0_i2c11; - i2c112 = &cfam0_i2c12; - i2c113 = &cfam0_i2c13; - i2c114 = &cfam0_i2c14; - i2c115 = &cfam0_i2c15; - i2c202 = &cfam1_i2c2; - i2c203 = &cfam1_i2c3; - i2c210 = &cfam1_i2c10; - i2c211 = &cfam1_i2c11; - i2c214 = &cfam1_i2c14; - i2c215 = &cfam1_i2c15; - i2c216 = &cfam1_i2c16; - i2c217 = &cfam1_i2c17; - serial4 = &uart5; i2c16 = &i2c11mux0chn0; i2c17 = &i2c11mux0chn1; i2c18 = &i2c11mux0chn2; i2c19 = &i2c11mux0chn3; - - spi10 = &cfam0_spi0; - spi11 = &cfam0_spi1; - spi12 = &cfam0_spi2; - spi13 = &cfam0_spi3; - spi20 = &cfam1_spi0; - spi21 = &cfam1_spi1; - spi22 = &cfam1_spi2; - spi23 = &cfam1_spi3; - }; chosen { @@ -197,313 +170,6 @@ clk-phase-mmc-hs200 = <180>, <180>; }; -&fsim0 { - status = "okay"; - - #address-cells = <2>; - #size-cells = <0>; - - cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_i2c0: i2c-bus@0 { - reg = <0>; /* OMI01 */ - }; - - cfam0_i2c1: i2c-bus@1 { - reg = <1>; /* OMI23 */ - }; - - cfam0_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam0_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam0_i2c12: i2c-bus@c { - reg = <12>; /* OP4A */ - }; - - cfam0_i2c13: i2c-bus@d { - reg = <13>; /* OP4B */ - }; - - cfam0_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam0_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam0_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam0_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam0_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ0: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub0: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - }; - }; -}; - -&fsi_hub0 { - cfam@1,0 { - reg = <1 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <1>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_i2c2: i2c-bus@2 { - reg = <2>; /* OMI45 */ - }; - - cfam1_i2c3: i2c-bus@3 { - reg = <3>; /* OMI67 */ - }; - - cfam1_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam1_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam1_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam1_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - - cfam1_i2c16: i2c-bus@10 { - reg = <16>; /* OP6A */ - }; - - cfam1_i2c17: i2c-bus@11 { - reg = <17>; /* OP6B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam1_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam1_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam1_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ1: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub1: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; -}; - &ibt { status = "okay"; }; @@ -913,3 +579,33 @@ aspeed,lpc-io-reg = <0xca2>; aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; }; + +#include "ibm-power10-dual.dtsi" + +&cfam0_i2c10 { + eeprom@50 { + compatible = "atmel,at30tse004a"; + reg = <0x50>; + }; +}; + +&cfam0_i2c11 { + eeprom@50 { + compatible = "atmel,at30tse004a"; + reg = <0x50>; + }; +}; + +&cfam0_i2c12 { + eeprom@50 { + compatible = "atmel,at30tse004a"; + reg = <0x50>; + }; +}; + +&cfam0_i2c13 { + eeprom@50 { + compatible = "atmel,at30tse004a"; + reg = <0x50>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts index c6f8f20914d1..214b2e6a4c6d 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-everest.dts @@ -12,38 +12,6 @@ compatible = "ibm,everest-bmc", "aspeed,ast2600"; aliases { - i2c100 = &cfam0_i2c0; - i2c101 = &cfam0_i2c1; - i2c110 = &cfam0_i2c10; - i2c111 = &cfam0_i2c11; - i2c112 = &cfam0_i2c12; - i2c113 = &cfam0_i2c13; - i2c114 = &cfam0_i2c14; - i2c115 = &cfam0_i2c15; - i2c202 = &cfam1_i2c2; - i2c203 = &cfam1_i2c3; - i2c210 = &cfam1_i2c10; - i2c211 = &cfam1_i2c11; - i2c214 = &cfam1_i2c14; - i2c215 = &cfam1_i2c15; - i2c216 = &cfam1_i2c16; - i2c217 = &cfam1_i2c17; - i2c300 = &cfam2_i2c0; - i2c301 = &cfam2_i2c1; - i2c310 = &cfam2_i2c10; - i2c311 = &cfam2_i2c11; - i2c312 = &cfam2_i2c12; - i2c313 = &cfam2_i2c13; - i2c314 = &cfam2_i2c14; - i2c315 = &cfam2_i2c15; - i2c402 = &cfam3_i2c2; - i2c403 = &cfam3_i2c3; - i2c410 = &cfam3_i2c10; - i2c411 = &cfam3_i2c11; - i2c414 = &cfam3_i2c14; - i2c415 = &cfam3_i2c15; - i2c416 = &cfam3_i2c16; - i2c417 = &cfam3_i2c17; i2c500 = &cfam4_i2c0; i2c501 = &cfam4_i2c1; i2c510 = &cfam4_i2c10; @@ -113,22 +81,72 @@ serial4 = &uart5; - spi10 = &cfam0_spi0; - spi11 = &cfam0_spi1; - spi12 = &cfam0_spi2; - spi13 = &cfam0_spi3; - spi20 = &cfam1_spi0; - spi21 = &cfam1_spi1; - spi22 = &cfam1_spi2; - spi23 = &cfam1_spi3; - spi30 = &cfam2_spi0; - spi31 = &cfam2_spi1; - spi32 = &cfam2_spi2; - spi33 = &cfam2_spi3; - spi40 = &cfam3_spi0; - spi41 = &cfam3_spi1; - spi42 = &cfam3_spi2; - spi43 = &cfam3_spi3; + sbefifo500 = &sbefifo500; + sbefifo501 = &sbefifo501; + sbefifo510 = &sbefifo510; + sbefifo511 = &sbefifo511; + sbefifo512 = &sbefifo512; + sbefifo513 = &sbefifo513; + sbefifo514 = &sbefifo514; + sbefifo515 = &sbefifo515; + sbefifo602 = &sbefifo602; + sbefifo603 = &sbefifo603; + sbefifo610 = &sbefifo610; + sbefifo611 = &sbefifo611; + sbefifo614 = &sbefifo614; + sbefifo615 = &sbefifo615; + sbefifo616 = &sbefifo616; + sbefifo617 = &sbefifo617; + sbefifo700 = &sbefifo700; + sbefifo701 = &sbefifo701; + sbefifo710 = &sbefifo710; + sbefifo711 = &sbefifo711; + sbefifo712 = &sbefifo712; + sbefifo713 = &sbefifo713; + sbefifo714 = &sbefifo714; + sbefifo715 = &sbefifo715; + sbefifo802 = &sbefifo802; + sbefifo803 = &sbefifo803; + sbefifo810 = &sbefifo810; + sbefifo811 = &sbefifo811; + sbefifo814 = &sbefifo814; + sbefifo815 = &sbefifo815; + sbefifo816 = &sbefifo816; + sbefifo817 = &sbefifo817; + + scom500 = &scom500; + scom501 = &scom501; + scom510 = &scom510; + scom511 = &scom511; + scom512 = &scom512; + scom513 = &scom513; + scom514 = &scom514; + scom515 = &scom515; + scom602 = &scom602; + scom603 = &scom603; + scom610 = &scom610; + scom611 = &scom611; + scom614 = &scom614; + scom615 = &scom615; + scom616 = &scom616; + scom617 = &scom617; + scom700 = &scom700; + scom701 = &scom701; + scom710 = &scom710; + scom711 = &scom711; + scom712 = &scom712; + scom713 = &scom713; + scom714 = &scom714; + scom715 = &scom715; + scom802 = &scom802; + scom803 = &scom803; + scom810 = &scom810; + scom811 = &scom811; + scom814 = &scom814; + scom815 = &scom815; + scom816 = &scom816; + scom817 = &scom817; + spi50 = &cfam4_spi0; spi51 = &cfam4_spi1; spi52 = &cfam4_spi2; @@ -399,7 +417,7 @@ "expander-cable-card5"; }; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; @@ -544,7 +562,7 @@ "expander-cable-card11"; }; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; @@ -701,7 +719,7 @@ &i2c6 { status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; @@ -1792,7 +1810,7 @@ reg = <0x50>; }; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; @@ -1929,7 +1947,7 @@ reg = <(0x62 | I2C_OWN_SLAVE_ADDRESS)>; }; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; @@ -2188,7 +2206,7 @@ }; }; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9546"; reg = <0x71>; #address-cells = <1>; @@ -2241,7 +2259,7 @@ &i2c15 { status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; @@ -2293,7 +2311,7 @@ }; }; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9546"; reg = <0x71>; #address-cells = <1>; @@ -2345,7 +2363,7 @@ }; }; - i2c-switch@72 { + i2c-mux@72 { compatible = "nxp,pca9546"; reg = <0x72>; #address-cells = <1>; @@ -2413,172 +2431,85 @@ clk-phase-mmc-hs200 = <210>, <228>; }; -&fsim0 { +&ibt { status = "okay"; +}; - #address-cells = <2>; - #size-cells = <0>; - - /* - * CFAM Reset is supposed to be active low but pass1 hardware is wired - * active high. - */ - cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; - - cfam@0,0 { /* DCM0_C0 */ - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_i2c0: i2c-bus@0 { - reg = <0>; /* OMI01 */ - }; - - cfam0_i2c1: i2c-bus@1 { - reg = <1>; /* OMI23 */ - }; - - cfam0_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam0_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam0_i2c12: i2c-bus@c { - reg = <12>; /* OP4A */ - }; - - cfam0_i2c13: i2c-bus@d { - reg = <13>; /* OP4B */ - }; - - cfam0_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam0_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam0_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; +&uart2 { + status = "okay"; +}; - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; +&vuart1 { + status = "okay"; +}; - cfam0_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; +&vuart2 { + status = "okay"; +}; - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; +}; - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; +&mac2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, + <&syscon ASPEED_CLK_MAC3RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; - cfam0_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; +&mac3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>, + <&syscon ASPEED_CLK_MAC4RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; +&wdt2 { + status = "okay"; +}; - fsi_occ0: occ { - compatible = "ibm,p10-occ"; +&xdma { + status = "okay"; + memory-region = <&vga_memory>; +}; - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; +&kcs2 { + status = "okay"; + aspeed,lpc-io-reg = <0xca8 0xcac>; +}; - fsi_hub0: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - }; - }; +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; + aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; }; +#include "ibm-power10-quad.dtsi" + &fsi_hub0 { - cfam@1,0 { /* DCM0_C1 */ - reg = <1 0>; + cfam@4,0 { /* DCM2_C0 */ + reg = <4 0>; #address-cells = <1>; #size-cells = <1>; - chip-id = <1>; + chip-id = <4>; scom@1000 { compatible = "ibm,fsi2pib"; @@ -2591,185 +2522,260 @@ #address-cells = <1>; #size-cells = <0>; - cfam1_i2c2: i2c-bus@2 { - reg = <2>; /* OMI45 */ - }; + cfam4_i2c0: i2c-bus@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* OM01 */ - cfam1_i2c3: i2c-bus@3 { - reg = <3>; /* OMI67 */ - }; + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; - cfam1_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; - cfam1_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; + scom500: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; - cfam1_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ + sbefifo500: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; - cfam1_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; + cfam4_i2c1: i2c-bus@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* OM23 */ - cfam1_i2c16: i2c-bus@10 { - reg = <16>; /* OP6A */ - }; + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; - cfam1_i2c17: i2c-bus@11 { - reg = <17>; /* OP6B */ - }; - }; + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; + scom501: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; - cfam1_spi0: spi@0 { - reg = <0x0>; + sbefifo501: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + cfam4_i2c10: i2c-bus@a { #address-cells = <1>; #size-cells = <0>; + reg = <10>; /* OP3A */ - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom510: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo510: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; - cfam1_spi1: spi@20 { - reg = <0x20>; + cfam4_i2c11: i2c-bus@b { #address-cells = <1>; #size-cells = <0>; + reg = <11>; /* OP3B */ - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom511: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo511: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; - cfam1_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; + cfam4_i2c12: i2c-bus@c { #address-cells = <1>; #size-cells = <0>; + reg = <12>; /* OP4A */ - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom512: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo512: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; - cfam1_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; + cfam4_i2c13: i2c-bus@d { #address-cells = <1>; #size-cells = <0>; + reg = <13>; /* OP4B */ - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; + scom513: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; - fsi_occ1: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; + sbefifo513: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; - }; - fsi_hub1: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; - - cfam@2,0 { /* DCM1_C0 */ - reg = <2 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <2>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; + cfam4_i2c14: i2c-bus@e { + #address-cells = <1>; + #size-cells = <0>; + reg = <14>; /* OP5A */ - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; - cfam2_i2c0: i2c-bus@0 { - reg = <0>; /* OM01 */ - }; + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; - cfam2_i2c1: i2c-bus@1 { - reg = <1>; /* OM23 */ - }; + scom514: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; - cfam2_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ + sbefifo514: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; - cfam2_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; + cfam4_i2c15: i2c-bus@f { + #address-cells = <1>; + #size-cells = <0>; + reg = <15>; /* OP5B */ - cfam2_i2c12: i2c-bus@c { - reg = <12>; /* OP4A */ - }; + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; - cfam2_i2c13: i2c-bus@d { - reg = <13>; /* OP4B */ - }; + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; - cfam2_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; + scom515: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; - cfam2_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ + sbefifo515: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; }; @@ -2779,7 +2785,7 @@ #address-cells = <1>; #size-cells = <0>; - cfam2_spi0: spi@0 { + cfam4_spi0: spi@0 { reg = <0x0>; #address-cells = <1>; #size-cells = <0>; @@ -2795,7 +2801,7 @@ }; }; - cfam2_spi1: spi@20 { + cfam4_spi1: spi@20 { reg = <0x20>; #address-cells = <1>; #size-cells = <0>; @@ -2811,9 +2817,9 @@ }; }; - cfam2_spi2: spi@40 { + cfam4_spi2: spi@40 { reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; + compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -2828,9 +2834,9 @@ }; }; - cfam2_spi3: spi@60 { + cfam4_spi3: spi@60 { reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; + compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -2852,7 +2858,7 @@ #address-cells = <1>; #size-cells = <0>; - fsi_occ2: occ { + fsi_occ4: occ { compatible = "ibm,p10-occ"; occ-hwmon { @@ -2862,7 +2868,7 @@ }; }; - fsi_hub2: hub@3400 { + fsi_hub4: hub@3400 { compatible = "fsi-master-hub"; reg = <0x3400 0x400>; #address-cells = <2>; @@ -2872,11 +2878,11 @@ }; }; - cfam@3,0 { /* DCM1_C1 */ - reg = <3 0>; + cfam@5,0 { /* DCM2_C1 */ + reg = <5 0>; #address-cells = <1>; #size-cells = <1>; - chip-id = <3>; + chip-id = <5>; scom@1000 { compatible = "ibm,fsi2pib"; @@ -2889,334 +2895,260 @@ #address-cells = <1>; #size-cells = <0>; - cfam3_i2c2: i2c-bus@2 { + cfam5_i2c2: i2c-bus@2 { + #address-cells = <1>; + #size-cells = <0>; reg = <2>; /* OM45 */ - }; - - cfam3_i2c3: i2c-bus@3 { - reg = <3>; /* OM67 */ - }; - - cfam3_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam3_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam3_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam3_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - - cfam3_i2c16: i2c-bus@10 { - reg = <16>; /* OP6A */ - }; - cfam3_i2c17: i2c-bus@11 { - reg = <17>; /* OP6B */ - }; - }; + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; - cfam3_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; + scom602: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; + sbefifo602: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; - cfam3_spi1: spi@20 { - reg = <0x20>; + cfam5_i2c3: i2c-bus@3 { #address-cells = <1>; #size-cells = <0>; + reg = <3>; /* OM67 */ - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; - cfam3_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; + scom603: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; + sbefifo603: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; - cfam3_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; + cfam5_i2c10: i2c-bus@a { #address-cells = <1>; #size-cells = <0>; + reg = <10>; /* OP3A */ - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; - fsi_occ3: occ { - compatible = "ibm,p10-occ"; + scom610: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; + sbefifo610: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; - }; - - fsi_hub3: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; - - cfam@4,0 { /* DCM2_C0 */ - reg = <4 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <4>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam4_i2c0: i2c-bus@0 { - reg = <0>; /* OM01 */ - }; - - cfam4_i2c1: i2c-bus@1 { - reg = <1>; /* OM23 */ - }; - cfam4_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam4_i2c11: i2c-bus@b { + cfam5_i2c11: i2c-bus@b { + #address-cells = <1>; + #size-cells = <0>; reg = <11>; /* OP3B */ - }; - cfam4_i2c12: i2c-bus@c { - reg = <12>; /* OP4A */ - }; - - cfam4_i2c13: i2c-bus@d { - reg = <13>; /* OP4B */ - }; + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; - cfam4_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; - cfam4_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - }; + scom611: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam4_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; + sbefifo611: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; - cfam4_spi1: spi@20 { - reg = <0x20>; + cfam5_i2c14: i2c-bus@e { #address-cells = <1>; #size-cells = <0>; + reg = <14>; /* OP5A */ - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; - cfam4_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; + scom614: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; + sbefifo614: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; - cfam4_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; + cfam5_i2c15: i2c-bus@f { #address-cells = <1>; #size-cells = <0>; + reg = <15>; /* OP5B */ - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; - fsi_occ4: occ { - compatible = "ibm,p10-occ"; + scom615: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; + sbefifo615: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; }; - }; - - fsi_hub4: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - no-scan-on-init; - }; - }; + cfam5_i2c16: i2c-bus@10 { + #address-cells = <1>; + #size-cells = <0>; + reg = <16>; /* OP6A */ - cfam@5,0 { /* DCM2_C1 */ - reg = <5 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <5>; + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; + scom616: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; - cfam5_i2c2: i2c-bus@2 { - reg = <2>; /* OM45 */ - }; - - cfam5_i2c3: i2c-bus@3 { - reg = <3>; /* OM67 */ - }; - - cfam5_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ + sbefifo616: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; - cfam5_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; + cfam5_i2c17: i2c-bus@11 { + #address-cells = <1>; + #size-cells = <0>; + reg = <17>; /* OP6B */ - cfam5_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; - cfam5_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; - cfam5_i2c16: i2c-bus@10 { - reg = <16>; /* OP6A */ - }; + scom617: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; - cfam5_i2c17: i2c-bus@11 { - reg = <17>; /* OP6B */ + sbefifo617: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; }; @@ -3260,7 +3192,7 @@ cfam5_spi2: spi@40 { reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; + compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -3277,7 +3209,7 @@ cfam5_spi3: spi@60 { reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; + compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -3337,35 +3269,259 @@ #size-cells = <0>; cfam6_i2c0: i2c-bus@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; /* OM01 */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom700: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo700: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; cfam6_i2c1: i2c-bus@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; /* OM23 */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom701: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo701: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; cfam6_i2c10: i2c-bus@a { + #address-cells = <1>; + #size-cells = <0>; reg = <10>; /* OP3A */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom710: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo710: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; cfam6_i2c11: i2c-bus@b { + #address-cells = <1>; + #size-cells = <0>; reg = <11>; /* OP3B */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom711: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo711: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; cfam6_i2c12: i2c-bus@c { + #address-cells = <1>; + #size-cells = <0>; reg = <12>; /* OP4A */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom712: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo712: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; cfam6_i2c13: i2c-bus@d { + #address-cells = <1>; + #size-cells = <0>; reg = <13>; /* OP4B */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom713: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo713: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; cfam6_i2c14: i2c-bus@e { + #address-cells = <1>; + #size-cells = <0>; reg = <14>; /* OP5A */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom714: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo714: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; cfam6_i2c15: i2c-bus@f { + #address-cells = <1>; + #size-cells = <0>; reg = <15>; /* OP5B */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom715: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo715: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; }; @@ -3409,7 +3565,7 @@ cfam6_spi2: spi@40 { reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; + compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -3426,7 +3582,7 @@ cfam6_spi3: spi@60 { reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; + compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -3486,35 +3642,259 @@ #size-cells = <0>; cfam7_i2c2: i2c-bus@2 { + #address-cells = <1>; + #size-cells = <0>; reg = <2>; /* OM45 */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom802: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo802: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; cfam7_i2c3: i2c-bus@3 { + #address-cells = <1>; + #size-cells = <0>; reg = <3>; /* OM67 */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom803: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo803: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; cfam7_i2c10: i2c-bus@a { + #address-cells = <1>; + #size-cells = <0>; reg = <10>; /* OP3A */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom810: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo810: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; cfam7_i2c11: i2c-bus@b { + #address-cells = <1>; + #size-cells = <0>; reg = <11>; /* OP3B */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom811: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo811: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; cfam7_i2c14: i2c-bus@e { + #address-cells = <1>; + #size-cells = <0>; reg = <14>; /* OP5A */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom814: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo814: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; cfam7_i2c15: i2c-bus@f { + #address-cells = <1>; + #size-cells = <0>; reg = <15>; /* OP5B */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom815: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo815: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; cfam7_i2c16: i2c-bus@10 { + #address-cells = <1>; + #size-cells = <0>; reg = <16>; /* OP6A */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom816: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo816: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; cfam7_i2c17: i2c-bus@11 { + #address-cells = <1>; + #size-cells = <0>; reg = <17>; /* OP6B */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom817: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo817: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; }; @@ -3558,7 +3938,7 @@ cfam7_spi2: spi@40 { reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; + compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -3575,7 +3955,7 @@ cfam7_spi3: spi@60 { reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; + compatible = "ibm,fsi2spi"; #address-cells = <1>; #size-cells = <0>; @@ -3619,22 +3999,6 @@ }; /* Legacy OCC numbering (to get rid of when userspace is fixed) */ -&fsi_occ0 { - reg = <1>; -}; - -&fsi_occ1 { - reg = <2>; -}; - -&fsi_occ2 { - reg = <3>; -}; - -&fsi_occ3 { - reg = <4>; -}; - &fsi_occ4 { reg = <5>; }; @@ -3650,74 +4014,3 @@ &fsi_occ7 { reg = <8>; }; - -&ibt { - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&vuart1 { - status = "okay"; -}; - -&vuart2 { - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; - memory-region = <&flash_memory>; -}; - -&mac2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii3_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, - <&syscon ASPEED_CLK_MAC3RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&mac3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rmii4_default>; - clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>, - <&syscon ASPEED_CLK_MAC4RCLK>; - clock-names = "MACCLK", "RCLK"; - use-ncsi; -}; - -&wdt1 { - aspeed,reset-type = "none"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; -}; - -&wdt2 { - status = "okay"; -}; - -&xdma { - status = "okay"; - memory-region = <&vga_memory>; -}; - -&kcs2 { - status = "okay"; - aspeed,lpc-io-reg = <0xca8 0xcac>; -}; - -&kcs3 { - status = "okay"; - aspeed,lpc-io-reg = <0xca2>; - aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts index 7162e65b8115..5cb0094e21e0 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-ibm-rainier.dts @@ -12,39 +12,6 @@ compatible = "ibm,rainier-bmc", "aspeed,ast2600"; aliases { - i2c100 = &cfam0_i2c0; - i2c101 = &cfam0_i2c1; - i2c110 = &cfam0_i2c10; - i2c111 = &cfam0_i2c11; - i2c112 = &cfam0_i2c12; - i2c113 = &cfam0_i2c13; - i2c114 = &cfam0_i2c14; - i2c115 = &cfam0_i2c15; - i2c202 = &cfam1_i2c2; - i2c203 = &cfam1_i2c3; - i2c210 = &cfam1_i2c10; - i2c211 = &cfam1_i2c11; - i2c214 = &cfam1_i2c14; - i2c215 = &cfam1_i2c15; - i2c216 = &cfam1_i2c16; - i2c217 = &cfam1_i2c17; - i2c300 = &cfam2_i2c0; - i2c301 = &cfam2_i2c1; - i2c310 = &cfam2_i2c10; - i2c311 = &cfam2_i2c11; - i2c312 = &cfam2_i2c12; - i2c313 = &cfam2_i2c13; - i2c314 = &cfam2_i2c14; - i2c315 = &cfam2_i2c15; - i2c402 = &cfam3_i2c2; - i2c403 = &cfam3_i2c3; - i2c410 = &cfam3_i2c10; - i2c411 = &cfam3_i2c11; - i2c414 = &cfam3_i2c14; - i2c415 = &cfam3_i2c15; - i2c416 = &cfam3_i2c16; - i2c417 = &cfam3_i2c17; - serial4 = &uart5; i2c16 = &i2c2mux0; i2c17 = &i2c2mux1; @@ -61,23 +28,6 @@ i2c28 = &i2c6mux0chn3; i2c29 = &i2c11mux0chn0; i2c30 = &i2c11mux0chn1; - - spi10 = &cfam0_spi0; - spi11 = &cfam0_spi1; - spi12 = &cfam0_spi2; - spi13 = &cfam0_spi3; - spi20 = &cfam1_spi0; - spi21 = &cfam1_spi1; - spi22 = &cfam1_spi2; - spi23 = &cfam1_spi3; - spi30 = &cfam2_spi0; - spi31 = &cfam2_spi1; - spi32 = &cfam2_spi2; - spi33 = &cfam2_spi3; - spi40 = &cfam3_spi0; - spi41 = &cfam3_spi1; - spi42 = &cfam3_spi2; - spi43 = &cfam3_spi3; }; chosen { @@ -301,632 +251,6 @@ clk-phase-mmc-hs200 = <180>, <180>; }; -&fsim0 { - status = "okay"; - - #address-cells = <2>; - #size-cells = <0>; - - /* - * CFAM Reset is supposed to be active low but pass1 hardware is wired - * active high. - */ - cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; - - cfam@0,0 { - reg = <0 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <0>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_i2c0: i2c-bus@0 { - reg = <0>; /* OMI01 */ - }; - - cfam0_i2c1: i2c-bus@1 { - reg = <1>; /* OMI23 */ - }; - - cfam0_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam0_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam0_i2c12: i2c-bus@c { - reg = <12>; /* OP4A */ - }; - - cfam0_i2c13: i2c-bus@d { - reg = <13>; /* OP4B */ - }; - - cfam0_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam0_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam0_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam0_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam0_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam0_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ0: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub0: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - }; - }; -}; - -&fsi_hub0 { - cfam@1,0 { - reg = <1 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <1>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_i2c2: i2c-bus@2 { - reg = <2>; /* OMI45 */ - }; - - cfam1_i2c3: i2c-bus@3 { - reg = <3>; /* OMI67 */ - }; - - cfam1_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam1_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam1_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam1_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - - cfam1_i2c16: i2c-bus@10 { - reg = <16>; /* OP6A */ - }; - - cfam1_i2c17: i2c-bus@11 { - reg = <17>; /* OP6B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam1_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam1_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam1_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam1_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ1: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub1: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; - - cfam@2,0 { - reg = <2 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <2>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam2_i2c0: i2c-bus@0 { - reg = <0>; /* OM01 */ - }; - - cfam2_i2c1: i2c-bus@1 { - reg = <1>; /* OM23 */ - }; - - cfam2_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam2_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam2_i2c12: i2c-bus@c { - reg = <12>; /* OP4A */ - }; - - cfam2_i2c13: i2c-bus@d { - reg = <13>; /* OP4B */ - }; - - cfam2_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam2_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam2_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam2_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam2_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam2_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ2: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub2: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; - - cfam@3,0 { - reg = <3 0>; - #address-cells = <1>; - #size-cells = <1>; - chip-id = <3>; - - scom@1000 { - compatible = "ibm,fsi2pib"; - reg = <0x1000 0x400>; - }; - - i2c@1800 { - compatible = "ibm,fsi-i2c-master"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam3_i2c2: i2c-bus@2 { - reg = <2>; /* OM45 */ - }; - - cfam3_i2c3: i2c-bus@3 { - reg = <3>; /* OM67 */ - }; - - cfam3_i2c10: i2c-bus@a { - reg = <10>; /* OP3A */ - }; - - cfam3_i2c11: i2c-bus@b { - reg = <11>; /* OP3B */ - }; - - cfam3_i2c14: i2c-bus@e { - reg = <14>; /* OP5A */ - }; - - cfam3_i2c15: i2c-bus@f { - reg = <15>; /* OP5B */ - }; - - cfam3_i2c16: i2c-bus@10 { - reg = <16>; /* OP6A */ - }; - - cfam3_i2c17: i2c-bus@11 { - reg = <17>; /* OP6B */ - }; - }; - - fsi2spi@1c00 { - compatible = "ibm,fsi2spi"; - reg = <0x1c00 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - cfam3_spi0: spi@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam3_spi1: spi@20 { - reg = <0x20>; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam3_spi2: spi@40 { - reg = <0x40>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - - cfam3_spi3: spi@60 { - reg = <0x60>; - compatible = "ibm,fsi2spi-restricted"; - #address-cells = <1>; - #size-cells = <0>; - - eeprom@0 { - at25,byte-len = <0x80000>; - at25,addr-mode = <4>; - at25,page-size = <256>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <1000000>; - }; - }; - }; - - sbefifo@2400 { - compatible = "ibm,p9-sbefifo"; - reg = <0x2400 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - fsi_occ3: occ { - compatible = "ibm,p10-occ"; - - occ-hwmon { - compatible = "ibm,p10-occ-hwmon"; - ibm,no-poll-on-init; - }; - }; - }; - - fsi_hub3: hub@3400 { - compatible = "fsi-master-hub"; - reg = <0x3400 0x400>; - #address-cells = <2>; - #size-cells = <0>; - - no-scan-on-init; - }; - }; -}; - -/* Legacy OCC numbering (to get rid of when userspace is fixed) */ -&fsi_occ0 { - reg = <1>; -}; - -&fsi_occ1 { - reg = <2>; -}; - -&fsi_occ2 { - reg = <3>; -}; - -&fsi_occ3 { - reg = <4>; -}; - &ibt { status = "okay"; }; @@ -1017,7 +341,7 @@ reg = <0x4a>; }; - pca9546@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; @@ -1099,7 +423,7 @@ reg = <0x49>; }; - pca9546@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; @@ -1201,7 +525,7 @@ reg = <0x4b>; }; - pca9546@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; @@ -2031,7 +1355,7 @@ reg = <0x49>; }; - pca9546@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; @@ -2092,11 +1416,6 @@ &i2c12 { status = "okay"; - tpm@2e { - compatible = "nuvoton,npct75x"; - reg = <0x2e>; - }; - eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; @@ -2418,3 +1737,5 @@ aspeed,lpc-io-reg = <0xca2>; aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; }; + +#include "ibm-power10-quad.dtsi" diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts index 208b0f094ed9..0dea014e4f30 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-fp5280g2.dts @@ -348,7 +348,7 @@ label = "outlet"; }; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; @@ -432,7 +432,7 @@ &i2c7 { status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-nf5280m6.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-nf5280m6.dts index b3c1e3ba5831..92b9b3987c92 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-nf5280m6.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-inspur-nf5280m6.dts @@ -215,7 +215,7 @@ label = "outlet"; }; - pca9548@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; reg = <0x70>; }; @@ -224,17 +224,17 @@ &i2c3 { status = "okay"; - pca9548@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; reg = <0x70>; }; - pca9548@71 { + i2c-mux@71 { compatible = "nxp,pca9548"; reg = <0x71>; }; - pca9548@72 { + i2c-mux@72 { compatible = "nxp,pca9548"; reg = <0x72>; }; @@ -248,7 +248,7 @@ &i2c5 { status = "okay"; - pca9548@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; reg = <0x70>; }; @@ -257,7 +257,7 @@ &i2c6 { status = "okay"; - pca9548@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; reg = <0x70>; }; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-starscream.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-starscream.dts new file mode 100644 index 000000000000..ec82af94e1fb --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-starscream.dts @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2023 Inventec Corp. + +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include "aspeed-g6-pinctrl.dtsi" +#include <dt-bindings/i2c/i2c.h> +#include <dt-bindings/gpio/aspeed-gpio.h> + +/ { + model = "STARSCREAM BMC"; + compatible = "inventec,starscream-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + video_engine_memory: video { + size = <0x04000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-uid { + label = "UID_LED"; + gpios = <&gpio0 186 GPIO_ACTIVE_LOW>; + }; + + led-heartbeat { + label = "HB_LED"; + gpios = <&gpio0 127 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&mdio0 { + status = "okay"; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mac2 { + status = "okay"; + pinctrl-names = "default"; + phy-mode = "rmii"; + pinctrl-0 = <&pinctrl_rmii3_default>; + use-ncsi; +}; + +&mac3 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii4_default>; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; +#include "openbmc-flash-layout.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "bmc2"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bios"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&vuart1 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xca2>; + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; +&i2c1 { + status = "okay"; +}; +&i2c2 { + status = "okay"; +}; +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + // I2C EXPANDER + i2c-mux@71 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + // AMD SB-TSI CPU1 + sbtsi@4c { + compatible = "amd,sbtsi"; + reg = <0x4c>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + // AMD SB-TSI CPU2 + sbtsi@48 { + compatible = "amd,sbtsi"; + reg = <0x48>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + // I2C EXPANDER U153 + i2c-mux@70 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + usb_hub: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + riser1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + riser2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c6 { + status = "okay"; + + // Motherboard Temp_U89 + temperature-sensor@4e { + compatible = "ti,tmp421"; + reg = <0x4e>; + }; + + // RunBMC Temp_U6 + temperature-sensor@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; +}; + +&i2c7 { + status = "okay"; + // I2C EXPANDER U40 + i2c-mux@70 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c8 { + status = "okay"; + // FRU RunBMC + eeprom@51 { + compatible = "atmel,24c512"; + reg = <0x51>; + pagesize = <128>; + }; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; + // FRU SCM + eeprom@51 { + compatible = "atmel,24c512"; + reg = <0x51>; + pagesize = <128>; + }; + + // SCM Temp_U17 + temperature-sensor@4f { + compatible = "ti,tmp75"; + reg = <0x4f>; + }; +}; + +&gpio0 { + status = "okay"; + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "alert-psu0-smb-r-n","bmc-ready","","assert-cpu0-prochot-r-n", + "","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "","","","","reset-sgpio-r-n","","","", + /*G0-G7*/ "","","scm-jtag-mux-select","","","","","", + /*H0-H7*/ "","","","","reset-out","power-out","","", + /*I0-I7*/ "","","","","","","irq-bmc-cpu0-buf-nmi-n","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "","","ncsi-ocp-clk-en-n","","","","","", + /*O0-O7*/ "","","","","","","cpu1-thermal-trip-n","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "cpu0-prochot-n","","cpu1-prochot-n","","cpu0-pe-rst0","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","", + "","PCH_SLP_S4_BMC_N","cpu0-thermtrip-n","alert-psu1-smb-r-n", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "bios-recovery-buf-n","","assert-cpu1-prochot-r-n","", + "power-chassis-good","","","", + /*W0-W7*/ "","","","","","","","", + /*X0-X7*/ "","","","","platform-type","","","", + /*Y0-Y7*/ "","","","","","","","", + /*Z0-Z7*/ "","cpld-power-break-n","","","","","","", + /*AA0-AA7*/ "","","","","","","","", + /*AB0-AB7*/ "","","","","","","","", + /*AC0-AC7*/ "","","","","","","",""; +}; + +&sgpiom0 { + status = "okay"; + ngpios = <64>; + bus-frequency = <1000000>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + status = "okay"; + non-removable; + max-frequency = <52000000>; + bus-width = <8>; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +&vhub { + status = "okay"; + aspeed,vhub-downstream-ports = <7>; + aspeed,vhub-generic-endpoints = <21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2ad_default>; +}; + +&rtc { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-transformers.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-transformers.dts index caf66651e5b5..c713cb7a6187 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-transformers.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-inventec-transformers.dts @@ -193,14 +193,14 @@ // I2C EXPANDER status = "okay"; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; reg = <0x71>; }; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; @@ -212,7 +212,7 @@ // I2C EXPANDER status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9544"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr630.dts index 8f543cca7c21..ddbcbc64e235 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr630.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr630.dts @@ -208,7 +208,7 @@ * Slot 3 */ - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9545"; reg = <0x70>; #address-cells = <1>; @@ -249,7 +249,7 @@ * Slot 2, * Slot 3 */ - i2c-switch@76 { + i2c-mux@76 { compatible = "nxp,pca9546"; reg = <0x76>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts index bcc1820f5c07..6045b60b80da 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-lenovo-hr855xg2.dts @@ -175,7 +175,7 @@ &i2c0 { status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9545"; reg = <0x70>; #address-cells = <1>; @@ -227,7 +227,7 @@ &i2c3 { status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts index 0cb7b20ff3ab..3d2d8db73ca6 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-opp-zaius.dts @@ -231,7 +231,7 @@ &i2c1 { status = "okay"; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9546"; reg = <0x71>; #address-cells = <1>; @@ -282,7 +282,7 @@ &i2c4 { status = "okay"; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9546"; reg = <0x71>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-q71l.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-q71l.dts index 9605e53f5bbf..fed2791f5994 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-q71l.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-q71l.dts @@ -197,7 +197,7 @@ * Slot 6, * Slot 7 */ - i2c-switch@74 { + i2c-mux@74 { compatible = "nxp,pca9546"; reg = <0x74>; #address-cells = <1>; @@ -238,7 +238,7 @@ * SSD 1, * SSD 2 */ - i2c-switch@77 { + i2c-mux@77 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -325,7 +325,7 @@ * PSU3 * PSU2 */ - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts index 46cbba6305b8..983853eedaef 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-quanta-s6q.dts @@ -285,7 +285,7 @@ reg = <0x4b>; }; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9546"; reg = <0x70>; #address-cells = <1>; @@ -321,7 +321,7 @@ &i2c1 { status = "okay"; - i2c-switch@59 { + i2c-mux@59 { compatible = "nxp,pca9848"; reg = <0x59>; #address-cells = <1>; @@ -393,7 +393,7 @@ #size-cells = <0>; reg = <7>; - i2c-switch@77 { + i2c-mux@77 { compatible = "nxp,pca9546"; reg = <0x77>; #address-cells = <1>; @@ -490,7 +490,7 @@ &i2c6 { status = "okay"; - i2c-switch@77 { + i2c-mux@77 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -556,7 +556,7 @@ &i2c7 { status = "okay"; - i2c-switch@75 { + i2c-mux@75 { compatible = "nxp,pca9546"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-n110.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-n110.dts index 24319267d550..44b9853f6e63 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-n110.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-n110.dts @@ -88,16 +88,16 @@ &i2c13 { /* SMB_PCIE2_STBY_LVC3 */ - mux-expa@73 { - compatible = "nxp,pca9545"; - reg = <0x73>; + i2c-mux@71 { + compatible = "nxp,pca9543"; + reg = <0x71>; #address-cells = <1>; #size-cells = <0>; i2c-mux-idle-disconnect; }; - mux-sata@71 { - compatible = "nxp,pca9543"; - reg = <0x71>; + i2c-mux@73 { + compatible = "nxp,pca9545"; + reg = <0x73>; #address-cells = <1>; #size-cells = <0>; i2c-mux-idle-disconnect; @@ -106,7 +106,7 @@ &i2c2 { /* SMB_PCIE_STBY_LVC3 */ - mux-expb@71 { + i2c-mux@71 { compatible = "nxp,pca9545"; reg = <0x71>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts index ebbb68b55559..b8f0b08018a3 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-rx20.dts @@ -133,7 +133,7 @@ &i2c13 { /* SMB_PCIE2_STBY_LVC3 */ - mux-expa@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; reg = <0x70>; #address-cells = <1>; @@ -144,7 +144,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - rsra-mux@72 { + i2c-mux@72 { compatible = "nxp,pca9548"; reg = <0x72>; #address-cells = <1>; @@ -165,7 +165,7 @@ }; }; }; - mux-sata@71 { + i2c-mux@71 { compatible = "nxp,pca9543"; reg = <0x71>; #address-cells = <1>; @@ -176,7 +176,7 @@ &i2c2 { /* SMB_PCIE_STBY_LVC3 */ - mux-expb@71 { + i2c-mux@71 { compatible = "nxp,pca9548"; reg = <0x71>; #address-cells = <1>; @@ -187,7 +187,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; - rsrb-mux@72 { + i2c-mux@72 { compatible = "nxp,pca9548"; reg = <0x72>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-sx20.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-sx20.dts index e36ee4704994..933ca831d375 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-sx20.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-vegman-sx20.dts @@ -88,16 +88,16 @@ &i2c13 { /* SMB_PCIE2_STBY_LVC3 */ - mux-expa@73 { - compatible = "nxp,pca9545"; - reg = <0x73>; + i2c-mux@71 { + compatible = "nxp,pca9543"; + reg = <0x71>; #address-cells = <1>; #size-cells = <0>; i2c-mux-idle-disconnect; }; - mux-sata@71 { - compatible = "nxp,pca9543"; - reg = <0x71>; + i2c-mux@73 { + compatible = "nxp,pca9545"; + reg = <0x73>; #address-cells = <1>; #size-cells = <0>; i2c-mux-idle-disconnect; @@ -106,7 +106,7 @@ &i2c2 { /* SMB_PCIE_STBY_LVC3 */ - mux-expb@71 { + i2c-mux@71 { compatible = "nxp,pca9545"; reg = <0x71>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi index 7cd4f075e325..289668f051eb 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6-pinctrl.dtsi @@ -297,6 +297,16 @@ groups = "I2C9"; }; + pinctrl_i3c1_default: i3c1_default { + function = "I3C1"; + groups = "I3C1"; + }; + + pinctrl_i3c2_default: i3c2_default { + function = "I3C2"; + groups = "I3C2"; + }; + pinctrl_i3c3_default: i3c3_default { function = "I3C3"; groups = "I3C3"; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 172dd748d807..c4d1faade8be 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -729,6 +729,16 @@ status = "disabled"; }; + vuart3: serial@1e787800 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e787800 0x40>; + reg-shift = <2>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_APB2>; + no-loopback-test; + status = "disabled"; + }; + vuart2: serial@1e788000 { compatible = "aspeed,ast2500-vuart"; reg = <0x1e788000 0x40>; @@ -739,6 +749,16 @@ status = "disabled"; }; + vuart4: serial@1e788800 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e788800 0x40>; + reg-shift = <2>; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_APB2>; + no-loopback-test; + status = "disabled"; + }; + uart2: serial@1e78d000 { compatible = "ns16550a"; reg = <0x1e78d000 0x20>; diff --git a/arch/arm/boot/dts/aspeed/ast2500-facebook-netbmc-common.dtsi b/arch/arm/boot/dts/aspeed/ast2500-facebook-netbmc-common.dtsi index c0c43b8644ee..7f1ae3f4df9d 100644 --- a/arch/arm/boot/dts/aspeed/ast2500-facebook-netbmc-common.dtsi +++ b/arch/arm/boot/dts/aspeed/ast2500-facebook-netbmc-common.dtsi @@ -4,6 +4,10 @@ #include "aspeed-g5.dtsi" / { + aliases { + spi0 = &fmc; + }; + memory@80000000 { reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/aspeed/ibm-power10-dual.dtsi b/arch/arm/boot/dts/aspeed/ibm-power10-dual.dtsi new file mode 100644 index 000000000000..cc466910bb52 --- /dev/null +++ b/arch/arm/boot/dts/aspeed/ibm-power10-dual.dtsi @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2023 IBM Corp. + +&fsim0 { + status = "okay"; + + #address-cells = <2>; + #size-cells = <0>; + + cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_i2c0: i2c-bus@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* OMI01 */ + }; + + cfam0_i2c1: i2c-bus@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* OMI23 */ + }; + + cfam0_i2c10: i2c-bus@a { + #address-cells = <1>; + #size-cells = <0>; + reg = <10>; /* OP3A */ + }; + + cfam0_i2c11: i2c-bus@b { + #address-cells = <1>; + #size-cells = <0>; + reg = <11>; /* OP3B */ + }; + + cfam0_i2c12: i2c-bus@c { + #address-cells = <1>; + #size-cells = <0>; + reg = <12>; /* OP4A */ + }; + + cfam0_i2c13: i2c-bus@d { + #address-cells = <1>; + #size-cells = <0>; + reg = <13>; /* OP4B */ + }; + + cfam0_i2c14: i2c-bus@e { + #address-cells = <1>; + #size-cells = <0>; + reg = <14>; /* OP5A */ + }; + + cfam0_i2c15: i2c-bus@f { + #address-cells = <1>; + #size-cells = <0>; + reg = <15>; /* OP5B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam0_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ0: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub0: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + }; + }; +}; + +&fsi_hub0 { + cfam@1,0 { + reg = <1 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <1>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_i2c2: i2c-bus@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; /* OMI45 */ + }; + + cfam1_i2c3: i2c-bus@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; /* OMI67 */ + }; + + cfam1_i2c10: i2c-bus@a { + #address-cells = <1>; + #size-cells = <0>; + reg = <10>; /* OP3A */ + }; + + cfam1_i2c11: i2c-bus@b { + #address-cells = <1>; + #size-cells = <0>; + reg = <11>; /* OP3B */ + }; + + cfam1_i2c14: i2c-bus@e { + #address-cells = <1>; + #size-cells = <0>; + reg = <14>; /* OP5A */ + }; + + cfam1_i2c15: i2c-bus@f { + #address-cells = <1>; + #size-cells = <0>; + reg = <15>; /* OP5B */ + }; + + cfam1_i2c16: i2c-bus@10 { + #address-cells = <1>; + #size-cells = <0>; + reg = <16>; /* OP6A */ + }; + + cfam1_i2c17: i2c-bus@11 { + #address-cells = <1>; + #size-cells = <0>; + reg = <17>; /* OP6B */ + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam1_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ1: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub1: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +/* Legacy OCC numbering (to get rid of when userspace is fixed) */ +&fsi_occ0 { + reg = <1>; +}; + +&fsi_occ1 { + reg = <2>; +}; + +/ { + aliases { + i2c100 = &cfam0_i2c0; + i2c101 = &cfam0_i2c1; + i2c110 = &cfam0_i2c10; + i2c111 = &cfam0_i2c11; + i2c112 = &cfam0_i2c12; + i2c113 = &cfam0_i2c13; + i2c114 = &cfam0_i2c14; + i2c115 = &cfam0_i2c15; + i2c202 = &cfam1_i2c2; + i2c203 = &cfam1_i2c3; + i2c210 = &cfam1_i2c10; + i2c211 = &cfam1_i2c11; + i2c214 = &cfam1_i2c14; + i2c215 = &cfam1_i2c15; + i2c216 = &cfam1_i2c16; + i2c217 = &cfam1_i2c17; + + spi10 = &cfam0_spi0; + spi11 = &cfam0_spi1; + spi12 = &cfam0_spi2; + spi13 = &cfam0_spi3; + spi20 = &cfam1_spi0; + spi21 = &cfam1_spi1; + spi22 = &cfam1_spi2; + spi23 = &cfam1_spi3; + }; +}; diff --git a/arch/arm/boot/dts/aspeed/ibm-power10-quad.dtsi b/arch/arm/boot/dts/aspeed/ibm-power10-quad.dtsi new file mode 100644 index 000000000000..57494c744b5d --- /dev/null +++ b/arch/arm/boot/dts/aspeed/ibm-power10-quad.dtsi @@ -0,0 +1,1305 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2023 IBM Corp. + +#include "ibm-power10-dual.dtsi" + +&cfam0_i2c0 { + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom100: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo100: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cfam0_i2c1 { + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom101: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo101: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cfam0_i2c10 { + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom110: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo110: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cfam0_i2c11 { + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom111: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo111: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cfam0_i2c12 { + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom112: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo112: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cfam0_i2c13 { + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom113: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo113: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cfam0_i2c14 { + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom114: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo114: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cfam0_i2c15 { + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom115: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo115: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cfam1_i2c2 { + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom202: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo202: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cfam1_i2c3 { + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom203: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo203: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cfam1_i2c10 { + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom210: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo210: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cfam1_i2c11 { + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom211: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo211: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cfam1_i2c14 { + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom214: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo214: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cfam1_i2c15 { + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom215: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo215: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cfam1_i2c16 { + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom216: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo216: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&cfam1_i2c17 { + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom217: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo217: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; +}; + +&fsi_hub0 { + cfam@2,0 { + reg = <2 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <2>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam2_i2c0: i2c-bus@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; /* OM01 */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom300: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo300: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + cfam2_i2c1: i2c-bus@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; /* OM23 */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom301: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo301: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + cfam2_i2c10: i2c-bus@a { + #address-cells = <1>; + #size-cells = <0>; + reg = <10>; /* OP3A */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom310: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo310: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + cfam2_i2c11: i2c-bus@b { + #address-cells = <1>; + #size-cells = <0>; + reg = <11>; /* OP3B */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom311: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo311: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + cfam2_i2c12: i2c-bus@c { + #address-cells = <1>; + #size-cells = <0>; + reg = <12>; /* OP4A */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom312: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo312: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + cfam2_i2c13: i2c-bus@d { + #address-cells = <1>; + #size-cells = <0>; + reg = <13>; /* OP4B */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom313: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo313: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + cfam2_i2c14: i2c-bus@e { + #address-cells = <1>; + #size-cells = <0>; + reg = <14>; /* OP5A */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom314: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo314: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + cfam2_i2c15: i2c-bus@f { + #address-cells = <1>; + #size-cells = <0>; + reg = <15>; /* OP5B */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom315: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo315: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam2_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam2_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam2_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam2_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ2: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub2: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; + + cfam@3,0 { + reg = <3 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <3>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam3_i2c2: i2c-bus@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; /* OM45 */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom402: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo402: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + cfam3_i2c3: i2c-bus@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; /* OM67 */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom403: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo403: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + cfam3_i2c10: i2c-bus@a { + #address-cells = <1>; + #size-cells = <0>; + reg = <10>; /* OP3A */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom410: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo410: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + cfam3_i2c11: i2c-bus@b { + #address-cells = <1>; + #size-cells = <0>; + reg = <11>; /* OP3B */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom411: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo411: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + cfam3_i2c14: i2c-bus@e { + #address-cells = <1>; + #size-cells = <0>; + reg = <14>; /* OP5A */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom414: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo414: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + cfam3_i2c15: i2c-bus@f { + #address-cells = <1>; + #size-cells = <0>; + reg = <15>; /* OP5B */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom415: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo415: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + cfam3_i2c16: i2c-bus@10 { + #address-cells = <1>; + #size-cells = <0>; + reg = <16>; /* OP6A */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom416: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo416: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + + cfam3_i2c17: i2c-bus@11 { + #address-cells = <1>; + #size-cells = <0>; + reg = <17>; /* OP6B */ + + i2cr@20 { + compatible = "ibm,i2cr-fsi-master"; + reg = <0x20>; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom417: scom@1000 { + compatible = "ibm,i2cr-scom"; + reg = <0x1000 0x400>; + }; + + sbefifo417: sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + }; + + fsi2spi@1c00 { + compatible = "ibm,fsi2spi"; + reg = <0x1c00 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam3_spi0: spi@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam3_spi1: spi@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam3_spi2: spi@40 { + reg = <0x40>; + compatible = "ibm,fsi2spi"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + + cfam3_spi3: spi@60 { + reg = <0x60>; + compatible = "ibm,fsi2spi"; + #address-cells = <1>; + #size-cells = <0>; + + eeprom@0 { + at25,byte-len = <0x80000>; + at25,addr-mode = <4>; + at25,page-size = <256>; + + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ3: occ { + compatible = "ibm,p10-occ"; + + occ-hwmon { + compatible = "ibm,p10-occ-hwmon"; + ibm,no-poll-on-init; + }; + }; + }; + + fsi_hub3: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +/* Legacy OCC numbering (to get rid of when userspace is fixed) */ +&fsi_occ2 { + reg = <3>; +}; + +&fsi_occ3 { + reg = <4>; +}; + +/ { + aliases { + i2c300 = &cfam2_i2c0; + i2c301 = &cfam2_i2c1; + i2c310 = &cfam2_i2c10; + i2c311 = &cfam2_i2c11; + i2c312 = &cfam2_i2c12; + i2c313 = &cfam2_i2c13; + i2c314 = &cfam2_i2c14; + i2c315 = &cfam2_i2c15; + i2c402 = &cfam3_i2c2; + i2c403 = &cfam3_i2c3; + i2c410 = &cfam3_i2c10; + i2c411 = &cfam3_i2c11; + i2c414 = &cfam3_i2c14; + i2c415 = &cfam3_i2c15; + i2c416 = &cfam3_i2c16; + i2c417 = &cfam3_i2c17; + + sbefifo100 = &sbefifo100; + sbefifo101 = &sbefifo101; + sbefifo110 = &sbefifo110; + sbefifo111 = &sbefifo111; + sbefifo112 = &sbefifo112; + sbefifo113 = &sbefifo113; + sbefifo114 = &sbefifo114; + sbefifo115 = &sbefifo115; + sbefifo202 = &sbefifo202; + sbefifo203 = &sbefifo203; + sbefifo210 = &sbefifo210; + sbefifo211 = &sbefifo211; + sbefifo214 = &sbefifo214; + sbefifo215 = &sbefifo215; + sbefifo216 = &sbefifo216; + sbefifo217 = &sbefifo217; + sbefifo300 = &sbefifo300; + sbefifo301 = &sbefifo301; + sbefifo310 = &sbefifo310; + sbefifo311 = &sbefifo311; + sbefifo312 = &sbefifo312; + sbefifo313 = &sbefifo313; + sbefifo314 = &sbefifo314; + sbefifo315 = &sbefifo315; + sbefifo402 = &sbefifo402; + sbefifo403 = &sbefifo403; + sbefifo410 = &sbefifo410; + sbefifo411 = &sbefifo411; + sbefifo414 = &sbefifo414; + sbefifo415 = &sbefifo415; + sbefifo416 = &sbefifo416; + sbefifo417 = &sbefifo417; + + scom100 = &scom100; + scom101 = &scom101; + scom110 = &scom110; + scom111 = &scom111; + scom112 = &scom112; + scom113 = &scom113; + scom114 = &scom114; + scom115 = &scom115; + scom202 = &scom202; + scom203 = &scom203; + scom210 = &scom210; + scom211 = &scom211; + scom214 = &scom214; + scom215 = &scom215; + scom216 = &scom216; + scom217 = &scom217; + scom300 = &scom300; + scom301 = &scom301; + scom310 = &scom310; + scom311 = &scom311; + scom312 = &scom312; + scom313 = &scom313; + scom314 = &scom314; + scom315 = &scom315; + scom402 = &scom402; + scom403 = &scom403; + scom410 = &scom410; + scom411 = &scom411; + scom414 = &scom414; + scom415 = &scom415; + scom416 = &scom416; + scom417 = &scom417; + + spi30 = &cfam2_spi0; + spi31 = &cfam2_spi1; + spi32 = &cfam2_spi2; + spi33 = &cfam2_spi3; + spi40 = &cfam3_spi0; + spi41 = &cfam3_spi1; + spi42 = &cfam3_spi2; + spi43 = &cfam3_spi3; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/Makefile b/arch/arm/boot/dts/broadcom/Makefile index 95b0ef2a4215..7099d9560033 100644 --- a/arch/arm/boot/dts/broadcom/Makefile +++ b/arch/arm/boot/dts/broadcom/Makefile @@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4709-netgear-r7000.dtb \ bcm4709-netgear-r8000.dtb \ bcm4709-tplink-archer-c9-v1.dtb \ + bcm47094-asus-rt-ac3100.dtb \ bcm47094-asus-rt-ac88u.dtb \ bcm47094-dlink-dir-885l.dtb \ bcm47094-dlink-dir-890l.dtb \ diff --git a/arch/arm/boot/dts/broadcom/bcm-hr2.dtsi b/arch/arm/boot/dts/broadcom/bcm-hr2.dtsi index 33e6ba63a1ee..788a6806191a 100644 --- a/arch/arm/boot/dts/broadcom/bcm-hr2.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm-hr2.dtsi @@ -54,8 +54,8 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>; }; diff --git a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi index dae9c47ace76..88fda18af1f8 100644 --- a/arch/arm/boot/dts/broadcom/bcm-ns.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm-ns.dtsi @@ -272,14 +272,32 @@ gmac0: ethernet@24000 { reg = <0x24000 0x800>; + phy-mode = "internal"; + + fixed-link { + speed = <1000>; + full-duplex; + }; }; gmac1: ethernet@25000 { reg = <0x25000 0x800>; + phy-mode = "internal"; + + fixed-link { + speed = <1000>; + full-duplex; + }; }; gmac2: ethernet@26000 { reg = <0x26000 0x800>; + phy-mode = "internal"; + + fixed-link { + speed = <1000>; + full-duplex; + }; }; gmac3: ethernet@27000 { diff --git a/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi b/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi index 5b1dc58d40ba..9d20ba3b1ffb 100644 --- a/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi @@ -72,8 +72,8 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>; }; diff --git a/arch/arm/boot/dts/broadcom/bcm11351.dtsi b/arch/arm/boot/dts/broadcom/bcm11351.dtsi index b271a9bf06a9..53857e572080 100644 --- a/arch/arm/boot/dts/broadcom/bcm11351.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm11351.dtsi @@ -111,13 +111,12 @@ gpio: gpio@35003000 { compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio"; reg = <0x35003000 0x800>; - interrupts = - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; #interrupt-cells = <2>; gpio-controller; diff --git a/arch/arm/boot/dts/broadcom/bcm21664.dtsi b/arch/arm/boot/dts/broadcom/bcm21664.dtsi index 2eb7f5b0c1dc..fa73600e883e 100644 --- a/arch/arm/boot/dts/broadcom/bcm21664.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm21664.dtsi @@ -101,11 +101,10 @@ gpio: gpio@35003000 { compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio"; reg = <0x35003000 0x524>; - interrupts = - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; #interrupt-cells = <2>; gpio-controller; diff --git a/arch/arm/boot/dts/broadcom/bcm23550.dtsi b/arch/arm/boot/dts/broadcom/bcm23550.dtsi index 445eadb8d871..50ebe93d6bd0 100644 --- a/arch/arm/boot/dts/broadcom/bcm23550.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm23550.dtsi @@ -101,11 +101,10 @@ gpio: gpio@1003000 { compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio"; reg = <0x01003000 0x524>; - interrupts = - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; #gpio-cells = <2>; #interrupt-cells = <2>; gpio-controller; diff --git a/arch/arm/boot/dts/broadcom/bcm2711.dtsi b/arch/arm/boot/dts/broadcom/bcm2711.dtsi index 097e9f252235..4a379a14966d 100644 --- a/arch/arm/boot/dts/broadcom/bcm2711.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2711.dtsi @@ -76,7 +76,7 @@ }; }; - dma: dma@7e007000 { + dma: dma-controller@7e007000 { compatible = "brcm,bcm2835-dma"; reg = <0x7e007000 0xb00>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, @@ -278,7 +278,7 @@ clocks = <&clocks BCM2835_CLOCK_PWM>; assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; assigned-clock-rates = <10000000>; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/broadcom/bcm28155-ap.dts b/arch/arm/boot/dts/broadcom/bcm28155-ap.dts index 0a8ad1d673d8..2f3634545e64 100644 --- a/arch/arm/boot/dts/broadcom/bcm28155-ap.dts +++ b/arch/arm/boot/dts/broadcom/bcm28155-ap.dts @@ -15,64 +15,64 @@ device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; +}; - serial@3e000000 { - status = "okay"; - }; - - i2c@3e016000 { - clock-frequency = <400000>; - status = "okay"; - }; +&bsc1 { + clock-frequency = <400000>; + status = "okay"; +}; - i2c@3e017000 { - clock-frequency = <400000>; - status = "okay"; - }; +&bsc2 { + clock-frequency = <400000>; + status = "okay"; +}; - i2c@3e018000 { - clock-frequency = <400000>; - status = "okay"; - }; +&bsc3 { + clock-frequency = <400000>; + status = "okay"; +}; - i2c@3500d000 { - clock-frequency = <100000>; - status = "okay"; +&pmu_bsc { + clock-frequency = <100000>; + status = "okay"; - pmu: pmu@8 { - reg = <0x08>; - }; + pmu: pmu@8 { + reg = <0x08>; }; +}; - sdio2: mmc@3f190000 { - non-removable; - max-frequency = <48000000>; - vmmc-supply = <&camldo1_reg>; - vqmmc-supply = <&iosr1_reg>; - status = "okay"; - }; +&pwm { + status = "okay"; +}; - sdio4: mmc@3f1b0000 { - max-frequency = <48000000>; - cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>; - vmmc-supply = <&sdldo_reg>; - vqmmc-supply = <&sdxldo_reg>; - status = "okay"; - }; +&sdio2 { + non-removable; + max-frequency = <48000000>; + vmmc-supply = <&camldo1_reg>; + vqmmc-supply = <&iosr1_reg>; + status = "okay"; +}; - pwm: pwm@3e01a000 { - status = "okay"; - }; +&sdio4 { + max-frequency = <48000000>; + cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>; + vmmc-supply = <&sdldo_reg>; + vqmmc-supply = <&sdxldo_reg>; + status = "okay"; +}; - usbotg: usb@3f120000 { - vusb_d-supply = <&usbldo_reg>; - vusb_a-supply = <&iosr1_reg>; - status = "okay"; - }; +&uartb { + status = "okay"; +}; - usbphy: usb-phy@3f130000 { - status = "okay"; - }; +&usbotg { + vusb_d-supply = <&usbldo_reg>; + vusb_a-supply = <&iosr1_reg>; + status = "okay"; +}; + +&usbphy { + status = "okay"; }; #include "bcm59056.dtsi" diff --git a/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi index bb7e8f7facaf..9261b67dbee1 100644 --- a/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2835-common.dtsi @@ -8,7 +8,7 @@ interrupt-parent = <&intc>; soc { - dma: dma@7e007000 { + dma: dma-controller@7e007000 { compatible = "brcm,bcm2835-dma"; reg = <0x7e007000 0xf00>; interrupts = <1 16>, diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-a-plus.dts index 02ce817868ba..069b48272aa5 100644 --- a/arch/arm/boot/dts/broadcom/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-a-plus.dts @@ -81,6 +81,7 @@ "SD_DATA2_R", "SD_DATA3_R"; + pinctrl-names = "default"; pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-a.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-a.dts index 3fdf60eb11dc..2726c00431e8 100644 --- a/arch/arm/boot/dts/broadcom/bcm2835-rpi-a.dts +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-a.dts @@ -83,6 +83,7 @@ "SD_DATA2_R", "SD_DATA3_R"; + pinctrl-names = "default"; pinctrl-0 = <&gpioout &alt0 &i2s_alt2>; /* I2S interface */ diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-plus.dts index 9956fd06a4b6..c57b999a4520 100644 --- a/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-plus.dts @@ -83,6 +83,7 @@ "SD_DATA2_R", "SD_DATA3_R"; + pinctrl-names = "default"; pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-rev2.dts index 4e1770afb145..ae6d3a9586ab 100644 --- a/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b-rev2.dts @@ -83,6 +83,7 @@ "SD_DATA2_R", "SD_DATA3_R"; + pinctrl-names = "default"; pinctrl-0 = <&gpioout &alt0 &i2s_alt2>; /* I2S interface */ diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-b.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b.dts index eec1d0892d33..72764be75a79 100644 --- a/arch/arm/boot/dts/broadcom/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-b.dts @@ -83,6 +83,7 @@ "SD_DATA2_R", "SD_DATA3_R"; + pinctrl-names = "default"; pinctrl-0 = <&gpioout &alt0>; }; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1-io1.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1-io1.dts index 87958a96c3e0..3f9d198ac3ab 100644 --- a/arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1-io1.dts +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-cm1-io1.dts @@ -73,6 +73,7 @@ "SD_DATA2_R", "SD_DATA3_R"; + pinctrl-names = "default"; pinctrl-0 = <&gpioout &alt0>; }; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero-w.dts index dbf825985ec0..1f0b163e400c 100644 --- a/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero-w.dts +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero-w.dts @@ -97,6 +97,7 @@ "SD_DATA2_R", "SD_DATA3_R"; + pinctrl-names = "default"; pinctrl-0 = <&gpioout &alt0>; }; @@ -111,6 +112,7 @@ }; &sdhci { + pinctrl-names = "default"; pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; }; diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero.dts index f80e65a825fd..539c19c10946 100644 --- a/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero.dts +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi-zero.dts @@ -85,6 +85,7 @@ "SD_DATA2_R", "SD_DATA3_R"; + pinctrl-names = "default"; pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ diff --git a/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi index ee9ee9d1fe65..f0acc9390f31 100644 --- a/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm2835-rpi.dtsi @@ -26,8 +26,6 @@ }; &gpio { - pinctrl-names = "default"; - gpioout: gpioout { brcm,pins = <6>; brcm,function = <BCM2835_FSEL_GPIO_OUT>; diff --git a/arch/arm/boot/dts/broadcom/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/broadcom/bcm2836-rpi-2-b.dts index 6068ec390081..79918033750e 100644 --- a/arch/arm/boot/dts/broadcom/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/broadcom/bcm2836-rpi-2-b.dts @@ -82,6 +82,7 @@ "SD_DATA2_R", "SD_DATA3_R"; + pinctrl-names = "default"; pinctrl-0 = <&gpioout &alt0 &i2s_alt0>; /* I2S interface */ diff --git a/arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts index cf84e69fced8..72d26d130efa 100644 --- a/arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts +++ b/arch/arm/boot/dts/broadcom/bcm2837-rpi-cm3-io3.dts @@ -72,6 +72,7 @@ "SD_DATA2_R", "SD_DATA3_R"; + pinctrl-names = "default"; pinctrl-0 = <&gpioout &alt0>; }; diff --git a/arch/arm/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts b/arch/arm/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts index b9cc4594398b..85cf594724ef 100644 --- a/arch/arm/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts +++ b/arch/arm/boot/dts/broadcom/bcm2837-rpi-zero-2-w.dts @@ -95,6 +95,7 @@ "SD_DATA2_R", "SD_DATA3_R"; + pinctrl-names = "default"; pinctrl-0 = <&gpioout &alt0>; }; @@ -109,6 +110,7 @@ }; &sdhci { + pinctrl-names = "default"; pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; }; diff --git a/arch/arm/boot/dts/broadcom/bcm283x.dtsi b/arch/arm/boot/dts/broadcom/bcm283x.dtsi index c9c52a19ef3b..2ca8a2505a4d 100644 --- a/arch/arm/boot/dts/broadcom/bcm283x.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm283x.dtsi @@ -416,7 +416,7 @@ clocks = <&clocks BCM2835_CLOCK_PWM>; assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; assigned-clock-rates = <10000000>; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts index f1412ba83def..0454423fe166 100644 --- a/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts +++ b/arch/arm/boot/dts/broadcom/bcm4708-linksys-ea6500-v2.dts @@ -19,7 +19,8 @@ memory@0 { device_type = "memory"; - reg = <0x00000000 0x08000000>; + reg = <0x00000000 0x08000000>, + <0x88000000 0x08000000>; }; gpio-keys { diff --git a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dts b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dts new file mode 100644 index 000000000000..5f089307cd8c --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Author: Arınç ÃœNAL <arinc.unal@arinc9.com> + */ + +/dts-v1/; + +#include "bcm47094-asus-rt-ac3100.dtsi" + +/ { + compatible = "asus,rt-ac3100", "brcm,bcm47094", "brcm,bcm4708"; + model = "ASUS RT-AC3100"; + + nvram@1c080000 { + et0macaddr: et0macaddr { + }; + }; +}; + +&gmac0 { + nvmem-cells = <&et0macaddr>; + nvmem-cell-names = "mac-address"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi new file mode 100644 index 000000000000..09cefce27fb1 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac3100.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Author: Arınç ÃœNAL <arinc.unal@arinc9.com> + */ + +#include "bcm47094.dtsi" +#include "bcm5301x-nand-cs0-bch8.dtsi" + +/ { + chosen { + bootargs = "earlycon"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x08000000>, + <0x88000000 0x18000000>; + }; + + nvram@1c080000 { + compatible = "brcm,nvram"; + reg = <0x1c080000 0x00180000>; + }; + + leds { + compatible = "gpio-leds"; + + led-power { + label = "white:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-wan-red { + label = "red:wan"; + gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; + }; + + led-lan { + label = "white:lan"; + gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; + }; + + led-usb2 { + label = "white:usb2"; + gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; + trigger-sources = <&ehci_port2>; + linux,default-trigger = "usbport"; + }; + + led-usb3 { + label = "white:usb3"; + gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; + trigger-sources = <&ehci_port1>, <&xhci_port1>; + linux,default-trigger = "usbport"; + }; + + led-wps { + label = "white:wps"; + gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-wps { + label = "WPS"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; + }; + + button-reset { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + button-wifi { + label = "Wi-Fi"; + linux,code = <KEY_RFKILL>; + gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; + }; + + button-led { + label = "Backlight"; + linux,code = <KEY_BRIGHTNESS_ZERO>; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&srab { + compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; + status = "okay"; + + ports { + port@0 { + label = "lan4"; + }; + + port@1 { + label = "lan3"; + }; + + port@2 { + label = "lan2"; + }; + + port@3 { + label = "lan1"; + }; + + port@4 { + label = "wan"; + }; + + port@5 { + label = "cpu"; + }; + + port@7 { + label = "cpu"; + }; + + port@8 { + label = "cpu"; + }; + }; +}; + +&usb2 { + vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +}; + +&usb3_phy { + status = "okay"; +}; + +&nandcs { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00080000>; + read-only; + }; + + partition@80000 { + label = "nvram"; + reg = <0x00080000 0x00180000>; + }; + + partition@200000 { + label = "firmware"; + reg = <0x00200000 0x07e00000>; + compatible = "brcm,trx"; + }; + }; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts index 4d5747aa5dc8..fd344b55087e 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-asus-rt-ac88u.dts @@ -1,102 +1,21 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* - * Copyright (C) 2021-2022 Arınç ÃœNAL <arinc.unal@arinc9.com> + * Author: Arınç ÃœNAL <arinc.unal@arinc9.com> */ /dts-v1/; -#include "bcm47094.dtsi" -#include "bcm5301x-nand-cs0-bch8.dtsi" +#include "bcm47094-asus-rt-ac3100.dtsi" / { compatible = "asus,rt-ac88u", "brcm,bcm47094", "brcm,bcm4708"; - model = "Asus RT-AC88U"; - - chosen { - bootargs = "earlycon"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00000000 0x08000000>, - <0x88000000 0x18000000>; - }; + model = "ASUS RT-AC88U"; nvram@1c080000 { - compatible = "brcm,nvram"; - reg = <0x1c080000 0x00180000>; - et1macaddr: et1macaddr { }; }; - leds { - compatible = "gpio-leds"; - - led-power { - label = "white:power"; - gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-on"; - }; - - led-wan-red { - label = "red:wan"; - gpios = <&chipcommon 5 GPIO_ACTIVE_HIGH>; - }; - - led-lan { - label = "white:lan"; - gpios = <&chipcommon 21 GPIO_ACTIVE_LOW>; - }; - - led-usb2 { - label = "white:usb2"; - gpios = <&chipcommon 16 GPIO_ACTIVE_LOW>; - trigger-sources = <&ehci_port2>; - linux,default-trigger = "usbport"; - }; - - led-usb3 { - label = "white:usb3"; - gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>; - trigger-sources = <&ehci_port1>, <&xhci_port1>; - linux,default-trigger = "usbport"; - }; - - led-wps { - label = "white:wps"; - gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>; - }; - }; - - gpio-keys { - compatible = "gpio-keys"; - - button-wps { - label = "WPS"; - linux,code = <KEY_WPS_BUTTON>; - gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>; - }; - - button-reset { - label = "Reset"; - linux,code = <KEY_RESTART>; - gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; - }; - - button-wifi { - label = "Wi-Fi"; - linux,code = <KEY_RFKILL>; - gpios = <&chipcommon 18 GPIO_ACTIVE_LOW>; - }; - - button-led { - label = "Backlight"; - linux,code = <KEY_BRIGHTNESS_ZERO>; - gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; - }; - }; - switch { compatible = "realtek,rtl8365mb"; /* 7 = MDIO (has input reads), 6 = MDC (clock, output only) */ @@ -175,31 +94,9 @@ }; &srab { - compatible = "brcm,bcm53012-srab", "brcm,bcm5301x-srab"; - status = "okay"; dsa,member = <0 0>; ports { - port@0 { - label = "lan4"; - }; - - port@1 { - label = "lan3"; - }; - - port@2 { - label = "lan2"; - }; - - port@3 { - label = "lan1"; - }; - - port@4 { - label = "wan"; - }; - sw0_p5: port@5 { /delete-property/ethernet; @@ -212,19 +109,6 @@ pause; }; }; - - port@7 { - label = "cpu"; - - fixed-link { - speed = <1000>; - full-duplex; - }; - }; - - port@8 { - label = "cpu"; - }; }; }; @@ -236,36 +120,3 @@ nvmem-cells = <&et1macaddr>; nvmem-cell-names = "mac-address"; }; - -&usb2 { - vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; -}; - -&usb3_phy { - status = "okay"; -}; - -&nandcs { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "boot"; - reg = <0x00000000 0x00080000>; - read-only; - }; - - partition@80000 { - label = "nvram"; - reg = <0x00080000 0x00180000>; - }; - - partition@200000 { - label = "firmware"; - reg = <0x00200000 0x07e00000>; - compatible = "brcm,trx"; - }; - }; -}; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts index 51ce510b3e3a..c914569ddd5e 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-885l.dts @@ -33,6 +33,7 @@ #size-cells = <1>; partition@0 { + compatible = "seama"; label = "firmware"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts index 60744f82c2b7..f050acbea0b2 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-dlink-dir-890l.dts @@ -149,6 +149,7 @@ * partitions: this device uses SEAMA. */ firmware@0 { + compatible = "seama"; label = "firmware"; reg = <0x00000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts b/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts index 8036c04d81cb..2b5c80d835e9 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-linksys-panamera.dts @@ -279,7 +279,7 @@ reg = <0x080000 0x0100000>; }; - partition@180000{ + partition@180000 { label = "devinfo"; reg = <0x0180000 0x080000>; }; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts index 6875625869d9..afc635c8cdeb 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xap-1610.dts @@ -64,6 +64,43 @@ nvmem-cell-names = "mac-address"; }; + +&pcie0 { + #address-cells = <3>; + #size-cells = <2>; + + bridge@0,0 { + reg = <0x0000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + wifi@0,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; + reg = <0x0000 0 0 0 0>; + brcm,ccode-map = "AU-AU-920", "CA-CA-892", "GB-DE-964", "NZ-AU-920", "US-US-825"; + }; + }; +}; + +&pcie1 { + #address-cells = <3>; + #size-cells = <2>; + + bridge@0,0 { + reg = <0x0000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + wifi@0,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; + reg = <0x0000 0 0 0 0>; + brcm,ccode-map = "AU-AU-920", "CA-CA-892", "GB-DE-964", "NZ-AU-920", "US-US-825"; + }; + }; +}; + &spi_nor { status = "okay"; }; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts index 789dd2a3d226..e28f7a350117 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-luxul-xwr-3150-v1.dts @@ -81,6 +81,42 @@ nvmem-cell-names = "mac-address"; }; +&pcie0 { + #address-cells = <3>; + #size-cells = <2>; + + bridge@0,0 { + reg = <0x0000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + wifi@0,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; + reg = <0x0000 0 0 0 0>; + brcm,ccode-map = "AU-AU-953", "CA-CA-946", "GB-E0-846", "NZ-AU-953", "US-Q2-930"; + }; + }; +}; + +&pcie1 { + #address-cells = <3>; + #size-cells = <2>; + + bridge@0,0 { + reg = <0x0000 0 0 0 0>; + + #address-cells = <3>; + #size-cells = <2>; + + wifi@0,0 { + compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac"; + reg = <0x0000 0 0 0 0>; + brcm,ccode-map = "AU-AU-953", "CA-CA-946", "GB-E0-846", "NZ-AU-953", "US-Q2-930"; + }; + }; +}; + &usb3 { vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/broadcom/bcm47094-phicomm-k3.dts b/arch/arm/boot/dts/broadcom/bcm47094-phicomm-k3.dts index 3bf6e24978ac..bb1bc4e61bc2 100644 --- a/arch/arm/boot/dts/broadcom/bcm47094-phicomm-k3.dts +++ b/arch/arm/boot/dts/broadcom/bcm47094-phicomm-k3.dts @@ -55,7 +55,7 @@ reg = <0x0080000 0x0100000>; }; - partition@180000{ + partition@180000 { label = "phicomm"; reg = <0x0180000 0x0280000>; read-only; diff --git a/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-1440.dts index 0734aa249b8e..ac44c745bdf8 100644 --- a/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-1440.dts +++ b/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-1440.dts @@ -26,7 +26,6 @@ led-wlan { label = "bcm53xx:blue:wlan"; gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>; - linux,default-trigger = "default-off"; }; led-system { @@ -46,3 +45,22 @@ }; }; }; + +&gmac0 { + phy-mode = "rgmii"; + phy-handle = <&bcm54210e>; + + /delete-node/ fixed-link; + + mdio { + /delete-node/ switch@1e; + + bcm54210e: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gmac1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-810.dts index e6fb6cbe6963..fd071da26cfa 100644 --- a/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-810.dts +++ b/arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-810.dts @@ -26,7 +26,6 @@ led-5ghz { label = "bcm53xx:blue:5ghz"; gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; }; led-system { @@ -42,7 +41,6 @@ led-2ghz { label = "bcm53xx:blue:2ghz"; gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "default-off"; }; }; @@ -83,3 +81,22 @@ }; }; }; + +&gmac0 { + phy-mode = "rgmii"; + phy-handle = <&bcm54210e>; + + /delete-node/ fixed-link; + + mdio { + /delete-node/ switch@1e; + + bcm54210e: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gmac1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm47189-tenda-ac9.dts b/arch/arm/boot/dts/broadcom/bcm47189-tenda-ac9.dts index dab2e5f63a72..3ac6cac541ca 100644 --- a/arch/arm/boot/dts/broadcom/bcm47189-tenda-ac9.dts +++ b/arch/arm/boot/dts/broadcom/bcm47189-tenda-ac9.dts @@ -111,34 +111,27 @@ ports { port@0 { - reg = <0>; label = "wan"; }; port@1 { - reg = <1>; label = "lan1"; }; port@2 { - reg = <2>; label = "lan2"; }; port@3 { - reg = <3>; label = "lan3"; }; port@4 { - reg = <4>; label = "lan4"; }; - port@5 { - reg = <5>; + port@8 { label = "cpu"; - ethernet = <&gmac0>; }; }; }; diff --git a/arch/arm/boot/dts/broadcom/bcm53573.dtsi b/arch/arm/boot/dts/broadcom/bcm53573.dtsi index 3f03a381db0f..2df80740d181 100644 --- a/arch/arm/boot/dts/broadcom/bcm53573.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm53573.dtsi @@ -127,6 +127,9 @@ pcie0: pcie@2000 { reg = <0x00002000 0x1000>; + + #address-cells = <3>; + #size-cells = <2>; }; usb2: usb2@4000 { @@ -156,8 +159,6 @@ }; ohci: usb@d000 { - #usb-cells = <0>; - compatible = "generic-ohci"; reg = <0xd000 0x1000>; interrupt-parent = <&gic>; @@ -180,6 +181,12 @@ gmac0: ethernet@5000 { reg = <0x5000 0x1000>; + phy-mode = "internal"; + + fixed-link { + speed = <1000>; + full-duplex; + }; mdio { #address-cells = <1>; @@ -191,10 +198,44 @@ status = "disabled"; - /* ports are defined in board DTS */ ports { #address-cells = <1>; #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + }; + + port@5 { + reg = <5>; + ethernet = <&gmac1>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@8 { + reg = <8>; + ethernet = <&gmac0>; + }; }; }; }; @@ -202,6 +243,12 @@ gmac1: ethernet@b000 { reg = <0xb000 0x1000>; + phy-mode = "internal"; + + fixed-link { + speed = <1000>; + full-duplex; + }; }; pmu@12000 { diff --git a/arch/arm/boot/dts/broadcom/bcm947189acdbmr.dts b/arch/arm/boot/dts/broadcom/bcm947189acdbmr.dts index 3709baa2376f..0b8727ae6f16 100644 --- a/arch/arm/boot/dts/broadcom/bcm947189acdbmr.dts +++ b/arch/arm/boot/dts/broadcom/bcm947189acdbmr.dts @@ -60,9 +60,9 @@ spi { compatible = "spi-gpio"; num-chipselects = <1>; - gpio-sck = <&chipcommon 21 0>; - gpio-miso = <&chipcommon 22 0>; - gpio-mosi = <&chipcommon 23 0>; + sck-gpios = <&chipcommon 21 0>; + miso-gpios = <&chipcommon 22 0>; + mosi-gpios = <&chipcommon 23 0>; cs-gpios = <&chipcommon 24 0>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/hisilicon/hi3519.dtsi b/arch/arm/boot/dts/hisilicon/hi3519.dtsi index c524c854d319..a42b71cdc5d7 100644 --- a/arch/arm/boot/dts/hisilicon/hi3519.dtsi +++ b/arch/arm/boot/dts/hisilicon/hi3519.dtsi @@ -54,7 +54,7 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg HI3519_UART0_CLK>, <&crg HI3519_UART0_CLK>; clock-names = "uartclk", "apb_pclk"; - status = "disable"; + status = "disabled"; }; uart1: serial@12101000 { @@ -63,7 +63,7 @@ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg HI3519_UART1_CLK>, <&crg HI3519_UART1_CLK>; clock-names = "uartclk", "apb_pclk"; - status = "disable"; + status = "disabled"; }; uart2: serial@12102000 { @@ -72,7 +72,7 @@ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg HI3519_UART2_CLK>, <&crg HI3519_UART2_CLK>; clock-names = "uartclk", "apb_pclk"; - status = "disable"; + status = "disabled"; }; uart3: serial@12103000 { @@ -81,7 +81,7 @@ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg HI3519_UART3_CLK>, <&crg HI3519_UART3_CLK>; clock-names = "uartclk", "apb_pclk"; - status = "disable"; + status = "disabled"; }; uart4: serial@12104000 { @@ -90,7 +90,7 @@ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg HI3519_UART4_CLK>, <&crg HI3519_UART4_CLK>; clock-names = "uartclk", "apb_pclk"; - status = "disable"; + status = "disabled"; }; dual_timer0: timer@12000000 { @@ -100,7 +100,7 @@ reg = <0x12000000 0x1000>; clocks = <&clk_3m>; clock-names = "apb_pclk"; - status = "disable"; + status = "disabled"; }; dual_timer1: timer@12001000 { @@ -110,7 +110,7 @@ reg = <0x12001000 0x1000>; clocks = <&clk_3m>; clock-names = "apb_pclk"; - status = "disable"; + status = "disabled"; }; dual_timer2: timer@12002000 { @@ -120,7 +120,7 @@ reg = <0x12002000 0x1000>; clocks = <&clk_3m>; clock-names = "apb_pclk"; - status = "disable"; + status = "disabled"; }; spi_bus0: spi@12120000 { @@ -132,7 +132,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; - status = "disable"; + status = "disabled"; }; spi_bus1: spi@12121000 { @@ -144,7 +144,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; - status = "disable"; + status = "disabled"; }; spi_bus2: spi@12122000 { @@ -156,7 +156,7 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; - status = "disable"; + status = "disabled"; }; sysctrl: system-controller@12020000 { diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index 72c55e5187ca..f36063c57c7f 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -440,7 +440,7 @@ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -460,7 +460,7 @@ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; @@ -480,7 +480,7 @@ clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>; clock-names = "stmmaceth", "ptp_ref"; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; snps,axi-config = <&socfpga_axi_setup>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/marvell/armada-370-dlink-dns327l.dts b/arch/arm/boot/dts/marvell/armada-370-dlink-dns327l.dts index 561195b749eb..d4c4efabd254 100644 --- a/arch/arm/boot/dts/marvell/armada-370-dlink-dns327l.dts +++ b/arch/arm/boot/dts/marvell/armada-370-dlink-dns327l.dts @@ -105,54 +105,45 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - pinctrl-0 = <&xhci_pwr_pin>; - pinctrl-names = "default"; - regulator-name = "USB3.0 Port Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; - }; + usb_power: regulator-1 { + compatible = "regulator-fixed"; + pinctrl-0 = <&xhci_pwr_pin>; + pinctrl-names = "default"; + regulator-name = "USB3.0 Port Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; + }; - sata_r_power: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - pinctrl-0 = <&sata_r_pwr_pin>; - pinctrl-names = "default"; - regulator-name = "SATA-R Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <2000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - }; + sata_r_power: regulator-2 { + compatible = "regulator-fixed"; + pinctrl-0 = <&sata_r_pwr_pin>; + pinctrl-names = "default"; + regulator-name = "SATA-R Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <2000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; + }; - sata_l_power: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - pinctrl-0 = <&sata_l_pwr_pin>; - pinctrl-names = "default"; - regulator-name = "SATA-L Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <4000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; - }; + sata_l_power: regulator-3 { + compatible = "regulator-fixed"; + pinctrl-0 = <&sata_l_pwr_pin>; + pinctrl-names = "default"; + regulator-name = "SATA-L Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <4000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/marvell/armada-370-seagate-nas-4bay.dts b/arch/arm/boot/dts/marvell/armada-370-seagate-nas-4bay.dts index 9cb69999b1db..370ca9c43247 100644 --- a/arch/arm/boot/dts/marvell/armada-370-seagate-nas-4bay.dts +++ b/arch/arm/boot/dts/marvell/armada-370-seagate-nas-4bay.dts @@ -46,29 +46,26 @@ }; }; - regulators { - regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "SATA2 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&pca9554 6 GPIO_ACTIVE_HIGH>; - }; - regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "SATA3 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&pca9554 7 GPIO_ACTIVE_HIGH>; - }; + regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "SATA2 power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&pca9554 6 GPIO_ACTIVE_HIGH>; + }; + + regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "SATA3 power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&pca9554 7 GPIO_ACTIVE_HIGH>; }; gpio-leds { diff --git a/arch/arm/boot/dts/marvell/armada-370-seagate-nas-xbay.dtsi b/arch/arm/boot/dts/marvell/armada-370-seagate-nas-xbay.dtsi index 822f10734946..ffb3179033e7 100644 --- a/arch/arm/boot/dts/marvell/armada-370-seagate-nas-xbay.dtsi +++ b/arch/arm/boot/dts/marvell/armada-370-seagate-nas-xbay.dtsi @@ -70,34 +70,26 @@ }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; - }; - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - }; + regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "SATA0 power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + }; + + regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "SATA1 power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; }; gpio-fan { diff --git a/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud-2bay.dts b/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud-2bay.dts index 5ee572dc9242..45d8ec5dfeb7 100644 --- a/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud-2bay.dts +++ b/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud-2bay.dts @@ -32,17 +32,14 @@ }; }; - regulators { - regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA1 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; - }; + regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "SATA1 power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dtsi index 124a8ba279e3..054124857235 100644 --- a/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dtsi +++ b/arch/arm/boot/dts/marvell/armada-370-seagate-personal-cloud.dtsi @@ -53,32 +53,25 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 27 GPIO_ACTIVE_LOW>; - }; - regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA0 power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; - }; + regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 27 GPIO_ACTIVE_LOW>; + }; + + regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "SATA0 power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; }; gpio-keys { diff --git a/arch/arm/boot/dts/marvell/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/marvell/armada-370-synology-ds213j.dts index f0893cc06607..b07d11d1f124 100644 --- a/arch/arm/boot/dts/marvell/armada-370-synology-ds213j.dts +++ b/arch/arm/boot/dts/marvell/armada-370-synology-ds213j.dts @@ -142,38 +142,32 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>; + sata1_regulator: sata1-regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <2000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sata1_pwr_pin>; pinctrl-names = "default"; + }; - sata1_regulator: sata1-regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <2000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; - }; - - sata2_regulator: sata2-regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA2 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <4000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>; - }; + sata2_regulator: sata2-regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "SATA2 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <4000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sata2_pwr_pin>; + pinctrl-names = "default"; }; }; diff --git a/arch/arm/boot/dts/marvell/armada-382-rd-ac3x-48g4x2xl.dts b/arch/arm/boot/dts/marvell/armada-382-rd-ac3x-48g4x2xl.dts index 584f0d0398a5..6ab65d21861a 100644 --- a/arch/arm/boot/dts/marvell/armada-382-rd-ac3x-48g4x2xl.dts +++ b/arch/arm/boot/dts/marvell/armada-382-rd-ac3x-48g4x2xl.dts @@ -40,7 +40,7 @@ pinctrl-0 = <&i2c0_pins>; status = "okay"; - eeprom@53{ + eeprom@53 { compatible = "atmel,24c64"; reg = <0x53>; }; @@ -95,11 +95,11 @@ reg = <0x00000000 0x00500000>; label = "u-boot"; }; - partition@500000{ + partition@500000 { reg = <0x00500000 0x00400000>; label = "u-boot env"; }; - partition@900000{ + partition@900000 { reg = <0x00900000 0x3F700000>; label = "user"; }; diff --git a/arch/arm/boot/dts/marvell/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/marvell/armada-xp-synology-ds414.dts index 5551bac1962c..1b65059794bf 100644 --- a/arch/arm/boot/dts/marvell/armada-xp-synology-ds414.dts +++ b/arch/arm/boot/dts/marvell/armada-xp-synology-ds414.dts @@ -109,65 +109,60 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin - &sata3_pwr_pin &sata4_pwr_pin>; + sata1_regulator: sata1-regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <2000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sata1_pwr_pin>; pinctrl-names = "default"; + }; - sata1_regulator: sata1-regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "SATA1 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <2000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; - }; - - sata2_regulator: sata2-regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "SATA2 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <4000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - }; + sata2_regulator: sata2-regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "SATA2 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <4000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sata2_pwr_pin>; + pinctrl-names = "default"; + }; - sata3_regulator: sata3-regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "SATA3 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <6000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; - }; + sata3_regulator: sata3-regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "SATA3 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <6000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sata3_pwr_pin>; + pinctrl-names = "default"; + }; - sata4_regulator: sata4-regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "SATA4 Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - startup-delay-us = <8000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - }; + sata4_regulator: sata4-regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "SATA4 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <8000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sata4_pwr_pin>; + pinctrl-names = "default"; }; }; diff --git a/arch/arm/boot/dts/marvell/dove-cm-a510.dtsi b/arch/arm/boot/dts/marvell/dove-cm-a510.dtsi index 1082fdfbfe60..621cb145a8f6 100644 --- a/arch/arm/boot/dts/marvell/dove-cm-a510.dtsi +++ b/arch/arm/boot/dts/marvell/dove-cm-a510.dtsi @@ -108,18 +108,12 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - wifi_power: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "WiFi Power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; - }; + wifi_power: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "WiFi Power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/marvell/dove-cubox.dts b/arch/arm/boot/dts/marvell/dove-cubox.dts index dbba0c8cdab1..bfde99486a87 100644 --- a/arch/arm/boot/dts/marvell/dove-cubox.dts +++ b/arch/arm/boot/dts/marvell/dove-cubox.dts @@ -28,24 +28,17 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 1 0>; - pinctrl-0 = <&pmx_gpio_1>; - pinctrl-names = "default"; - }; + usb_power: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 1 0>; + pinctrl-0 = <&pmx_gpio_1>; + pinctrl-names = "default"; }; clocks { diff --git a/arch/arm/boot/dts/marvell/dove-d3plug.dts b/arch/arm/boot/dts/marvell/dove-d3plug.dts index 5aa5d4a7d51d..a451fd576990 100644 --- a/arch/arm/boot/dts/marvell/dove-d3plug.dts +++ b/arch/arm/boot/dts/marvell/dove-d3plug.dts @@ -37,24 +37,17 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - usb_power: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - regulator-always-on; - regulator-boot-on; - gpio = <&gpio0 8 0>; - pinctrl-0 = <&pmx_gpio_8>; - pinctrl-names = "default"; - }; + usb_power: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 8 0>; + pinctrl-0 = <&pmx_gpio_8>; + pinctrl-names = "default"; }; }; diff --git a/arch/arm/boot/dts/marvell/dove-sbc-a510.dts b/arch/arm/boot/dts/marvell/dove-sbc-a510.dts index df021f9b0117..8585ee5533bf 100644 --- a/arch/arm/boot/dts/marvell/dove-sbc-a510.dts +++ b/arch/arm/boot/dts/marvell/dove-sbc-a510.dts @@ -76,22 +76,20 @@ stdout-path = &uart0; }; - regulators { - usb0_power: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "USB Power"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio_ext 0 GPIO_ACTIVE_HIGH>; - }; - - mmc_power: regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "MMC Power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio_ext 13 GPIO_ACTIVE_HIGH>; - }; + usb0_power: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "USB Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio_ext 0 GPIO_ACTIVE_HIGH>; + }; + + mmc_power: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "MMC Power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio_ext 13 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-l-50.dts b/arch/arm/boot/dts/marvell/kirkwood-l-50.dts index 9fd3581bb24b..dffb9f84e67c 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-l-50.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-l-50.dts @@ -62,7 +62,7 @@ status = "okay"; clock-frequency = <400000>; - gpio2: gpio-expander@20{ + gpio2: gpio-expander@20 { #gpio-cells = <2>; #interrupt-cells = <2>; compatible = "semtech,sx1505q"; @@ -76,7 +76,7 @@ * 5: mPCIE reset (active low) * 6: Express card reset (active low) */ - gpio3: gpio-expander@21{ + gpio3: gpio-expander@21 { #gpio-cells = <2>; #interrupt-cells = <2>; compatible = "semtech,sx1505q"; diff --git a/arch/arm/boot/dts/marvell/pxa168.dtsi b/arch/arm/boot/dts/marvell/pxa168.dtsi index 16212b912b94..22ed10cb5619 100644 --- a/arch/arm/boot/dts/marvell/pxa168.dtsi +++ b/arch/arm/boot/dts/marvell/pxa168.dtsi @@ -153,7 +153,7 @@ }; }; - soc_clocks: clocks{ + soc_clocks: clocks { compatible = "marvell,pxa168-clock"; reg = <0xd4050000 0x1000>, <0xd4282800 0x400>, diff --git a/arch/arm/boot/dts/marvell/pxa910.dtsi b/arch/arm/boot/dts/marvell/pxa910.dtsi index 352a39357810..bd64ac1ec66f 100644 --- a/arch/arm/boot/dts/marvell/pxa910.dtsi +++ b/arch/arm/boot/dts/marvell/pxa910.dtsi @@ -163,7 +163,7 @@ }; }; - soc_clocks: clocks{ + soc_clocks: clocks { compatible = "marvell,pxa910-clock"; reg = <0xd4050000 0x1000>, <0xd4282800 0x400>, diff --git a/arch/arm/boot/dts/microchip/Makefile b/arch/arm/boot/dts/microchip/Makefile index 0f5193d05a31..31e03747cdf4 100644 --- a/arch/arm/boot/dts/microchip/Makefile +++ b/arch/arm/boot/dts/microchip/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +# Enables support for device-tree overlays DTC_FLAGS_at91-sam9x60_curiosity := -@ DTC_FLAGS_at91-sam9x60ek := -@ DTC_FLAGS_at91-sama5d27_som1_ek := -@ @@ -54,21 +55,9 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \ at91sam9g35ek.dtb \ at91sam9x25ek.dtb \ at91sam9x35ek.dtb -# Enables support for device-tree overlays -DTC_FLAGS_at91-sam9x60_curiosity := -@ -DTC_FLAGS_at91-sam9x60ek := -@ dtb-$(CONFIG_SOC_SAM9X60) += \ at91-sam9x60_curiosity.dtb \ at91-sam9x60ek.dtb -# Enables support for device-tree overlays -DTC_FLAGS_at91-sama5d27_som1_ek := -@ -DTC_FLAGS_at91-sama5d27_wlsom1_ek := -@ -DTC_FLAGS_at91-sama5d2_icp := -@ -DTC_FLAGS_at91-sama5d2_ptc_ek := -@ -DTC_FLAGS_at91-sama5d2_xplained := -@ -DTC_FLAGS_at91-sama5d3_eds := -@ -DTC_FLAGS_at91-sama5d3_xplained := -@ -DTC_FLAGS_at91-sama5d4_xplained := -@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-kizbox2-2.dtb \ at91-kizbox3-hs.dtb \ @@ -95,8 +84,6 @@ dtb-$(CONFIG_SOC_SAM_V7) += \ at91-sama5d4_xplained.dtb \ at91-sama5d4ek.dtb \ at91-vinco.dtb -# Enables support for device-tree overlays -DTC_FLAGS_at91-sama7g5ek := -@ dtb-$(CONFIG_SOC_SAMA7G5) += \ at91-sama7g5ek.dtb diff --git a/arch/arm/boot/dts/microchip/at91-sama5d3_ksz9477_evb.dts b/arch/arm/boot/dts/microchip/at91-sama5d3_ksz9477_evb.dts index 14af1fd6d247..b66570080894 100644 --- a/arch/arm/boot/dts/microchip/at91-sama5d3_ksz9477_evb.dts +++ b/arch/arm/boot/dts/microchip/at91-sama5d3_ksz9477_evb.dts @@ -152,6 +152,7 @@ label = "cpu"; ethernet = <&macb0>; phy-mode = "rgmii-txid"; + tx-internal-delay-ps = <2000>; fixed-link { speed = <1000>; @@ -162,6 +163,18 @@ }; }; +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + &usb0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; diff --git a/arch/arm/boot/dts/microchip/at91-vinco.dts b/arch/arm/boot/dts/microchip/at91-vinco.dts index ebeaa6ab500e..ecbdacf48708 100644 --- a/arch/arm/boot/dts/microchip/at91-vinco.dts +++ b/arch/arm/boot/dts/microchip/at91-vinco.dts @@ -159,7 +159,7 @@ atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usba_vbus>; - status = "disable"; + status = "disabled"; }; usb1: ohci@500000 { @@ -168,7 +168,7 @@ &pioE 11 GPIO_ACTIVE_LOW &pioE 12 GPIO_ACTIVE_LOW >; - status = "disable"; + status = "disabled"; }; usb2: ehci@600000 { diff --git a/arch/arm/boot/dts/microchip/at91rm9200.dtsi b/arch/arm/boot/dts/microchip/at91rm9200.dtsi index 37b500f6f395..16c675e3a890 100644 --- a/arch/arm/boot/dts/microchip/at91rm9200.dtsi +++ b/arch/arm/boot/dts/microchip/at91rm9200.dtsi @@ -135,9 +135,9 @@ #address-cells = <1>; #size-cells = <0>; reg = <0xfffa0000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 - 18 IRQ_TYPE_LEVEL_HIGH 0 - 19 IRQ_TYPE_LEVEL_HIGH 0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>, + <18 IRQ_TYPE_LEVEL_HIGH 0>, + <19 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&slow_xtal>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -147,9 +147,9 @@ #address-cells = <1>; #size-cells = <0>; reg = <0xfffa4000 0x100>; - interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 - 21 IRQ_TYPE_LEVEL_HIGH 0 - 22 IRQ_TYPE_LEVEL_HIGH 0>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>, + <21 IRQ_TYPE_LEVEL_HIGH 0>, + <22 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&slow_xtal>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; diff --git a/arch/arm/boot/dts/microchip/at91sam9260.dtsi b/arch/arm/boot/dts/microchip/at91sam9260.dtsi index 35a007365b6a..e56d5546554c 100644 --- a/arch/arm/boot/dts/microchip/at91sam9260.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9260.dtsi @@ -65,7 +65,7 @@ clock-frequency = <0>; }; - adc_op_clk: adc_op_clk{ + adc_op_clk: adc_op_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <5000000>; @@ -148,9 +148,9 @@ #address-cells = <1>; #size-cells = <0>; reg = <0xfffa0000 0x100>; - interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 - 18 IRQ_TYPE_LEVEL_HIGH 0 - 19 IRQ_TYPE_LEVEL_HIGH 0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>, + <18 IRQ_TYPE_LEVEL_HIGH 0>, + <19 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&pmc PMC_TYPE_CORE PMC_SLOW>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; @@ -160,9 +160,9 @@ #address-cells = <1>; #size-cells = <0>; reg = <0xfffdc000 0x100>; - interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 - 27 IRQ_TYPE_LEVEL_HIGH 0 - 28 IRQ_TYPE_LEVEL_HIGH 0>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>, + <27 IRQ_TYPE_LEVEL_HIGH 0>, + <28 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 28>, <&pmc PMC_TYPE_CORE PMC_SLOW>; clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; }; diff --git a/arch/arm/boot/dts/microchip/at91sam9261.dtsi b/arch/arm/boot/dts/microchip/at91sam9261.dtsi index 528ffc6f6f96..307b60658014 100644 --- a/arch/arm/boot/dts/microchip/at91sam9261.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9261.dtsi @@ -205,7 +205,7 @@ status = "disabled"; }; - usart2: serial@fffb8000{ + usart2: serial@fffb8000 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffb8000 0x200>; atmel,usart-mode = <AT91_USART_MODE_SERIAL>; diff --git a/arch/arm/boot/dts/microchip/at91sam9g20ek_2mmc.dts b/arch/arm/boot/dts/microchip/at91sam9g20ek_2mmc.dts index 2db95e8ffc64..172af6ff4b18 100644 --- a/arch/arm/boot/dts/microchip/at91sam9g20ek_2mmc.dts +++ b/arch/arm/boot/dts/microchip/at91sam9g20ek_2mmc.dts @@ -12,7 +12,7 @@ compatible = "atmel,at91sam9g20ek_2mmc", "atmel,at91sam9g20", "atmel,at91sam9"; ahb { - apb{ + apb { mmc0: mmc@fffa8000 { /* clk already mux wuth slot0 */ pinctrl-0 = < diff --git a/arch/arm/boot/dts/microchip/at91sam9g45.dtsi b/arch/arm/boot/dts/microchip/at91sam9g45.dtsi index 7cccc606e36c..325c63a53118 100644 --- a/arch/arm/boot/dts/microchip/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9g45.dtsi @@ -70,7 +70,7 @@ clock-frequency = <0>; }; - adc_op_clk: adc_op_clk{ + adc_op_clk: adc_op_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <300000>; diff --git a/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts b/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts index 7f45e81ca165..071db4f16313 100644 --- a/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/microchip/at91sam9m10g45ek.dts @@ -164,7 +164,7 @@ }; }; - spi0: spi@fffa4000{ + spi0: spi@fffa4000 { status = "okay"; cs-gpios = <&pioB 3 0>, <0>, <0>, <0>; flash@0 { diff --git a/arch/arm/boot/dts/microchip/at91sam9rl.dtsi b/arch/arm/boot/dts/microchip/at91sam9rl.dtsi index 3d089ffbe162..7436b5c862b1 100644 --- a/arch/arm/boot/dts/microchip/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9rl.dtsi @@ -67,7 +67,7 @@ clock-frequency = <0>; }; - adc_op_clk: adc_op_clk{ + adc_op_clk: adc_op_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; diff --git a/arch/arm/boot/dts/microchip/at91sam9x5.dtsi b/arch/arm/boot/dts/microchip/at91sam9x5.dtsi index a1fed912f2ee..a7456c2191fa 100644 --- a/arch/arm/boot/dts/microchip/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/microchip/at91sam9x5.dtsi @@ -68,7 +68,7 @@ clock-frequency = <0>; }; - adc_op_clk: adc_op_clk{ + adc_op_clk: adc_op_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; diff --git a/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts b/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts index 8804e8ba5370..3b7577e48b46 100644 --- a/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts +++ b/arch/arm/boot/dts/microchip/lan966x-pcb8290.dts @@ -28,7 +28,7 @@ &gpio { miim_a_pins: mdio-pins { /* MDC, MDIO */ - pins = "GPIO_28", "GPIO_29"; + pins = "GPIO_28", "GPIO_29"; function = "miim_a"; }; diff --git a/arch/arm/boot/dts/microchip/sama5d2.dtsi b/arch/arm/boot/dts/microchip/sama5d2.dtsi index daeeb24e5f4d..5f8e297e19ed 100644 --- a/arch/arm/boot/dts/microchip/sama5d2.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d2.dtsi @@ -382,9 +382,9 @@ macb0: ethernet@f8008000 { compatible = "atmel,sama5d2-gem"; reg = <0xf8008000 0x1000>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */ - 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */ - 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 0 */ + <66 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 1 */ + <67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */ clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>; clock-names = "hclk", "pclk"; status = "disabled"; diff --git a/arch/arm/boot/dts/microchip/sama5d3.dtsi b/arch/arm/boot/dts/microchip/sama5d3.dtsi index d9e66700d1c2..d4fc0c1dfc10 100644 --- a/arch/arm/boot/dts/microchip/sama5d3.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d3.dtsi @@ -74,7 +74,7 @@ clock-frequency = <0>; }; - adc_op_clk: adc_op_clk{ + adc_op_clk: adc_op_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; diff --git a/arch/arm/boot/dts/microchip/sama5d4.dtsi b/arch/arm/boot/dts/microchip/sama5d4.dtsi index 41284e013f53..50650e2f4267 100644 --- a/arch/arm/boot/dts/microchip/sama5d4.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d4.dtsi @@ -72,7 +72,7 @@ clock-frequency = <0>; }; - adc_op_clk: adc_op_clk{ + adc_op_clk: adc_op_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; diff --git a/arch/arm/boot/dts/microchip/sama7g5.dtsi b/arch/arm/boot/dts/microchip/sama7g5.dtsi index 9642a42d84e6..269e0a3ca269 100644 --- a/arch/arm/boot/dts/microchip/sama7g5.dtsi +++ b/arch/arm/boot/dts/microchip/sama7g5.dtsi @@ -366,8 +366,8 @@ compatible = "bosch,m_can"; reg = <0xe0828000 0x100>, <0x100000 0x7800>; reg-names = "m_can", "message_ram"; - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>; clock-names = "hclk", "cclk"; @@ -382,8 +382,8 @@ compatible = "bosch,m_can"; reg = <0xe082c000 0x100>, <0x100000 0xbc00>; reg-names = "m_can", "message_ram"; - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>; clock-names = "hclk", "cclk"; @@ -398,8 +398,8 @@ compatible = "bosch,m_can"; reg = <0xe0830000 0x100>, <0x100000 0x10000>; reg-names = "m_can", "message_ram"; - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>; clock-names = "hclk", "cclk"; @@ -414,8 +414,8 @@ compatible = "bosch,m_can"; reg = <0xe0834000 0x100>, <0x110000 0x4400>; reg-names = "m_can", "message_ram"; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>; clock-names = "hclk", "cclk"; @@ -430,8 +430,8 @@ compatible = "bosch,m_can"; reg = <0xe0838000 0x100>, <0x110000 0x8800>; reg-names = "m_can", "message_ram"; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>; clock-names = "hclk", "cclk"; @@ -446,8 +446,8 @@ compatible = "bosch,m_can"; reg = <0xe083c000 0x100>, <0x110000 0xcc00>; reg-names = "m_can", "message_ram"; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; clock-names = "hclk", "cclk"; @@ -845,12 +845,12 @@ gmac0: ethernet@e2800000 { compatible = "microchip,sama7g5-gem"; reg = <0xe2800000 0x1000>; - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>; clock-names = "pclk", "hclk", "tx_clk", "tsu_clk"; assigned-clocks = <&pmc PMC_TYPE_GCK 51>; @@ -861,8 +861,8 @@ gmac1: ethernet@e2804000 { compatible = "microchip,sama7g5-emac"; reg = <0xe2804000 0x1000>; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>; clock-names = "pclk", "hclk"; status = "disabled"; diff --git a/arch/arm/boot/dts/nspire/nspire-classic.dtsi b/arch/arm/boot/dts/nspire/nspire-classic.dtsi index 01e1bb7c3c6c..a6e9cbf51524 100644 --- a/arch/arm/boot/dts/nspire/nspire-classic.dtsi +++ b/arch/arm/boot/dts/nspire/nspire-classic.dtsi @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * linux/arch/arm/boot/nspire-classic.dts - * * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> */ diff --git a/arch/arm/boot/dts/nspire/nspire-clp.dts b/arch/arm/boot/dts/nspire/nspire-clp.dts index f52f38c61588..c5773f770fd4 100644 --- a/arch/arm/boot/dts/nspire/nspire-clp.dts +++ b/arch/arm/boot/dts/nspire/nspire-clp.dts @@ -1,37 +1,82 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * linux/arch/arm/boot/nspire-clp.dts - * * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> */ + /dts-v1/; +#include <dt-bindings/input/input.h> + /include/ "nspire-classic.dtsi" &keypad { linux,keymap = < - 0x0000001c 0x0001001c 0x00020039 - 0x0004002c 0x00050034 0x00060015 - 0x0007000b 0x0008002d 0x01000033 - 0x0101004e 0x01020011 0x01030004 - 0x0104002f 0x01050003 0x01060016 - 0x01070002 0x01080014 0x02000062 - 0x0201000c 0x0202001f 0x02030007 - 0x02040013 0x02050006 0x02060010 - 0x02070005 0x02080019 0x03000027 - 0x03010037 0x03020018 0x0303000a - 0x03040031 0x03050009 0x03060032 - 0x03070008 0x03080026 0x04000028 - 0x04010035 0x04020025 0x04040024 - 0x04060017 0x04080023 0x05000028 - 0x05020022 0x0503001b 0x05040021 - 0x0505001a 0x05060012 0x0507006f - 0x05080020 0x0509002a 0x0601001c - 0x0602002e 0x06030068 0x06040030 - 0x0605006d 0x0606001e 0x06070001 - 0x0608002b 0x0609000f 0x07000067 - 0x0702006a 0x0704006c 0x07060069 - 0x0707000e 0x0708001d 0x070a000d + MATRIX_KEY(0, 0, 0x1c) + MATRIX_KEY(0, 1, 0x1c) + MATRIX_KEY(0, 2, 0x39) + MATRIX_KEY(0, 4, 0x2c) + MATRIX_KEY(0, 5, 0x34) + MATRIX_KEY(0, 6, 0x15) + MATRIX_KEY(0, 7, 0x0b) + MATRIX_KEY(0, 8, 0x2d) + MATRIX_KEY(1, 0, 0x33) + MATRIX_KEY(1, 1, 0x4e) + MATRIX_KEY(1, 2, 0x11) + MATRIX_KEY(1, 3, 0x04) + MATRIX_KEY(1, 4, 0x2f) + MATRIX_KEY(1, 5, 0x03) + MATRIX_KEY(1, 6, 0x16) + MATRIX_KEY(1, 7, 0x02) + MATRIX_KEY(1, 8, 0x14) + MATRIX_KEY(2, 0, 0x62) + MATRIX_KEY(2, 1, 0x0c) + MATRIX_KEY(2, 2, 0x1f) + MATRIX_KEY(2, 3, 0x07) + MATRIX_KEY(2, 4, 0x13) + MATRIX_KEY(2, 5, 0x06) + MATRIX_KEY(2, 6, 0x10) + MATRIX_KEY(2, 7, 0x05) + MATRIX_KEY(2, 8, 0x19) + MATRIX_KEY(3, 0, 0x27) + MATRIX_KEY(3, 1, 0x37) + MATRIX_KEY(3, 2, 0x18) + MATRIX_KEY(3, 3, 0x0a) + MATRIX_KEY(3, 4, 0x31) + MATRIX_KEY(3, 5, 0x09) + MATRIX_KEY(3, 6, 0x32) + MATRIX_KEY(3, 7, 0x08) + MATRIX_KEY(3, 8, 0x26) + MATRIX_KEY(4, 0, 0x28) + MATRIX_KEY(4, 1, 0x35) + MATRIX_KEY(4, 2, 0x25) + MATRIX_KEY(4, 4, 0x24) + MATRIX_KEY(4, 6, 0x17) + MATRIX_KEY(4, 8, 0x23) + MATRIX_KEY(5, 0, 0x28) + MATRIX_KEY(5, 2, 0x22) + MATRIX_KEY(5, 3, 0x1b) + MATRIX_KEY(5, 4, 0x21) + MATRIX_KEY(5, 5, 0x1a) + MATRIX_KEY(5, 6, 0x12) + MATRIX_KEY(5, 7, 0x6f) + MATRIX_KEY(5, 8, 0x20) + MATRIX_KEY(5, 9, 0x2a) + MATRIX_KEY(6, 1, 0x1c) + MATRIX_KEY(6, 2, 0x2e) + MATRIX_KEY(6, 3, 0x68) + MATRIX_KEY(6, 4, 0x30) + MATRIX_KEY(6, 5, 0x6d) + MATRIX_KEY(6, 6, 0x1e) + MATRIX_KEY(6, 7, 0x01) + MATRIX_KEY(6, 8, 0x2b) + MATRIX_KEY(6, 9, 0x0f) + MATRIX_KEY(7, 0, 0x67) + MATRIX_KEY(7, 2, 0x6a) + MATRIX_KEY(7, 4, 0x6c) + MATRIX_KEY(7, 6, 0x69) + MATRIX_KEY(7, 7, 0x0e) + MATRIX_KEY(7, 8, 0x1d) + MATRIX_KEY(7, 10, 0x0d) >; }; diff --git a/arch/arm/boot/dts/nspire/nspire-cx.dts b/arch/arm/boot/dts/nspire/nspire-cx.dts index 590b7dff6ae5..29f0181e5b38 100644 --- a/arch/arm/boot/dts/nspire/nspire-cx.dts +++ b/arch/arm/boot/dts/nspire/nspire-cx.dts @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * linux/arch/arm/boot/nspire-cx.dts - * * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> */ + /dts-v1/; +#include <dt-bindings/input/input.h> + /include/ "nspire.dtsi" &lcd { @@ -24,7 +25,7 @@ compatible = "arm,pl011", "arm,primecell"; clocks = <&uart_clk>, <&apb_pclk>; - clock-names = "uart_clk", "apb_pclk"; + clock-names = "uartclk", "apb_pclk"; }; &timer0 { @@ -45,28 +46,72 @@ &keypad { linux,keymap = < - 0x0000001c 0x0001001c 0x00040039 - 0x0005002c 0x00060015 0x0007000b - 0x0008000f 0x0100002d 0x01010011 - 0x0102002f 0x01030004 0x01040016 - 0x01050014 0x0106001f 0x01070002 - 0x010a006a 0x02000013 0x02010010 - 0x02020019 0x02030007 0x02040018 - 0x02050031 0x02060032 0x02070005 - 0x02080028 0x0209006c 0x03000026 - 0x03010025 0x03020024 0x0303000a - 0x03040017 0x03050023 0x03060022 - 0x03070008 0x03080035 0x03090069 - 0x04000021 0x04010012 0x04020020 - 0x0404002e 0x04050030 0x0406001e - 0x0407000d 0x04080037 0x04090067 - 0x05010038 0x0502000c 0x0503001b - 0x05040034 0x0505001a 0x05060006 - 0x05080027 0x0509000e 0x050a006f - 0x0600002b 0x0602004e 0x06030068 - 0x06040003 0x0605006d 0x06060009 - 0x06070001 0x0609000f 0x0708002a - 0x0709001d 0x070a0033 >; + MATRIX_KEY(0, 0, 0x1c) + MATRIX_KEY(0, 1, 0x1c) + MATRIX_KEY(0, 4, 0x39) + MATRIX_KEY(0, 5, 0x2c) + MATRIX_KEY(0, 6, 0x15) + MATRIX_KEY(0, 7, 0x0b) + MATRIX_KEY(0, 8, 0x0f) + MATRIX_KEY(1, 0, 0x2d) + MATRIX_KEY(1, 1, 0x11) + MATRIX_KEY(1, 2, 0x2f) + MATRIX_KEY(1, 3, 0x04) + MATRIX_KEY(1, 4, 0x16) + MATRIX_KEY(1, 5, 0x14) + MATRIX_KEY(1, 6, 0x1f) + MATRIX_KEY(1, 7, 0x02) + MATRIX_KEY(1, 10, 0x6a) + MATRIX_KEY(2, 0, 0x13) + MATRIX_KEY(2, 1, 0x10) + MATRIX_KEY(2, 2, 0x19) + MATRIX_KEY(2, 3, 0x07) + MATRIX_KEY(2, 4, 0x18) + MATRIX_KEY(2, 5, 0x31) + MATRIX_KEY(2, 6, 0x32) + MATRIX_KEY(2, 7, 0x05) + MATRIX_KEY(2, 8, 0x28) + MATRIX_KEY(2, 9, 0x6c) + MATRIX_KEY(3, 0, 0x26) + MATRIX_KEY(3, 1, 0x25) + MATRIX_KEY(3, 2, 0x24) + MATRIX_KEY(3, 3, 0x0a) + MATRIX_KEY(3, 4, 0x17) + MATRIX_KEY(3, 5, 0x23) + MATRIX_KEY(3, 6, 0x22) + MATRIX_KEY(3, 7, 0x08) + MATRIX_KEY(3, 8, 0x35) + MATRIX_KEY(3, 9, 0x69) + MATRIX_KEY(4, 0, 0x21) + MATRIX_KEY(4, 1, 0x12) + MATRIX_KEY(4, 2, 0x20) + MATRIX_KEY(4, 4, 0x2e) + MATRIX_KEY(4, 5, 0x30) + MATRIX_KEY(4, 6, 0x1e) + MATRIX_KEY(4, 7, 0x0d) + MATRIX_KEY(4, 8, 0x37) + MATRIX_KEY(4, 9, 0x67) + MATRIX_KEY(5, 1, 0x38) + MATRIX_KEY(5, 2, 0x0c) + MATRIX_KEY(5, 3, 0x1b) + MATRIX_KEY(5, 4, 0x34) + MATRIX_KEY(5, 5, 0x1a) + MATRIX_KEY(5, 6, 0x06) + MATRIX_KEY(5, 8, 0x27) + MATRIX_KEY(5, 9, 0x0e) + MATRIX_KEY(5, 10, 0x6f) + MATRIX_KEY(6, 0, 0x2b) + MATRIX_KEY(6, 2, 0x4e) + MATRIX_KEY(6, 3, 0x68) + MATRIX_KEY(6, 4, 0x03) + MATRIX_KEY(6, 5, 0x6d) + MATRIX_KEY(6, 6, 0x09) + MATRIX_KEY(6, 7, 0x01) + MATRIX_KEY(6, 9, 0x0f) + MATRIX_KEY(7, 8, 0x2a) + MATRIX_KEY(7, 9, 0x1d) + MATRIX_KEY(7, 10, 0x33) + >; }; &vbus_reg { diff --git a/arch/arm/boot/dts/nspire/nspire-tp.dts b/arch/arm/boot/dts/nspire/nspire-tp.dts index f7d0faacd4cc..3f0107f1c2c7 100644 --- a/arch/arm/boot/dts/nspire/nspire-tp.dts +++ b/arch/arm/boot/dts/nspire/nspire-tp.dts @@ -1,37 +1,82 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * linux/arch/arm/boot/nspire-tp.dts - * * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> */ + /dts-v1/; +#include <dt-bindings/input/input.h> + /include/ "nspire-classic.dtsi" &keypad { linux,keymap = < - 0x0000001c 0x0001001c 0x00040039 - 0x0005002c 0x00060015 0x0007000b - 0x0008000f 0x0100002d 0x01010011 - 0x0102002f 0x01030004 0x01040016 - 0x01050014 0x0106001f 0x01070002 - 0x010a006a 0x02000013 0x02010010 - 0x02020019 0x02030007 0x02040018 - 0x02050031 0x02060032 0x02070005 - 0x02080028 0x0209006c 0x03000026 - 0x03010025 0x03020024 0x0303000a - 0x03040017 0x03050023 0x03060022 - 0x03070008 0x03080035 0x03090069 - 0x04000021 0x04010012 0x04020020 - 0x0404002e 0x04050030 0x0406001e - 0x0407000d 0x04080037 0x04090067 - 0x05010038 0x0502000c 0x0503001b - 0x05040034 0x0505001a 0x05060006 - 0x05080027 0x0509000e 0x050a006f - 0x0600002b 0x0602004e 0x06030068 - 0x06040003 0x0605006d 0x06060009 - 0x06070001 0x0609000f 0x0708002a - 0x0709001d 0x070a0033 >; + MATRIX_KEY(0, 0, 0x1c) + MATRIX_KEY(0, 1, 0x1c) + MATRIX_KEY(0, 4, 0x39) + MATRIX_KEY(0, 5, 0x2c) + MATRIX_KEY(0, 6, 0x15) + MATRIX_KEY(0, 7, 0x0b) + MATRIX_KEY(0, 8, 0x0f) + MATRIX_KEY(1, 0, 0x2d) + MATRIX_KEY(1, 1, 0x11) + MATRIX_KEY(1, 2, 0x2f) + MATRIX_KEY(1, 3, 0x04) + MATRIX_KEY(1, 4, 0x16) + MATRIX_KEY(1, 5, 0x14) + MATRIX_KEY(1, 6, 0x1f) + MATRIX_KEY(1, 7, 0x02) + MATRIX_KEY(1, 10, 0x6a) + MATRIX_KEY(2, 0, 0x13) + MATRIX_KEY(2, 1, 0x10) + MATRIX_KEY(2, 2, 0x19) + MATRIX_KEY(2, 3, 0x07) + MATRIX_KEY(2, 4, 0x18) + MATRIX_KEY(2, 5, 0x31) + MATRIX_KEY(2, 6, 0x32) + MATRIX_KEY(2, 7, 0x05) + MATRIX_KEY(2, 8, 0x28) + MATRIX_KEY(2, 9, 0x6c) + MATRIX_KEY(3, 0, 0x26) + MATRIX_KEY(3, 1, 0x25) + MATRIX_KEY(3, 2, 0x24) + MATRIX_KEY(3, 3, 0x0a) + MATRIX_KEY(3, 4, 0x17) + MATRIX_KEY(3, 5, 0x23) + MATRIX_KEY(3, 6, 0x22) + MATRIX_KEY(3, 7, 0x08) + MATRIX_KEY(3, 8, 0x35) + MATRIX_KEY(3, 9, 0x69) + MATRIX_KEY(4, 0, 0x21) + MATRIX_KEY(4, 1, 0x12) + MATRIX_KEY(4, 2, 0x20) + MATRIX_KEY(4, 4, 0x2e) + MATRIX_KEY(4, 5, 0x30) + MATRIX_KEY(4, 6, 0x1e) + MATRIX_KEY(4, 7, 0x0d) + MATRIX_KEY(4, 8, 0x37) + MATRIX_KEY(4, 9, 0x67) + MATRIX_KEY(5, 1, 0x38) + MATRIX_KEY(5, 2, 0x0c) + MATRIX_KEY(5, 3, 0x1b) + MATRIX_KEY(5, 4, 0x34) + MATRIX_KEY(5, 5, 0x1a) + MATRIX_KEY(5, 6, 0x06) + MATRIX_KEY(5, 8, 0x27) + MATRIX_KEY(5, 9, 0x0e) + MATRIX_KEY(5, 10, 0x6f) + MATRIX_KEY(6, 0, 0x2b) + MATRIX_KEY(6, 2, 0x4e) + MATRIX_KEY(6, 3, 0x68) + MATRIX_KEY(6, 4, 0x03) + MATRIX_KEY(6, 5, 0x6d) + MATRIX_KEY(6, 6, 0x09) + MATRIX_KEY(6, 7, 0x01) + MATRIX_KEY(6, 9, 0x0f) + MATRIX_KEY(7, 8, 0x2a) + MATRIX_KEY(7, 9, 0x1d) + MATRIX_KEY(7, 10, 0x33) + >; }; / { diff --git a/arch/arm/boot/dts/nspire/nspire.dtsi b/arch/arm/boot/dts/nspire/nspire.dtsi index 088bcc38589f..d56fef7250db 100644 --- a/arch/arm/boot/dts/nspire/nspire.dtsi +++ b/arch/arm/boot/dts/nspire/nspire.dtsi @@ -1,7 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * linux/arch/arm/boot/nspire.dtsi - * * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au> */ @@ -11,8 +9,13 @@ interrupt-parent = <&intc>; cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; }; }; @@ -21,8 +24,15 @@ }; sram: sram@a4000000 { - device = "memory"; - reg = <0xa4000000 0x20000>; + compatible = "mmio-sram"; + reg = <0xa4000000 0x20000>; /* 128k */ + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xa4000000 0x20000>; + + sram@0 { + reg = <0x0 0x20000>; + }; }; timer_clk: timer_clk { @@ -59,7 +69,6 @@ compatible = "regulator-fixed"; regulator-name = "USB VBUS output"; - regulator-type = "voltage"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; @@ -172,7 +181,14 @@ }; misc: misc@900a0000 { + compatible = "ti,nspire-misc", "syscon", "simple-mfd"; reg = <0x900a0000 0x1000>; + + reboot { + compatible = "syscon-reboot"; + offset = <0x08>; + value = <0x02>; + }; }; pwr: pwr@900b0000 { diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts index 9e9eba8bad5e..9f64c85e1c20 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gbs.dts @@ -525,7 +525,7 @@ clock-frequency = <100000>; status = "okay"; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9546"; #address-cells = <1>; #size-cells = <0>; @@ -666,7 +666,7 @@ reg = <0x50>; }; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9546"; #address-cells = <1>; #size-cells = <0>; @@ -727,7 +727,7 @@ clock-frequency = <100000>; status = "okay"; - i2c-switch@73 { + i2c-mux@73 { compatible = "nxp,pca9545"; #address-cells = <1>; #size-cells = <0>; @@ -763,7 +763,7 @@ clock-frequency = <100000>; status = "okay"; - i2c-switch@72 { + i2c-mux@72 { compatible = "nxp,pca9545"; #address-cells = <1>; #size-cells = <0>; @@ -812,7 +812,7 @@ clock-frequency = <100000>; status = "okay"; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9546"; #address-cells = <1>; #size-cells = <0>; @@ -866,7 +866,7 @@ clock-frequency = <100000>; status = "okay"; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9545"; #address-cells = <1>; #size-cells = <0>; @@ -902,7 +902,7 @@ clock-frequency = <100000>; status = "okay"; - i2c-switch@76 { + i2c-mux@76 { compatible = "nxp,pca9545"; #address-cells = <1>; #size-cells = <0>; @@ -961,7 +961,7 @@ clock-frequency = <100000>; status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9545"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts index 2a394cc15284..9b1cc7f4adf0 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-gsj.dts @@ -303,7 +303,7 @@ &i2c15 { status = "okay"; - i2c-switch@75 { + i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts index f7b38bee039b..58329adbd918 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts @@ -494,7 +494,7 @@ &i2c1 { status = "okay"; - i2c-switch@75 { + i2c-mux@75 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -573,7 +573,7 @@ }; }; }; - i2c-switch@77 { + i2c-mux@77 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -613,7 +613,7 @@ &i2c4 { status = "okay"; - i2c-switch@77 { + i2c-mux@77 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -684,7 +684,7 @@ &i2c13 { status = "okay"; - i2c-switch@77 { + i2c-mux@77 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts index 87359ab05db3..209fa3400317 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts @@ -208,7 +208,7 @@ &i2c1 { status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; @@ -258,7 +258,7 @@ }; }; - i2c-switch@71 { + i2c-mux@71 { compatible = "nxp,pca9546"; reg = <0x71>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts index 84a3eb38e71d..763ab812eb87 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/nvidia/tegra114-asus-tf701t.dts @@ -271,6 +271,8 @@ }; serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra114-dalmore.dts b/arch/arm/boot/dts/nvidia/tegra114-dalmore.dts index a685fcb129d0..c06b52fe330a 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/nvidia/tegra114-dalmore.dts @@ -755,6 +755,8 @@ }; serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra114-roth.dts b/arch/arm/boot/dts/nvidia/tegra114-roth.dts index b9d00009d1f4..a89b16573b42 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-roth.dts +++ b/arch/arm/boot/dts/nvidia/tegra114-roth.dts @@ -779,6 +779,8 @@ /* Usable on reworked devices only */ serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra114-tn7.dts b/arch/arm/boot/dts/nvidia/tegra114-tn7.dts index f02d8c79eee7..bfbdb345575a 100644 --- a/arch/arm/boot/dts/nvidia/tegra114-tn7.dts +++ b/arch/arm/boot/dts/nvidia/tegra114-tn7.dts @@ -50,6 +50,8 @@ }; serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi index 09996acad639..86f14e2fd29f 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -315,7 +315,6 @@ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_UARTA>; resets = <&tegra_car 6>; - reset-names = "serial"; dmas = <&apbdma 8>, <&apbdma 8>; dma-names = "rx", "tx"; status = "disabled"; @@ -328,7 +327,6 @@ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_UARTB>; resets = <&tegra_car 7>; - reset-names = "serial"; dmas = <&apbdma 9>, <&apbdma 9>; dma-names = "rx", "tx"; status = "disabled"; @@ -341,7 +339,6 @@ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_UARTC>; resets = <&tegra_car 55>; - reset-names = "serial"; dmas = <&apbdma 10>, <&apbdma 10>; dma-names = "rx", "tx"; status = "disabled"; @@ -354,7 +351,6 @@ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_UARTD>; resets = <&tegra_car 65>; - reset-names = "serial"; dmas = <&apbdma 19>, <&apbdma 19>; dma-names = "rx", "tx"; status = "disabled"; diff --git a/arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dts b/arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dts index 2df2d8a6b552..0f3debeb294b 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/nvidia/tegra124-apalis-eval.dts @@ -52,6 +52,8 @@ /* Apalis UART1 */ serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2-eval.dts index f4521fd15f6a..d13b8d25ca6a 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2-eval.dts @@ -53,6 +53,8 @@ /* Apalis UART1 */ serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2.dtsi index 75cfe718737c..54b7da4b6920 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124-apalis-v1.2.dtsi @@ -1557,16 +1557,19 @@ serial@70006040 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; }; serial@70006200 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; }; diff --git a/arch/arm/boot/dts/nvidia/tegra124-apalis.dtsi b/arch/arm/boot/dts/nvidia/tegra124-apalis.dtsi index 554c8089491c..c5a0d6aebaec 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124-apalis.dtsi @@ -1550,16 +1550,19 @@ serial@70006040 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; }; serial@70006200 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; }; diff --git a/arch/arm/boot/dts/nvidia/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/nvidia/tegra124-jetson-tk1.dts index 4196f2401c90..f09109be1152 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/nvidia/tegra124-jetson-tk1.dts @@ -1385,6 +1385,7 @@ */ serial@70006000 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; status = "okay"; }; @@ -1398,12 +1399,15 @@ */ serial@70006040 { compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; status = "okay"; }; /* DB9 serial port */ serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi index 0c35ca2e9121..a2ee37180200 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124-nyan.dtsi @@ -70,6 +70,8 @@ serial@70006000 { /* Debug connector on the bottom of the board near SD card. */ + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra124-venice2.dts b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts index c697301c443c..3924ee385dee 100644 --- a/arch/arm/boot/dts/nvidia/tegra124-venice2.dts +++ b/arch/arm/boot/dts/nvidia/tegra124-venice2.dts @@ -609,6 +609,8 @@ }; serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi index b3fbecf5c818..8f1fff373461 100644 --- a/arch/arm/boot/dts/nvidia/tegra124.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi @@ -380,7 +380,6 @@ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA124_CLK_UARTA>; resets = <&tegra_car 6>; - reset-names = "serial"; dmas = <&apbdma 8>, <&apbdma 8>; dma-names = "rx", "tx"; status = "disabled"; @@ -393,7 +392,6 @@ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA124_CLK_UARTB>; resets = <&tegra_car 7>; - reset-names = "serial"; dmas = <&apbdma 9>, <&apbdma 9>; dma-names = "rx", "tx"; status = "disabled"; @@ -406,7 +404,6 @@ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA124_CLK_UARTC>; resets = <&tegra_car 55>; - reset-names = "serial"; dmas = <&apbdma 10>, <&apbdma 10>; dma-names = "rx", "tx"; status = "disabled"; @@ -419,7 +416,6 @@ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA124_CLK_UARTD>; resets = <&tegra_car 65>; - reset-names = "serial"; dmas = <&apbdma 19>, <&apbdma 19>; dma-names = "rx", "tx"; status = "disabled"; diff --git a/arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts index 08b42952f4de..486fd244291e 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-acer-a500-picasso.dts @@ -393,12 +393,14 @@ uartb: serial@70006040 { compatible = "nvidia,tegra20-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; /* GPS BCM4751 */ }; uartc: serial@70006200 { compatible = "nvidia,tegra20-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; status = "okay"; diff --git a/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts index c2a9c3fb5b33..a3757b7daeda 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-asus-tf101.dts @@ -450,12 +450,14 @@ serial@70006040 { compatible = "nvidia,tegra20-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; /* GPS BCM4751 */ }; serial@70006200 { compatible = "nvidia,tegra20-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; status = "okay"; @@ -482,6 +484,8 @@ }; serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/nvidia/tegra20-colibri-eval-v3.dts index 612f4e54cb20..be2ead4147f2 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-colibri-eval-v3.dts @@ -102,6 +102,8 @@ /* Colibri UART-A */ serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra20-colibri-iris.dts b/arch/arm/boot/dts/nvidia/tegra20-colibri-iris.dts index 25a9f5dfe62d..1da202ad1ded 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-colibri-iris.dts @@ -102,6 +102,8 @@ /* Colibri UART-A */ serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi b/arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi index 0e03910abbe6..16b374e6482f 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra20-colibri.dtsi @@ -453,11 +453,13 @@ serial@70006040 { compatible = "nvidia,tegra20-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra20-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; }; diff --git a/arch/arm/boot/dts/nvidia/tegra20-harmony.dts b/arch/arm/boot/dts/nvidia/tegra20-harmony.dts index 11f21aeba8e9..5c31a6c8dabe 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-harmony.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-harmony.dts @@ -273,6 +273,8 @@ }; serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra20-paz00.dts b/arch/arm/boot/dts/nvidia/tegra20-paz00.dts index e995f428dc2e..afb922bd79a7 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-paz00.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-paz00.dts @@ -279,10 +279,14 @@ }; serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; serial@70006200 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; @@ -307,20 +311,19 @@ clock-frequency = <100000>; }; - nvec@7000c500 { + i2c@7000c500 { compatible = "nvidia,nvec"; - reg = <0x7000c500 0x100>; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; + + /delete-property/ #address-cells; + /delete-property/ #size-cells; + /delete-property/ dmas; + /delete-property/ dma-names; + clock-frequency = <80000>; request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; slave-addr = <138>; - clocks = <&tegra_car TEGRA20_CLK_I2C3>, - <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; - clock-names = "div-clk", "fast-clk"; - resets = <&tegra_car 67>; - reset-names = "i2c"; + + status = "okay"; }; i2c@7000d000 { diff --git a/arch/arm/boot/dts/nvidia/tegra20-seaboard.dts b/arch/arm/boot/dts/nvidia/tegra20-seaboard.dts index bd4ff8b40b20..e944ae9b86c2 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-seaboard.dts @@ -324,6 +324,8 @@ }; serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra20-tamonten.dtsi b/arch/arm/boot/dts/nvidia/tegra20-tamonten.dtsi index ddb84e4a9f8b..5c214dd060bb 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra20-tamonten.dtsi @@ -288,6 +288,8 @@ }; serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra20-trimslice.dts b/arch/arm/boot/dts/nvidia/tegra20-trimslice.dts index 1944121e2dd6..7cae6ad57544 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-trimslice.dts @@ -276,6 +276,8 @@ }; serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra20-ventana.dts b/arch/arm/boot/dts/nvidia/tegra20-ventana.dts index 433575a6ad38..f3273941437c 100644 --- a/arch/arm/boot/dts/nvidia/tegra20-ventana.dts +++ b/arch/arm/boot/dts/nvidia/tegra20-ventana.dts @@ -323,6 +323,8 @@ }; serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra20.dtsi b/arch/arm/boot/dts/nvidia/tegra20.dtsi index 4177d04265d8..8da75ccc4402 100644 --- a/arch/arm/boot/dts/nvidia/tegra20.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra20.dtsi @@ -442,7 +442,6 @@ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_UARTA>; resets = <&tegra_car 6>; - reset-names = "serial"; dmas = <&apbdma 8>, <&apbdma 8>; dma-names = "rx", "tx"; status = "disabled"; @@ -455,7 +454,6 @@ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_UARTB>; resets = <&tegra_car 7>; - reset-names = "serial"; dmas = <&apbdma 9>, <&apbdma 9>; dma-names = "rx", "tx"; status = "disabled"; @@ -468,7 +466,6 @@ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_UARTC>; resets = <&tegra_car 55>; - reset-names = "serial"; dmas = <&apbdma 10>, <&apbdma 10>; dma-names = "rx", "tx"; status = "disabled"; @@ -481,7 +478,6 @@ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_UARTD>; resets = <&tegra_car 65>; - reset-names = "serial"; dmas = <&apbdma 19>, <&apbdma 19>; dma-names = "rx", "tx"; status = "disabled"; @@ -494,7 +490,6 @@ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_UARTE>; resets = <&tegra_car 66>; - reset-names = "serial"; dmas = <&apbdma 20>, <&apbdma 20>; dma-names = "rx", "tx"; status = "disabled"; diff --git a/arch/arm/boot/dts/nvidia/tegra30-apalis-eval.dts b/arch/arm/boot/dts/nvidia/tegra30-apalis-eval.dts index 842b5faba285..fc284155cd76 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-apalis-eval.dts @@ -59,6 +59,8 @@ /* Apalis UART1 */ serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1-eval.dts index ca277bf1df78..9d08e2b094b4 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1-eval.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1-eval.dts @@ -60,6 +60,8 @@ /* Apalis UART1 */ serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1.dtsi index a4b7fe5c3d23..1640763fd4af 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-apalis-v1.1.dtsi @@ -829,16 +829,19 @@ serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; }; serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; }; diff --git a/arch/arm/boot/dts/nvidia/tegra30-apalis.dtsi b/arch/arm/boot/dts/nvidia/tegra30-apalis.dtsi index d73103884000..3b6fad273cab 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-apalis.dtsi @@ -820,16 +820,19 @@ serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; }; serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; }; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi index c0062353c1f1..a9342e04b14b 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-nexus7-grouper-common.dtsi @@ -798,12 +798,14 @@ uartb: serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; /* GPS BCM4751 */ }; uartc: serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; status = "okay"; @@ -1090,15 +1092,11 @@ display-panel { /* - * Nexus 7 supports two compatible panel models: - * - * 1. hydis,hv070wx2-1e0 - * 2. chunghwa,claa070wp03xg - * - * We want to use timing which is optimized for Nexus 7, - * hence we need to customize the timing. + * Some device variants come with a Hydis HV070WX2-1E0, but + * since they are all largely compatible, we'll go with the + * Chunghwa one here. */ - compatible = "panel-lvds"; + compatible = "chunghwa,claa070wp03xg", "panel-lvds"; width-mm = <94>; height-mm = <150>; diff --git a/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi index bdb898ad6262..ead95306840f 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-asus-transformer-common.dtsi @@ -1088,6 +1088,7 @@ serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; status = "okay"; @@ -1096,6 +1097,7 @@ serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; status = "okay"; diff --git a/arch/arm/boot/dts/nvidia/tegra30-beaver.dts b/arch/arm/boot/dts/nvidia/tegra30-beaver.dts index 51769d5132ae..1d74179dde79 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-beaver.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-beaver.dts @@ -1733,6 +1733,8 @@ }; serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra30-cardhu.dtsi b/arch/arm/boot/dts/nvidia/tegra30-cardhu.dtsi index 37a9c5a0ca30..0120859d6d72 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-cardhu.dtsi @@ -170,11 +170,14 @@ }; serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/nvidia/tegra30-colibri-eval-v3.dts index 36615c5fda2c..1990bf8e122d 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-colibri-eval-v3.dts @@ -38,6 +38,8 @@ /* Colibri UART-A */ serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra30-colibri.dtsi b/arch/arm/boot/dts/nvidia/tegra30-colibri.dtsi index ed6106f1bea1..4eb526fe9c55 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30-colibri.dtsi @@ -710,11 +710,13 @@ serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; }; serial@70006300 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; }; diff --git a/arch/arm/boot/dts/nvidia/tegra30-ouya.dts b/arch/arm/boot/dts/nvidia/tegra30-ouya.dts index eef27c82987b..7e3de26ca960 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-ouya.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-ouya.dts @@ -2004,6 +2004,7 @@ uartc: serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; status = "okay"; @@ -2033,6 +2034,8 @@ }; uartd: serial@70006300 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm/boot/dts/nvidia/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/nvidia/tegra30-pegatron-chagall.dts index 8d10eb8b48b9..4012f9c799a8 100644 --- a/arch/arm/boot/dts/nvidia/tegra30-pegatron-chagall.dts +++ b/arch/arm/boot/dts/nvidia/tegra30-pegatron-chagall.dts @@ -1110,6 +1110,7 @@ uartb: serial@70006040 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; status = "okay"; @@ -1118,6 +1119,7 @@ uartc: serial@70006200 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; /delete-property/ reg-shift; status = "okay"; @@ -2626,7 +2628,7 @@ }; display-panel { - compatible = "panel-lvds"; + compatible = "hannstar,hsd101pww2", "panel-lvds"; width-mm = <217>; height-mm = <136>; diff --git a/arch/arm/boot/dts/nvidia/tegra30.dtsi b/arch/arm/boot/dts/nvidia/tegra30.dtsi index 9cba67b54111..f866fa7b55a5 100644 --- a/arch/arm/boot/dts/nvidia/tegra30.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30.dtsi @@ -563,7 +563,6 @@ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_UARTA>; resets = <&tegra_car 6>; - reset-names = "serial"; dmas = <&apbdma 8>, <&apbdma 8>; dma-names = "rx", "tx"; status = "disabled"; @@ -576,7 +575,6 @@ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_UARTB>; resets = <&tegra_car 7>; - reset-names = "serial"; dmas = <&apbdma 9>, <&apbdma 9>; dma-names = "rx", "tx"; status = "disabled"; @@ -589,7 +587,6 @@ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_UARTC>; resets = <&tegra_car 55>; - reset-names = "serial"; dmas = <&apbdma 10>, <&apbdma 10>; dma-names = "rx", "tx"; status = "disabled"; @@ -602,7 +599,6 @@ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_UARTD>; resets = <&tegra_car 65>; - reset-names = "serial"; dmas = <&apbdma 19>, <&apbdma 19>; dma-names = "rx", "tx"; status = "disabled"; @@ -615,7 +611,6 @@ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_UARTE>; resets = <&tegra_car 66>; - reset-names = "serial"; dmas = <&apbdma 20>, <&apbdma 20>; dma-names = "rx", "tx"; status = "disabled"; diff --git a/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts index 77b21aa7a146..1f11e9542a72 100644 --- a/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts +++ b/arch/arm/boot/dts/nxp/imx/imx1-apf9328.dts @@ -58,10 +58,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eth>; compatible = "davicom,dm9000"; - reg = < - 4 0x00c00000 0x2 - 4 0x00c00002 0x2 - >; + reg = <4 0x00c00000 0x2>, + <4 0x00c00002 0x2>; interrupt-parent = <&gpio2>; interrupts = <14 IRQ_TYPE_LEVEL_LOW>; fsl,weim-cs-timing = <0x0000c700 0x19190d01>; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts index 7d4301b22b90..fc8a502fc957 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts +++ b/arch/arm/boot/dts/nxp/imx/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts @@ -30,22 +30,15 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_lcd_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_lcd_3v3>; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_lcd_3v3: regulator-0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcd_3v3>; + regulator-name = "lcd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + enable-active-high; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-karo-tx25.dts b/arch/arm/boot/dts/nxp/imx/imx25-karo-tx25.dts index 0950eb66d3d9..458b94d3d4ed 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25-karo-tx25.dts +++ b/arch/arm/boot/dts/nxp/imx/imx25-karo-tx25.dts @@ -14,20 +14,13 @@ stdout-path = &uart1; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_fec_phy: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "fec-phy"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 9 0>; - enable-active-high; - }; + reg_fec_phy: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "fec-phy"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 9 0>; + enable-active-high; }; memory@80000000 { @@ -39,46 +32,46 @@ &iomuxc { pinctrl_uart1: uart1grp { fsl,pins = < - MX25_PAD_UART1_TXD__UART1_TXD 0x80000000 - MX25_PAD_UART1_RXD__UART1_RXD 0x80000000 - MX25_PAD_UART1_CTS__UART1_CTS 0x80000000 - MX25_PAD_UART1_RTS__UART1_RTS 0x80000000 + MX25_PAD_UART1_TXD__UART1_TXD 0x00000020 + MX25_PAD_UART1_RXD__UART1_RXD 0x000000a0 + MX25_PAD_UART1_CTS__UART1_CTS 0x00000060 + MX25_PAD_UART1_RTS__UART1_RTS 0x000000e0 >; }; pinctrl_fec: fecgrp { fsl,pins = < - MX25_PAD_D11__GPIO_4_9 0x80000000 /* FEC PHY power on pin */ - MX25_PAD_D13__GPIO_4_7 0x80000000 /* FEC reset */ - MX25_PAD_FEC_MDC__FEC_MDC 0x80000000 - MX25_PAD_FEC_MDIO__FEC_MDIO 0x80000000 - MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000 - MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000 - MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000 - MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000 - MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000 - MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x80000000 - MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000 + MX25_PAD_D11__GPIO_4_9 0x00000021 /* FEC PHY power on pin */ + MX25_PAD_D13__GPIO_4_7 0x000000a1 /* FEC reset */ + MX25_PAD_FEC_MDC__FEC_MDC 0x00000060 + MX25_PAD_FEC_MDIO__FEC_MDIO 0x000001f0 + MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x00000060 + MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x00000060 + MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x00000060 + MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x000000c1 + MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x000000c0 + MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x000000c0 + MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x000000c0 >; }; pinctrl_nfc: nfcgrp { fsl,pins = < - MX25_PAD_NF_CE0__NF_CE0 0x80000000 + MX25_PAD_NF_CE0__NF_CE0 0x00000001 MX25_PAD_NFWE_B__NFWE_B 0x80000000 MX25_PAD_NFRE_B__NFRE_B 0x80000000 MX25_PAD_NFALE__NFALE 0x80000000 MX25_PAD_NFCLE__NFCLE 0x80000000 MX25_PAD_NFWP_B__NFWP_B 0x80000000 - MX25_PAD_NFRB__NFRB 0x80000000 - MX25_PAD_D7__D7 0x80000000 - MX25_PAD_D6__D6 0x80000000 - MX25_PAD_D5__D5 0x80000000 - MX25_PAD_D4__D4 0x80000000 - MX25_PAD_D3__D3 0x80000000 - MX25_PAD_D2__D2 0x80000000 - MX25_PAD_D1__D1 0x80000000 - MX25_PAD_D0__D0 0x80000000 + MX25_PAD_NFRB__NFRB 0x000000e0 + MX25_PAD_D7__D7 0x00000080 + MX25_PAD_D6__D6 0x00000080 + MX25_PAD_D5__D5 0x00000080 + MX25_PAD_D4__D4 0x00000080 + MX25_PAD_D3__D3 0x00000080 + MX25_PAD_D2__D2 0x00000080 + MX25_PAD_D1__D1 0x00000000 + MX25_PAD_D0__D0 0x00000080 >; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts b/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts index fb66884d8a2f..04f4b127a172 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx25-pdk.dts @@ -16,45 +16,35 @@ reg = <0x80000000 0x4000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_fec_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "fec-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 3 0>; - enable-active-high; - }; + reg_fec_3v3: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "fec-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 3 0>; + enable-active-high; + }; - reg_2p5v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - }; + reg_2p5v: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; - reg_3p3v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + reg_3p3v: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; - reg_can_3v3: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "can-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 6 0>; - }; + reg_can_3v3: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 6 0>; }; sound { diff --git a/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts b/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts index 6f1e8ce9e76e..a21f1f7c24b8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts +++ b/arch/arm/boot/dts/nxp/imx/imx27-apf27dev.dts @@ -54,19 +54,12 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_max5821: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "max5821-reg"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; + reg_max5821: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "max5821-reg"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts index 9c3ec82ec7e5..145e459625b3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts +++ b/arch/arm/boot/dts/nxp/imx/imx27-eukrea-mbimxsd27-baseboard.dts @@ -54,22 +54,15 @@ }; }; - regulators { - #address-cells = <1>; - #size-cells = <0>; - compatible = "simple-bus"; - - reg_lcd: regulator@0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdreg>; - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "LCD"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_lcd: regulator-0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdreg>; + regulator-name = "LCD"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>; + enable-active-high; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts index 188639738dc3..25442eba21c1 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycard-s-rdk.dts @@ -33,19 +33,12 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3v3: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts index 344e77790152..7f0cd4d3ec2d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-rdk.dts @@ -37,18 +37,15 @@ }; }; - regulators { - regulator@2 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_csien>; - reg = <2>; - regulator-name = "CSI_EN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; - regulator-always-on; - }; + regulator-2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csien>; + regulator-name = "CSI_EN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 24 GPIO_ACTIVE_LOW>; + regulator-always-on; }; usbphy { diff --git a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi index 3d10273177e9..7191e10712b9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx27-phytec-phycore-som.dtsi @@ -15,26 +15,18 @@ reg = <0xa0000000 0x08000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3v3: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + reg_3v3: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; - reg_5v0: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + reg_5v0: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; }; usbphy { diff --git a/arch/arm/boot/dts/nxp/imx/imx27.dtsi b/arch/arm/boot/dts/nxp/imx/imx27.dtsi index e140307be2e7..faba12ee7465 100644 --- a/arch/arm/boot/dts/nxp/imx/imx27.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx27.dtsi @@ -534,7 +534,7 @@ clock-names = "ipg", "ahb"; }; - clks: ccm@10027000{ + clks: ccm@10027000 { compatible = "fsl,imx27-ccm"; reg = <0x10027000 0x1000>; #clock-cells = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx31.dtsi b/arch/arm/boot/dts/nxp/imx/imx31.dtsi index 95c05f17a6d5..e1ae7c175f7d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx31.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx31.dtsi @@ -232,7 +232,7 @@ reg = <0x53f00000 0x100000>; ranges; - clks: ccm@53f80000{ + clks: ccm@53f80000 { compatible = "fsl,imx31-ccm"; reg = <0x53f80000 0x4000>; interrupts = <31>, <53>; diff --git a/arch/arm/boot/dts/nxp/imx/imx50-evk.dts b/arch/arm/boot/dts/nxp/imx/imx50-evk.dts index 4ea5c23f181b..3f45c01d9cce 100644 --- a/arch/arm/boot/dts/nxp/imx/imx50-evk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx50-evk.dts @@ -23,7 +23,7 @@ cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>, <&gpio4 13 GPIO_ACTIVE_LOW>; status = "okay"; - flash: m25p32@1 { + flash: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p32", "jedec,spi-nor"; diff --git a/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts b/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts index 467db6b4ed7f..b1a6a9c58ac3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts +++ b/arch/arm/boot/dts/nxp/imx/imx50-kobo-aura.dts @@ -73,7 +73,7 @@ states = <3300000 0>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - enable-gpio = <&gpio4 12 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; startup-delay-us = <100000>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx50.dtsi b/arch/arm/boot/dts/nxp/imx/imx50.dtsi index 3d9a9f37f672..c5b25d2f6264 100644 --- a/arch/arm/boot/dts/nxp/imx/imx50.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx50.dtsi @@ -335,7 +335,7 @@ #reset-cells = <1>; }; - clks: ccm@53fd4000{ + clks: ccm@53fd4000 { compatible = "fsl,imx50-ccm"; reg = <0x53fd4000 0x4000>; interrupts = <0 71 0x04 0 72 0x04>; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts index a1f9c6a72275..16ff543f3fbf 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts @@ -173,22 +173,15 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_hub_reset: regulator@0 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotgreg>; - reg = <0>; - regulator-name = "hub_reset"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_hub_reset: regulator-hub-reset { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotgreg>; + regulator-name = "hub_reset"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; }; sound { diff --git a/arch/arm/boot/dts/nxp/imx/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/nxp/imx/imx51-eukrea-mbimxsd51-baseboard.dts index b6d931e96a8f..aff380e999c7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-eukrea-mbimxsd51-baseboard.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-eukrea-mbimxsd51-baseboard.dts @@ -45,21 +45,14 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_can: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "CAN_RST"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - startup-delay-us = <20000>; - enable-active-high; - }; + reg_can: regulator-can { + compatible = "regulator-fixed"; + regulator-name = "CAN_RST"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + startup-delay-us = <20000>; + enable-active-high; }; sound { diff --git a/arch/arm/boot/dts/nxp/imx/imx51.dtsi b/arch/arm/boot/dts/nxp/imx/imx51.dtsi index ba92a3ea6872..2b3195f5e32c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx51.dtsi @@ -455,7 +455,7 @@ #reset-cells = <1>; }; - clks: ccm@73fd4000{ + clks: ccm@73fd4000 { compatible = "fsl,imx51-ccm"; reg = <0x73fd4000 0x4000>; interrupts = <0 71 0x04 0 72 0x04>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-ard.dts b/arch/arm/boot/dts/nxp/imx/imx53-ard.dts index 23a7492e2929..165e1b00b721 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-ard.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-ard.dts @@ -43,19 +43,12 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; }; gpio-keys { diff --git a/arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi index fe5e0d308e99..00b8d7ca41a2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53-m53.dtsi @@ -15,28 +15,20 @@ <0xb0000000 0x20000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p2v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; + reg_3p2v: regulator-3p2v { + compatible = "regulator-fixed"; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; - reg_backlight: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "lcd-supply"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + regulator-name = "lcd-supply"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts index 2bd2432d317f..c323b4dbe9f0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts @@ -65,28 +65,20 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usbh1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 2 0>; - }; + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 0>; + }; - reg_usb_otg_vbus: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 4 0>; - }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 0>; }; sound { diff --git a/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts b/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts index 09eee0dd44c1..6a37616cef1c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-mba53.dts @@ -38,27 +38,19 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_backlight: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "lcd-supply"; - gpio = <&gpio2 5 0>; - startup-delay-us = <5000>; - }; + reg_backlight: regulator-backlight { + compatible = "regulator-fixed"; + regulator-name = "lcd-supply"; + gpio = <&gpio2 5 0>; + startup-delay-us = <5000>; + }; - reg_3p2v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; + reg_3p2v: regulator-3p2v { + compatible = "regulator-fixed"; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; }; sound { @@ -169,6 +161,7 @@ codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>; VDDA-supply = <®_3p2v>; VDDIO-supply = <®_3p2v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi index 50fef8dd3675..d80440446473 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi @@ -16,6 +16,13 @@ <0xb0000000 0x20000000>; }; + backlight_parallel: backlight-parallel { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + }; + display0: disp0 { compatible = "fsl,imx-parallel-display"; pinctrl-names = "default"; @@ -80,6 +87,10 @@ panel { compatible = "sii,43wvf1g"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_display_power>; + backlight = <&backlight_parallel>; + enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; port { panel_in: endpoint { @@ -88,29 +99,21 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p2v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P2V"; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3200000>; - regulator-always-on; - }; + reg_3p2v: regulator-3p2v { + compatible = "regulator-fixed"; + regulator-name = "3P2V"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-always-on; + }; - reg_usb_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 8 0>; - enable-active-high; - }; + reg_usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 8 0>; + enable-active-high; }; sound { @@ -202,6 +205,12 @@ >; }; + pinctrl_display_power: displaypowergrp { + fsl,pins = < + MX53_PAD_EIM_D24__GPIO3_24 0x1e4 + >; + }; + pinctrl_esdhc1: esdhc1grp { fsl,pins = < MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 @@ -292,6 +301,12 @@ >; }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX53_PAD_GPIO_1__PWM2_PWMO 0x5 + >; + }; + pinctrl_vga_sync: vgasync-grp { fsl,pins = < /* VGA_HSYNC, VSYNC with max drive strength */ @@ -367,6 +382,12 @@ status = "okay"; }; +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + &sata { status = "okay"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-smd.dts b/arch/arm/boot/dts/nxp/imx/imx53-smd.dts index f8d17967a67e..55435dfdff8a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-smd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-smd.dts @@ -67,10 +67,10 @@ reg = <0>; }; - flash: m25p32@1 { + flash: flash@1 { #address-cells = <1>; #size-cells = <1>; - compatible = "st,m25p32", "st,m25p", "jedec,spi-nor"; + compatible = "st,m25p32", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi index d930739674a1..294811bfc8d2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53-tqma53.dtsi @@ -15,19 +15,12 @@ reg = <0x70000000 0x40000000>; /* Up to 1GiB */ }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-voipac-dmm-668.dtsi index 24859d0c09c1..c0622cf7188c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-voipac-dmm-668.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53-voipac-dmm-668.dtsi @@ -15,29 +15,21 @@ <0xb0000000 0x20000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_usb_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 31 0>; /* PEN */ - enable-active-high; - }; + reg_usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 31 0>; /* PEN */ + enable-active-high; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx53.dtsi b/arch/arm/boot/dts/nxp/imx/imx53.dtsi index 17dc13719639..0ebc35e6e985 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53.dtsi @@ -595,7 +595,7 @@ #reset-cells = <1>; }; - clks: ccm@53fd4000{ + clks: ccm@53fd4000 { compatible = "fsl,imx53-ccm"; reg = <0x53fd4000 0x4000>; interrupts = <0 71 0x04 0 72 0x04>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-b105pv2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b105pv2.dts index 411aa72d344b..7d4ae113c381 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-b105pv2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-b105pv2.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT +// SPDX-License-Identifier: GPL-2.0 OR MIT // // Device Tree Source for General Electric B105Pv2 // diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-b105v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b105v2.dts index d011127c635b..9c5938e16d99 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-b105v2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-b105v2.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT +// SPDX-License-Identifier: GPL-2.0 OR MIT // // Device Tree Source for General Electric B105v2 // diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-b125pv2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b125pv2.dts index ca840fa84052..01df7cffcef2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-b125pv2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-b125pv2.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT +// SPDX-License-Identifier: GPL-2.0 OR MIT // // Device Tree Source for General Electric B125Pv2 // diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-b125v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b125v2.dts index 81e5a9cb8900..a015453daf10 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-b125v2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-b125v2.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT +// SPDX-License-Identifier: GPL-2.0 OR MIT // // Device Tree Source for General Electric B125v2 // diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-b155v2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-b155v2.dts index c861937b30f6..b71ee6b79208 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-b155v2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-b155v2.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT +// SPDX-License-Identifier: GPL-2.0 OR MIT // // Device Tree Source for General Electric B155v2 // diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5pv2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5pv2.dtsi index 37697fac9dea..9f1655540cb9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5pv2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5pv2.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT +// SPDX-License-Identifier: GPL-2.0 OR MIT // // Device Tree Source for General Electric B1x5Pv2 // patient monitor series @@ -257,7 +257,7 @@ simple-audio-card,bitclock-master = <&dailink_master>; simple-audio-card,frame-master = <&dailink_master>; simple-audio-card,widgets = "Speaker", "Ext Spk"; - simple-audio-card,audio-routing = "Ext Spk", "LINE"; + simple-audio-card,routing = "Ext Spk", "LINE"; simple-audio-card,cpu { sound-dai = <&ssi1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5v2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5v2.dtsi index f028b6a191df..590dcc0953cc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5v2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-b1x5v2.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT +// SPDX-License-Identifier: GPL-2.0 OR MIT // // Device Tree Source for General Electric B1x5v2 // patient monitor series diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dts index 407ad8d43c84..77d7600b2675 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-emcon-avari.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Copyright (C) 2018 emtrion GmbH // diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi index 05fd8ff4da1e..8a637fdff073 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-qmx6.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT +// SPDX-License-Identifier: GPL-2.0 OR MIT // // Device Tree Source for i.MX6DL based congatec QMX6 // System on Module diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts index 0366d1037ef4..114739d10447 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-riotboard.dts @@ -172,6 +172,7 @@ codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-arm2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-arm2.dts index 75586299d9ca..631d6d690959 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-arm2.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-arm2.dts @@ -17,29 +17,21 @@ reg = <0x10000000 0x80000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_usb_otg_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; }; leds { diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts b/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts index 8263bfef9bf8..02648806c275 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-bosch-acc.dts @@ -314,7 +314,6 @@ }; sw3a_reg: sw3a { - compatible = "regulator-fixed"; regulator-name = "DDR_1V5a"; regulator-boot-on; regulator-always-on; @@ -322,7 +321,6 @@ }; sw3b_reg: sw3b { - compatible = "regulator-fixed"; regulator-name = "DDR_1V5b"; regulator-boot-on; regulator-always-on; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi index ead83091e193..99f4f6ac71d4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-bx50v3.dtsi @@ -228,6 +228,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&mclk>; VDDA-supply = <®_1p8v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts index ffb3b8eeae5d..95b49fc83f7b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-cm-fx6.dts @@ -263,7 +263,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "st,m25p", "jedec,spi-nor"; + compatible = "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts index 3815cb660ff7..9f7ac7158c46 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-dmo-edmqmx6.dts @@ -28,40 +28,31 @@ reg = <0x10000000 0x80000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_usb_otg_switch: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg_switch"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio7 12 0>; - regulator-boot-on; - regulator-always-on; - }; + reg_usb_otg_switch: regulator-usb-otg-switch { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_switch"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio7 12 0>; + regulator-boot-on; + regulator-always-on; + }; - reg_usb_host1: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_host1_en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 31 0>; - enable-active-high; - }; + reg_usb_host1: regulator-usb-host1 { + compatible = "regulator-fixed"; + regulator-name = "usb_host1_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 31 0>; + enable-active-high; }; gpio-leds { diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts b/arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts index 137db38f0d27..d2d0a82ea178 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-dms-ba16.dts @@ -96,6 +96,7 @@ sgtl5000: codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&sys_mclk>; lrclk-strength = <0x3>; VDDA-supply = <®_1p8v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-emcon-avari.dts b/arch/arm/boot/dts/nxp/imx/imx6q-emcon-avari.dts index 0f582a9d4c0e..02813368a820 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-emcon-avari.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-emcon-avari.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Copyright (C) 2018 emtrion GmbH // diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gk802.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gk802.dts index 2fda68f9d3f6..ce55c9558679 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-gk802.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gk802.dts @@ -19,19 +19,12 @@ reg = <0x10000000 0x40000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; }; gpio-keys { diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts index 0ba802b891b5..c5c144879fa6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw5400-a.dts @@ -67,47 +67,37 @@ status = "okay"; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_1p0v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; + reg_1p0v: regulator-1p0v { + compatible = "regulator-fixed"; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_usb_h1_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - reg_usb_otg_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; }; sound { @@ -320,6 +310,7 @@ codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <&sw4_reg>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-h100.dts b/arch/arm/boot/dts/nxp/imx/imx6q-h100.dts index 3fe4591e21f5..a603562ea49a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-h100.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-h100.dts @@ -179,6 +179,7 @@ sgtl5000: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_h100_sgtl5000>; clocks = <&clks IMX6QDL_CLK_CKO>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts b/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts index 109b46a22b5e..fb9f320103c6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-pistachio.dts @@ -196,6 +196,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1_sgtl5000>; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_1p8v>; VDDIO-supply = <®_1p8v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts b/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts index d8fa83effd63..3508a2cd928a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-prti6q.dts @@ -359,8 +359,11 @@ keep-power-in-suspend; status = "okay"; - wifi { + #address-cells = <1>; + #size-cells = <0>; + wifi@2 { compatible = "ti,wl1271"; + reg = <2>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wifi>; interrupts-extended = <&gpio1 30 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts b/arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts index 2f576e2ce73f..7c298d9aa21e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts @@ -141,6 +141,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; reg = <0x0a>; + #sound-dai-cells = <0>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi index 2577eb4f535a..338d292553ad 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-apf6dev.dtsi @@ -181,6 +181,7 @@ codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi index 6b64b2fc3995..db1bc511e71f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-aristainetos2.dtsi @@ -301,12 +301,12 @@ pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; - eeprom@50{ + eeprom@50 { compatible = "atmel,24c64"; reg = <0x50>; }; - eeprom@57{ + eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi index 570995707504..11d9c7a2dacb 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-colibri.dtsi @@ -26,7 +26,7 @@ extcon_usbc_det: usbc-det { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ + id-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbc_det>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-dfi-fs700-m60.dtsi index 2c1d6f28e695..0a6c3a092b34 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-dfi-fs700-m60.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-dfi-fs700-m60.dtsi @@ -2,26 +2,18 @@ #include <dt-bindings/gpio/gpio.h> / { - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - dummy_reg: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "dummy-supply"; - }; + dummy_reg: regulator-dummy { + compatible = "regulator-fixed"; + regulator-name = "dummy-supply"; + }; - reg_usb_otg_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; }; chosen { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon-avari.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon-avari.dtsi index c4e146f3341b..f1a41c76729c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon-avari.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon-avari.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Copyright (C) 2018 emtrion GmbH // diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi index ee2dd75cead6..a63e73adc1fc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-emcon.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Copyright (C) 2018 emtrion GmbH // diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi index 47d9a8d08197..535679c27d6f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi @@ -455,6 +455,7 @@ codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_1p8v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi index fb1d29abe099..3e1c572af582 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi @@ -452,6 +452,7 @@ codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_1p8v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi index a642be45ffe2..0ffa0357a6fa 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi @@ -114,57 +114,47 @@ status = "okay"; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_1p0v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "1P0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; + reg_1p0v: regulator-1p0v { + compatible = "regulator-fixed"; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_can1_stby: regulator-can1-stby { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_can1>; - regulator-name = "can1_stby"; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can1>; + regulator-name = "can1_stby"; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; - reg_usb_h1_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - reg_usb_otg_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; }; sound-analog { @@ -509,6 +499,7 @@ sgtl5000: audio-codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <&sw4_reg>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi index 7d032d1f3b47..da0f8dae1ea8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6.dtsi @@ -36,21 +36,21 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpiobuttons>; - button1 { + button-1 { label = "s6"; linux,code = <KEY_F6>; gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; wakeup-source; }; - button2 { + button-2 { label = "s7"; linux,code = <KEY_F7>; gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; wakeup-source; }; - button3 { + button-3 { label = "s8"; linux,code = <KEY_F8>; gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi index 27fec340c380..238f3af42822 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi @@ -15,6 +15,7 @@ lm75: temperature-sensor@49 { compatible = "national,lm75"; reg = <0x49>; + vs-supply = <®_mba6_3p3v>; }; m24c64_57: eeprom@57 { @@ -23,6 +24,7 @@ pagesize = <32>; #address-cells = <1>; #size-cells = <1>; + vcc-supply = <®_mba6_3p3v>; mba_mac_address: mac-address@20 { reg = <0x20 0x6>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi index 0a9f076eeb36..a587bc88f76f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi @@ -25,6 +25,7 @@ lm75: temperature-sensor@49 { compatible = "national,lm75"; reg = <0x49>; + vs-supply = <®_mba6_3p3v>; }; m24c64_57: eeprom@57 { @@ -33,6 +34,7 @@ pagesize = <32>; #address-cells = <1>; #size-cells = <1>; + vcc-supply = <®_mba6_3p3v>; mba_mac_address: mac-address@20 { reg = <0x20 0x6>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi index 6d4eab1942b9..f2542d725ce7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi @@ -15,51 +15,41 @@ reg = <0x10000000 0x20000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan_vmmc: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio6 7 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_wlan_vmmc: regulator-wlan-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan_vmmc>; + regulator-name = "reg_wlan_vmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio6 7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; }; gpio-keys { @@ -236,6 +226,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi index 81a9a302aec1..763831dc0e24 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi @@ -15,83 +15,70 @@ reg = <0x10000000 0xF0000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; - reg_1p8v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; - reg_2p5v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_3p3v: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_usb_otg_vbus: regulator-usb-otg { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usb_otg_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usb_h1_vbus: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - reg_wlan_vmmc: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - reg_can_xcvr: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; + reg_wlan_vmmc: regulator-wlan-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan_vmmc>; + regulator-name = "reg_wlan_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + reg_can_xcvr: regulator-can-xcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_xcvr>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; }; gpio-keys { @@ -378,6 +365,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi index 000e9dc97b1a..414196b75991 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi @@ -286,6 +286,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi index 731759bdd7f5..f278b14911ce 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi @@ -17,74 +17,62 @@ reg = <0x10000000 0x40000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - - reg_can_xcvr: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - reg_wlan_vmmc: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; - startup-delay-us = <70000>; - enable-active-high; - }; - - reg_usb_h1_vbus: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + + reg_can_xcvr: regulator-can-xcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_xcvr>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + + reg_wlan_vmmc: regulator-wlan-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wlan_vmmc>; + regulator-name = "reg_wlan_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + enable-active-high; }; gpio-keys { @@ -309,6 +297,7 @@ codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pbab01.dtsi index a41e47c06ef4..e40041871b28 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pbab01.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pbab01.dtsi @@ -10,22 +10,18 @@ stdout-path = &uart4; }; - regulators { - sound_1v8: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "i2s-audio-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; + sound_1v8: regulator-sound-1v8 { + compatible = "regulator-fixed"; + regulator-name = "i2s-audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - sound_3v3: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "i2s-audio-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + sound_3v3: regulator-sound-3v3 { + compatible = "regulator-fixed"; + regulator-name = "i2s-audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; tlv320_mclk: oscillator { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi index 80adb2a02cc9..113974520d54 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-pfla02.dtsi @@ -14,32 +14,24 @@ reg = <0x10000000 0x80000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_otg_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 15 0>; - enable-active-high; - }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 15 0>; + enable-active-high; + }; - reg_usb_h1_vbus: regulator@1 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - reg = <1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 0 0>; - enable-active-high; - }; + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 0 0>; + enable-active-high; }; gpio_leds: leds { @@ -464,3 +456,11 @@ vmmc-supply = <&vdd_sd0_reg>; status = "disabled"; }; + +&wdog1 { + /* + * Rely on PMIC reboot handler. Internal i.MX6 watchdog, that is also + * used for reboot, does not reset all external PMIC voltages on reset. + */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi index 28a805384668..86b4269e0e01 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-phycore-som.dtsi @@ -309,3 +309,11 @@ >; }; }; + +&wdog1 { + /* + * Rely on PMIC reboot handler. Internal i.MX6 watchdog, that is also + * used for reboot, does not reset all external PMIC voltages on reset. + */ + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi index f804ff95a6ad..eba698d04243 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-rex.dtsi @@ -13,41 +13,32 @@ stdout-path = &uart1; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_usbh1_vbus: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - pinctrl-names = "default"; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - pinctrl-names = "default"; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; }; leds { @@ -120,6 +111,7 @@ codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi index 12573e1f917c..84c8a9531e18 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabrelite.dtsi @@ -24,88 +24,74 @@ reg = <0x10000000 0x40000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; - reg_2p5v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usb_otg_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; - enable-active-high; - }; - - reg_can_xcvr: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_can_xcvr>; - gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; - }; - - reg_1p5v: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "1P5V"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - - reg_1p8v: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - reg_2p8v: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "2P8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - reg_usb_h1_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + + reg_can_xcvr: regulator-can-xcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_xcvr>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + + reg_1p5v: regulator-1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_2p8v: regulator-2p8v { + compatible = "regulator-fixed"; + regulator-name = "2P8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + enable-active-high; }; mipi_xclk: mipi_xclk { @@ -334,6 +320,7 @@ codec: sgtl5000@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi index aff46f3040c1..68525f0205d3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6a.dtsi @@ -30,6 +30,7 @@ sensor@48 { compatible = "national,lm75"; reg = <0x48>; + vs-supply = <®_3p3v>; }; eeprom@50 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi index a3f6543c3aaa..aeba0a273600 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tqma6b.dtsi @@ -23,6 +23,7 @@ sensor@48 { compatible = "national,lm75"; reg = <0x48>; + vs-supply = <®_3p3v>; }; eeprom@50 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi index 1e0a041e9f60..e2db875b61c4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-ts7970.dtsi @@ -235,6 +235,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi index 93a8123da27d..647ba5e623dd 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-udoo.dtsi @@ -59,29 +59,21 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb_h1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */ - gpio = <&gpio7 12 0>; - }; + reg_usb_h1_vbus: regulator-usb-h1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */ + gpio = <&gpio7 12 0>; + }; - reg_panel: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "lcd_panel"; - enable-active-high; - gpio = <&gpio1 2 0>; - }; + reg_panel: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "lcd_panel"; + enable-active-high; + gpio = <&gpio1 2 0>; }; sound { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard.dtsi index e4f63423d8ee..38abb6b50f6c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-wandboard.dtsi @@ -119,6 +119,7 @@ pinctrl-0 = <&pinctrl_mclk>; compatible = "fsl,sgtl5000"; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts index a2c79bcf9a11..cd9cbc9ccc9e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-nitrogen6sx.dts @@ -72,7 +72,6 @@ pinctrl-0 = <&pinctrl_reg_wlan>; compatible = "regulator-fixed"; clocks = <&clks IMX6SX_CLK_CKO>; - clock-names = "slow"; regulator-name = "wlan-en"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -196,6 +195,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; reg = <0x0a>; + #sound-dai-cells = <0>; clocks = <&clks IMX6SX_CLK_CKO2>; VDDA-supply = <®_1p8v>; VDDIO-supply = <®_1p8v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi index a05069d49cb8..f6b35923ad83 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi @@ -221,7 +221,7 @@ clocks = <&clks IMX6SX_CLK_APBH_DMA>; }; - gpmi: nand-controller@1806000{ + gpmi: nand-controller@1806000 { compatible = "fsl,imx6sx-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; @@ -1311,6 +1311,10 @@ <&clks IMX6SX_CLK_LCDIF_APB>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pix", "axi", "disp_axi"; + assigned-clocks = <&clks IMX6SX_CLK_LCDIF1_PRE_SEL>, + <&clks IMX6SX_CLK_LCDIF1_SEL>; + assigned-clock-parents = <&clks IMX6SX_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6SX_CLK_LCDIF1_PODF>; power-domains = <&pd_disp>; status = "disabled"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi index 155515fe13fa..2ac40d69425b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi @@ -442,14 +442,14 @@ >; }; - pinctrl_flexcan1: flexcan1grp{ + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 >; }; - pinctrl_flexcan2: flexcan2grp{ + pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts index 3792679c0c90..ad7f63ca521a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcexpress.dts @@ -145,7 +145,7 @@ >; }; - pinctrl_flexcan1: flexcan1grp{ + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts index 3ec042bfccba..1762bc47e18d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsbcpro.dts @@ -291,20 +291,20 @@ >; }; - pinctrl_flexcan1: flexcan1grp{ + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 >; }; - pinctrl_flexcan2: flexcan2grp{ + pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 >; }; - pinctrl_goodix_touch: goodixgrp{ + pinctrl_goodix_touch: goodixgrp { fsl,pins = < MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1020 >; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi index 7d1a391431bd..4a03ea6d24dc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-ccimx6ulsom.dtsi @@ -114,7 +114,6 @@ }; vdda_adc_3v3: vldo1 { - compatible = "regulator-fixed"; regulator-name = "vref-adc-3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts index a0097da03f38..875ae699c5cb 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-geam.dts @@ -148,7 +148,6 @@ reg = <0x0a>; #sound-dai-cells = <0>; clocks = <&clks IMX6UL_CLK_OSC>; - clock-names = "mclk"; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; VDDD-supply = <®_1p8v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi index 43868311f48a..33d5f27285a4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi @@ -272,7 +272,7 @@ >; }; - pinctrl_flexcan2: flexcan2grp{ + pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dts index 5a74c7f68eb6..fb206c1d8aca 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-dwarf.dts @@ -40,6 +40,7 @@ sgtl5000: audio-codec@a { reg = <0x0a>; compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; clocks = <&sys_mclk>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts index 09f7ffa9ad8c..bf7dbb4f1f3e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts @@ -51,6 +51,7 @@ sgtl5000: codec@a { reg = <0x0a>; compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; clocks = <&sys_mclk>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts index 6cd7d5877d20..6cfc943a8fa3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts @@ -51,6 +51,7 @@ sgtl5000: codec@a { reg = <0x0a>; compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; clocks = <&sys_mclk>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts index 92ac0edcb608..ef76ece21010 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul-mainboard.dts @@ -133,7 +133,7 @@ pinctrl-0 = <&pinctrl_disp0_3>; }; -®_usbotg_vbus{ +®_usbotg_vbus { status = "disabled"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi index 0174f3edbd16..3b87d980e9f4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi @@ -179,7 +179,7 @@ gpmi: nand-controller@1806000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; reg = <0x01806000 0x2000>, <0x01808000 0x2000>; reg-names = "gpmi-nand", "bch"; interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi index fde8a19aac0f..ec3c1e7301f4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-colibri.dtsi @@ -102,7 +102,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "+V3.3_ETH"; - regulator-type = "voltage"; vin-supply = <®_module_3v3>; clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; startup-delay-us = <150000>; diff --git a/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi index 104580d51d74..9fe51884af79 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7-colibri.dtsi @@ -29,7 +29,7 @@ extcon_usbc_det: usbc-det { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ + id-gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; /* SODIMM 137 / USBC_DET */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbc_det>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts index fdc10563f147..12361fcbe24a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts @@ -40,6 +40,7 @@ sgtl5000: audio-codec@a { reg = <0x0a>; compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; clocks = <&sys_mclk>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico-nymph.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-nymph.dts index 5afb1674e012..af26284297a2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-nymph.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-nymph.dts @@ -51,6 +51,7 @@ sgtl5000: audio-codec@a { reg = <0x0a>; compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; clocks = <&sys_mclk>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi index 73d90845e85c..c5eefe89cd99 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico.dtsi @@ -509,7 +509,7 @@ >; }; - pinctrl_pwm4: pwm4grp{ + pinctrl_pwm4: pwm4grp { fsl,pins = < MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x7f >; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts index 75f1cd14bea1..0462e43ec09b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts @@ -10,6 +10,11 @@ model = "Freescale i.MX7 SabreSD Board"; compatible = "fsl,imx7d-sdb", "fsl,imx7d"; + aliases { + ethernet0 = &fec1; + ethernet1 = &fec2; + }; + chosen { stdout-path = &uart1; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi index 6ffb428dc939..e152d08f27d4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7s.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7s.dtsi @@ -1275,7 +1275,7 @@ clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; }; - gpmi: nand-controller@33002000{ + gpmi: nand-controller@33002000 { compatible = "fsl,imx7d-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi index e3b2d23068f7..ebf97fcdd8ea 100644 --- a/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/mba6ulx.dtsi @@ -277,10 +277,9 @@ reg = <0x41>; interrupts = <21 IRQ_TYPE_EDGE_FALLING>; interrupt-parent = <&gpio4>; - interrupt-controller; status = "disabled"; - stmpe_touchscreen { + touchscreen { compatible = "st,stmpe-ts"; st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */ st,ave-ctrl = <3>; /* 8 sample average control */ diff --git a/arch/arm/boot/dts/nxp/ls/Makefile b/arch/arm/boot/dts/nxp/ls/Makefile index 3cb1d516f6fb..14759331dba2 100644 --- a/arch/arm/boot/dts/nxp/ls/Makefile +++ b/arch/arm/boot/dts/nxp/ls/Makefile @@ -3,5 +3,6 @@ dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-iot.dtb \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ + ls1021a-tqmls1021a-mbls1021a.dtb \ ls1021a-tsn.dtb \ ls1021a-twr.dtb diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts index ce8e26d7791f..e13ccae629a7 100644 --- a/arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-iot.dts @@ -62,19 +62,19 @@ }; }; -&can0{ +&can0 { status = "disabled"; }; -&can1{ +&can1 { status = "disabled"; }; -&can2{ +&can2 { status = "disabled"; }; -&can3{ +&can3 { status = "okay"; }; @@ -125,7 +125,7 @@ status = "okay"; }; -&esdhc{ +&esdhc { status = "okay"; }; diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a.dts b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a.dts new file mode 100644 index 000000000000..34636fcdfd6a --- /dev/null +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a-mbls1021a.dts @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/leds/leds-pca9532.h> +#include <dt-bindings/net/ti-dp83867.h> + +#include "ls1021a-tqmls1021a.dtsi" + +/ { + model = "TQMLS102xA SOM on MBLS102xA"; + compatible = "tq,ls1021a-tqmls1021a-mbls102xa", "tq,ls1021a-tqmls1021a", "fsl,ls1021a"; + + audio_mclk: audio-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + backlight_dcu: backlight { + compatible = "gpio-backlight"; + gpios = <&pca9530 0 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + switch-1 { + label = "S6"; + linux,code = <BTN_0>; + gpios = <&pca9554_0 0 GPIO_ACTIVE_LOW>; + }; + + btn2: switch-2 { + label = "S7"; + linux,code = <BTN_1>; + gpios = <&pca9554_0 1 GPIO_ACTIVE_LOW>; + }; + + switch-3 { + label = "S8"; + linux,code = <BTN_2>; + gpios = <&pca9554_0 2 GPIO_ACTIVE_LOW>; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + function-enumerator = <0>; + gpios = <&pca9554_2 4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + function-enumerator = <1>; + gpios = <&pca9554_2 5 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-2 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + function-enumerator = <2>; + gpios = <&pca9554_2 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + led-3 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <0>; + gpios = <&pca9554_2 7 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + lvds_encoder: lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; + power-supply = <®_3p3v>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_encoder_in: endpoint {}; + }; + + port@1 { + reg = <1>; + + lvds_encoder_out: endpoint {}; + }; + }; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "1P2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + vin-supply = <®_3p3v>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + hdmi_out: hdmi { + compatible = "hdmi-connector"; + type = "a"; + ddc-i2c-bus = <&i2c0>; + status = "disabled"; + + port { + hdmi_in: endpoint { + remote-endpoint = <&sii9022a_out>; + }; + }; + }; + + display: panel { + backlight = <&backlight_dcu>; + enable-gpios = <&pca9554_1 3 GPIO_ACTIVE_HIGH>; + status = "disabled"; + + port { + panel_in: endpoint {}; + }; + }; + + sound { + compatible = "fsl,imx-audio-tlv320aic32x4"; + model = "ls1021a-mbls1021a-tlv320aic32"; + ssi-controller = <&sai1>; + audio-codec = <&tlv320aic32x4>; + }; + +}; + +&can0 { + xceiver-supply = <®_3p3v>; + status = "okay"; +}; + +&can1 { + xceiver-supply = <®_3p3v>; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; + +&enet0 { + phy-handle = <&rgmii_phy0c>; + phy-mode = "rgmii-id"; + mac-address = [ 00 00 00 00 00 00 ]; + status = "okay"; +}; + +&enet1 { + tbi-handle = <&tbi1>; + phy-handle = <&sgmii_phy03>; + phy-mode = "sgmii"; + mac-address = [ 00 00 00 00 00 00 ]; + status = "okay"; +}; + +&enet2 { + phy-handle = <&rgmii_phy04>; + phy-mode = "rgmii-id"; + mac-address = [ 00 00 00 00 00 00 ]; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&audio_mclk>; + clock-names = "mclk"; + ldoin-supply = <®_3p3v>; + iov-supply = <®_3p3v>; + }; + + pca9554_0: gpio-expander@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + vcc-supply = <®_3p3v>; + gpio-line-names = "BUTTON0", "BUTTON1", + "BUTTON2", "EMMC_SEL", + "DIP2", "DIP3", + "EXT_TOUCH_INT", "GPIO_1"; + }; + + pca9554_1: gpio-expander@21 { + compatible = "nxp,pca9554"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + vcc-supply = <®_3p3v>; + gpio-line-names = "PCIE_PWR_EN", "MPCIE_DISABLE#", + "MPCIE_WAKE#", "LCD_BLT_EN", + "LCD_PWR_EN", "EC1_PHY_PWDN", + "EC3_PHY_PWDN", "SGMII_PHY_PWDN"; + }; + + pca9554_2: gpio-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&extirq>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + vcc-supply = <®_3p3v>; + gpio-line-names = "MUX_SEL0", "MUX_SEL1", + "MUX_SEL2", "MUX_SEL3", + "V95", "V96", "V97", "V98"; + }; + + sii9022a: hdmi-transmitter@3b { + compatible = "sil,sii9022"; + reg = <0x3b>; + iovcc-supply = <®_3p3v>; + cvcc12-supply = <®_1p2v>; + interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022a_in: endpoint {}; + }; + + port@1 { + reg = <1>; + + sii9022a_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; + }; + + stmpe811: port-expander@41 { + compatible = "st,stmpe811"; + reg = <0x41>; + interrupt-parent = <&gpio0>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + vcc-supply = <®_3p3v>; + vio-supply = <®_3p3v>; + + gpio { + compatible = "st,stmpe-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + /* GPIO 5-7 used for touch */ + st,norequest-mask = <0xf0>; + gpio-line-names = "GPIO_ADC_I2C1_1", + "GPIO_ADC_I2C1_2", + "GPIO_ADC_I2C1_3", + "GPIO_ADC_I2C1_4"; + }; + + touchscreen { + compatible = "st,stmpe-ts"; + status = "disabled"; + }; + }; + + pca9530: leds@60 { + compatible = "nxp,pca9530"; + reg = <0x60>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "PWM_0", "PWM_1"; + + led-0 { + type = <PCA9532_TYPE_GPIO>; + }; + + led-1 { + type = <PCA9532_TYPE_GPIO>; + }; + }; + +}; + +&i2c1 { + status = "okay"; +}; + +&lpuart0 { + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&mdio0 { + sgmii_phy03: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x03>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + ti,dp83867-rxctrl-strap-quirk; + }; + + rgmii_phy04: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x04>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + + rgmii_phy0c: ethernet-phy@c { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0c>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_50_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; +}; + +&pwm6 { + status = "okay"; +}; + +&pwm7 { + status = "okay"; +}; + +&sai1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb3 { + /* + * Although DR connector, VBUS is always driven, so + * restrict to host mode. + */ + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a.dtsi b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a.dtsi new file mode 100644 index 000000000000..1b13851ad997 --- /dev/null +++ b/arch/arm/boot/dts/nxp/ls/ls1021a-tqmls1021a.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +#include "ls1021a.dtsi" + +/ { + model = "TQMLS102xA SOM"; + compatible = "tq,ls1021a-tqmls1021a", "fsl,ls1021a"; + + reg_3p3v_som: regulator-3p3v-som { + compatible = "regulator-fixed"; + regulator-name = "3P3V_SOM"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&esdhc { + /* e-MMC over 8 data lines */ + bus-width = <8>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + /* MC34VR500 DC/DC regulator at 0x8, managed by PMIC */ + /* On-board PMC at 0x11 */ + + sa56004: temperature-sensor@4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + vcc-supply = <®_3p3v_som>; + }; + + rtc0: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <12500>; + }; + + m24c64_54: eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + read-only; + vcc-supply = <®_3p3v_som>; + }; +}; + +&mdio0 { + tbi1: tbi-phy@8 { + reg = <0x8>; + device_type = "tbi-phy"; + }; +}; + +&qspi { + status = "okay"; + + qflash0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + uboot@0 { + label = "U-Boot-PBL"; + reg = <0x0 0xe0000>; + }; + + env@e0000 { + label = "U-Boot Environment"; + reg = <0xe0000 0x10000>; + }; + + dtb@f0000 { + label = "DTB"; + reg = <0xf0000 0x10000>; + }; + + linux@100000 { + label = "Linux"; + reg = <0x100000 0x700000>; + }; + + rootfs@800000 { + label = "RootFS"; + reg = <0x800000 0x3800000>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts b/arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts index 0729e72f2283..229e727b222e 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx23-olinuxino.dts @@ -101,21 +101,14 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */ - gpio = <&gpio0 17 0>; - }; + reg_usb0_vbus: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + startup-delay-us = <300>; /* LAN9215 requires a POR of 200us minimum */ + gpio = <&gpio0 17 0>; }; leds { diff --git a/arch/arm/boot/dts/nxp/mxs/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/nxp/mxs/imx23-stmp378x_devb.dts index da4b88f32eaa..69124ba6a666 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx23-stmp378x_devb.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx23-stmp378x_devb.dts @@ -59,18 +59,11 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_vddio_sd0: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio1 29 0>; - }; + reg_vddio_sd0: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 29 0>; }; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx23.dtsi b/arch/arm/boot/dts/nxp/mxs/imx23.dtsi index a3668a0827fc..5eca942a52fd 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx23.dtsi +++ b/arch/arm/boot/dts/nxp/mxs/imx23.dtsi @@ -62,8 +62,8 @@ dma_apbh: dma-controller@80004000 { compatible = "fsl,imx23-dma-apbh"; reg = <0x80004000 0x2000>; - interrupts = <0 14 20 0 - 13 13 13 13>; + interrupts = <0>, <14>, <20>, <0>, + <13>, <13>, <13>, <13>; #dma-cells = <1>; dma-channels = <8>; clocks = <&clks 15>; @@ -415,10 +415,10 @@ dma_apbx: dma-apbx@80024000 { compatible = "fsl,imx23-dma-apbx"; reg = <0x80024000 0x2000>; - interrupts = <7 5 9 26 - 19 0 25 23 - 60 58 9 0 - 0 0 0 0>; + interrupts = <7>, <5>, <9>, <26>, + <19>, <0>, <25>, <23>, + <60>, <58>, <9>, <0>, + <0>, <0>, <0>, <0>; interrupt-names = "audio-adc", "audio-dac", "spdif-tx", "i2c", "saif0", "empty", "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", "saif1", "empty", @@ -431,7 +431,7 @@ dcp: crypto@80028000 { compatible = "fsl,imx23-dcp"; reg = <0x80028000 0x2000>; - interrupts = <53 54>; + interrupts = <53>, <54>; status = "okay"; }; @@ -456,7 +456,7 @@ lcdif@80030000 { compatible = "fsl,imx23-lcdif"; reg = <0x80030000 2000>; - interrupts = <46 45>; + interrupts = <46>, <45>; clocks = <&clks 38>; status = "disabled"; }; @@ -525,7 +525,8 @@ lradc: lradc@80050000 { compatible = "fsl,imx23-lradc"; reg = <0x80050000 0x2000>; - interrupts = <36 37 38 39 40 41 42 43 44>; + interrupts = <36>, <37>, <38>, <39>, <40>, + <41>, <42>, <43>, <44>; status = "disabled"; clocks = <&clks 26>; #io-channel-cells = <1>; @@ -568,7 +569,7 @@ timrot@80068000 { compatible = "fsl,imx23-timrot", "fsl,timrot"; reg = <0x80068000 0x2000>; - interrupts = <28 29 30 31>; + interrupts = <28>, <29>, <30>, <31>; clocks = <&clks 28>; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts b/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts index 4704b6141836..fd6fee63ad2f 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-apf28dev.dts @@ -10,28 +10,20 @@ model = "Armadeus Systems APF28Dev docking/development board"; compatible = "armadeus,imx28-apf28dev", "armadeus,imx28-apf28", "fsl,imx28"; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 23 1>; - enable-active-high; - }; + reg_usb0_vbus: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 23 1>; + enable-active-high; + }; - reg_can0_vcc: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "can0_vcc"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + reg_can0_vcc: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "can0_vcc"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; }; leds { diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10037.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10037.dts index d3e9a731525b..c72fe2d392f1 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10037.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10037.dts @@ -64,20 +64,13 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins_cfa10037>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 7 1>; - }; + reg_usb1_vbus: regulator-0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins_cfa10037>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 7 1>; }; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts index c5a7f56d83db..953e3162d2d2 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10049.dts @@ -78,21 +78,14 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins_cfa10049>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 7 1>; - }; + reg_usb1_vbus: regulator-0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins_cfa10049>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 7 1>; }; spi-2 { diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10057.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10057.dts index 27602c01f162..0be7356941ee 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10057.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10057.dts @@ -14,21 +14,14 @@ model = "Crystalfontz CFA-10057 Board"; compatible = "crystalfontz,cfa10057", "crystalfontz,cfa10036", "fsl,imx28"; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb1_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins_cfa10057>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 7 1>; - }; + reg_usb1_vbus: regulator-0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins_cfa10057>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 7 1>; }; backlight { diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10058.dts b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10058.dts index 931c4d089b26..aae0f1801461 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-cfa10058.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-cfa10058.dts @@ -14,21 +14,14 @@ model = "Crystalfontz CFA-10058 Board"; compatible = "crystalfontz,cfa10058", "crystalfontz,cfa10036", "fsl,imx28"; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb1_vbus: regulator@0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb_pins_cfa10058>; - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio0 7 1>; - }; + reg_usb1_vbus: regulator-0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb_pins_cfa10058>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 7 1>; }; backlight { diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx283lc.dts b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx283lc.dts index 29f8a3a245d4..7ae2d4ca8ef0 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx283lc.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx283lc.dts @@ -47,7 +47,7 @@ status = "okay"; }; -&pinctrl{ +&pinctrl { pinctrl-names = "default"; pinctrl-0 = <&hog_pins_cpuimx283>; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx28lc.dtsi index b285a946e2c2..6633cde305e5 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx28lc.dtsi +++ b/arch/arm/boot/dts/nxp/mxs/imx28-eukrea-mbmx28lc.dtsi @@ -69,55 +69,45 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_lcd_3v3: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - pinctrl-names = "default"; - pinctrl-0 = <®_lcd_3v3_pins_mbmx28lc>; - regulator-name = "lcd-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_lcd_3v3: regulator-1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <®_lcd_3v3_pins_mbmx28lc>; + regulator-name = "lcd-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usb0_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - pinctrl-names = "default"; - pinctrl-0 = <®_usb0_vbus_pins_mbmx28lc>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb0_vbus: regulator-2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <®_usb0_vbus_pins_mbmx28lc>; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usb1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - pinctrl-names = "default"; - pinctrl-0 = <®_usb1_vbus_pins_mbmx28lc>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usb1_vbus: regulator-3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <®_usb1_vbus_pins_mbmx28lc>; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 19 GPIO_ACTIVE_HIGH>; + enable-active-high; }; sound { diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-m28.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28-m28.dtsi index c08b14ad7cd5..66facef10ba9 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-m28.dtsi +++ b/arch/arm/boot/dts/nxp/mxs/imx28-m28.dtsi @@ -14,19 +14,12 @@ reg = <0x40000000 0x08000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; }; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts b/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts index 6b01de9efd02..8241c2d159fa 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-m28cu3.dts @@ -40,47 +40,37 @@ }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_vddio_sd0: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 29 0>; - }; + reg_vddio_sd0: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 29 0>; + }; - reg_vddio_sd1: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "vddio-sd1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 0>; - }; + reg_vddio_sd1: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 0>; + }; - reg_usb1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 8 0>; - enable-active-high; - }; + reg_usb1_vbus: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 8 0>; + enable-active-high; }; }; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-m28evk.dts b/arch/arm/boot/dts/nxp/mxs/imx28-m28evk.dts index e350d57a4cec..6bf26f386a5e 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-m28evk.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-m28evk.dts @@ -18,33 +18,28 @@ default-brightness-level = <6>; }; - regulators { - reg_vddio_sd0: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vddio-sd0"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 28 0>; - }; + reg_vddio_sd0: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "vddio-sd0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 28 0>; + }; - reg_usb0_vbus: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 12 0>; - }; + reg_usb0_vbus: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 12 0>; + }; - reg_usb1_vbus: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "usb1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 13 0>; - }; + reg_usb1_vbus: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 13 0>; }; sound { diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts b/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts index 5d74a68c56ff..0f01dded4e3d 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-sps1.dts @@ -15,19 +15,12 @@ reg = <0x40000000 0x08000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_usb0_vbus: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "usb0_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 9 0>; - }; + reg_usb0_vbus: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 9 0>; }; leds { diff --git a/arch/arm/boot/dts/nxp/mxs/imx28.dtsi b/arch/arm/boot/dts/nxp/mxs/imx28.dtsi index 29e37b1fae66..763adeb995ee 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28.dtsi +++ b/arch/arm/boot/dts/nxp/mxs/imx28.dtsi @@ -81,10 +81,10 @@ dma_apbh: dma-controller@80004000 { compatible = "fsl,imx28-dma-apbh"; reg = <0x80004000 0x2000>; - interrupts = <82 83 84 85 - 88 88 88 88 - 88 88 88 88 - 87 86 0 0>; + interrupts = <82>, <83>, <84>, <85>, + <88>, <88>, <88>, <88>, + <88>, <88>, <88>, <88>, + <87>, <86>, <0>, <0>; #dma-cells = <1>; dma-channels = <16>; clocks = <&clks 25>; @@ -993,10 +993,10 @@ dma_apbx: dma-apbx@80024000 { compatible = "fsl,imx28-dma-apbx"; reg = <0x80024000 0x2000>; - interrupts = <78 79 66 0 - 80 81 68 69 - 70 71 72 73 - 74 75 76 77>; + interrupts = <78>, <79>, <66>, <0>, + <80>, <81>, <68>, <69>, + <70>, <71>, <72>, <73>, + <74>, <75>, <76>, <77>; #dma-cells = <1>; dma-channels = <16>; clocks = <&clks 26>; @@ -1005,7 +1005,7 @@ dcp: crypto@80028000 { compatible = "fsl,imx28-dcp", "fsl,imx23-dcp"; reg = <0x80028000 0x2000>; - interrupts = <52 53 54>; + interrupts = <52>, <53>, <54>; status = "okay"; }; @@ -1136,8 +1136,8 @@ lradc: lradc@80050000 { compatible = "fsl,imx28-lradc"; reg = <0x80050000 0x2000>; - interrupts = <10 14 15 16 17 18 19 - 20 21 22 23 24 25>; + interrupts = <10>, <14>, <15>, <16>, <17>, <18>, <19>, + <20>, <21>, <22>, <23>, <24>, <25>; status = "disabled"; clocks = <&clks 41>; #io-channel-cells = <1>; @@ -1193,7 +1193,7 @@ timer: timrot@80068000 { compatible = "fsl,imx28-timrot", "fsl,timrot"; reg = <0x80068000 0x2000>; - interrupts = <48 49 50 51>; + interrupts = <48>, <49>, <50>, <51>; clocks = <&clks 26>; }; diff --git a/arch/arm/boot/dts/nxp/vf/vf610-twr.dts b/arch/arm/boot/dts/nxp/vf/vf610-twr.dts index 6c246d5aa032..876c14ecceb6 100644 --- a/arch/arm/boot/dts/nxp/vf/vf610-twr.dts +++ b/arch/arm/boot/dts/nxp/vf/vf610-twr.dts @@ -30,27 +30,20 @@ clock-frequency = <50000000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_vcc_3v3_mcu: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "vcc_3v3_mcu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; sound { diff --git a/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi index 3f7dc787938e..d1095b700c56 100644 --- a/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi +++ b/arch/arm/boot/dts/nxp/vf/vfxxx.dtsi @@ -569,7 +569,7 @@ <20000000>; }; - esdhc0: esdhc@400b1000 { + esdhc0: mmc@400b1000 { compatible = "fsl,imx53-esdhc"; reg = <0x400b1000 0x1000>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; @@ -580,7 +580,7 @@ status = "disabled"; }; - esdhc1: esdhc@400b2000 { + esdhc1: mmc@400b2000 { compatible = "fsl,imx53-esdhc"; reg = <0x400b2000 0x1000>; interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi index b4d286a6fab1..7c545c50847b 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064-pins.dtsi @@ -233,6 +233,22 @@ }; }; + gsbi4_uart_pin_a: gsbi4-uart-pin-active-state { + rx-pins { + pins = "gpio11"; + function = "gsbi4"; + drive-strength = <2>; + bias-disable; + }; + + tx-pins { + pins = "gpio10"; + function = "gsbi4"; + drive-strength = <4>; + bias-disable; + }; + }; + gsbi6_uart_2pins: gsbi6_uart_2pins { mux { pins = "gpio14", "gpio15"; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index d2289205ff81..516f0d2495e2 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -226,46 +226,6 @@ hwlocks = <&sfpb_mutex 3>; }; - smd { - compatible = "qcom,smd"; - - modem-edge { - interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&l2cc 8 3>; - qcom,smd-edge = <0>; - - status = "disabled"; - }; - - q6-edge { - interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&l2cc 8 15>; - qcom,smd-edge = <1>; - - status = "disabled"; - }; - - dsps-edge { - interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&sps_sic_non_secure 0x4080 0>; - qcom,smd-edge = <3>; - - status = "disabled"; - }; - - riva-edge { - interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; - - qcom,ipc = <&l2cc 8 25>; - qcom,smd-edge = <6>; - - status = "disabled"; - }; - }; - smsm { compatible = "qcom,smsm"; @@ -555,6 +515,18 @@ #size-cells = <1>; ranges; + gsbi4_serial: serial@16340000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16340000 0x100>, + <0x16300000 0x3>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-0 = <&gsbi4_uart_pin_a>; + pinctrl-names = "default"; + clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + gsbi4_i2c: i2c@16380000 { compatible = "qcom,i2c-qup-v1.1.1"; pinctrl-0 = <&i2c4_pins>; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts index e0679436000b..6d1b2439ae3a 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom/qcom-apq8074-dragonboard.dts @@ -156,6 +156,11 @@ }; }; +&pm8941_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + &pm8941_wled { qcom,cs-out; qcom,switching-freq = <3200>; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index 8f178bc87e1d..2b1f9d0fb510 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -784,10 +784,10 @@ }; }; - smd { - compatible = "qcom,smd"; + rpm: remoteproc { + compatible = "qcom,apq8084-rpm-proc", "qcom,rpm-proc"; - rpm { + smd-edge { interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi index d90b4f4c63af..da67d55fa557 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi @@ -262,10 +262,11 @@ &usb3 { status = "okay"; - dwc3@8a00000 { - phys = <&usb3_hs_phy>; - phy-names = "usb2-phy"; }; + +&usb3_dwc { + phys = <&usb3_hs_phy>; + phy-names = "usb2-phy"; }; &usb2_hs_phy { diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index f0ef86fadc9d..9844e0b7cff9 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -230,9 +230,12 @@ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "hc_irq", "pwr_irq"; bus-width = <8>; - clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_DCD_XO_CLK>; - clock-names = "iface", "core", "xo"; + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo>; + clock-names = "iface", + "core", + "xo"; status = "disabled"; }; @@ -416,10 +419,10 @@ pcie0: pci@40000000 { compatible = "qcom,pcie-ipq4019"; - reg = <0x40000000 0xf1d - 0x40000f20 0xa8 - 0x80000 0x2000 - 0x40100000 0x1000>; + reg = <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x80000 0x2000>, + <0x40100000 0x1000>; reg-names = "dbi", "elbi", "parf", "config"; device_type = "pci"; linux,pci-domain = <0>; @@ -543,9 +546,9 @@ <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7", - "msi8", "msi9", "msi10", "msi11", + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", + "msi8", "msi9", "msi10", "msi11", "msi12", "msi13", "msi14", "msi15", "legacy"; status = "disabled"; @@ -585,9 +588,9 @@ <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "msi0", "msi1", "msi2", "msi3", - "msi4", "msi5", "msi6", "msi7", - "msi8", "msi9", "msi10", "msi11", + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7", + "msi8", "msi9", "msi10", "msi11", "msi12", "msi13", "msi14", "msi15", "legacy"; status = "disabled"; @@ -621,7 +624,7 @@ }; }; - usb3_ss_phy: ssphy@9a000 { + usb3_ss_phy: usb-phy@9a000 { compatible = "qcom,usb-ss-ipq4019-phy"; #phy-cells = <0>; reg = <0x9a000 0x800>; @@ -631,7 +634,7 @@ status = "disabled"; }; - usb3_hs_phy: hsphy@a6000 { + usb3_hs_phy: usb-phy@a6000 { compatible = "qcom,usb-hs-ipq4019-phy"; #phy-cells = <0>; reg = <0xa6000 0x40>; @@ -641,7 +644,7 @@ status = "disabled"; }; - usb3: usb3@8af8800 { + usb3: usb@8af8800 { compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; reg = <0x8af8800 0x100>; #address-cells = <1>; @@ -653,7 +656,7 @@ ranges; status = "disabled"; - dwc3@8a00000 { + usb3_dwc: usb@8a00000 { compatible = "snps,dwc3"; reg = <0x8a00000 0xf8000>; interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; @@ -663,7 +666,7 @@ }; }; - usb2_hs_phy: hsphy@a8000 { + usb2_hs_phy: usb-phy@a8000 { compatible = "qcom,usb-hs-ipq4019-phy"; #phy-cells = <0>; reg = <0xa8000 0x40>; @@ -673,7 +676,7 @@ status = "disabled"; }; - usb2: usb2@60f8800 { + usb2: usb@60f8800 { compatible = "qcom,ipq4019-dwc3", "qcom,dwc3"; reg = <0x60f8800 0x100>; #address-cells = <1>; @@ -685,7 +688,7 @@ ranges; status = "disabled"; - dwc3@6000000 { + usb@6000000 { compatible = "snps,dwc3"; reg = <0x6000000 0xf8000>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts index 104eb729c2d6..1796ded31d17 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-rb3011.dts @@ -282,7 +282,6 @@ spi4: spi@1a280000 { status = "okay"; - spi-max-frequency = <50000000>; pinctrl-0 = <&spi_pins>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi index c5abe7151f14..17f65e140e02 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064-v1.0.dtsi @@ -30,7 +30,6 @@ spi4: spi@1a280000 { status = "okay"; - spi-max-frequency = <50000000>; pinctrl-0 = <&spi_pins>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi index b40c52ddf9b4..fc4f52f9e9f7 100644 --- a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-mdm9615.h> +#include <dt-bindings/clock/qcom,lcc-msm8960.h> #include <dt-bindings/reset/qcom,gcc-mdm9615.h> #include <dt-bindings/mfd/qcom-rpm.h> #include <dt-bindings/soc/qcom,gsbi.h> @@ -39,7 +40,7 @@ }; clocks { - cxo_board { + cxo_board: cxo_board { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <19200000>; @@ -106,6 +107,8 @@ #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; + clocks = <&cxo_board>, + <&lcc PLL4>; }; lcc: clock-controller@28000000 { @@ -113,6 +116,20 @@ reg = <0x28000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + clocks = <&cxo_board>, + <&gcc PLL4_VOTE>, + <0>, + <0>, <0>, + <0>, <0>, + <0>; + clock-names = "cxo", + "pll4_vote", + "mi2s_codec_clk", + "codec_i2s_mic_codec_clk", + "spare_i2s_mic_codec_clk", + "codec_i2s_spkr_codec_clk", + "spare_i2s_spkr_codec_clk", + "pcm_codec_clk"; }; l2cc: clock-controller@2011000 { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 313a726f4704..44f3f0127fd7 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -53,26 +53,10 @@ IRQ_TYPE_LEVEL_HIGH)>; }; - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - smem_region: smem@3000000 { - reg = <0x3000000 0x100000>; - no-map; - }; + rpm: remoteproc { + compatible = "qcom,msm8226-rpm-proc", "qcom,rpm-proc"; - adsp_region: adsp@dc00000 { - reg = <0x0dc00000 0x1900000>; - no-map; - }; - }; - - smd { - compatible = "qcom,smd"; - - rpm { + smd-edge { interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; @@ -120,6 +104,22 @@ }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + smem_region: smem@3000000 { + reg = <0x3000000 0x100000>; + no-map; + }; + + adsp_region: adsp@dc00000 { + reg = <0x0dc00000 0x1900000>; + no-map; + }; + }; + smem { compatible = "qcom,smem"; @@ -784,6 +784,23 @@ }; }; + sram@fdd00000 { + compatible = "qcom,msm8226-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x20000>; + reg-names = "ctrl", "mem"; + ranges = <0 0xfec00000 0x20000>; + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>; + clock-names = "core"; + + #address-cells = <1>; + #size-cells = <1>; + + gmu_sram: gmu-sram@0 { + reg = <0x0 0x20000>; + }; + }; + sram@fe805000 { compatible = "qcom,msm8226-imem", "syscon", "simple-mfd"; reg = <0xfe805000 0x1000>; @@ -797,6 +814,133 @@ mode-recovery = <0x77665502>; }; }; + + mdss: display-subsystem@fd900000 { + compatible = "qcom,mdss"; + reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&mmcc MDSS_GDSC>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "vsync"; + + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@fd900000 { + compatible = "qcom,msm8226-mdp5", "qcom,mdp5"; + reg = <0xfd900100 0x22000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_mdp_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@fd922800 { + compatible = "qcom,msm8226-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0xfd922800 0x1f8>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core", + "core_mmss"; + + phys = <&mdss_dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdss_mdp_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@fd922a00 { + compatible = "qcom,dsi-phy-28nm-8226"; + reg = <0xfd922a00 0xd4>, + <0xfd922b00 0x280>, + <0xfd922d80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "ref"; + }; + }; }; thermal-zones { diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index fa2013388d99..d13080fcbeea 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -364,7 +364,6 @@ #size-cells = <0>; reg = <0x16080000 0x1000>; interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; - spi-max-frequency = <24000000>; cs-gpios = <&msmgpio 8 0>; clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index aeca504918a0..706fef53767e 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -113,6 +113,28 @@ interrupts = <GIC_PPI 7 0xf04>; }; + rpm: remoteproc { + compatible = "qcom,msm8974-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8974"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + }; + }; + }; + reserved-memory { #address-cells = <1>; #size-cells = <1>; @@ -293,28 +315,6 @@ }; }; - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8974"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; - #clock-cells = <1>; - clocks = <&xo_board>; - clock-names = "xo"; - }; - }; - }; - }; - soc: soc { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts index f531d2679f6c..42d253b75dad 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-fairphone-fp2.dts @@ -414,7 +414,7 @@ wcnss_pin_a: wcnss-pin-active-state { wlan-pins { - pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; + pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; function = "wlan"; drive-strength = <6>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts index 154639d56f35..11468d1409f7 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -125,15 +125,15 @@ syna,startup-delay-ms = <100>; - rmi-f01@1 { + rmi4-f01@1 { reg = <0x1>; - syna,nosleep = <1>; + syna,nosleep-mode = <1>; }; - rmi-f11@11 { + rmi4-f11@11 { reg = <0x11>; - syna,f11-flip-x = <1>; syna,sensor-type = <1>; + touchscreen-inverted-x; }; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-pm8226.dtsi index 3b8ad28cecb0..2413778f3715 100644 --- a/arch/arm/boot/dts/qcom/qcom-pm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-pm8226.dtsi @@ -102,27 +102,27 @@ #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@7 { + channel@7 { reg = <VADC_VSYS>; qcom,pre-scaling = <1 3>; label = "vph_pwr"; }; - adc-chan@8 { + channel@8 { reg = <VADC_DIE_TEMP>; label = "die_temp"; }; - adc-chan@9 { + channel@9 { reg = <VADC_REF_625MV>; label = "ref_625mv"; }; - adc-chan@a { + channel@a { reg = <VADC_REF_1250MV>; label = "ref_1250mv"; }; - adc-chan@e { + channel@e { reg = <VADC_GND_REF>; }; - adc-chan@f { + channel@f { reg = <VADC_VDD_VADC>; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi index b3e246bacd78..ed0ba591c755 100644 --- a/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-pm8941.dtsi @@ -50,12 +50,24 @@ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; - pwrkey@800 { - compatible = "qcom,pm8941-pwrkey"; + pon@800 { + compatible = "qcom,pm8941-pon"; reg = <0x800>; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + }; + + pm8941_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; }; usb_id: usb-detect@900 { @@ -133,31 +145,31 @@ #io-channel-cells = <1>; - adc-chan@6 { + channel@6 { reg = <VADC_VBAT_SNS>; }; - adc-chan@8 { + channel@8 { reg = <VADC_DIE_TEMP>; }; - adc-chan@9 { + channel@9 { reg = <VADC_REF_625MV>; }; - adc-chan@a { + channel@a { reg = <VADC_REF_1250MV>; }; - adc-chan@e { + channel@e { reg = <VADC_GND_REF>; }; - adc-chan@f { + channel@f { reg = <VADC_VDD_VADC>; }; - adc-chan@30 { + channel@30 { reg = <VADC_LR_MUX1_BAT_THERM>; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom/qcom-pma8084.dtsi index 2dd4c6aa71c9..2985f4805b93 100644 --- a/arch/arm/boot/dts/qcom/qcom-pma8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-pma8084.dtsi @@ -64,27 +64,27 @@ #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@8 { + channel@8 { reg = <VADC_DIE_TEMP>; }; - adc-chan@9 { + channel@9 { reg = <VADC_REF_625MV>; }; - adc-chan@a { + channel@a { reg = <VADC_REF_1250MV>; }; - adc-chan@c { + channel@c { reg = <VADC_SPARE1>; }; - adc-chan@e { + channel@e { reg = <VADC_GND_REF>; }; - adc-chan@f { + channel@f { reg = <VADC_VDD_VADC>; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-pmx55.dtsi b/arch/arm/boot/dts/qcom/qcom-pmx55.dtsi index e1b869480bbd..da0851173c69 100644 --- a/arch/arm/boot/dts/qcom/qcom-pmx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-pmx55.dtsi @@ -40,25 +40,25 @@ #io-channel-cells = <1>; interrupts = <0x8 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = <ADC5_REF_GND>; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = <ADC5_1P25VREF>; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = <ADC5_DIE_TEMP>; qcom,pre-scaling = <1 1>; label = "die_temp"; }; - chg-temp@9 { + channel@9 { reg = <ADC5_CHG_TEMP>; qcom,pre-scaling = <1 1>; label = "chg_temp"; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index df3cd9c4ffb9..55ce87b75253 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -603,7 +603,7 @@ resets = <&gcc GCC_USB30_BCR>; - usb_dwc3: dwc3@a600000 { + usb_dwc3: usb@a600000 { compatible = "snps,dwc3"; reg = <0x0a600000 0xcd00>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts index 02d8d6e241ae..fcf1c51c5e7a 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom/qcom-sdx65-mtp.dts @@ -7,7 +7,7 @@ #include "qcom-sdx65.dtsi" #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <arm64/qcom/pmk8350.dtsi> -#include <arm64/qcom/pm8150b.dtsi> +#include <arm64/qcom/pm7250b.dtsi> #include "qcom-pmx65.dtsi" / { diff --git a/arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dts index fa09295052c6..d21e00e1f401 100644 --- a/arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/renesas/r8a7740-armadillo800eva.dts @@ -58,7 +58,7 @@ regulator-max-microvolt = <3300000>; vin-supply = <&vcc_sdhi0>; - enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>; + enable-gpios = <&pfc 74 GPIO_ACTIVE_HIGH>; gpios = <&pfc 17 GPIO_ACTIVE_HIGH>; states = <3300000 0>, <1800000 1>; diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts index c18bbd7141c4..31cdca3e623c 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts @@ -67,7 +67,7 @@ status = "okay"; }; -&pinctrl{ +&pinctrl { pins_can0: pins_can0 { pinmux = <RZN1_PINMUX(162, RZN1_FUNC_CAN)>, /* CAN0_TXD */ <RZN1_PINMUX(163, RZN1_FUNC_CAN)>; /* CAN0_RXD */ diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts index 3340fc3f0739..3d587602e13a 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts +++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts @@ -20,6 +20,35 @@ chosen { stdout-path = "serial2:1500000n8"; }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + v3v3_sys: v3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "v3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; }; &gmac { diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi index cc64ba4be344..7ea8d7d16f5f 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2.dtsi @@ -11,15 +11,6 @@ mmc0 = &emmc; }; - vcc5v0_sys: vcc5v0-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - vccio_flash: vccio-flash-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -52,7 +43,7 @@ bus-width = <8>; non-removable; pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk>; rockchip,default-sample-phase = <90>; vmmc-supply = <&vcc_3v3>; vqmmc-supply = <&vccio_flash>; @@ -301,6 +292,22 @@ status = "okay"; }; +&sfc { + pinctrl-names = "default"; + pinctrl-0 = <&fspi_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + &sdio { bus-width = <4>; cap-sd-highspeed; diff --git a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi index b77021772781..554353e0a758 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126-pinctrl.dtsi @@ -59,6 +59,24 @@ <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; }; }; + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PA3 3 &pcfg_pull_down>, + /* fspi_cs0n */ + <0 RK_PD4 3 &pcfg_pull_up>, + /* fspi_d0 */ + <1 RK_PA0 3 &pcfg_pull_up>, + /* fspi_d1 */ + <1 RK_PA1 3 &pcfg_pull_up>, + /* fspi_d2 */ + <0 RK_PD6 3 &pcfg_pull_up>, + /* fspi_d3 */ + <1 RK_PA2 3 &pcfg_pull_up>; + }; + }; i2c0 { /omit-if-no-ref/ i2c0_xfer: i2c0-xfer { @@ -249,5 +267,13 @@ /* uart5_tx_m0 */ <3 RK_PA6 4 &pcfg_pull_up>; }; + /omit-if-no-ref/ + uart5m2_xfer: uart5m2-xfer { + rockchip,pins = + /* uart5_rx_m2 */ + <2 RK_PA1 3 &pcfg_pull_up>, + /* uart5_tx_m2 */ + <2 RK_PA0 3 &pcfg_pull_up>; + }; }; }; diff --git a/arch/arm/boot/dts/rockchip/rv1126.dtsi b/arch/arm/boot/dts/rockchip/rv1126.dtsi index 1f07d0a4fa73..9c918420ecd5 100644 --- a/arch/arm/boot/dts/rockchip/rv1126.dtsi +++ b/arch/arm/boot/dts/rockchip/rv1126.dtsi @@ -83,6 +83,11 @@ clock-frequency = <24000000>; }; + display_subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + xin24m: oscillator { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -125,6 +130,26 @@ reg = <0xfe86c000 0x20>; }; + qos_iep: qos@fe8a0000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0000 0x20>; + }; + + qos_rga_rd: qos@fe8a0080 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0080 0x20>; + }; + + qos_rga_wr: qos@fe8a0100 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0100 0x20>; + }; + + qos_vop: qos@fe8a0180 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe8a0180 0x20>; + }; + gic: interrupt-controller@feff0000 { compatible = "arm,gic-400"; interrupt-controller; @@ -170,6 +195,25 @@ pm_qos = <&qos_sdio>; #power-domain-cells = <0>; }; + + power-domain@RV1126_PD_VO { + reg = <RV1126_PD_VO>; + clocks = <&cru ACLK_RGA>, + <&cru HCLK_RGA>, + <&cru CLK_RGA_CORE>, + <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP>, + <&cru PCLK_DSIHOST>, + <&cru ACLK_IEP>, + <&cru HCLK_IEP>, + <&cru CLK_IEP_CORE>; + pm_qos = <&qos_rga_rd>, + <&qos_rga_wr>, + <&qos_vop>, + <&qos_iep>; + #power-domain-cells = <0>; + }; }; }; @@ -332,6 +376,43 @@ clock-names = "pclk", "timer"; }; + vop: vop@ffb00000 { + compatible = "rockchip,rv1126-vop"; + reg = <0xffb00000 0x200>, <0xffb00a00 0x400>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; + reset-names = "axi", "ahb", "dclk"; + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; + iommus = <&vop_mmu>; + power-domains = <&power RV1126_PD_VO>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_rgb: endpoint@0 { + reg = <0>; + }; + + vop_out_dsi: endpoint@1 { + reg = <1>; + }; + }; + }; + + vop_mmu: iommu@ffb00f00 { + compatible = "rockchip,iommu"; + reg = <0xffb00f00 0x100>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + #iommu-cells = <0>; + power-domains = <&power RV1126_PD_VO>; + status = "disabled"; + }; + gmac: ethernet@ffc40000 { compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; reg = <0xffc40000 0x4000>; @@ -419,6 +500,18 @@ status = "disabled"; }; + sfc: spi@ffc90000 { + compatible = "rockchip,sfc"; + reg = <0xffc90000 0x4000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <80000000>; + clock-names = "clk_sfc", "hclk_sfc"; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + power-domains = <&power RV1126_PD_NVM>; + status = "disabled"; + }; + pinctrl: pinctrl { compatible = "rockchip,rv1126-pinctrl"; rockchip,grf = <&grf>; diff --git a/arch/arm/boot/dts/samsung/Makefile b/arch/arm/boot/dts/samsung/Makefile index c8d067abdd59..7becf36656b1 100644 --- a/arch/arm/boot/dts/samsung/Makefile +++ b/arch/arm/boot/dts/samsung/Makefile @@ -9,6 +9,9 @@ dtb-$(CONFIG_ARCH_EXYNOS4) += \ exynos4210-smdkv310.dtb \ exynos4210-trats.dtb \ exynos4210-universal_c210.dtb \ + exynos4212-tab3-3g8.dtb \ + exynos4212-tab3-lte8.dtb \ + exynos4212-tab3-wifi8.dtb \ exynos4412-i9300.dtb \ exynos4412-i9305.dtb \ exynos4412-itop-elite.dtb \ diff --git a/arch/arm/boot/dts/samsung/exynos4210-i9100.dts b/arch/arm/boot/dts/samsung/exynos4210-i9100.dts index 37cd4dde53e4..a9ec1f6c1dea 100644 --- a/arch/arm/boot/dts/samsung/exynos4210-i9100.dts +++ b/arch/arm/boot/dts/samsung/exynos4210-i9100.dts @@ -207,8 +207,8 @@ power-on-delay = <10>; reset-delay = <10>; - panel-width-mm = <90>; - panel-height-mm = <154>; + panel-width-mm = <56>; + panel-height-mm = <93>; display-timings { timing { diff --git a/arch/arm/boot/dts/samsung/exynos4210-trats.dts b/arch/arm/boot/dts/samsung/exynos4210-trats.dts index bfb04b31e11b..95e0e01b6ff6 100644 --- a/arch/arm/boot/dts/samsung/exynos4210-trats.dts +++ b/arch/arm/boot/dts/samsung/exynos4210-trats.dts @@ -20,10 +20,10 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x10000000 - 0x50000000 0x10000000 - 0x60000000 0x10000000 - 0x70000000 0x10000000>; + reg = <0x40000000 0x10000000 + 0x50000000 0x10000000 + 0x60000000 0x10000000 + 0x70000000 0x10000000>; }; aliases { diff --git a/arch/arm/boot/dts/samsung/exynos4210-universal_c210.dts b/arch/arm/boot/dts/samsung/exynos4210-universal_c210.dts index c84af3d27c1c..bdc30f8cf748 100644 --- a/arch/arm/boot/dts/samsung/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/samsung/exynos4210-universal_c210.dts @@ -20,8 +20,8 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x10000000 - 0x50000000 0x10000000>; + reg = <0x40000000 0x10000000 + 0x50000000 0x10000000>; }; aliases { diff --git a/arch/arm/boot/dts/samsung/exynos4212-tab3-3g8.dts b/arch/arm/boot/dts/samsung/exynos4212-tab3-3g8.dts new file mode 100644 index 000000000000..d96b2dd44608 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4212-tab3-3g8.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4212 based Galaxy Tab 3 8.0 3G board device tree + * source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4212-tab3.dtsi" + +/ { + model = "Samsung Galaxy Tab 3 8.0 3G (SM-T311) based on Exynos4212"; + compatible = "samsung,t311", "samsung,tab3", "samsung,exynos4212", "samsung,exynos4"; + chassis-type = "tablet"; +}; + +/* Pin control sleep state overrides */ +&sleep0 { + PIN_SLP(gpb-5, INPUT, UP); +}; + +&sleep1 { + PIN_SLP(gpl0-0, OUT0, NONE); + PIN_SLP(gpl1-0, OUT0, NONE); + PIN_SLP(gpl2-4, OUT0, NONE); + PIN_SLP(gpm3-3, OUT1, NONE); +}; diff --git a/arch/arm/boot/dts/samsung/exynos4212-tab3-lte8.dts b/arch/arm/boot/dts/samsung/exynos4212-tab3-lte8.dts new file mode 100644 index 000000000000..bbb398eca7b0 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4212-tab3-lte8.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4212 based Galaxy Tab 3 8.0 LTE board device tree + * source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4212-tab3.dtsi" + +/ { + model = "Samsung Galaxy Tab 3 8.0 LTE (SM-T315) based on Exynos4212"; + compatible = "samsung,t315", "samsung,tab3", "samsung,exynos4212", "samsung,exynos4"; + chassis-type = "tablet"; +}; + +/* Pin control sleep state overrides */ +&sleep0 { + PIN_SLP(gpa0-4, INPUT, UP); + PIN_SLP(gpa0-5, INPUT, UP); + + PIN_SLP(gpb-5, INPUT, UP); + + PIN_SLP(gpc0-0, PREV, NONE); + PIN_SLP(gpc1-3, INPUT, NONE); + + PIN_SLP(gpf1-6, INPUT, NONE); + PIN_SLP(gpf2-2, PREV, NONE); +}; + +&sleep1 { + PIN_SLP(gpl0-0, PREV, NONE); + + PIN_SLP(gpl1-0, PREV, NONE); + + PIN_SLP(gpl2-1, INPUT, DOWN); + PIN_SLP(gpl2-2, INPUT, DOWN); + PIN_SLP(gpl2-4, OUT0, NONE); + PIN_SLP(gpl2-5, PREV, NONE); + + PIN_SLP(gpm3-3, OUT1, NONE); +}; diff --git a/arch/arm/boot/dts/samsung/exynos4212-tab3-wifi8.dts b/arch/arm/boot/dts/samsung/exynos4212-tab3-wifi8.dts new file mode 100644 index 000000000000..54cb01703b60 --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4212-tab3-wifi8.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4212 based Galaxy Tab 3 8.0 WiFi board device tree + * source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4212-tab3.dtsi" + +/ { + model = "Samsung Galaxy Tab 3 8.0 WiFi (SM-T310) based on Exynos4212"; + compatible = "samsung,t310", "samsung,tab3", "samsung,exynos4212", "samsung,exynos4"; + chassis-type = "tablet"; +}; + +&i2c_lightsensor { + status = "okay"; + + lightsensor@10 { + compatible = "capella,cm3323"; + reg = <0x10>; + }; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi new file mode 100644 index 000000000000..ce81e42bf5eb --- /dev/null +++ b/arch/arm/boot/dts/samsung/exynos4212-tab3.dtsi @@ -0,0 +1,1310 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4212 based Galaxy Tab 3 board common source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4212.dtsi" +#include "exynos4412-ppmu-common.dtsi" +#include "exynos-mfc-reserved-memory.dtsi" +#include <dt-bindings/clock/samsung,s2mps11.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/input/gpio-keys.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "exynos-pinctrl.h" + +/ { + compatible = "samsung,tab3", "samsung,exynos4212", "samsung,exynos4"; + + memory@40000000 { + device_type = "memory"; + + /* + * Technically 1.5GB is available, but the latter 512MB is handled + * in a special way by downstream (every second page is skipped), + * and thus doesn't initialize correctly on mainline. Only 1020M is + * used for now. + */ + reg = <0x40000000 0x3fc00000>; + }; + + aliases { + mmc0 = &mshc_0; /* Internal storage */ + mmc1 = &sdhci_2; /* SD card */ + mmc2 = &sdhci_3; /* WiFi */ + }; + + chosen { + stdout-path = &serial_2; + + /* Default S-BOOT bootloader loads initramfs here */ + linux,initrd-start = <0x42000000>; + linux,initrd-end = <0x42800000>; + }; + + firmware@204f000 { + compatible = "samsung,secure-firmware"; + reg = <0x0204F000 0x1000>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; + + key-power { + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + label = "power"; + debounce-interval = <10>; + wakeup-source; + }; + + key-up { + gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + label = "volume down"; + debounce-interval = <10>; + }; + + key-down { + gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + label = "volume up"; + debounce-interval = <10>; + }; + + key-home { + gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOME>; + label = "home"; + debounce-interval = <10>; + }; + + switch-hall-sensor { + gpios = <&gpx2 4 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + linux,can-disable; + label = "hall effect sensor"; + debounce-interval = <10>; + wakeup-source; + }; + }; + + led-touchkeys { + compatible = "regulator-led"; + vled-supply = <&ldo20_reg>; + default-state = "off"; + function = LED_FUNCTION_KBD_BACKLIGHT; + color = <LED_COLOR_ID_WHITE>; + }; + + i2c_max77693: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpm2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpm2 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "maxim,max77693"; + reg = <0x66>; + interrupt-parent = <&gpx1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&max77693_irq>; + + regulators { + esafeout1_reg: ESAFEOUT1 { + regulator-name = "ESAFEOUT1"; + regulator-boot-on; + }; + + esafeout2_reg: ESAFEOUT2 { + regulator-name = "ESAFEOUT2"; + }; + + charger_reg: CHARGER { + regulator-name = "CHARGER"; + regulator-min-microamp = <60000>; + regulator-max-microamp = <2580000>; + regulator-boot-on; + }; + }; + + charger { + compatible = "maxim,max77693-charger"; + + maxim,constant-microvolt = <4350000>; + maxim,min-system-microvolt = <3600000>; + maxim,thermal-regulation-celsius = <100>; + maxim,battery-overcurrent-microamp = <3500000>; + maxim,charge-input-threshold-microvolt = <4300000>; + }; + }; + }; + + i2c_max77693_fuel: i2c-gpio-2 { + compatible = "i2c-gpio"; + sda-gpios = <&gpy0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + fuel-gauge@36 { + compatible = "maxim,max17050"; + reg = <0x36>; + interrupt-parent = <&gpx2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&max77693_fuel_irq>; + + maxim,over-heat-temp = <500>; + maxim,over-volt = <4500>; + }; + }; + + i2c_magnetometer: i2c-gpio-3 { + compatible = "i2c-gpio"; + sda-gpios = <&gpy2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@2e { + compatible = "yamaha,yas532"; + reg = <0x2e>; + iovdd-supply = <&ldo3_reg>; + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; + }; + + i2c_lightsensor: i2c-gpio-4 { + compatible = "i2c-gpio"; + sda-gpios = <&gpl0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpl0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + /* WiFi model uses CM3323, 3G/LTE use CM36653 */ + }; + + i2c_bl: i2c-gpio-5 { + compatible = "i2c-gpio"; + sda-gpios = <&gpm4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpm4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + + backlight: backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + + bl-name = "lcd-bl"; + dev-ctrl = /bits/ 8 <0x80>; + init-brt = /bits/ 8 <0x78>; /* 120 */ + + power-supply = <&vbatt_reg>; + enable-supply = <&backlight_reset_supply>; + + pwms = <&pwm 1 78770 0>; + pwm-names = "lp8556"; + + rom-a3h { + rom-addr = /bits/ 8 <0xa3>; + rom-val = /bits/ 8 <0x5e>; + }; + + rom-a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x34>; + }; + + rom-a7h { + rom-addr = /bits/ 8 <0xa7>; + rom-val = /bits/ 8 <0xfa>; + }; + }; + }; + + vbatt_reg: voltage-regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VBATT"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + backlight_reset_supply: voltage-regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "BACKLIGHT_ENVDDIO"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_reset>; + gpio = <&gpm0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + display_3v3_supply: voltage-regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "DISPLAY_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_en>; + gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; /* LCD_EN */ + enable-active-high; + }; + + mic_bias_reg: voltage-regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "MICBIAS_LDO_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + submic_bias_reg: voltage-regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "SUB_MICBIAS_LDO_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + sound: sound { + compatible = "samsung,midas-audio"; + model = "TAB3"; + mic-bias-supply = <&mic_bias_reg>; + submic-bias-supply = <&submic_bias_reg>; + + samsung,audio-routing = + "HP", "HPOUT1L", + "HP", "HPOUT1R", + + "SPK", "SPKOUTLN", + "SPK", "SPKOUTLP", + "SPK", "SPKOUTRN", + "SPK", "SPKOUTRP", + + "RCV", "HPOUT2N", + "RCV", "HPOUT2P", + + "LINE", "LINEOUT2N", + "LINE", "LINEOUT2P", + + "HDMI", "LINEOUT1N", + "HDMI", "LINEOUT1P", + + "IN2LP:VXRN", "MICBIAS1", + "IN2LN", "MICBIAS1", + "Main Mic", "MICBIAS1", + + "IN1RP", "MICBIAS2", + "IN1RN", "MICBIAS2", + "Sub Mic", "MICBIAS2", + + "IN1LP", "Headset Mic", + "IN1LN", "Headset Mic"; + + cpu { + sound-dai = <&i2s0 0>; + }; + + codec { + sound-dai = <&wm1811>; + }; + }; + + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpm3 5 GPIO_ACTIVE_LOW>; + clocks = <&s5m8767_osc S2MPS11_CLK_BT>; + clock-names = "ext_clock"; + }; +}; + +&bus_acp { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_c2c { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_display { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_dmc { + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + +&bus_fsys { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_leftbus { + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; + vdd-supply = <&buck3_reg>; + status = "okay"; +}; + +&bus_mfc { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_peri { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_rightbus { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&cpu_thermal { + cooling-maps { + map0 { + /* Corresponds to 800MHz at freq_table */ + cooling-device = <&cpu0 7 7>, <&cpu1 7 7>; + }; + map1 { + /* Corresponds to 200MHz at freq_table */ + cooling-device = <&cpu0 13 13>, <&cpu1 13 13>; + }; + }; +}; + +&dsi_0 { + vddcore-supply = <&ldo8_reg>; + vddio-supply = <&ldo10_reg>; + samsung,burst-clock-frequency = <500000000>; + samsung,esc-clock-frequency = <20000000>; + samsung,pll-clock-frequency = <24000000>; + status = "okay"; + + panel@0 { + compatible = "samsung,lsl080al02", "samsung,s6d7aa0"; + reg = <0>; + power-supply = <&display_3v3_supply>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_nrst>; + reset-gpios = <&gpf0 4 GPIO_ACTIVE_LOW>; + backlight = <&backlight>; + }; +}; + +&exynos_usbphy { + vbus-supply = <&esafeout1_reg>; + status = "okay"; +}; + +&fimd { + status = "okay"; +}; + +&gpu { + mali-supply = <&buck4_reg>; + status = "okay"; +}; + +&hsotg { + vusb_d-supply = <&ldo15_reg>; + vusb_a-supply = <&ldo12_reg>; + dr_mode = "otg"; + status = "okay"; +}; + +&i2c_1 { + pinctrl-0 = <&i2c1_bus>; + pinctrl-names = "default"; + status = "okay"; + + lis3dh: accelerometer@19 { + /* K2DH seems to be the same as lis2dh12 in terms of registers */ + compatible = "st,lis2dh12-accel"; + reg = <0x19>; + + interrupt-parent = <&gpx0>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&ldo17_reg>; + vddio-supply = <&ldo3_reg>; + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; +}; + +&i2c_3 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + status = "okay"; + + touchscreen@48 { + /* MELFAS MMS252, using MMS114 compatible for now */ + compatible = "melfas,mms114"; + reg = <0x48>; + interrupt-parent = <&gpb>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <1280>; + avdd-supply = <&ldo21_reg>; + vdd-supply = <&ldo25_reg>; + linux,keycodes = <KEY_MENU KEY_BACK>; + }; +}; + +&i2c_4 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c4_bus>; + pinctrl-names = "default"; + status = "okay"; + + wm1811: audio-codec@1a { + compatible = "wlf,wm1811"; + reg = <0x1a>; + clocks = <&pmu_system_controller 0>; + clock-names = "MCLK1"; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpx3>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + #sound-dai-cells = <0>; + + wlf,gpio-cfg = <0x3 0x0 0x0 0x0 0x0 0x0 + 0x0 0x8000 0x0 0x0 0x0>; + wlf,micbias-cfg = <0x25 0x2f>; + + wlf,lineout1-feedback; + wlf,lineout1-se; + wlf,lineout2-se; + wlf,ldoena-always-driven; + + AVDD2-supply = <&ldo3_reg>; + CPVDD-supply = <&ldo3_reg>; + DBVDD1-supply = <&ldo3_reg>; + DBVDD2-supply = <&ldo3_reg>; + DBVDD3-supply = <&ldo3_reg>; + SPKVDD1-supply = <&vbatt_reg>; + SPKVDD2-supply = <&vbatt_reg>; + wlf,ldo1ena-gpios = <&gpm4 4 GPIO_ACTIVE_HIGH>; + wlf,ldo2ena-gpios = <&gpm4 4 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c_7 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c7_bus>; + pinctrl-names = "default"; + status = "okay"; + + s5m8767: pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + interrupt-parent = <&gpx0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>; + wakeup-source; + + s5m8767,pmic-buck-default-dvs-idx = <1>; + + s5m8767,pmic-buck-dvs-gpios = <&gpm3 0 GPIO_ACTIVE_HIGH>, + <&gpm3 1 GPIO_ACTIVE_HIGH>, + <&gpm3 2 GPIO_ACTIVE_HIGH>; + + s5m8767,pmic-buck-ds-gpios = <&gpf3 1 GPIO_ACTIVE_HIGH>, + <&gpf3 2 GPIO_ACTIVE_HIGH>, + <&gpf3 3 GPIO_ACTIVE_HIGH>; + + s5m8767,pmic-buck2-dvs-voltage = <1100000>, <1100000>, + <1100000>, <1100000>, + <1100000>, <1100000>, + <1100000>, <1100000>; + + s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, + <1100000>, <1100000>, + <1100000>, <1100000>, + <1100000>, <1100000>; + + s5m8767,pmic-buck4-dvs-voltage = <1100000>, <1100000>, + <1100000>, <1100000>, + <1100000>, <1100000>, + <1100000>, <1100000>; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VALIVE_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo2_reg: LDO2 { + regulator-name = "VM1M2_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo3_reg: LDO3 { + regulator-name = "VCC_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; + }; + + ldo5_reg: LDO5 { + regulator-name = "VCC_3.3V_MHL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + op_mode = <1>; + }; + + ldo8_reg: LDO8 { + regulator-name = "VMIPI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + op_mode = <3>; + }; + + ldo9_reg: LDO9 { + regulator-name = "VSIL_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + op_mode = <1>; + }; + + ldo10_reg: LDO10 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <3>; + }; + + ldo12_reg: LDO12 { + regulator-name = "VUOTG_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + op_mode = <1>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo13_reg: LDO13 { + regulator-name = "VCC_1.8V_MHL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; + }; + + ldo15_reg: LDO15 { + regulator-name = "VHSIC_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + op_mode = <1>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + regulator-name = "VCC_2.8V_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; + regulator-always-on; + }; + + ldo19_reg: LDO19 { + regulator-name = "VLED_IC_1.9V"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + op_mode = <1>; + regulator-always-on; + }; + + ldo20_reg: LDO20 { + regulator-name = "VTOUCH_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + op_mode = <1>; + }; + + ldo21_reg: LDO21 { + regulator-name = "TSP_VDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + op_mode = <1>; + }; + + ldo22_reg: LDO22 { + regulator-name = "5M_AF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; + }; + + ldo23_reg: LDO23 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <3>; + }; + + ldo24_reg: LDO24 { + regulator-name = "LEDA_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; + }; + + ldo25_reg: LDO25 { + regulator-name = "TSP_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; + }; + + ldo26_reg: LDO26 { + regulator-name = "CAM_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; + }; + + ldo27_reg: LDO27 { + regulator-name = "VTCAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; + }; + + buck1_reg: BUCK1 { + regulator-name = "VDD_MIF"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_INT"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck4_reg: BUCK4 { + regulator-name = "VDD_G3D"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + op_mode = <3>; + }; + + buck5_reg: BUCK5 { + regulator-name = "VMEM_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck6_reg: BUCK6 { + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + op_mode = <1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + s5m8767_osc: clocks { + compatible = "samsung,s5m8767-clk"; + #clock-cells = <1>; + clock-output-names = "en32khz_ap", + "en32khz_cp", + "en32khz_bt"; + }; + }; +}; + +&i2s0 { + pinctrl-0 = <&i2s0_bus>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mshc_0 { + broken-cd; + non-removable; + card-detect-delay = <200>; + vmmc-supply = <&ldo22_reg>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <0>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + status = "okay"; +}; + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + lcd_en: lcd-en-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + lcd_nrst: lcd-nrst-pins { + samsung,pins = "gpf0-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + s5m8767_ds: s5m8767-ds-pins { + samsung,pins = "gpf3-1", "gpf3-2", "gpf3-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + sleep0: sleep-state { + PIN_SLP(gpa0-0, INPUT, NONE); + PIN_SLP(gpa0-1, OUT0, NONE); + PIN_SLP(gpa0-2, INPUT, NONE); + PIN_SLP(gpa0-3, INPUT, UP); + PIN_SLP(gpa0-4, INPUT, DOWN); + PIN_SLP(gpa0-5, INPUT, DOWN); + PIN_SLP(gpa0-6, INPUT, DOWN); + PIN_SLP(gpa0-7, INPUT, DOWN); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, INPUT, DOWN); + PIN_SLP(gpa1-2, INPUT, DOWN); + PIN_SLP(gpa1-3, INPUT, DOWN); + PIN_SLP(gpa1-4, INPUT, DOWN); + PIN_SLP(gpa1-5, INPUT, DOWN); + + PIN_SLP(gpb-0, INPUT, NONE); + PIN_SLP(gpb-1, INPUT, NONE); + PIN_SLP(gpb-2, INPUT, NONE); + PIN_SLP(gpb-3, INPUT, NONE); + PIN_SLP(gpb-4, INPUT, DOWN); + PIN_SLP(gpb-5, INPUT, DOWN); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, INPUT, DOWN); + + PIN_SLP(gpc0-0, INPUT, DOWN); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, INPUT, NONE); + PIN_SLP(gpc0-3, INPUT, NONE); + PIN_SLP(gpc0-4, INPUT, NONE); + + PIN_SLP(gpc1-0, INPUT, DOWN); + PIN_SLP(gpc1-1, INPUT, DOWN); + PIN_SLP(gpc1-2, INPUT, DOWN); + PIN_SLP(gpc1-3, INPUT, DOWN); + PIN_SLP(gpc1-4, INPUT, DOWN); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, OUT0, NONE); + PIN_SLP(gpd0-2, INPUT, NONE); + PIN_SLP(gpd0-3, INPUT, NONE); + + PIN_SLP(gpd1-0, INPUT, DOWN); + PIN_SLP(gpd1-1, INPUT, DOWN); + PIN_SLP(gpd1-2, INPUT, NONE); + PIN_SLP(gpd1-3, INPUT, NONE); + + PIN_SLP(gpf0-0, INPUT, DOWN); + PIN_SLP(gpf0-1, INPUT, DOWN); + PIN_SLP(gpf0-2, INPUT, DOWN); + PIN_SLP(gpf0-3, INPUT, DOWN); + PIN_SLP(gpf0-4, OUT0, NONE); + PIN_SLP(gpf0-5, OUT0, NONE); + PIN_SLP(gpf0-6, INPUT, DOWN); + PIN_SLP(gpf0-7, INPUT, DOWN); + + PIN_SLP(gpf1-0, INPUT, DOWN); + PIN_SLP(gpf1-1, INPUT, DOWN); + PIN_SLP(gpf1-2, INPUT, DOWN); + PIN_SLP(gpf1-3, INPUT, DOWN); + PIN_SLP(gpf1-4, INPUT, DOWN); + PIN_SLP(gpf1-5, INPUT, DOWN); + PIN_SLP(gpf1-6, INPUT, DOWN); + PIN_SLP(gpf1-7, INPUT, DOWN); + + PIN_SLP(gpf2-0, INPUT, DOWN); + PIN_SLP(gpf2-1, INPUT, DOWN); + PIN_SLP(gpf2-2, INPUT, DOWN); + PIN_SLP(gpf2-3, INPUT, DOWN); + PIN_SLP(gpf2-4, INPUT, DOWN); + PIN_SLP(gpf2-5, INPUT, DOWN); + PIN_SLP(gpf2-6, INPUT, DOWN); + PIN_SLP(gpf2-7, INPUT, DOWN); + + PIN_SLP(gpf3-0, INPUT, DOWN); + PIN_SLP(gpf3-1, INPUT, DOWN); + PIN_SLP(gpf3-2, INPUT, DOWN); + PIN_SLP(gpf3-3, INPUT, DOWN); + PIN_SLP(gpf3-4, PREV, NONE); + PIN_SLP(gpf3-5, OUT0, DOWN); + + PIN_SLP(gpj0-0, INPUT, DOWN); + PIN_SLP(gpj0-1, INPUT, DOWN); + PIN_SLP(gpj0-2, INPUT, DOWN); + PIN_SLP(gpj0-3, OUT0, NONE); + PIN_SLP(gpj0-4, INPUT, DOWN); + PIN_SLP(gpj0-5, INPUT, DOWN); + PIN_SLP(gpj0-6, OUT0, NONE); + PIN_SLP(gpj0-7, OUT0, NONE); + + PIN_SLP(gpj1-0, OUT0, NONE); + PIN_SLP(gpj1-1, INPUT, DOWN); + PIN_SLP(gpj1-2, PREV, NONE); + PIN_SLP(gpj1-3, INPUT, DOWN); + PIN_SLP(gpj1-4, INPUT, DOWN); + }; +}; + +&pinctrl_1 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep1>; + + bt_shutdown: bt-shutdown-pins { + samsung,pins = "gpl0-6"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + bt_host_wakeup: bt-host-wakeup-pins { + samsung,pins = "gpx2-6"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + bt_device_wakeup: bt-device-wakeup-pins { + samsung,pins = "gpx3-1"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + backlight_reset: backlight-reset-pins { + samsung,pins = "gpm0-1"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + gpio_keys: gpio-keys-pins { + samsung,pins = "gpx1-2", "gpx2-2", "gpx2-4", "gpx2-7", "gpx3-3"; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + }; + + max77693_irq: max77693-irq-pins { + samsung,pins = "gpx1-5"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + max77693_fuel_irq: max77693-fuel-irq-pins { + samsung,pins = "gpx2-3"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + sdhci2_cd: sdhci2-cd-irq-pins { + samsung,pins = "gpx3-4"; + samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + s5m8767_dvs: s5m8767-dvs-pins { + samsung,pins = "gpm3-0", "gpm3-1", "gpm3-2"; + samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + s5m8767_irq: s5m8767-irq-pins { + samsung,pins = "gpx0-7"; + samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>; + samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>; + samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>; + }; + + sleep1: sleep-state { + PIN_SLP(gpk0-0, PREV, NONE); + PIN_SLP(gpk0-1, PREV, NONE); + PIN_SLP(gpk0-2, PREV, NONE); + PIN_SLP(gpk0-3, PREV, NONE); + PIN_SLP(gpk0-4, PREV, NONE); + PIN_SLP(gpk0-5, PREV, NONE); + PIN_SLP(gpk0-6, PREV, NONE); + + PIN_SLP(gpk1-0, INPUT, DOWN); + PIN_SLP(gpk1-1, INPUT, DOWN); + PIN_SLP(gpk1-2, INPUT, DOWN); + PIN_SLP(gpk1-3, PREV, NONE); + PIN_SLP(gpk1-4, PREV, NONE); + PIN_SLP(gpk1-5, PREV, NONE); + PIN_SLP(gpk1-6, PREV, NONE); + + PIN_SLP(gpk2-0, INPUT, DOWN); + PIN_SLP(gpk2-1, INPUT, DOWN); + PIN_SLP(gpk2-2, INPUT, DOWN); + PIN_SLP(gpk2-3, INPUT, DOWN); + PIN_SLP(gpk2-4, INPUT, DOWN); + PIN_SLP(gpk2-5, INPUT, DOWN); + PIN_SLP(gpk2-6, INPUT, DOWN); + + PIN_SLP(gpk3-0, OUT0, NONE); + PIN_SLP(gpk3-1, INPUT, NONE); + PIN_SLP(gpk3-2, INPUT, DOWN); + PIN_SLP(gpk3-3, INPUT, NONE); + PIN_SLP(gpk3-4, INPUT, NONE); + PIN_SLP(gpk3-5, INPUT, NONE); + PIN_SLP(gpk3-6, INPUT, NONE); + + PIN_SLP(gpl0-0, INPUT, DOWN); + PIN_SLP(gpl0-1, INPUT, NONE); + PIN_SLP(gpl0-2, INPUT, NONE); + PIN_SLP(gpl0-3, INPUT, DOWN); + PIN_SLP(gpl0-4, INPUT, DOWN); + PIN_SLP(gpl0-6, PREV, NONE); + + PIN_SLP(gpl1-0, INPUT, DOWN); + PIN_SLP(gpl1-1, OUT0, NONE); + PIN_SLP(gpl2-0, INPUT, DOWN); + PIN_SLP(gpl2-1, PREV, NONE); + PIN_SLP(gpl2-2, PREV, NONE); + PIN_SLP(gpl2-3, INPUT, DOWN); + PIN_SLP(gpl2-4, INPUT, DOWN); + PIN_SLP(gpl2-5, INPUT, DOWN); + PIN_SLP(gpl2-6, INPUT, DOWN); + PIN_SLP(gpl2-7, INPUT, DOWN); + + PIN_SLP(gpm0-0, PREV, NONE); + PIN_SLP(gpm0-1, OUT0, NONE); + PIN_SLP(gpm0-2, INPUT, DOWN); + PIN_SLP(gpm0-3, INPUT, DOWN); + PIN_SLP(gpm0-4, INPUT, DOWN); + PIN_SLP(gpm0-5, INPUT, DOWN); + PIN_SLP(gpm0-6, INPUT, DOWN); + PIN_SLP(gpm0-7, INPUT, DOWN); + + PIN_SLP(gpm1-0, INPUT, DOWN); + PIN_SLP(gpm1-1, INPUT, DOWN); + PIN_SLP(gpm1-2, INPUT, NONE); + PIN_SLP(gpm1-3, INPUT, NONE); + PIN_SLP(gpm1-4, INPUT, NONE); + PIN_SLP(gpm1-5, INPUT, NONE); + PIN_SLP(gpm1-6, OUT0, NONE); + + PIN_SLP(gpm2-0, INPUT, NONE); + PIN_SLP(gpm2-1, INPUT, NONE); + PIN_SLP(gpm2-2, OUT0, NONE); + PIN_SLP(gpm2-3, INPUT, DOWN); + PIN_SLP(gpm2-4, INPUT, DOWN); + + PIN_SLP(gpm3-0, PREV, NONE); + PIN_SLP(gpm3-1, PREV, NONE); + PIN_SLP(gpm3-2, PREV, NONE); + PIN_SLP(gpm3-3, INPUT, DOWN); + PIN_SLP(gpm3-4, INPUT, DOWN); + PIN_SLP(gpm3-5, PREV, NONE); + PIN_SLP(gpm3-6, INPUT, DOWN); + PIN_SLP(gpm3-7, OUT0, NONE); + + PIN_SLP(gpm4-0, INPUT, DOWN); + PIN_SLP(gpm4-1, INPUT, DOWN); + PIN_SLP(gpm4-2, INPUT, DOWN); + PIN_SLP(gpm4-3, INPUT, DOWN); + PIN_SLP(gpm4-4, PREV, NONE); + PIN_SLP(gpm4-5, INPUT, NONE); + PIN_SLP(gpm4-6, INPUT, DOWN); + PIN_SLP(gpm4-7, INPUT, DOWN); + + PIN_SLP(gpy0-0, INPUT, DOWN); + PIN_SLP(gpy0-1, INPUT, DOWN); + PIN_SLP(gpy0-2, INPUT, NONE); + PIN_SLP(gpy0-3, INPUT, NONE); + PIN_SLP(gpy0-4, INPUT, DOWN); + PIN_SLP(gpy0-5, INPUT, DOWN); + + PIN_SLP(gpy1-0, INPUT, DOWN); + PIN_SLP(gpy1-1, INPUT, DOWN); + PIN_SLP(gpy1-2, INPUT, DOWN); + PIN_SLP(gpy1-3, INPUT, DOWN); + + PIN_SLP(gpy2-0, PREV, NONE); + PIN_SLP(gpy2-1, INPUT, DOWN); + PIN_SLP(gpy2-2, INPUT, NONE); + PIN_SLP(gpy2-3, INPUT, NONE); + PIN_SLP(gpy2-4, INPUT, NONE); + PIN_SLP(gpy2-5, INPUT, NONE); + + PIN_SLP(gpy3-0, INPUT, DOWN); + PIN_SLP(gpy3-1, INPUT, DOWN); + PIN_SLP(gpy3-2, INPUT, DOWN); + PIN_SLP(gpy3-3, INPUT, DOWN); + PIN_SLP(gpy3-4, INPUT, DOWN); + PIN_SLP(gpy3-5, INPUT, DOWN); + PIN_SLP(gpy3-6, INPUT, DOWN); + PIN_SLP(gpy3-7, INPUT, DOWN); + + PIN_SLP(gpy4-0, INPUT, DOWN); + PIN_SLP(gpy4-1, INPUT, DOWN); + PIN_SLP(gpy4-2, INPUT, DOWN); + PIN_SLP(gpy4-3, INPUT, DOWN); + PIN_SLP(gpy4-4, INPUT, DOWN); + PIN_SLP(gpy4-5, INPUT, DOWN); + PIN_SLP(gpy4-6, INPUT, DOWN); + PIN_SLP(gpy4-7, INPUT, DOWN); + + PIN_SLP(gpy5-0, INPUT, DOWN); + PIN_SLP(gpy5-1, INPUT, DOWN); + PIN_SLP(gpy5-2, INPUT, DOWN); + PIN_SLP(gpy5-3, INPUT, DOWN); + PIN_SLP(gpy5-4, INPUT, DOWN); + PIN_SLP(gpy5-5, INPUT, DOWN); + PIN_SLP(gpy5-6, INPUT, DOWN); + PIN_SLP(gpy5-7, INPUT, DOWN); + + PIN_SLP(gpy6-0, INPUT, DOWN); + PIN_SLP(gpy6-1, INPUT, DOWN); + PIN_SLP(gpy6-2, INPUT, DOWN); + PIN_SLP(gpy6-3, INPUT, DOWN); + PIN_SLP(gpy6-4, INPUT, DOWN); + PIN_SLP(gpy6-5, INPUT, DOWN); + PIN_SLP(gpy6-6, INPUT, DOWN); + PIN_SLP(gpy6-7, INPUT, DOWN); + }; +}; + +&pinctrl_2 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep2>; + + sleep2: sleep-state { + PIN_SLP(gpz-0, INPUT, DOWN); + PIN_SLP(gpz-1, INPUT, DOWN); + PIN_SLP(gpz-2, INPUT, DOWN); + PIN_SLP(gpz-3, INPUT, DOWN); + PIN_SLP(gpz-4, INPUT, DOWN); + PIN_SLP(gpz-5, INPUT, DOWN); + PIN_SLP(gpz-6, INPUT, DOWN); + }; +}; + +&pinctrl_3 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep3>; + + sleep3: sleep-state { + PIN_SLP(gpv0-0, INPUT, DOWN); + PIN_SLP(gpv0-1, INPUT, DOWN); + PIN_SLP(gpv0-2, INPUT, DOWN); + PIN_SLP(gpv0-3, INPUT, DOWN); + PIN_SLP(gpv0-4, INPUT, DOWN); + PIN_SLP(gpv0-5, INPUT, DOWN); + PIN_SLP(gpv0-6, INPUT, DOWN); + PIN_SLP(gpv0-7, INPUT, DOWN); + + PIN_SLP(gpv1-0, INPUT, DOWN); + PIN_SLP(gpv1-1, INPUT, DOWN); + PIN_SLP(gpv1-2, INPUT, DOWN); + PIN_SLP(gpv1-3, INPUT, DOWN); + PIN_SLP(gpv1-4, INPUT, DOWN); + PIN_SLP(gpv1-5, INPUT, DOWN); + PIN_SLP(gpv1-6, INPUT, DOWN); + PIN_SLP(gpv1-7, INPUT, DOWN); + + PIN_SLP(gpv2-0, INPUT, DOWN); + PIN_SLP(gpv2-1, INPUT, DOWN); + PIN_SLP(gpv2-2, INPUT, DOWN); + PIN_SLP(gpv2-3, INPUT, DOWN); + PIN_SLP(gpv2-4, INPUT, DOWN); + PIN_SLP(gpv2-5, INPUT, DOWN); + PIN_SLP(gpv2-6, INPUT, DOWN); + PIN_SLP(gpv2-7, INPUT, DOWN); + + PIN_SLP(gpv3-0, INPUT, DOWN); + PIN_SLP(gpv3-1, INPUT, DOWN); + PIN_SLP(gpv3-2, INPUT, DOWN); + PIN_SLP(gpv3-3, INPUT, DOWN); + PIN_SLP(gpv3-4, INPUT, DOWN); + PIN_SLP(gpv3-5, INPUT, DOWN); + PIN_SLP(gpv3-6, INPUT, DOWN); + PIN_SLP(gpv3-7, INPUT, DOWN); + + PIN_SLP(gpv4-0, INPUT, DOWN); + PIN_SLP(gpv4-1, INPUT, DOWN); + }; +}; + +&pmu_system_controller { + assigned-clocks = <&pmu_system_controller 0>; + assigned-clock-parents = <&clock CLK_XUSBXTI>; +}; + +&pwm { + pinctrl-0 = <&pwm1_out>; + pinctrl-names = "default"; + samsung,pwm-outputs = <1>; + status = "okay"; +}; + +/* + * The internal RTC does not work; instead, the RTC provided by the + * S5M8766 PMIC is used. Disable the RTC to make sure the working + * one gets used. + * + * We add this node to avoid DTB check warnings, as the Exynos4 RTC + * requires two clocks, and only one is set up by default. + */ +&rtc { + clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; + status = "disabled"; +}; + +&sdhci_2 { + bus-width = <4>; + cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sdhci2_cd>; + pinctrl-names = "default"; + vmmc-supply = <&ldo23_reg>; + status = "okay"; +}; + +&sdhci_3 { + #address-cells = <1>; + #size-cells = <0>; + non-removable; + bus-width = <4>; + + mmc-pwrseq = <&wlan_pwrseq>; + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&serial_0 { + pinctrl-0 = <&uart0_data &uart0_fctl>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; /* BCM4334B0 */ + pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; + pinctrl-names = "default"; + max-speed = <3000000>; + shutdown-gpios = <&gpl0 6 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + clocks = <&s5m8767_osc S2MPS11_CLK_BT>; + }; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&tmu { + vtmu-supply = <&ldo10_reg>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi b/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi index e6b949c1a00f..7daf25865551 100644 --- a/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/samsung/exynos4412-midas.dtsi @@ -182,6 +182,38 @@ pinctrl-0 = <&max77693_irq>; reg = <0x66>; + muic { + compatible = "maxim,max77693-muic"; + + connector { + compatible = "samsung,usb-connector-11pin", + "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + muic_to_usb: endpoint { + remote-endpoint = <&usb_to_muic>; + }; + }; + + port@3 { + reg = <3>; + + muic_to_mhl: endpoint { + remote-endpoint = <&mhl_to_muic>; + }; + }; + }; + }; + }; + regulators { esafeout1_reg: ESAFEOUT1 { regulator-name = "ESAFEOUT1"; @@ -287,6 +319,14 @@ remote-endpoint = <&hdmi_to_mhl>; }; }; + + port@1 { + reg = <1>; + + mhl_to_muic: endpoint { + remote-endpoint = <&muic_to_mhl>; + }; + }; }; }; }; @@ -545,8 +585,16 @@ &hsotg { vusb_d-supply = <&ldo15_reg>; vusb_a-supply = <&ldo12_reg>; - dr_mode = "peripheral"; + dr_mode = "otg"; + role-switch-default-mode = "peripheral"; + usb-role-switch; status = "okay"; + + port { + usb_to_muic: endpoint { + remote-endpoint = <&muic_to_usb>; + }; + }; }; &i2c_0 { @@ -990,7 +1038,7 @@ &pmu_system_controller { assigned-clocks = <&pmu_system_controller 0>; - assigned-clock-parents = <&clock CLK_XUSBXTI>; + assigned-clock-parents = <&clock CLK_XUSBXTI>; }; &pinctrl_0 { diff --git a/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi index c82e2762e07c..65b000df176e 100644 --- a/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/samsung/exynos5250-snow-common.dtsi @@ -60,12 +60,9 @@ i2c-arbitrator { compatible = "i2c-arb-gpio-challenge"; - #address-cells = <1>; - #size-cells = <0>; - i2c-parent = <&i2c_4>; - our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>; + our-claim-gpios = <&gpf0 3 GPIO_ACTIVE_LOW>; their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; slew-delay-us = <10>; wait-retry-us = <3000>; @@ -75,8 +72,7 @@ pinctrl-0 = <&arb_our_claim &arb_their_claim>; /* Use ID 104 as a hint that we're on physical bus 4 */ - i2c_104: i2c@0 { - reg = <0>; + i2c_104: i2c-arb { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/samsung/s3c6410-mini6410.dts b/arch/arm/boot/dts/samsung/s3c6410-mini6410.dts index 17097da36f5e..0b07b3c31960 100644 --- a/arch/arm/boot/dts/samsung/s3c6410-mini6410.dts +++ b/arch/arm/boot/dts/samsung/s3c6410-mini6410.dts @@ -51,7 +51,7 @@ ethernet@18000000 { compatible = "davicom,dm9000"; - reg = <0x18000000 0x2 0x18000004 0x2>; + reg = <0x18000000 0x2>, <0x18000004 0x2>; interrupt-parent = <&gpn>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; davicom,no-eeprom; diff --git a/arch/arm/boot/dts/samsung/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/samsung/s5pv210-pinctrl.dtsi index af740abd9e0f..6ecdd504e5f4 100644 --- a/arch/arm/boot/dts/samsung/s5pv210-pinctrl.dtsi +++ b/arch/arm/boot/dts/samsung/s5pv210-pinctrl.dtsi @@ -832,12 +832,12 @@ }; lcd_data24: lcd-data-width24-pins { - samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", - "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", - "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", - "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", - "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", - "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; + samsung,pins = "gpf0-4", "gpf0-5", "gpf0-6", "gpf0-7", + "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3", + "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7", + "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", + "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; samsung,pin-function = <S5PV210_PIN_FUNC_2>; samsung,pin-pud = <S5PV210_PIN_PULL_NONE>; samsung,pin-drv = <S5PV210_PIN_DRV_LV1>; diff --git a/arch/arm/boot/dts/samsung/s5pv210-smdkv210.dts b/arch/arm/boot/dts/samsung/s5pv210-smdkv210.dts index 6e26c67e0a26..901e7197b136 100644 --- a/arch/arm/boot/dts/samsung/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/samsung/s5pv210-smdkv210.dts @@ -41,7 +41,7 @@ ethernet@a8000000 { compatible = "davicom,dm9000"; - reg = <0xA8000000 0x2 0xA8000002 0x2>; + reg = <0xa8000000 0x2>, <0xa8000002 0x2>; interrupt-parent = <&gph1>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; local-mac-address = [00 00 de ad be ef]; diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index b3e9d29390e3..44b264c399ec 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -56,6 +56,8 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-ev1.dtb \ stm32mp157c-ev1-scmi.dtb \ stm32mp157c-lxa-mc1.dtb \ + stm32mp157c-lxa-tac-gen1.dtb \ + stm32mp157c-lxa-tac-gen2.dtb \ stm32mp157c-odyssey.dtb \ stm32mp157c-phycore-stm32mp1-3.dtb dtb-$(CONFIG_ARCH_U8500) += \ diff --git a/arch/arm/boot/dts/st/spear1340.dtsi b/arch/arm/boot/dts/st/spear1340.dtsi index d54e10629a7d..51f6ffd08b42 100644 --- a/arch/arm/boot/dts/st/spear1340.dtsi +++ b/arch/arm/boot/dts/st/spear1340.dtsi @@ -63,8 +63,8 @@ compatible = "snps,designware-i2s"; reg = <0xb2400000 0x10000>; interrupt-names = "play_irq"; - interrupts = <0 98 0x4 - 0 99 0x4>; + interrupts = <0 98 0x4>, + <0 99 0x4>; play; channel = <8>; status = "disabled"; @@ -74,8 +74,8 @@ compatible = "snps,designware-i2s"; reg = <0xb2000000 0x10000>; interrupt-names = "record_irq"; - interrupts = <0 100 0x4 - 0 101 0x4>; + interrupts = <0 100 0x4>, + <0 101 0x4>; record; channel = <8>; status = "disabled"; diff --git a/arch/arm/boot/dts/st/spear13xx.dtsi b/arch/arm/boot/dts/st/spear13xx.dtsi index 913553367687..3b6897084e26 100644 --- a/arch/arm/boot/dts/st/spear13xx.dtsi +++ b/arch/arm/boot/dts/st/spear13xx.dtsi @@ -39,8 +39,8 @@ pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 6 0x04 - 0 7 0x04>; + interrupts = <0 6 0x04>, + <0 7 0x04>; }; L2: cache-controller { @@ -141,10 +141,10 @@ 0xb0820000 0x0010 /* NAND Base ADDR */ 0xb0810000 0x0010>; /* NAND Base CMD */ reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; - interrupts = <0 20 0x4 - 0 21 0x4 - 0 22 0x4 - 0 23 0x4>; + interrupts = <0 20 0x4>, + <0 21 0x4>, + <0 22 0x4>, + <0 23 0x4>; st,mode = <2>; status = "disabled"; }; @@ -152,8 +152,8 @@ gmac0: eth@e2000000 { compatible = "st,spear600-gmac"; reg = <0xe2000000 0x8000>; - interrupts = <0 33 0x4 - 0 34 0x4>; + interrupts = <0 33 0x4>, + <0 34 0x4>; interrupt-names = "macirq", "eth_wake_irq"; status = "disabled"; }; @@ -263,8 +263,8 @@ compatible = "st,designware-i2s"; reg = <0xe0180000 0x1000>; interrupt-names = "play_irq", "record_irq"; - interrupts = <0 10 0x4 - 0 11 0x4 >; + interrupts = <0 10 0x4>, + <0 11 0x4>; status = "disabled"; }; @@ -272,8 +272,8 @@ compatible = "st,designware-i2s"; reg = <0xe0200000 0x1000>; interrupt-names = "play_irq", "record_irq"; - interrupts = <0 26 0x4 - 0 53 0x4>; + interrupts = <0 26 0x4>, + <0 53 0x4>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi index 9f65403295ca..65480a9f5cc4 100644 --- a/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32f7-pinctrl.dtsi @@ -171,6 +171,16 @@ }; }; + i2c3_pins_a: i2c3-0 { + pins { + pinmux = <STM32_PINMUX('H', 8, AF4)>, /* I2C3_SDA */ + <STM32_PINMUX('H', 7, AF4)>; /* I2C3_SCL */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = <STM32_PINMUX('H', 4, AF10)>, /* OTG_HS_ULPI_NXT */ @@ -365,6 +375,41 @@ bias-pull-up; }; }; + + + ltdc_pins_a: ltdc-0 { + pins { + pinmux = <STM32_PINMUX('E', 4, AF14)>, /* LCD_B0 */ + <STM32_PINMUX('G',12, AF9)>, /* LCD_B4 */ + <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ + <STM32_PINMUX('I',10, AF14)>, /* LCD_HSYNC */ + <STM32_PINMUX('I',14, AF14)>, /* LCD_CLK */ + <STM32_PINMUX('I',15, AF14)>, /* LCD_R0 */ + <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ + <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ + <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ + <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ + <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ + <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */ + <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ + <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ + <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ + <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ + <STM32_PINMUX('J',10, AF14)>, /* LCD_G3 */ + <STM32_PINMUX('J',11, AF14)>, /* LCD_G4 */ + <STM32_PINMUX('J',13, AF14)>, /* LCD_B1 */ + <STM32_PINMUX('J',14, AF14)>, /* LCD_B2 */ + <STM32_PINMUX('J',15, AF14)>, /* LCD_B3 */ + <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ + <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ + <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ + <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ + <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ + <STM32_PINMUX('K', 6, AF14)>, /* LCD_B7 */ + <STM32_PINMUX('K', 7, AF14)>; /* LCD_DE */ + slew-rate = <2>; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/st/stm32f746-disco.dts b/arch/arm/boot/dts/st/stm32f746-disco.dts index c11616ed5fc6..37e3a905fc3c 100644 --- a/arch/arm/boot/dts/st/stm32f746-disco.dts +++ b/arch/arm/boot/dts/st/stm32f746-disco.dts @@ -43,8 +43,9 @@ /dts-v1/; #include "stm32f746.dtsi" #include "stm32f746-pinctrl.dtsi" -#include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> / { model = "STMicroelectronics STM32F746-DISCO board"; @@ -60,6 +61,19 @@ reg = <0xC0000000 0x800000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + no-map; + size = <0x80000>; + linux,dma-default; + }; + }; + aliases { serial0 = &usart1; }; @@ -79,12 +93,31 @@ regulator-always-on; }; - mmc_vcard: mmc_vcard { + vcc_3v3: vcc-3v3 { compatible = "regulator-fixed"; - regulator-name = "mmc_vcard"; + regulator-name = "vcc_3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpiok 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + panel_rgb: panel-rgb { + compatible = "rocktech,rk043fn48h"; + power-supply = <&vcc_3v3>; + backlight = <&backlight>; + enable-gpios = <&gpioi 12 GPIO_ACTIVE_HIGH>; + status = "okay"; + port { + panel_in_rgb: endpoint { + remote-endpoint = <<dc_out_rgb>; + }; + }; + }; }; &clk_hse { @@ -99,9 +132,37 @@ status = "okay"; }; +&i2c3 { + pinctrl-0 = <&i2c3_pins_a>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5306"; + reg = <0x38>; + interrupt-parent = <&gpioi>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <480>; + touchscreen-size-y = <272>; + }; +}; + +<dc { + pinctrl-0 = <<dc_pins_a>; + pinctrl-names = "default"; + status = "okay"; + + port { + ltdc_out_rgb: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; +}; + &sdio1 { status = "okay"; - vmmc-supply = <&mmc_vcard>; + vmmc-supply = <&vcc_3v3>; cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; pinctrl-names = "default", "opendrain"; pinctrl-0 = <&sdio_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi index 781197ef42d6..139f72b790c0 100644 --- a/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32f746-pinctrl.dtsi @@ -8,4 +8,48 @@ &pinctrl { compatible = "st,stm32f746-pinctrl"; + + gpioa: gpio@40020000 { + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@40020400 { + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@40020800 { + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@40020c00 { + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@40021000 { + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@40021400 { + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@40021800 { + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@40021c00 { + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@40022000 { + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@40022400 { + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@40022800 { + gpio-ranges = <&pinctrl 0 160 8>; + }; }; diff --git a/arch/arm/boot/dts/st/stm32f746.dtsi b/arch/arm/boot/dts/st/stm32f746.dtsi index d1802efd067c..53a8e2dec9a4 100644 --- a/arch/arm/boot/dts/st/stm32f746.dtsi +++ b/arch/arm/boot/dts/st/stm32f746.dtsi @@ -257,6 +257,23 @@ status = "disabled"; }; + can3: can@40003400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40003400 0x200>; + interrupts = <104>, <105>, <106>, <107>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F7_APB1_RESET(CAN3)>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; + st,gcan = <&gcan3>; + status = "disabled"; + }; + + gcan3: gcan@40003600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40003600 0x200>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN3)>; + }; + usart2: serial@40004400 { compatible = "st,stm32f7-uart"; reg = <0x40004400 0x400>; @@ -337,6 +354,36 @@ status = "disabled"; }; + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F7_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; + st,can-primary; + st,gcan = <&gcan1>; + status = "disabled"; + }; + + gcan1: gcan@40006600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40006600 0x200>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN1)>; + }; + + can2: can@40006800 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006800 0x200>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F7_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F7_APB1_CLOCK(CAN2)>; + st,can-secondary; + st,gcan = <&gcan1>; + status = "disabled"; + }; + cec: cec@40006c00 { compatible = "st,stm32-cec"; reg = <0x40006C00 0x400>; @@ -507,6 +554,16 @@ }; }; + ltdc: display-controller@40016800 { + compatible = "st,stm32-ltdc"; + reg = <0x40016800 0x200>; + interrupts = <88>, <89>; + resets = <&rcc STM32F7_APB2_RESET(LTDC)>; + clocks = <&rcc 1 CLK_LCD>; + clock-names = "lcd"; + status = "disabled"; + }; + pwrcfg: power-config@40007000 { compatible = "st,stm32-power-config", "syscon"; reg = <0x40007000 0x400>; diff --git a/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi index c26abc04e2ce..02c2a8b08468 100644 --- a/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32f769-pinctrl.dtsi @@ -8,4 +8,48 @@ &pinctrl { compatible = "st,stm32f769-pinctrl"; + + gpioa: gpio@40020000 { + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@40020400 { + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@40020800 { + gpio-ranges = <&pinctrl 0 32 16>; + }; + + gpiod: gpio@40020c00 { + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@40021000 { + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@40021400 { + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@40021800 { + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@40021c00 { + gpio-ranges = <&pinctrl 0 112 16>; + }; + + gpioi: gpio@40022000 { + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@40022400 { + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@40022800 { + gpio-ranges = <&pinctrl 0 160 8>; + }; }; diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index d163c267e34c..ac90fcbf0c09 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -33,6 +33,8 @@ optee { method = "smc"; compatible = "linaro,optee-tz"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; scmi: scmi { @@ -40,7 +42,6 @@ #address-cells = <1>; #size-cells = <0>; linaro,optee-channel-id = <0>; - shmem = <&scmi_shm>; scmi_clk: protocol@14 { reg = <0x14>; @@ -51,6 +52,28 @@ reg = <0x16>; #reset-cells = <1>; }; + + scmi_voltd: protocol@17 { + reg = <0x17>; + + scmi_regu: regulators { + #address-cells = <1>; + #size-cells = <0>; + + scmi_reg11: regulator@0 { + reg = <VOLTD_SCMI_REG11>; + regulator-name = "reg11"; + }; + scmi_reg18: regulator@1 { + reg = <VOLTD_SCMI_REG18>; + regulator-name = "reg18"; + }; + scmi_usb33: regulator@2 { + reg = <VOLTD_SCMI_USB33>; + regulator-name = "usb33"; + }; + }; + }; }; }; @@ -77,28 +100,6 @@ always-on; }; - /* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */ - reg11: reg11 { - compatible = "regulator-fixed"; - regulator-name = "reg11"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - }; - - reg18: reg18 { - compatible = "regulator-fixed"; - regulator-name = "reg18"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - usb33: usb33 { - compatible = "regulator-fixed"; - regulator-name = "usb33"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - soc { compatible = "simple-bus"; #address-cells = <1>; @@ -106,19 +107,6 @@ interrupt-parent = <&intc>; ranges; - scmi_sram: sram@2ffff000 { - compatible = "mmio-sram"; - reg = <0x2ffff000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2ffff000 0x1000>; - - scmi_shm: scmi-sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0 0x80>; - }; - }; - timers2: timer@40000000 { #address-cells = <1>; #size-cells = <0>; @@ -813,7 +801,7 @@ g-tx-fifo-size = <256 16 16 16 16 16 16 16>; dr_mode = "otg"; otg-rev = <0x200>; - usb33d-supply = <&usb33>; + usb33d-supply = <&scmi_usb33>; status = "disabled"; }; @@ -1343,8 +1331,8 @@ reg = <0x5a006000 0x1000>; clocks = <&rcc USBPHY_K>; resets = <&rcc USBPHY_R>; - vdda1v1-supply = <®11>; - vdda1v8-supply = <®18>; + vdda1v1-supply = <&scmi_reg11>; + vdda1v8-supply = <&scmi_reg18>; status = "disabled"; usbphyc_port0: usb-phy@0 { diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index f0900ca672b5..eea740d097c7 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -9,6 +9,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> +#include <dt-bindings/regulator/st,stm32mp13-regulator.h> #include "stm32mp135.dtsi" #include "stm32mp13xf.dtsi" #include "stm32mp13-pinctrl.dtsi" @@ -65,45 +66,13 @@ default-state = "off"; }; }; - - v3v3_sw: v3v3-sw { - compatible = "regulator-fixed"; - regulator-name = "v3v3_sw"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_adc: vdd-adc { - compatible = "regulator-fixed"; - regulator-name = "vdd_adc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_sd: vdd-sd { - compatible = "regulator-fixed"; - regulator-name = "vdd_sd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; - regulator-always-on; - }; - - vdd_usb: vdd-usb { - compatible = "regulator-fixed"; - regulator-name = "vdd_usb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; }; &adc_1 { pinctrl-names = "default"; pinctrl-0 = <&adc1_usb_cc_pins_a>; - vdda-supply = <&vdd_adc>; - vref-supply = <&vdd_adc>; + vdda-supply = <&scmi_vdd_adc>; + vref-supply = <&scmi_vdd_adc>; status = "okay"; adc1: adc@0 { status = "okay"; @@ -195,6 +164,29 @@ status = "okay"; }; +&scmi_regu { + scmi_vdd_adc: regulator@10 { + reg = <VOLTD_SCMI_STPMIC1_LDO1>; + regulator-name = "vdd_adc"; + }; + scmi_vdd_usb: regulator@13 { + reg = <VOLTD_SCMI_STPMIC1_LDO4>; + regulator-name = "vdd_usb"; + }; + scmi_vdd_sd: regulator@14 { + reg = <VOLTD_SCMI_STPMIC1_LDO5>; + regulator-name = "vdd_sd"; + }; + scmi_v1v8_periph: regulator@15 { + reg = <VOLTD_SCMI_STPMIC1_LDO6>; + regulator-name = "v1v8_periph"; + }; + scmi_v3v3_sw: regulator@19 { + reg = <VOLTD_SCMI_STPMIC1_PWR_SW2>; + regulator-name = "v3v3_sw"; + }; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; @@ -204,7 +196,7 @@ disable-wp; st,neg-edge; bus-width = <4>; - vmmc-supply = <&vdd_sd>; + vmmc-supply = <&scmi_vdd_sd>; status = "okay"; }; @@ -321,7 +313,7 @@ hub@1 { compatible = "usb424,2514"; reg = <1>; - vdd-supply = <&v3v3_sw>; + vdd-supply = <&scmi_v3v3_sw>; }; }; @@ -342,7 +334,7 @@ }; &usbphyc_port0 { - phy-supply = <&vdd_usb>; + phy-supply = <&scmi_vdd_usb>; st,current-boost-microamp = <1000>; st,decrease-hs-slew-rate; st,tune-hs-dc-level = <2>; @@ -356,7 +348,7 @@ }; &usbphyc_port1 { - phy-supply = <&vdd_usb>; + phy-supply = <&scmi_vdd_usb>; st,current-boost-microamp = <1000>; st,decrease-hs-slew-rate; st,tune-hs-dc-level = <2>; diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi index 05c9c4f8064c..098153ee99a3 100644 --- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi @@ -6,6 +6,17 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { + adc1_ain_pins_a: adc1-ain-0 { + pins { + pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* ADC1_INP2 */ + <STM32_PINMUX('B', 1, ANALOG)>, /* ADC1_INP5 */ + <STM32_PINMUX('B', 0, ANALOG)>, /* ADC1_INP9 */ + <STM32_PINMUX('C', 0, ANALOG)>, /* ADC1_INP10 */ + <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1_INP13 */ + <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1_INP15 */ + }; + }; + adc1_in6_pins_a: adc1-in6-0 { pins { pinmux = <STM32_PINMUX('F', 12, ANALOG)>; @@ -391,6 +402,46 @@ }; }; + ethernet0_rgmii_pins_e: rgmii-4 { + pins1 { + pinmux = <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, AF11)>; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ + <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_e: rgmii-sleep-4 { + pins1 { + pinmux = <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ + <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ + }; + }; + ethernet0_rmii_pins_a: rmii-0 { pins1 { pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ @@ -1154,6 +1205,20 @@ }; }; + pwm1_pins_c: pwm1-2 { + pins { + pinmux = <STM32_PINMUX('E', 11, AF1)>; /* TIM1_CH2 */ + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_sleep_pins_c: pwm1-sleep-2 { + pins { + pinmux = <STM32_PINMUX('E', 11, ANALOG)>; /* TIM1_CH2 */ + }; + }; + pwm2_pins_a: pwm2-0 { pins { pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ @@ -1280,6 +1345,26 @@ }; }; + pwm8_pins_b: pwm8-1 { + pins { + pinmux = <STM32_PINMUX('I', 5, AF3)>, /* TIM8_CH1 */ + <STM32_PINMUX('I', 6, AF3)>, /* TIM8_CH2 */ + <STM32_PINMUX('I', 7, AF3)>, /* TIM8_CH3 */ + <STM32_PINMUX('C', 9, AF3)>; /* TIM8_CH4 */ + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm8_sleep_pins_b: pwm8-sleep-1 { + pins { + pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* TIM8_CH1 */ + <STM32_PINMUX('I', 6, ANALOG)>, /* TIM8_CH2 */ + <STM32_PINMUX('I', 7, ANALOG)>, /* TIM8_CH3 */ + <STM32_PINMUX('C', 9, ANALOG)>; /* TIM8_CH4 */ + }; + }; + pwm12_pins_a: pwm12-0 { pins { pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */ @@ -2074,6 +2159,20 @@ }; }; + spi2_pins_c: spi2-2 { + pins1 { + pinmux = <STM32_PINMUX('I', 1, AF5)>, /* SPI2_SCK */ + <STM32_PINMUX('I', 3, AF5)>; /* SPI2_MOSI */ + bias-disable; + drive-push-pull; + }; + + pins2 { + pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI2_MISO */ + bias-pull-down; + }; + }; + spi4_pins_a: spi4-0 { pins { pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */ @@ -2088,6 +2187,21 @@ }; }; + spi5_pins_a: spi5-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, AF5)>, /* SPI5_SCK */ + <STM32_PINMUX('F', 9, AF5)>; /* SPI5_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('F', 8, AF5)>; /* SPI5_MISO */ + bias-disable; + }; + }; + stusb1600_pins_a: stusb1600-0 { pins { pinmux = <STM32_PINMUX('I', 11, GPIO)>; @@ -2578,6 +2692,21 @@ }; }; + usart3_pins_f: usart3-5 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ + <STM32_PINMUX('D', 12, AF7)>; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ + <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ + bias-disable; + }; + }; + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ diff --git a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi index 543f24c2f4f6..dc3b09f2f2af 100644 --- a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi @@ -16,7 +16,6 @@ #address-cells = <1>; #size-cells = <0>; linaro,optee-channel-id = <0>; - shmem = <&scmi_shm>; scmi_clk: protocol@14 { reg = <0x14>; @@ -35,22 +34,21 @@ #address-cells = <1>; #size-cells = <0>; - scmi_reg11: reg11@0 { + scmi_reg11: regulator@0 { reg = <0>; regulator-name = "reg11"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; }; - scmi_reg18: reg18@1 { - voltd-name = "reg18"; + scmi_reg18: regulator@1 { reg = <1>; regulator-name = "reg18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; - scmi_usb33: usb33@2 { + scmi_usb33: regulator@2 { reg = <2>; regulator-name = "usb33"; regulator-min-microvolt = <3300000>; @@ -60,21 +58,6 @@ }; }; }; - - soc { - scmi_sram: sram@2ffff000 { - compatible = "mmio-sram"; - reg = <0x2ffff000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x2ffff000 0x1000>; - - scmi_shm: scmi-sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0 0x80>; - }; - }; - }; }; ®11 { diff --git a/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts b/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts index 7ecf31263abc..c90d815f906b 100644 --- a/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts +++ b/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts @@ -23,6 +23,18 @@ clock-frequency = <25000000>; }; + pse_t1l1: ethernet-pse-1 { + compatible = "podl-pse-regulator"; + pse-supply = <®_t1l1>; + #pse-cells = <0>; + }; + + pse_t1l2: ethernet-pse-2 { + compatible = "podl-pse-regulator"; + pse-supply = <®_t1l2>; + #pse-cells = <0>; + }; + mdio0: mdio { compatible = "virtual,mdio-gpio"; #address-cells = <1>; @@ -32,6 +44,24 @@ }; + reg_t1l1: regulator-pse-t1l1 { + compatible = "regulator-fixed"; + regulator-name = "pse-t1l1"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpiog 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_t1l2: regulator-pse-t1l2 { + compatible = "regulator-fixed"; + regulator-name = "pse-t1l2"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpiog 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + wifi_pwrseq: wifi-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpiod 8 GPIO_ACTIVE_LOW>; @@ -92,6 +122,7 @@ reset-gpios = <&gpiog 12 GPIO_ACTIVE_LOW>; reset-assert-us = <10>; reset-deassert-us = <35>; + pses = <&pse_t1l1>; }; /* TI DP83TD510E */ @@ -102,6 +133,7 @@ reset-gpios = <&gpiog 11 GPIO_ACTIVE_LOW>; reset-assert-us = <10>; reset-deassert-us = <35>; + pses = <&pse_t1l2>; }; /* Micrel KSZ9031 */ diff --git a/arch/arm/boot/dts/st/stm32mp157.dtsi b/arch/arm/boot/dts/st/stm32mp157.dtsi index 5e733cd16ff9..6197d878894d 100644 --- a/arch/arm/boot/dts/st/stm32mp157.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157.dtsi @@ -22,9 +22,27 @@ reg = <0x5a000000 0x800>; clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; clock-names = "pclk", "ref", "px_clk"; + phy-dsi-supply = <®18>; resets = <&rcc DSI_R>; reset-names = "apb"; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi_out: endpoint { + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts index 4279b26547df..df97e03d2a5a 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts @@ -46,26 +46,14 @@ &dsi { status = "okay"; - phy-dsi-supply = <®18>; - - ports { - #address-cells = <1>; - #size-cells = <0>; +}; - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; +&dsi_in { + remote-endpoint = <<dc_ep0_out>; +}; - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&bridge_in>; - }; - }; - }; +&dsi_out { + remote-endpoint = <&bridge_in>; }; &i2c6 { diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts index efba54289820..f8e404346396 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts @@ -46,26 +46,14 @@ &dsi { status = "okay"; - phy-dsi-supply = <®18>; - - ports { - #address-cells = <1>; - #size-cells = <0>; +}; - port@0 { - reg = <0>; - dsi_in_ltdc: endpoint { - remote-endpoint = <<dc_out_dsi>; - }; - }; +&dsi_in { + remote-endpoint = <<dc_out_dsi>; +}; - port@1 { - reg = <1>; - dsi_out_bridge: endpoint { - remote-endpoint = <&bridge_in_dsi>; - }; - }; - }; +&dsi_out { + remote-endpoint = <&bridge_in_dsi>; }; &i2c6 { @@ -88,7 +76,7 @@ port@0 { reg = <0>; bridge_in_dsi: endpoint { - remote-endpoint = <&dsi_out_bridge>; + remote-endpoint = <&dsi_out>; data-lanes = <1 2>; }; }; @@ -108,7 +96,7 @@ port { ltdc_out_dsi: endpoint { - remote-endpoint = <&dsi_in_ltdc>; + remote-endpoint = <&dsi_in>; }; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts index 4bef2300ed7c..510cca5acb79 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts @@ -34,26 +34,6 @@ #address-cells = <1>; #size-cells = <0>; status = "okay"; - phy-dsi-supply = <®18>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_ep1_out>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; panel@0 { compatible = "orisetech,otm8009a"; @@ -70,6 +50,14 @@ }; }; +&dsi_in { + remote-endpoint = <<dc_ep1_out>; +}; + +&dsi_out { + remote-endpoint = <&panel_in>; +}; + &i2c1 { touchscreen@38 { compatible = "focaltech,ft6236"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-emsbc-argon.dts b/arch/arm/boot/dts/st/stm32mp157c-emsbc-argon.dts index 33b3f11d24bb..a19c488cf7c8 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-emsbc-argon.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-emsbc-argon.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Copyright (c) 2021 emtrion GmbH // Author: Reinhold Müller <reinhold.mueller@emtrion.de>. diff --git a/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi index 94e38141af67..f928cfb80b87 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157c-emstamp-argon.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Copyright (c) 2021 emtrion GmbH // Author: Reinhold Müller <reinhold.mueller@emtrion.de>. @@ -310,7 +310,6 @@ vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; - regulator-over-current-protection; }; bst_out: boost { @@ -321,7 +320,7 @@ vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = <IT_OCP_OTG 0>; - regulator-active-discharge; + regulator-active-discharge = <1>; }; vbus_usbh: pwr_sw2 { @@ -368,8 +367,8 @@ &m4_rproc { memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; interrupt-parent = <&exti>; interrupts = <68 1>; interrupt-names = "wdg"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts index af3800501875..cd9c3ff5378b 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts @@ -100,30 +100,10 @@ }; &dsi { - phy-dsi-supply = <®18>; #address-cells = <1>; #size-cells = <0>; status = "okay"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dsi_in: endpoint { - remote-endpoint = <<dc_ep0_out>; - }; - }; - - port@1 { - reg = <1>; - dsi_out: endpoint { - remote-endpoint = <&dsi_panel_in>; - }; - }; - }; - panel@0 { compatible = "raydium,rm68200"; reg = <0>; @@ -140,6 +120,14 @@ }; }; +&dsi_in { + remote-endpoint = <<dc_ep0_out>; +}; + +&dsi_out { + remote-endpoint = <&dsi_panel_in>; +}; + ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen1.dts b/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen1.dts new file mode 100644 index 000000000000..81f254fb88b0 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen1.dts @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2021 Rouven Czerwinski, Pengutronix + * Copyright (C) 2023 Leonard Göhrs, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc-lxa-tac.dtsi" + +/ { + model = "Linux Automation Test Automation Controller (TAC) Gen 1"; + compatible = "lxa,stm32mp157c-tac-gen1", "oct,stm32mp15xx-osd32", "st,stm32mp157"; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&v3v3>; + + brightness-levels = <0 31 63 95 127 159 191 223 255>; + default-brightness-level = <7>; + pwms = <&backlight_pwm 1 1000000 0>; + }; + + reg_iobus_12v: regulator-iobus-12v { + compatible = "regulator-fixed"; + vin-supply = <®_12v>; + + gpio = <&gpioh 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "12V_IOBUS"; + }; +}; + +&gpioa { + gpio-line-names = "", "", "STACK_CS2", "", "STACK_CS3", /* 0 */ + "ETH_GPIO1", "ETH_INT", "", "", "", /* 5 */ + "", "", "", "BOOTROM_LED", "ETH_LAB_LEDRP", /* 10 */ + ""; /* 15 */ +}; + +&gpioc { + gpio-line-names = "", "STACK_CS1", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", ""; /* 10 */ +}; + +&gpu { + status = "disabled"; +}; + +&i2c1 { + powerboard_gpio: gpio@24 { + compatible = "nxp,pca9570"; + reg = <0x24>; + + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "DUT_PWR_EN", "DUT_PWR_DISCH", "DUT_PWR_ADCRST", ""; + }; +}; + +&spi2 { + adc@0 { + compatible = "ti,lmp92064"; + reg = <0>; + spi-max-frequency = <5000000>; + vdd-supply = <®_pb_3v3>; + vdig-supply = <®_pb_3v3>; + reset-gpios = <&powerboard_gpio 2 GPIO_ACTIVE_HIGH>; + + shunt-resistor-micro-ohms = <15000>; + }; +}; + +&timers1 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + backlight_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm1_pins_c>; + pinctrl-1 = <&pwm1_sleep_pins_c>; + + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen2.dts b/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen2.dts new file mode 100644 index 000000000000..8a34d15e9005 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157c-lxa-tac-gen2.dts @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2021 Rouven Czerwinski, Pengutronix + * Copyright (C) 2023 Leonard Göhrs, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc-lxa-tac.dtsi" + +/ { + model = "Linux Automation Test Automation Controller (TAC) Gen 2"; + compatible = "lxa,stm32mp157c-tac-gen2", "oct,stm32mp15xx-osd32", "st,stm32mp157"; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&v3v3>; + + brightness-levels = <0 31 63 95 127 159 191 223 255>; + default-brightness-level = <7>; + pwms = <&led_pwm 3 1000000 0>; + }; + + reg_iobus_12v: regulator-iobus-12v { + compatible = "regulator-fixed"; + vin-supply = <®_12v>; + gpio = <&gpioh 13 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "12V_IOBUS"; + }; + + led-controller-1 { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + max-brightness = <65535>; + + led-red { + active-low; + color = <LED_COLOR_ID_RED>; + pwms = <&led_pwm 0 1000000 0>; + }; + + led-green { + active-low; + color = <LED_COLOR_ID_GREEN>; + pwms = <&led_pwm 2 1000000 0>; + }; + + led-blue { + active-low; + color = <LED_COLOR_ID_BLUE>; + pwms = <&led_pwm 1 1000000 0>; + }; + }; + }; + + led-controller-2 { + compatible = "gpio-leds"; + + led-5 { + label = "tac:green:iobus"; + gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>; + }; + + led-6 { + label = "tac:green:can"; + gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>; + }; + + led-7 { + label = "tac:green:out0"; + gpios = <&gpiob 8 GPIO_ACTIVE_HIGH>; + }; + + led-8 { + label = "tac:green:out1"; + gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; + }; + + led-9 { + label = "tac:green:uarttx"; + gpios = <&gpiod 3 GPIO_ACTIVE_HIGH>; + }; + + led-10 { + label = "tac:green:uartrx"; + gpios = <&gpiof 6 GPIO_ACTIVE_HIGH>; + }; + + led-11 { + label = "tac:green:usbh1"; + gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>; + }; + + led-12 { + label = "tac:green:usbh2"; + gpios = <&gpiod 6 GPIO_ACTIVE_HIGH>; + }; + + led-13 { + label = "tac:green:usbh3"; + gpios = <&gpiob 9 GPIO_ACTIVE_HIGH>; + }; + + led-14 { + label = "tac:green:usbg"; + gpios = <&gpiod 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "usb-gadget"; + }; + + led-15 { + label = "tac:green:dutpwr"; + gpios = <&gpioa 15 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gpioa { + gpio-line-names = "", "", "DUT_PWR_EN", "", "STACK_CS3", /* 0 */ + "ETH_GPIO1", "ETH_INT", "", "", "", /* 5 */ + "", "", "", "BOOTROM_LED", "ETH_LAB_LEDRP", /* 10 */ + ""; /* 15 */ +}; + +&gpioc { + gpio-line-names = "", "DUT_PWR_DISCH", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", ""; /* 10 */ +}; + +&gpu { + status = "disabled"; +}; + +&m_can2 { + termination-gpios = <&gpioe 4 GPIO_ACTIVE_HIGH>; + termination-ohms = <120>; +}; + +&spi2 { + adc@0 { + compatible = "ti,lmp92064"; + reg = <0>; + + reset-gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>; + shunt-resistor-micro-ohms = <15000>; + spi-max-frequency = <5000000>; + vdd-supply = <®_pb_3v3>; + vdig-supply = <®_pb_3v3>; + }; +}; + +&timers8 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + led_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm8_pins_b>; + pinctrl-1 = <&pwm8_sleep_pins_b>; + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi index e22871dc580c..cf7485251490 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi @@ -230,8 +230,8 @@ &m4_rproc { memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; interrupt-parent = <&exti>; interrupts = <68 1>; status = "okay"; diff --git a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi new file mode 100644 index 000000000000..184b8bb4ebbf --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi @@ -0,0 +1,610 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2021 Rouven Czerwinski, Pengutronix + * Copyright (C) 2023 Leonard Göhrs, Pengutronix + */ + +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-osd32.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + aliases { + ethernet0 = ðernet0; + ethernet1 = &port_uplink; + ethernet2 = &port_dut; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &usart3; + }; + + chosen { + stdout-path = &uart4; + }; + + led-controller-0 { + compatible = "gpio-leds"; + + led-0 { + label = "tac:green:user1"; + gpios = <&gpiof 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "tac:green:user2"; + gpios = <&gpiog 7 GPIO_ACTIVE_HIGH>; + }; + + led-2 { + label = "tac:green:statusdut"; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + }; + + /* led-3 and led-4 are internally connected antiparallel to one + * another inside the ethernet jack like this: + * GPIOA14 ---+---|led-3|>--+--- GPIOD15 + * +--<|led-4|---+ + * E.g. only one of the LEDs can be illuminated at a time while + * the other output must be driven low. + * This should likely be implemented using a multi color LED + * driver for antiparallel LEDs. + */ + led-3 { + label = "tac:green:statuslab"; + gpios = <&gpioa 14 GPIO_ACTIVE_HIGH>; + }; + + led-4 { + label = "tac:orange:statuslab"; + gpios = <&gpiod 15 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-lower { + label = "USER_BTN2"; + linux,code = <KEY_ESC>; + gpios = <&gpioe 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-upper { + label = "USER_BTN"; + linux,code = <KEY_HOME>; + gpios = <&gpioi 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; + + /* supplied by either barrel connector or PoE */ + reg_12v: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_12v>; + }; + + reg_1v2: regulator-1v2 { + compatible = "regulator-fixed"; + regulator-name = "1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + vin-supply = <®_5v>; + }; + + reg_pb_5v: regulator-pb-5v { + compatible = "regulator-fixed"; + regulator-name = "5V_POWERBOARD"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <®_5v>; + }; + + reg_pb_3v3: regulator-pb-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3_POWERBOARD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_pb_5v>; + }; + + output-iobus-12v { + compatible = "regulator-output"; + vout-supply = <®_iobus_12v>; + }; + + output-vuart { + compatible = "regulator-output"; + vout-supply = <&v3v3_hdmi>; + }; +}; + +baseboard_eeprom: &sip_eeprom { +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_ain_pins_a>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vrefbuf>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 2 5 9 10 13 15>; + st,min-sample-time-nsecs = <5000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@0 { + reg = <0>; + label = "HOST_2_CURR_FB"; + }; + + channel@1 { + reg = <1>; + label = "HOST_3_CURR_FB"; + }; + + channel@2 { + reg = <2>; + label = "OUT_0_FB"; + }; + + channel@5 { + reg = <5>; + label = "IOBUS_CURR_FB"; + }; + + channel@9 { + reg = <9>; + label = "IOBUS_VOLT_FB"; + }; + + channel@10 { + reg = <10>; + label = "OUT_1_FB"; + }; + + channel@13 { + reg = <13>; + label = "HOST_CURR_FB"; + }; + + channel@15 { + reg = <15>; + label = "HOST_1_CURR_FB"; + }; + }; + + adc2: adc@100 { + st,adc-channels = <12>; + st,min-sample-time-nsecs = <500000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@12 { + reg = <12>; + label = "TEMP_INTERNAL"; + }; + }; +}; + +&crc1 { + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF */ + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ðernet0_rgmii_pins_e>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_e>; + + st,eth-clk-sel; + phy-mode = "rgmii-id"; + + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +ðernet0_rgmii_pins_e { + pins1 { + /* Reduce EMI emission by reducing RGMII drive strength */ + slew-rate = <1>; + }; +}; + +&gpiob { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "USB_RESET", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpiod { + gpio-line-names = "", "", "", "", "TP38", /* 0 */ + "TP39", "", "", "TP41", "TP42", /* 5 */ + "OLED_DC", "", "", "ETH_CS", "", /* 10 */ + "ETH_LAB_LEDRN"; /* 15 */ +}; + +&gpioe { + gpio-line-names = "TP35", "", "", "", "CAN_1_120R", /* 0 */ + "", "", "USER_BTN2", "TP48", "UART_TX_EN", /* 5 */ + "UART_RX_EN", "TP24", "", "TP25", "TP26", /* 10 */ + "TP27"; /* 15 */ +}; + +&gpiof { + gpio-line-names = "TP36", "TP37", "", "", "OLED_CS", /* 0 */ + "", "", "", "", "", /* 5 */ + "USER_LED1", "", "STACK_CS0", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpiog { + gpio-line-names = "ETH_RESET", "", "", "", "", /* 0 */ + "IOBUS_FLT_FB", "", "USER_LED2", "ETH1_PPS_A", "CAN_0_120R", /* 5 */ + "TP49", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioh { + gpio-line-names = "", "", "OUT_1", "OUT_0", "OLED_RESET", /* 0 */ + "", "", "", "", "", /* 5 */ + "ETH1_PPS_B", "ETH_GPIO2", "", "IOBUS_PWR_EN", "", /* 10 */ + "TP33"; /* 15 */ +}; + +&gpioi { + gpio-line-names = "TIM_RTS", "", "", "", "DEVICE_DATA_EN", /* 0 */ + "", "", "", "ETH_WOL", "TP43", /* 5 */ + "", "USER_BTN"; /* 10 */ +}; + +&gpioz { + gpio-line-names = "HWID0", "HWID1", "HWID2", "HWID3", "", /* 0 */ + "", "HWID4", "HWID5"; /* 5 */ +}; + +&hash1 { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-1 = <&i2c1_sleep_pins_b>; + status = "okay"; + + powerboard_eeprom: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + vcc-supply = <&v3v3>; + }; + + temperature-sensor@48 { + compatible = "national,lm75a"; + reg = <0x48>; + status = "disabled"; + }; +}; + +&i2c5 { + /delete-property/dmas; + /delete-property/dma-names; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_b>; + pinctrl-1 = <&i2c5_sleep_pins_b>; + + status = "okay"; + + usbhub: usbhub@2c { + compatible ="microchip,usb2514b"; + reg = <0x2c>; + vdd-supply = <&v3v3>; + reset-gpios = <&gpiob 6 GPIO_ACTIVE_LOW>; + }; +}; + +&iwdg2 { + timeout-sec = <8>; + status = "okay"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_b>; + pinctrl-1 = <&m_can1_sleep_pins_b>; + status = "okay"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; + +&pmic { + regulators { + buck1-supply = <®_5v>; /* VIN */ + buck2-supply = <®_5v>; /* VIN */ + buck3-supply = <®_5v>; /* VIN */ + buck4-supply = <®_5v>; /* VIN */ + ldo2-supply = <®_5v>; /* PMIC_LDO25IN */ + ldo4-supply = <®_5v>; /* VIN */ + ldo5-supply = <®_5v>; /* PMIC_LDO25IN */ + vref_ddr-supply = <®_5v>; /* VIN */ + boost-supply = <®_5v>; /* PMIC_BSTIN */ + pwr_sw2-supply = <&bst_out>; /* PMIC_SWIN */ + }; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + vmmc-supply = <&v3v3>; + + bus-width = <8>; + mmc-ddr-3_3v; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_c>; + cs-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins_a>; + cs-gpios = <&gpiof 4 GPIO_ACTIVE_LOW>; + status = "okay"; + + lcd: display@0 { + compatible = "shineworld,lh133k", "panel-mipi-dbi-spi"; + reg = <0>; + power-supply = <&v3v3>; + io-supply = <&v3v3>; + backlight = <&backlight>; + dc-gpios = <&gpiod 10 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpioh 4 GPIO_ACTIVE_HIGH>; + spi-3wire; + spi-max-frequency = <32000000>; + + width-mm = <23>; + height-mm = <23>; + rotation = <180>; + + panel-timing { + hactive = <240>; + vactive = <240>; + hback-porch = <0>; + vback-porch = <0>; + + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; +}; + +&spi5 { + pinctrl-names = "default"; + pinctrl-0 = <&spi5_pins_a>; + + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + cs-gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; + + status = "okay"; + + switch: switch@0 { + compatible = "microchip,ksz9563"; + reg = <0>; + + reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; + spi-max-frequency = <44000000>; + + interrupt-parent = <&gpioa>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port_dut: port@0 { + reg = <0>; + label = "dut"; + }; + + port_uplink: port@1 { + reg = <1>; + label = "uplink"; + }; + + port_cpu: port@2 { + reg = <2>; + label = "cpu"; + + ethernet = <ðernet0>; + + phy-mode = "rgmii-id"; + rx-internal-delay-ps = <2000>; + tx-internal-delay-ps = <2000>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&timers2 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@1 { + status = "okay"; + }; +}; + +&timers3 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@2 { + status = "okay"; + }; +}; + +&timers4 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@3 { + status = "okay"; + }; +}; + +&uart4 { + label = "debug"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; +}; + +&usart3 { + label = "dut"; + uart-has-rtscts; + + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_f>; + + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + + status = "okay"; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + + vusb_d-supply = <&vdd_usb>; + vusb_a-supply = <®18>; + + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; + +&v3v3_hdmi { + /delete-property/regulator-always-on; +}; + +&vrefbuf { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vdda-supply = <&vdda>; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi index e61df23d361a..74a11ccc5333 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi @@ -416,8 +416,8 @@ &m4_rproc { memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; interrupt-parent = <&exti>; interrupts = <68 1>; status = "okay"; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi index bba19f21e527..89881a26c614 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi @@ -227,8 +227,8 @@ &m4_rproc { memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>; - mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; - mbox-names = "vq0", "vq1", "shutdown"; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names = "vq0", "vq1", "shutdown", "detach"; interrupt-parent = <&exti>; interrupts = <68 1>; status = "okay"; diff --git a/arch/arm/boot/dts/ti/davinci/da850-evm.dts b/arch/arm/boot/dts/ti/davinci/da850-evm.dts index 111708d992ca..6c5936278e75 100644 --- a/arch/arm/boot/dts/ti/davinci/da850-evm.dts +++ b/arch/arm/boot/dts/ti/davinci/da850-evm.dts @@ -161,7 +161,7 @@ &pmx_core { status = "okay"; - mcasp0_pins: pinmux_mcasp0_pins { + mcasp0_pins: mcasp0-pins { pinctrl-single,bits = < /* * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR, @@ -172,7 +172,7 @@ 0x04 0x00011000 0x000ff000 >; }; - nand_pins: nand_pins { + nand_pins: nand-pins { pinctrl-single,bits = < /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */ 0x1c 0x10110110 0xf0ff0ff0 diff --git a/arch/arm/boot/dts/ti/davinci/da850-lcdk.dts b/arch/arm/boot/dts/ti/davinci/da850-lcdk.dts index e379d6e7ad49..8390d71b000a 100644 --- a/arch/arm/boot/dts/ti/davinci/da850-lcdk.dts +++ b/arch/arm/boot/dts/ti/davinci/da850-lcdk.dts @@ -199,7 +199,7 @@ &pmx_core { status = "okay"; - mcasp0_pins: pinmux_mcasp0_pins { + mcasp0_pins: mcasp0-pins { pinctrl-single,bits = < /* AHCLKX AFSX ACLKX */ 0x00 0x00101010 0x00f0f0f0 @@ -208,7 +208,7 @@ >; }; - nand_pins: nand_pins { + nand_pins: nand-pins { pinctrl-single,bits = < /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */ 0x1c 0x10110010 0xf0ff00f0 diff --git a/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts b/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts index afd04a423856..4df10379ff22 100644 --- a/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts +++ b/arch/arm/boot/dts/ti/davinci/da850-lego-ev3.dts @@ -234,7 +234,7 @@ &pmx_core { status = "okay"; - ev3_lcd_pins: pinmux_lcd { + ev3_lcd_pins: lcd-pins { pinctrl-single,bits = < /* SIMO, CLK */ 0x14 0x00100100 0x00f00f00 @@ -391,7 +391,7 @@ pinctrl-names = "default"; cs-gpios = <&gpio 44 GPIO_ACTIVE_LOW>; - display@0{ + display@0 { compatible = "lego,ev3-lcd"; reg = <0>; spi-max-frequency = <10000000>; diff --git a/arch/arm/boot/dts/ti/davinci/da850.dtsi b/arch/arm/boot/dts/ti/davinci/da850.dtsi index e46e4d22db39..f759fdfe1b10 100644 --- a/arch/arm/boot/dts/ti/davinci/da850.dtsi +++ b/arch/arm/boot/dts/ti/davinci/da850.dtsi @@ -170,55 +170,55 @@ #pinctrl-single,gpio-range-cells = <3>; }; - serial0_rtscts_pins: pinmux_serial0_rtscts_pins { + serial0_rtscts_pins: serial0-rtscts-pins { pinctrl-single,bits = < /* UART0_RTS UART0_CTS */ 0x0c 0x22000000 0xff000000 >; }; - serial0_rxtx_pins: pinmux_serial0_rxtx_pins { + serial0_rxtx_pins: serial0-rxtx-pins { pinctrl-single,bits = < /* UART0_TXD UART0_RXD */ 0x0c 0x00220000 0x00ff0000 >; }; - serial1_rtscts_pins: pinmux_serial1_rtscts_pins { + serial1_rtscts_pins: serial1-rtscts-pins { pinctrl-single,bits = < /* UART1_CTS UART1_RTS */ 0x00 0x00440000 0x00ff0000 >; }; - serial1_rxtx_pins: pinmux_serial1_rxtx_pins { + serial1_rxtx_pins: serial1-rxtx-pins { pinctrl-single,bits = < /* UART1_TXD UART1_RXD */ 0x10 0x22000000 0xff000000 >; }; - serial2_rtscts_pins: pinmux_serial2_rtscts_pins { + serial2_rtscts_pins: serial2-rtscts-pins { pinctrl-single,bits = < /* UART2_CTS UART2_RTS */ 0x00 0x44000000 0xff000000 >; }; - serial2_rxtx_pins: pinmux_serial2_rxtx_pins { + serial2_rxtx_pins: serial2-rxtx-pins { pinctrl-single,bits = < /* UART2_TXD UART2_RXD */ 0x10 0x00220000 0x00ff0000 >; }; - i2c0_pins: pinmux_i2c0_pins { + i2c0_pins: i2c0-pins { pinctrl-single,bits = < /* I2C0_SDA,I2C0_SCL */ 0x10 0x00002200 0x0000ff00 >; }; - i2c1_pins: pinmux_i2c1_pins { + i2c1_pins: i2c1-pins { pinctrl-single,bits = < /* I2C1_SDA, I2C1_SCL */ 0x10 0x00440000 0x00ff0000 >; }; - mmc0_pins: pinmux_mmc_pins { + mmc0_pins: mmc-pins { pinctrl-single,bits = < /* MMCSD0_DAT[3] MMCSD0_DAT[2] * MMCSD0_DAT[1] MMCSD0_DAT[0] @@ -227,85 +227,85 @@ 0x28 0x00222222 0x00ffffff >; }; - ehrpwm0a_pins: pinmux_ehrpwm0a_pins { + ehrpwm0a_pins: ehrpwm0a-pins { pinctrl-single,bits = < /* EPWM0A */ 0xc 0x00000002 0x0000000f >; }; - ehrpwm0b_pins: pinmux_ehrpwm0b_pins { + ehrpwm0b_pins: ehrpwm0b-pins { pinctrl-single,bits = < /* EPWM0B */ 0xc 0x00000020 0x000000f0 >; }; - ehrpwm1a_pins: pinmux_ehrpwm1a_pins { + ehrpwm1a_pins: ehrpwm1a-pins { pinctrl-single,bits = < /* EPWM1A */ 0x14 0x00000002 0x0000000f >; }; - ehrpwm1b_pins: pinmux_ehrpwm1b_pins { + ehrpwm1b_pins: ehrpwm1b-pins { pinctrl-single,bits = < /* EPWM1B */ 0x14 0x00000020 0x000000f0 >; }; - ecap0_pins: pinmux_ecap0_pins { + ecap0_pins: ecap0-pins { pinctrl-single,bits = < /* ECAP0_APWM0 */ 0x8 0x20000000 0xf0000000 >; }; - ecap1_pins: pinmux_ecap1_pins { + ecap1_pins: ecap1-pins { pinctrl-single,bits = < /* ECAP1_APWM1 */ 0x4 0x40000000 0xf0000000 >; }; - ecap2_pins: pinmux_ecap2_pins { + ecap2_pins: ecap2-pins { pinctrl-single,bits = < /* ECAP2_APWM2 */ 0x4 0x00000004 0x0000000f >; }; - spi0_pins: pinmux_spi0_pins { + spi0_pins: spi0-pins { pinctrl-single,bits = < /* SIMO, SOMI, CLK */ 0xc 0x00001101 0x0000ff0f >; }; - spi0_cs0_pin: pinmux_spi0_cs0 { + spi0_cs0_pin: spi0-cs0-pins { pinctrl-single,bits = < /* CS0 */ 0x10 0x00000010 0x000000f0 >; }; - spi0_cs3_pin: pinmux_spi0_cs3_pin { + spi0_cs3_pin: spi0-cs3-pins { pinctrl-single,bits = < /* CS3 */ 0xc 0x01000000 0x0f000000 >; }; - spi1_pins: pinmux_spi1_pins { + spi1_pins: spi1-pins { pinctrl-single,bits = < /* SIMO, SOMI, CLK */ 0x14 0x00110100 0x00ff0f00 >; }; - spi1_cs0_pin: pinmux_spi1_cs0 { + spi1_cs0_pin: spi1-cs0-pins { pinctrl-single,bits = < /* CS0 */ 0x14 0x00000010 0x000000f0 >; }; - mdio_pins: pinmux_mdio_pins { + mdio_pins: mdio-pins { pinctrl-single,bits = < /* MDIO_CLK, MDIO_D */ 0x10 0x00000088 0x000000ff >; }; - mii_pins: pinmux_mii_pins { + mii_pins: mii-pins { pinctrl-single,bits = < /* * MII_TXEN, MII_TXCLK, MII_COL @@ -321,7 +321,7 @@ 0xc 0x88888888 0xffffffff >; }; - lcd_pins: pinmux_lcd_pins { + lcd_pins: lcd-pins { pinctrl-single,bits = < /* * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5], @@ -342,7 +342,7 @@ 0x4c 0x02000022 0x0f0000ff >; }; - vpif_capture_pins: vpif_capture_pins { + vpif_capture_pins: vpif-capture-pins { pinctrl-single,bits = < /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */ 0x38 0x11111111 0xffffffff @@ -352,7 +352,7 @@ 0x40 0x00000011 0x000000ff >; }; - vpif_display_pins: vpif_display_pins { + vpif_display_pins: vpif-display-pins { pinctrl-single,bits = < /* VP_DOUT[2..7] */ 0x40 0x11111100 0xffffff00 @@ -421,7 +421,7 @@ /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */ reg = <0x0 0x8000>; reg-names = "edma3_cc"; - interrupts = <11 12>; + interrupts = <11>, <12>; interrupt-names = "edma3_ccint", "edma3_ccerrint"; #dma-cells = <2>; @@ -447,7 +447,7 @@ /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */ reg = <0x230000 0x8000>; reg-names = "edma3_cc"; - interrupts = <93 94>; + interrupts = <93>, <94>; interrupt-names = "edma3_ccint", "edma3_ccerrint"; #dma-cells = <2>; @@ -494,8 +494,7 @@ rtc0: rtc@23000 { compatible = "ti,da830-rtc"; reg = <0x23000 0x1000>; - interrupts = <19 - 19>; + interrupts = <19>, <19>; clocks = <&pll0_auxclk>; clock-names = "int-clk"; status = "disabled"; @@ -725,11 +724,7 @@ ti,davinci-ctrl-ram-offset = <0>; ti,davinci-ctrl-ram-size = <0x2000>; local-mac-address = [ 00 00 00 00 00 00 ]; - interrupts = <33 - 34 - 35 - 36 - >; + interrupts = <33>, <34>, <35>,<36>; clocks = <&psc1 5>; power-domains = <&psc1 5>; status = "disabled"; @@ -748,7 +743,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0x226000 0x1000>; - interrupts = <42 43 44 45 46 47 48 49 50>; + interrupts = <42>, <43>, <44>, <45>, <46>, <47>, <48>, <49>, <50>; ti,ngpio = <144>; ti,davinci-gpio-unbanked = <0>; clocks = <&psc1 3>; diff --git a/arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi b/arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi index 8949578e62e8..2062fe561642 100644 --- a/arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi +++ b/arch/arm/boot/dts/ti/keystone/keystone-k2l.dtsi @@ -137,7 +137,7 @@ >; }; - dfesync_rp1_pins: dfesync-rp1-pins{ + dfesync_rp1_pins: dfesync-rp1-pins { pinctrl-single,bits = < /* DFESYNC_RP1_SEL */ 0x0 0x0 0x2 diff --git a/arch/arm/boot/dts/ti/omap/am335x-boneblack.dts b/arch/arm/boot/dts/ti/omap/am335x-boneblack.dts index b956e2f60fe0..16b567e3cb47 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-boneblack.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-boneblack.dts @@ -20,7 +20,8 @@ * BeagleBone Blacks have PG 2.0 silicon which is guaranteed * to support 1GHz OPP so enable it for PG 2.0 on this board. */ - oppnitro-1000000000 { + opp-1000000000 { + /* OPP Nitro */ opp-supported-hw = <0x06 0x0100>; }; }; diff --git a/arch/arm/boot/dts/ti/omap/am335x-osd335x-common.dtsi b/arch/arm/boot/dts/ti/omap/am335x-osd335x-common.dtsi index 9863bf499a39..93a3af83feac 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-osd335x-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/am335x-osd335x-common.dtsi @@ -28,7 +28,8 @@ * the HW OPP table, the silicon looks like it is Revision 1.0 (ie the * EFUSE_SMA register reads as all zeros). */ - oppnitro-1000000000 { + opp-1000000000 { + /* OPP Nitro */ opp-supported-hw = <0x06 0x0100>; }; }; diff --git a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi index 7e50fe633d8a..d6a143abae5f 100644 --- a/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/am33xx-l4.dtsi @@ -455,8 +455,8 @@ rtc: rtc@0 { compatible = "ti,am3352-rtc", "ti,da830-rtc"; reg = <0x0 0x1000>; - interrupts = <75 - 76>; + interrupts = <75>, + <76>; }; }; @@ -739,7 +739,7 @@ * c0_tx_pend * c0_misc_pend */ - interrupts = <40 41 42 43>; + interrupts = <40>, <41>, <42>, <43>; ranges = <0 0 0x8000>; syscon = <&scm_conf>; status = "disabled"; @@ -779,7 +779,7 @@ syscon = <&scm_conf>; status = "disabled"; - interrupts = <40 41 42 43>; + interrupts = <40>, <41>, <42>, <43>; interrupt-names = "rx_thresh", "rx", "tx", "misc"; ethernet-ports { @@ -899,7 +899,7 @@ pruss_intc: interrupt-controller@20000 { compatible = "ti,pruss-intc"; reg = <0x20000 0x2000>; - interrupts = <20 21 22 23 24 25 26 27>; + interrupts = <20>, <21>, <22>, <23>, <24>, <25>, <26>, <27>; interrupt-names = "host_intr0", "host_intr1", "host_intr2", "host_intr3", "host_intr4", "host_intr5", diff --git a/arch/arm/boot/dts/ti/omap/am33xx.dtsi b/arch/arm/boot/dts/ti/omap/am33xx.dtsi index 32d397b3950b..1a2cd5baf402 100644 --- a/arch/arm/boot/dts/ti/omap/am33xx.dtsi +++ b/arch/arm/boot/dts/ti/omap/am33xx.dtsi @@ -80,64 +80,74 @@ * because the can not be enabled simultaneously on a * single SoC. */ - opp50-300000000 { + opp-50-300000000{ + /* OPP50 */ opp-hz = /bits/ 64 <300000000>; opp-microvolt = <950000 931000 969000>; opp-supported-hw = <0x06 0x0010>; opp-suspend; }; - opp100-275000000 { + opp-100-275000000{ + /* OPP100-1 */ opp-hz = /bits/ 64 <275000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0x01 0x00FF>; opp-suspend; }; - opp100-300000000 { + opp-100-300000000{ + /* OPP100-2 */ opp-hz = /bits/ 64 <300000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0x06 0x0020>; opp-suspend; }; - opp100-500000000 { + opp-100-500000000{ + /* OPP100-3 */ opp-hz = /bits/ 64 <500000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0x01 0xFFFF>; }; - opp100-600000000 { + opp-100-600000000 { + /* OPP100-4 */ opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0x06 0x0040>; }; - opp120-600000000 { + opp-120-600000000 { + /* OPP120-1 */ opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1200000 1176000 1224000>; opp-supported-hw = <0x01 0xFFFF>; }; - opp120-720000000 { + opp-120-720000000 { + /* OPP120-2 */ opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1200000 1176000 1224000>; opp-supported-hw = <0x06 0x0080>; }; - oppturbo-720000000 { + opp-720000000 { + /* OPP Turbo-1 */ opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1260000 1234800 1285200>; opp-supported-hw = <0x01 0xFFFF>; }; - oppturbo-800000000 { + opp-800000000 { + /* OPP Turbo-2 */ opp-hz = /bits/ 64 <800000000>; opp-microvolt = <1260000 1234800 1285200>; opp-supported-hw = <0x06 0x0100>; }; - oppnitro-1000000000 { + opp-1000000000 { + /* OPP Nitro */ opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <1325000 1298500 1351500>; opp-supported-hw = <0x04 0x0200>; diff --git a/arch/arm/boot/dts/ti/omap/am3517.dtsi b/arch/arm/boot/dts/ti/omap/am3517.dtsi index 823f63502e9f..fbfc956f4e4d 100644 --- a/arch/arm/boot/dts/ti/omap/am3517.dtsi +++ b/arch/arm/boot/dts/ti/omap/am3517.dtsi @@ -34,14 +34,16 @@ * appear to operate at 300MHz as well. Since AM3517 only * lists one operating voltage, it will remain fixed at 1.2V */ - opp50-300000000 { + opp-50-300000000 { + /* OPP50 */ opp-hz = /bits/ 64 <300000000>; opp-microvolt = <1200000>; opp-supported-hw = <0xffffffff 0xffffffff>; opp-suspend; }; - opp100-600000000 { + opp-100-600000000 { + /* OPP100 */ opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1200000>; opp-supported-hw = <0xffffffff 0xffffffff>; diff --git a/arch/arm/boot/dts/ti/omap/am4372.dtsi b/arch/arm/boot/dts/ti/omap/am4372.dtsi index 8613355bbd5e..9d2c064534f7 100644 --- a/arch/arm/boot/dts/ti/omap/am4372.dtsi +++ b/arch/arm/boot/dts/ti/omap/am4372.dtsi @@ -70,32 +70,37 @@ compatible = "operating-points-v2-ti-cpu"; syscon = <&scm_conf>; - opp50-300000000 { + opp-50-300000000 { + /* OPP50 */ opp-hz = /bits/ 64 <300000000>; opp-microvolt = <950000 931000 969000>; opp-supported-hw = <0xFF 0x01>; opp-suspend; }; - opp100-600000000 { + opp-100-600000000 { + /* OPP100 */ opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1100000 1078000 1122000>; opp-supported-hw = <0xFF 0x04>; }; - opp120-720000000 { + opp-120-720000000 { + /* OPP120 */ opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1200000 1176000 1224000>; opp-supported-hw = <0xFF 0x08>; }; - oppturbo-800000000 { + opp-800000000{ + /* OPP Turbo */ opp-hz = /bits/ 64 <800000000>; opp-microvolt = <1260000 1234800 1285200>; opp-supported-hw = <0xFF 0x10>; }; - oppnitro-1000000000 { + opp-1000000000 { + /* OPP Nitro */ opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <1325000 1298500 1351500>; opp-supported-hw = <0xFF 0x20>; diff --git a/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts b/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts index 863552393c07..00682ce7e14c 100644 --- a/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/ti/omap/am437x-idk-evm.dts @@ -58,7 +58,7 @@ vin-supply = <&vdd_corereg>; }; - v1_8dreg: fixed-regulator-v1_8dreg{ + v1_8dreg: fixed-regulator-v1_8dreg { compatible = "regulator-fixed"; regulator-name = "V1_8DREG"; regulator-min-microvolt = <1800000>; @@ -68,7 +68,7 @@ vin-supply = <&v24_0d>; }; - v1_8d: fixed-regulator-v1_8d{ + v1_8d: fixed-regulator-v1_8d { compatible = "regulator-fixed"; regulator-name = "V1_8D"; regulator-min-microvolt = <1800000>; @@ -78,7 +78,7 @@ vin-supply = <&v1_8dreg>; }; - v1_5dreg: fixed-regulator-v1_5dreg{ + v1_5dreg: fixed-regulator-v1_5dreg { compatible = "regulator-fixed"; regulator-name = "V1_5DREG"; regulator-min-microvolt = <1500000>; @@ -88,7 +88,7 @@ vin-supply = <&v24_0d>; }; - v1_5d: fixed-regulator-v1_5d{ + v1_5d: fixed-regulator-v1_5d { compatible = "regulator-fixed"; regulator-name = "V1_5D"; regulator-min-microvolt = <1500000>; @@ -527,11 +527,13 @@ * Supply voltage supervisor on board will not allow opp50 so * disable it and set opp100 as suspend OPP. */ - opp50-300000000 { + opp-50-300000000 { + /* opp50-300000000 */ status = "disabled"; }; - opp100-600000000 { + opp-100-600000000 { + /* opp100-600000000 */ opp-suspend; }; }; diff --git a/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi b/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi index 415210b034ef..824b9415ebbe 100644 --- a/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi +++ b/arch/arm/boot/dts/ti/omap/am437x-l4.dtsi @@ -442,8 +442,8 @@ compatible = "ti,am4372-rtc", "ti,am3352-rtc", "ti,da830-rtc"; reg = <0x0 0x1000>; - interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk_32768_ck>; clock-names = "int-clk"; system-power-controller; @@ -549,10 +549,10 @@ syscon = <&scm_conf>; status = "disabled"; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "rx_thresh", "rx", "tx", "misc"; ethernet-ports { diff --git a/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts index 149cfafb90bf..9a234dc1431d 100644 --- a/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts +++ b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts @@ -677,12 +677,6 @@ clock-frequency = <100000>; }; -&cpu0_opp_table { - opp_slow-500000000 { - opp-shared; - }; -}; - &ipu2 { status = "okay"; memory-region = <&ipu2_memory_region>; diff --git a/arch/arm/boot/dts/ti/omap/dra7.dtsi b/arch/arm/boot/dts/ti/omap/dra7.dtsi index 97ce0c4f1df7..3f3e52e3b375 100644 --- a/arch/arm/boot/dts/ti/omap/dra7.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7.dtsi @@ -101,7 +101,8 @@ compatible = "operating-points-v2-ti-cpu"; syscon = <&scm_wkup>; - opp_nom-1000000000 { + opp-1000000000 { + /* OPP NOM */ opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <1060000 850000 1150000>, <1060000 850000 1150000>; @@ -109,7 +110,8 @@ opp-suspend; }; - opp_od-1176000000 { + opp-1176000000 { + /* OPP OD */ opp-hz = /bits/ 64 <1176000000>; opp-microvolt = <1160000 885000 1160000>, <1160000 885000 1160000>; @@ -117,7 +119,8 @@ opp-supported-hw = <0xFF 0x02>; }; - opp_high@1500000000 { + opp-1500000000 { + /* OPP High */ opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <1210000 950000 1250000>, <1210000 950000 1250000>; diff --git a/arch/arm/boot/dts/ti/omap/dra76x.dtsi b/arch/arm/boot/dts/ti/omap/dra76x.dtsi index 931db7932c11..1045eb24aa0d 100644 --- a/arch/arm/boot/dts/ti/omap/dra76x.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra76x.dtsi @@ -130,7 +130,8 @@ }; &cpu0_opp_table { - opp_plus@1800000000 { + opp-1800000000 { + /* OPP Plus */ opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <1250000 950000 1250000>, <1250000 950000 1250000>; diff --git a/arch/arm/boot/dts/ti/omap/omap34xx.dtsi b/arch/arm/boot/dts/ti/omap/omap34xx.dtsi index 9dbf62797f0f..fc7233ac183a 100644 --- a/arch/arm/boot/dts/ti/omap/omap34xx.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap34xx.dtsi @@ -25,7 +25,7 @@ compatible = "operating-points-v2-ti-cpu"; syscon = <&scm_conf>; - opp1-125000000 { + opp-125000000 { opp-hz = /bits/ 64 <125000000>; /* * we currently only select the max voltage from table @@ -40,32 +40,32 @@ opp-supported-hw = <0xffffffff 3>; }; - opp2-250000000 { + opp-250000000 { opp-hz = /bits/ 64 <250000000>; opp-microvolt = <1075000 1075000 1075000>; opp-supported-hw = <0xffffffff 3>; opp-suspend; }; - opp3-500000000 { + opp-500000000 { opp-hz = /bits/ 64 <500000000>; opp-microvolt = <1200000 1200000 1200000>; opp-supported-hw = <0xffffffff 3>; }; - opp4-550000000 { + opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-microvolt = <1275000 1275000 1275000>; opp-supported-hw = <0xffffffff 3>; }; - opp5-600000000 { + opp-600000000 { opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1350000 1350000 1350000>; opp-supported-hw = <0xffffffff 3>; }; - opp6-720000000 { + opp-720000000 { opp-hz = /bits/ 64 <720000000>; opp-microvolt = <1350000 1350000 1350000>; /* only high-speed grade omap3530 devices */ diff --git a/arch/arm/boot/dts/ti/omap/omap36xx.dtsi b/arch/arm/boot/dts/ti/omap/omap36xx.dtsi index fff9c3d34193..e6d8070c1bf8 100644 --- a/arch/arm/boot/dts/ti/omap/omap36xx.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap36xx.dtsi @@ -30,7 +30,8 @@ compatible = "operating-points-v2-ti-cpu"; syscon = <&scm_conf>; - opp50-300000000 { + opp-50-300000000 { + /* OPP50 */ opp-hz = /bits/ 64 <300000000>; /* * we currently only select the max voltage from table @@ -48,21 +49,24 @@ opp-suspend; }; - opp100-600000000 { + opp-100-600000000 { + /* OPP100 */ opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1200000 1200000 1200000>, <1200000 1200000 1200000>; opp-supported-hw = <0xffffffff 3>; }; - opp130-800000000 { + opp-130-800000000 { + /* OPP130 */ opp-hz = /bits/ 64 <800000000>; opp-microvolt = <1325000 1325000 1325000>, <1325000 1325000 1325000>; opp-supported-hw = <0xffffffff 3>; }; - opp1g-1000000000 { + opp-1000000000 { + /* OPP1G */ opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <1375000 1375000 1375000>, <1375000 1375000 1375000>; @@ -71,7 +75,7 @@ }; }; - opp_supply_mpu_iva: opp_supply { + opp_supply_mpu_iva: opp-supply { compatible = "ti,omap-opp-supply"; ti,absolute-max-voltage-uv = <1375000>; }; diff --git a/arch/arm/boot/dts/ti/omap/omap5-board-common.dtsi b/arch/arm/boot/dts/ti/omap/omap5-board-common.dtsi index 6f46f1ecf1e5..8946b5580cd9 100644 --- a/arch/arm/boot/dts/ti/omap/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap5-board-common.dtsi @@ -415,9 +415,9 @@ gpadc: gpadc { compatible = "ti,palmas-gpadc"; - interrupts = <18 0 - 16 0 - 17 0>; + interrupts = <18 0>, + <16 0>, + <17 0>; #io-channel-cells = <1>; ti,channel0-current-microamp = <5>; ti,channel3-current-microamp = <10>; diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 6a96494a2e0a..3b0ad5406238 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -40,3 +40,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts index d34c2bb1079f..f5c5c1464482 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100-allwinner-perf1.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi index 97e3e6907acd..a3dccf193765 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts index 686f58e77004..b710f1a0f53a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-model-b.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2019 Corentin LABBE <clabbe@baylibre.com> */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi new file mode 100644 index 000000000000..15290e6892fc --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2020 Arm Ltd. + * + * DT nodes common between Orange Pi Zero 2 and Orange Pi Zero 3. + * Excludes PMIC nodes and properties, since they are different between the two. + */ + +#include "sun50i-h616.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/leds/common.h> + +/ { + aliases { + ethernet0 = &emac0; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_RED>; + gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ + default-state = "on"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_vcc5v>; + enable-active-high; + gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ + }; +}; + +&ehci1 { + status = "okay"; +}; + +/* USB 2 & 3 are on headers only. */ + +&emac0 { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii"; + phy-handle = <&ext_rgmii_phy>; + allwinner,rx-delay-ps = <3100>; + allwinner,tx-delay-ps = <700>; + status = "okay"; +}; + +&mdio0 { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +&usbotg { + /* + * PHY0 pins are connected to a USB-C socket, but a role switch + * is not implemented: both CC pins are pulled to GND. + * The VBUS pins power the device, so a fixed peripheral mode + * is the best choice. + * The board can be powered via GPIOs, in this case port0 *can* + * act as a host (with a cable/adapter ignoring CC), as VBUS is + * then provided by the GPIOs. Any user of this setup would + * need to adjust the DT accordingly: dr_mode set to "host", + * enabling OHCI0 and EHCI0. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts index cb8600d0ea1e..d83852e72f06 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts @@ -1,99 +1,23 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2020 Arm Ltd. */ /dts-v1/; -#include "sun50i-h616.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/leds/common.h> +#include "sun50i-h616-orangepi-zero.dtsi" / { model = "OrangePi Zero2"; compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616"; - - aliases { - ethernet0 = &emac0; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - function = LED_FUNCTION_POWER; - color = <LED_COLOR_ID_RED>; - gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ - default-state = "on"; - }; - - led-1 { - function = LED_FUNCTION_STATUS; - color = <LED_COLOR_ID_GREEN>; - gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */ - }; - }; - - reg_vcc5v: vcc5v { - /* board wide 5V supply directly from the USB-C socket */ - compatible = "regulator-fixed"; - regulator-name = "vcc-5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_vcc5v>; - enable-active-high; - gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */ - }; }; -&ehci1 { - status = "okay"; -}; - -/* USB 2 & 3 are on headers only. */ - &emac0 { - pinctrl-names = "default"; - pinctrl-0 = <&ext_rgmii_pins>; - phy-mode = "rgmii"; - phy-handle = <&ext_rgmii_phy>; phy-supply = <®_dcdce>; - allwinner,rx-delay-ps = <3100>; - allwinner,tx-delay-ps = <700>; - status = "okay"; -}; - -&mdio0 { - ext_rgmii_phy: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - }; }; &mmc0 { vmmc-supply = <®_dcdce>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ - bus-width = <4>; - status = "okay"; -}; - -&ohci1 { - status = "okay"; }; &r_rsb { @@ -211,44 +135,3 @@ vcc-ph-supply = <®_aldo1>; vcc-pi-supply = <®_aldo1>; }; - -&spi0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>; - - flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_ph_pins>; - status = "okay"; -}; - -&usbotg { - /* - * PHY0 pins are connected to a USB-C socket, but a role switch - * is not implemented: both CC pins are pulled to GND. - * The VBUS pins power the device, so a fixed peripheral mode - * is the best choice. - * The board can be powered via GPIOs, in this case port0 *can* - * act as a host (with a cable/adapter ignoring CC), as VBUS is - * then provided by the GPIOs. Any user of this setup would - * need to adjust the DT accordingly: dr_mode set to "host", - * enabling OHCI0 and EHCI0. - */ - dr_mode = "peripheral"; - status = "okay"; -}; - -&usbphy { - usb1_vbus-supply = <®_usb1_vbus>; - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts index 07424c28b696..959b6fd18483 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2021 Arm Ltd. */ diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts new file mode 100644 index 000000000000..00fe28caac93 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616-orangepi-zero.dtsi" + +/ { + model = "OrangePi Zero3"; + compatible = "xunlong,orangepi-zero3", "allwinner,sun50i-h618"; +}; + +&emac0 { + phy-supply = <®_dldo1>; +}; + +&ext_rgmii_phy { + motorcomm,clk-out-frequency-hz = <125000000>; +}; + +&mmc0 { + /* + * The schematic shows the card detect pin wired up to PF6, via an + * inverter, but it just doesn't work. + */ + broken-cd; + vmmc-supply = <®_dldo1>; +}; + +&r_i2c { + status = "okay"; + + axp313: pmic@36 { + compatible = "x-powers,axp313a"; + reg = <0x36>; + #interrupt-cells = <1>; + interrupt-controller; + interrupt-parent = <&pio>; + interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */ + + vin1-supply = <®_vcc5v>; + vin2-supply = <®_vcc5v>; + vin3-supply = <®_vcc5v>; + + regulators { + /* Supplies VCC-PLL, so needs to be always on. */ + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8"; + }; + + /* Supplies VCC-IO, so needs to be always on. */ + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <990000>; + regulator-name = "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-dram"; + }; + }; + }; +}; + +&pio { + vcc-pc-supply = <®_dldo1>; + vcc-pf-supply = <®_dldo1>; + vcc-pg-supply = <®_aldo1>; + vcc-ph-supply = <®_dldo1>; + vcc-pi-supply = <®_dldo1>; +}; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 41c9eb51d0ee..439497ab967d 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -153,7 +153,7 @@ interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; clock-names = "stmmaceth", "ptp_ref"; tx-fifo-depth = <16384>; @@ -171,7 +171,7 @@ interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; clock-names = "stmmaceth", "ptp_ref"; tx-fifo-depth = <16384>; @@ -189,7 +189,7 @@ interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; clock-names = "stmmaceth", "ptp_ref"; tx-fifo-depth = <16384>; @@ -331,6 +331,9 @@ ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xffe00000 0x100000>; }; pdma: dma-controller@ffda0000 { @@ -484,12 +487,6 @@ status = "disabled"; }; - usbphy0: usbphy@0 { - #phy-cells = <0>; - compatible = "usb-nop-xceiv"; - status = "okay"; - }; - usb0: usb@ffb00000 { compatible = "snps,dwc2"; reg = <0xffb00000 0x40000>; @@ -636,4 +633,9 @@ }; }; }; + + usbphy0: usbphy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 3037f58057c9..468fcc7da066 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -38,10 +38,10 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0 0x80000000 0 0>; }; ref_033v: regulator-v-ref { @@ -202,12 +202,12 @@ qspi_boot: partition@0 { label = "Boot and fpga data"; - reg = <0x0 0x03FE0000>; + reg = <0x0 0x04200000>; }; - qspi_rootfs: partition@3FE0000 { - label = "Root Filesystem - JFFS2"; - reg = <0x03FE0000 0x0C020000>; + root: partition@4200000 { + label = "Root Filesystem - UBIFS"; + reg = <0x04200000 0x0BE00000>; }; }; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts index f4cf30bac557..532164a6354c 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts @@ -38,10 +38,10 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0 0x80000000 0 0>; }; ref_033v: regulator-v-ref { @@ -103,9 +103,9 @@ status = "okay"; flash@0 { + reg = <0>; #address-cells = <1>; #size-cells = <1>; - reg = <0>; nand-bus-width = <16>; partition@0 { @@ -194,7 +194,7 @@ reg = <0x0 0x03FE0000>; }; - qspi_rootfs: partition@3FE0000 { + qspi_rootfs: partition@3fe0000 { label = "Root Filesystem - JFFS2"; reg = <0x03FE0000 0x0C020000>; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts index a8db58573954..ff413f8e3b07 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts @@ -29,7 +29,7 @@ linux,initrd-end = <0x125c8324>; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 6f61798a109f..8b6f57a94863 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_MESON) += amlogic-c3-c302x-aw409.dtb +dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-an400.dtb +dtb-$(CONFIG_ARCH_MESON) += amlogic-t7-a311d2-khadas-vim4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j110-rev-2.dtb diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi index 60ad4f3eef9d..998f5050795c 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -47,6 +47,15 @@ #clock-cells = <0>; }; + sm: secure-monitor { + compatible = "amlogic,meson-gxbb-sm"; + + pwrc: power-controller { + compatible = "amlogic,c3-pwrc"; + #power-domain-cells = <1>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -72,6 +81,32 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + periphs_pinctrl: pinctrl@4000 { + compatible = "amlogic,c3-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@4000 { + reg = <0x0 0x4000 0x0 0x004c>, + <0x0 0x4100 0x0 0x01de>; + reg-names = "mux", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 0 55>; + }; + }; + + gpio_intc: interrupt-controller@4080 { + compatible = "amlogic,meson-gpio-intc", + "amlogic,c3-gpio-intc"; + reg = <0x0 0x4080 0x0 0x0020>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <10 11 12 13 14 15 16 17 18 19 20 21>; + }; + uart_b: serial@7a000 { compatible = "amlogic,meson-s4-uart", "amlogic,meson-ao-uart"; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts new file mode 100644 index 000000000000..c05edebb90b5 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-an400.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "amlogic-t7.dtsi" + +/ { + model = "Amlogic A311D2 AN400 Development Board"; + compatible = "amlogic,an400", "amlogic,a311d2", "amlogic,t7"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart_a; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x00000000 0x00000000 0xE0000000 + 0x00000001 0x00000000 0x00000000 0x20000000>; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; +}; + +&uart_a { + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts new file mode 100644 index 000000000000..fffdab96b12e --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Wesion, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "amlogic-t7.dtsi" + +/ { + model = "Khadas vim4"; + compatible = "khadas,vim4", "amlogic,a311d2", "amlogic,t7"; + + aliases { + serial0 = &uart_a; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x2 0x0>; /* 8 GB */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@5000000 { + reg = <0x0 0x05000000 0x0 0x300000>; + no-map; + }; + + /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ + secmon_reserved_bl32: secmon@5300000 { + reg = <0x0 0x05300000 0x0 0x2000000>; + no-map; + }; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + +}; + +&uart_a { + status = "okay"; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; +}; diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi new file mode 100644 index 000000000000..1423d4a79156 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu100>; + }; + core1 { + cpu = <&cpu101>; + }; + core2 { + cpu = <&cpu102>; + }; + core3 { + cpu = <&cpu103>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu100: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x100>; + enable-method = "psci"; + }; + + cpu101: cpu@101{ + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x101>; + enable-method = "psci"; + }; + + cpu102: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x102>; + enable-method = "psci"; + }; + + cpu103: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x103>; + enable-method = "psci"; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + sm: secure-monitor { + compatible = "amlogic,meson-gxbb-sm"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@fff01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfff01000 0 0x1000>, + <0x0 0xfff02000 0 0x0100>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + apb4: bus@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x480000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + + uart_a: serial@78000 { + compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart"; + reg = <0x0 0x78000 0x0 0x18>; + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + }; + + }; +}; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts index 359589d1dfa9..df16eead2c80 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts @@ -280,7 +280,6 @@ assigned-clock-rates = <589824000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 0c49655cc90c..6d39faba7c3f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -1733,7 +1733,7 @@ clock-names = "xtal", "mpeg-clk"; }; - ao_pinctrl: pinctrl@14 { + ao_pinctrl: pinctrl { compatible = "amlogic,meson-g12a-aobus-pinctrl"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts index cf0a9be83fc4..fcd7e1d8e16f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-radxa-zero.dts @@ -145,7 +145,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts index 4fb31c2ba31c..0ad0c2b7dfef 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts @@ -209,7 +209,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts index b2bb94981838..8237aa1f05e9 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -166,7 +166,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts index 1b0c3881c6a1..13d478f9c891 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4-cm4io.dts @@ -65,7 +65,7 @@ compatible = "amlogic,axg-sound-card"; model = "BPI-CM4IO"; audio-aux-devs = <&tdmout_b>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", "TDMOUT_B IN 1", "FRDDR_B OUT 1", "TDMOUT_B IN 2", "FRDDR_C OUT 1", "TDM_B Playback", "TDMOUT_B OUT"; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi index 97e522921b06..86adc1423385 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi-cm4.dtsi @@ -56,7 +56,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - enable-gpio = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>; + enable-gpios = <&gpio_ao GPIOAO_3 GPIO_OPEN_DRAIN>; enable-active-high; regulator-always-on; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi index 83709787eb91..42f30112b56a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-bananapi.dtsi @@ -47,8 +47,6 @@ fan0: pwm-fan { compatible = "pwm-fan"; #cooling-cells = <2>; - cooling-min-state = <0>; - cooling-max-state = <3>; cooling-levels = <0 120 170 220>; pwms = <&pwm_cd 1 40000 0>; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts index 1fa6e75abd21..bb73e10b5e74 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gsking-x.dts @@ -55,7 +55,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts index afe375fa83ca..6eeedd54ab91 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts @@ -56,7 +56,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts index 5d96c1449050..3e826095e792 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts @@ -45,7 +45,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts index 29d642e746d4..276e95b34022 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-go-ultra.dts @@ -221,7 +221,7 @@ "Headphone", "Headphones", "Speaker", "Internal Speakers"; audio-aux-devs = <&tdmout_b>, <&tdmin_b>, <&speaker_amp>; - audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", + audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1", "TDM_B Playback", "TDMOUT_B OUT", "TDMIN_B IN 1", "TDM_B Capture", "TDMIN_B IN 4", "TDM_B Loopback", diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi index 24d0442dffb2..08fde513bac9 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi @@ -78,7 +78,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; @@ -241,7 +240,7 @@ * This signal should be handled by a USB specific power sequence * in order to reset the Hub when USB bus is powered down. */ - hog-0 { + usb-hub-hog { gpio-hog; gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts index 70919f40d597..e26f3e3258e1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2l.dts @@ -46,7 +46,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts index 0c7892600d56..098a3af6d381 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-ugoos-am6.dts @@ -40,7 +40,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi index 4e84ab87cc7d..5e7b9273b062 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi @@ -201,7 +201,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi index dafc841f7c16..18f7b730289e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi @@ -137,8 +137,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; - dai-link-0 { sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts index 7d94160f5802..1fd2e56e6b08 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts @@ -142,7 +142,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts index 63137ce3cb9d..4aab1ab705b4 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts @@ -149,7 +149,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts index 01356437a077..e6d2de7c45a9 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts @@ -184,7 +184,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi index 66daf3af34c3..e8303089bff6 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi @@ -116,7 +116,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts index 58733017eda8..af9ea32a2876 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts @@ -23,7 +23,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts index 505ffcd8eb76..e1b74b174915 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts @@ -56,7 +56,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts index 213a0705ebdc..a29b49f051ae 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts @@ -130,7 +130,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts index ff906becd2ab..c0d6eb55100a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-p241.dts @@ -135,7 +135,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts index 02f81839d4e3..fea65f20523a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -74,7 +74,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts index 6c4e68e0e625..2825db91e462 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts @@ -167,7 +167,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts index 82bfabfbd39c..27093e6ac9e2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts @@ -149,7 +149,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index 74897a154891..860f307494c5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -157,7 +157,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts index 236c0a144142..7d525bdb0e06 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts @@ -94,7 +94,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts index 50137aafab10..50d49aec41bd 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-rbox-pro.dts @@ -109,7 +109,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi index c9705941e4ab..514a6dd4b124 100644 --- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi @@ -189,7 +189,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts index d1debccdc1c2..7991fafed05c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air-gbit.dts @@ -29,7 +29,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts index c94f2870b78b..6e34fd80ed71 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-a95xf3-air.dts @@ -29,7 +29,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts index 0f6660e68e72..85d7e7110596 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-h96-max.dts @@ -29,7 +29,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts index 74088e7280fe..846a2d6c20e5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts @@ -19,8 +19,6 @@ fan0: pwm-fan { compatible = "pwm-fan"; #cooling-cells = <2>; - cooling-min-state = <0>; - cooling-max-state = <3>; cooling-levels = <0 120 170 220>; pwms = <&pwm_cd 1 40000 0>; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi index 2fce44939f45..cdb80e0a7718 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid.dtsi @@ -181,7 +181,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts index 9068a334ea57..cf4f78e6bd21 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts @@ -247,7 +247,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts index 7e1a74046ba5..fda0630c235b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air-gbit.dts @@ -29,7 +29,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts index cd93d798f2a3..9ea969255b4f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-x96-air.dts @@ -29,7 +29,6 @@ assigned-clock-rates = <294912000>, <270950400>, <393216000>; - status = "okay"; dai-link-0 { sound-dai = <&frddr_a>; diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts index 26b0f1b3cea6..901a7fc83307 100644 --- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT +// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright (c) 2022, Arm Limited. All rights reserved. * Copyright (c) 2022, Linaro Limited. All rights reserved. diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts index e3146747c2d9..10d265be0c02 100644 --- a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts +++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT +// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright (c) 2022, Arm Limited. All rights reserved. * Copyright (c) 2022, Linaro Limited. All rights reserved. diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi index 21f1f952e985..6ad7829f9e28 100644 --- a/arch/arm64/boot/dts/arm/corstone1000.dtsi +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 or MIT +// SPDX-License-Identifier: GPL-2.0 OR MIT /* * Copyright (c) 2022, Arm Limited. All rights reserved. * Copyright (c) 2022, Linaro Limited. All rights reserved. @@ -43,10 +43,10 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x1c010000 0x1000>, - <0x1c02f000 0x2000>, - <0x1c04f000 0x1000>, - <0x1c06f000 0x2000>; + reg = <0x1c010000 0x1000>, + <0x1c02f000 0x2000>, + <0x1c04f000 0x1000>, + <0x1c06f000 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; @@ -77,14 +77,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | - IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | - IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; }; uartclk: uartclk { diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi index e4a3c7dbcc20..17fba3bc99cd 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv3.dtsi @@ -12,11 +12,11 @@ #size-cells = <1>; ranges = <0x0 0x0 0x2f000000 0x100000>; interrupt-controller; - reg = <0x0 0x2f000000 0x0 0x10000>, - <0x0 0x2f100000 0x0 0x200000>, - <0x0 0x2c000000 0x0 0x2000>, - <0x0 0x2c010000 0x0 0x2000>, - <0x0 0x2c02f000 0x0 0x2000>; + reg = <0x0 0x2f000000 0x0 0x10000>, + <0x0 0x2f100000 0x0 0x200000>, + <0x0 0x2c000000 0x0 0x2000>, + <0x0 0x2c010000 0x0 0x2000>, + <0x0 0x2c02f000 0x0 0x2000>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; its: msi-controller@2f020000 { diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi index f549bda8c48c..2f124b027bbf 100644 --- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi @@ -577,7 +577,7 @@ #size-cells = <0>; }; - hsspi: spi@1000{ + hsspi: spi@1000 { #address-cells = <1>; #size-cells = <0>; compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0"; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts index 699f7742ce7f..1d314f17bbdd 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts @@ -114,7 +114,7 @@ reg = <0x04000000 0x06400000>; /* 100MB */ }; - partition@a400000{ + partition@a400000 { label = "ncustfs"; reg = <0x0a400000 0x35c00000>; /* 860MB */ }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts index a41facd7d79b..66471a25e4ac 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958802a802x.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) /* *Copyright(c) 2018 Broadcom */ diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi index 82a24711d0d8..cdd709491f01 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-board-base.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) /* * Copyright(c) 2016-2018 Broadcom */ diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi index 33a472ab17e8..663e51756746 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-pcie.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) /* *Copyright(c) 2018 Broadcom */ diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi index 5401a646c840..ac4f7b8f9273 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-usb.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause) +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) /* *Copyright(c) 2018 Broadcom */ diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 7aece79bf882..f049687d6b96 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -565,7 +565,7 @@ iommus = <&smmu 0x6000 0x0000>; }; - enet: ethernet@340000{ + enet: ethernet@340000 { compatible = "brcm,amac"; reg = <0x00340000 0x1000>; reg-names = "amac_base"; diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi index e4ed788413fe..d163891cd399 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi @@ -137,7 +137,6 @@ /* Receiver */ "RCV", "HPOUT3L", "RCV", "HPOUT3R"; - status = "okay"; }; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 5ea8bda2bfa6..54ed5167d0f6 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -138,10 +138,10 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x11001000 0x1000>, - <0x11002000 0x2000>, - <0x11004000 0x2000>, - <0x11006000 0x2000>; + reg = <0x11001000 0x1000>, + <0x11002000 0x2000>, + <0x11004000 0x2000>, + <0x11006000 0x2000>; }; pdma0: dma-controller@10e10000 { diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts index 101f51bf565a..bc1815f6ada2 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts @@ -49,6 +49,12 @@ }; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_tout3>; + status = "okay"; +}; + &serial_0 { pinctrl-0 = <&uart0_bus_dual>; status = "okay"; diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index d3c5cdeff47f..b228cd7e351e 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -313,7 +313,7 @@ }; }; - pinctrl_aud: pinctrl@19c60000{ + pinctrl_aud: pinctrl@19c60000 { compatible = "samsung,exynosautov9-pinctrl"; reg = <0x19c60000 0x1000>; }; @@ -1560,6 +1560,17 @@ samsung,syscon-phandle = <&pmu_system_controller>; samsung,cluster-index = <1>; }; + + pwm: pwm@103f0000 { + compatible = "samsung,exynosautov9-pwm", + "samsung,exynos4210-pwm"; + reg = <0x103f0000 0x100>; + samsung,pwm-outputs = <0>, <1>, <2>, <3>; + #pwm-cells = <3>; + clocks = <&xtcxo>; + clock-names = "timers"; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index a750be13ace8..c6872b7e9471 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7901.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7905-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb @@ -93,6 +94,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb @@ -100,6 +102,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw71xx-2x.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw73xx-2x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw7905-2x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb @@ -141,24 +146,31 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb -imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo +imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo +imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo imx8mm-venice-gw72xx-0x-rs232-rts-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo imx8mm-venice-gw72xx-0x-rs422-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs422.dtbo imx8mm-venice-gw72xx-0x-rs485-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs485.dtbo imx8mm-venice-gw73xx-0x-imx219-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-imx219.dtbo +imx8mm-venice-gw73xx-0x-rpidsi-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rpidsi.dtbo imx8mm-venice-gw73xx-0x-rs232-rts-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs232-rts.dtbo imx8mm-venice-gw73xx-0x-rs422-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs422.dtbo imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo +imx8mp-venice-gw74xx-rpidsi-dtbs := imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-rpidsi.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-imx219.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rpidsi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs232-rts.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs422.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-rs485.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-imx219.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rpidsi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts index 73eb6061c73e..af9194eca556 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dts @@ -56,10 +56,14 @@ }; &enetc_port2 { + nvmem-cells = <&base_mac_address 2>; + nvmem-cell-names = "mac-address"; status = "okay"; }; &enetc_port3 { + nvmem-cells = <&base_mac_address 3>; + nvmem-cell-names = "mac-address"; status = "okay"; }; @@ -80,6 +84,8 @@ managed = "in-band-status"; phy-handle = <&qsgmii_phy0>; phy-mode = "qsgmii"; + nvmem-cells = <&base_mac_address 4>; + nvmem-cell-names = "mac-address"; status = "okay"; }; @@ -88,6 +94,8 @@ managed = "in-band-status"; phy-handle = <&qsgmii_phy1>; phy-mode = "qsgmii"; + nvmem-cells = <&base_mac_address 5>; + nvmem-cell-names = "mac-address"; status = "okay"; }; @@ -96,6 +104,8 @@ managed = "in-band-status"; phy-handle = <&qsgmii_phy2>; phy-mode = "qsgmii"; + nvmem-cells = <&base_mac_address 6>; + nvmem-cell-names = "mac-address"; status = "okay"; }; @@ -104,6 +114,8 @@ managed = "in-band-status"; phy-handle = <&qsgmii_phy3>; phy-mode = "qsgmii"; + nvmem-cells = <&base_mac_address 7>; + nvmem-cell-names = "mac-address"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts index 7cd29ab970d9..1f34c7553459 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts @@ -55,5 +55,7 @@ &enetc_port1 { phy-handle = <&phy0>; phy-mode = "rgmii-id"; + nvmem-cells = <&base_mac_address 0>; + nvmem-cell-names = "mac-address"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts index 113b1df74bf8..aac41192caa1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts @@ -36,10 +36,14 @@ }; &enetc_port2 { + nvmem-cells = <&base_mac_address 2>; + nvmem-cell-names = "mac-address"; status = "okay"; }; &enetc_port3 { + nvmem-cells = <&base_mac_address 3>; + nvmem-cell-names = "mac-address"; status = "okay"; }; @@ -52,6 +56,8 @@ managed = "in-band-status"; phy-handle = <&phy0>; phy-mode = "sgmii"; + nvmem-cells = <&base_mac_address 0>; + nvmem-cell-names = "mac-address"; status = "okay"; }; @@ -60,6 +66,8 @@ managed = "in-band-status"; phy-handle = <&phy1>; phy-mode = "sgmii"; + nvmem-cells = <&base_mac_address 1>; + nvmem-cell-names = "mac-address"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts index 9b5e92fb753e..a4421db3784e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts @@ -43,5 +43,7 @@ &enetc_port1 { phy-handle = <&phy1>; phy-mode = "rgmii-id"; + nvmem-cells = <&base_mac_address 1>; + nvmem-cell-names = "mac-address"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts index 4ab17b984b03..8b65af4a7147 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -92,6 +92,8 @@ phy-handle = <&phy0>; phy-mode = "sgmii"; managed = "in-band-status"; + nvmem-cells = <&base_mac_address 0>; + nvmem-cell-names = "mac-address"; status = "okay"; }; @@ -154,6 +156,21 @@ label = "bootloader environment"; }; }; + + otp-1 { + compatible = "user-otp"; + + nvmem-layout { + compatible = "kontron,sl28-vpd"; + + serial_number: serial-number { + }; + + base_mac_address: base-mac-address { + #nvmem-cell-cells = <1>; + }; + }; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 9cbb31191cf9..eefe3577d94e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -28,6 +28,12 @@ reg = <0x0>; enable-method = "psci"; clocks = <&clockgen QORIQ_CLK_CMUX 0>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PW20>; #cooling-cells = <2>; @@ -39,6 +45,12 @@ reg = <0x1>; enable-method = "psci"; clocks = <&clockgen QORIQ_CLK_CMUX 0>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PW20>; #cooling-cells = <2>; @@ -48,6 +60,9 @@ compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi index 52c5a43b30a0..e2c94da6d6e8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi @@ -69,7 +69,7 @@ mdio-parent-bus = <&emdio1>; reg = <0x54 1>; /* BRDCFG4 */ mux-mask = <0xe0>; /* EMI1_MDIO */ - #address-cells=<1>; + #address-cells = <1>; #size-cells = <0>; /* Child MDIO buses, one for each riser card: diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index bd5d771637ca..9b1b522517f8 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -684,15 +684,15 @@ }; /* Messaging Units */ -&mu_m0{ +&mu_m0 { status = "okay"; }; -&mu1_m0{ +&mu1_m0 { status = "okay"; }; -&mu2_m0{ +&mu2_m0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index e62a43591361..fc1a5d34382b 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -157,12 +157,10 @@ conn_subsys: bus@5b000000 { usbotg3_cdns3: usb@5b120000 { compatible = "cdns,usb3"; - reg = <0x5b130000 0x10000>, /* memory area for HOST registers */ - <0x5b140000 0x10000>, /* memory area for DEVICE registers */ - <0x5b120000 0x10000>; /* memory area for OTG/DRD registers */ - reg-names = "xhci", "dev", "otg"; - #address-cells = <1>; - #size-cells = <1>; + reg = <0x5b120000 0x10000>, /* memory area for OTG/DRD registers */ + <0x5b130000 0x10000>, /* memory area for HOST registers */ + <0x5b140000 0x10000>; /* memory area for DEVICE registers */ + reg-names = "otg", "xhci", "dev"; interrupt-parent = <&gic>; interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index f542476187b3..b9157ca08b03 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -362,7 +362,6 @@ }; &lpspi3 { - fsl,spi-num-chipselects = <1>; fsl,spi-only-use-cs1-sel; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpspi3>; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi index 6881330ab4c6..e2eeddf38aa3 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -36,22 +36,22 @@ }; &lpuart0 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart"; interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; }; &lpuart1 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart"; interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; }; &lpuart2 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart"; interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; }; &lpuart3 { - compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart"; interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index bc531175ff76..b10e2a703a44 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -141,11 +141,11 @@ pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - camera@3c { + camera@10 { compatible = "ovti,ov5640"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x3c>; + reg = <0x10>; clocks = <&clk IMX8MM_CLK_CLKO1>; clock-names = "xclk"; assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; @@ -289,7 +289,6 @@ }; &usbotg2 { - pinctrl-names = "default"; disable-over-current; dr_mode = "host"; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts index 74a7b0cc10c2..905c98cb080d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dts @@ -16,4 +16,135 @@ chosen { stdout-path = &uart2; }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + + reg_hdmi: regulator-hdmi-dvdd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_hdmi>; + regulator-name = "hdmi_pwr_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <70000>; + regulator-always-on; + }; + + sound-hdmi { + compatible = "simple-audio-card"; + simple-audio-card,name = "sound-hdmi"; + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { + sound-dai = <&sai5>; + system-clock-direction-out; + }; + + simple-audio-card,codec { + sound-dai = <&adv_bridge>; + }; + }; +}; + +&i2c2 { + adv_bridge: hdmi@3d { + compatible = "adi,adv7535"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_bridge>; + reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; + reg-names = "main", "cec", "edid", "packet"; + adi,dsi-lanes = <4>; + avdd-supply = <®_hdmi>; + a2vdd-supply = <®_hdmi>; + dvdd-supply = <®_hdmi>; + pvdd-supply = <®_hdmi>; + v1p2-supply = <®_hdmi>; + v3p3-supply = <®_hdmi>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7535_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + adv7535_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <20000000>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&iomuxc { + pinctrl_hdmi_bridge: hdmibridgegrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_reg_hdmi: reghdmigrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 201325f566cb..f264102bdb27 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -112,7 +112,7 @@ rohm,reset-snvs-powered; #clock-cells = <0>; - clocks = <&osc_32k 0>; + clocks = <&osc_32k>; clock-output-names = "clk-32k-out"; regulators { diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts index b2e8967e9687..c8ff70212602 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Copyright (c) 2021 emtrion GmbH // Author: Frank Erdrich <frank.erdrich@emtrion.com> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi index 5028f232b6bd..d897a8527335 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Copyright (C) 2021 emtrion GmbH // Author: Frank Erdrich <frank.erdrich@emtrion.com> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi index 4e9e58acd262..af7dc8d1f5f1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Copyright 2018 NXP // Copyright (C) 2021 emtrion GmbH @@ -108,8 +108,6 @@ }; &iomuxc { - pinctrl-names = "default"; - pinctrl_csi_pwn: csi-pwn-grp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 @@ -411,7 +409,7 @@ regulators { buck1_reg: BUCK1 { - regulator-name = "BUCK1"; + regulator-name = "buck1"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-boot-on; @@ -420,7 +418,7 @@ }; buck2_reg: BUCK2 { - regulator-name = "BUCK2"; + regulator-name = "buck2"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; regulator-boot-on; @@ -432,7 +430,7 @@ buck3_reg: BUCK3 { // BUCK5 in datasheet - regulator-name = "BUCK3"; + regulator-name = "buck3"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1350000>; regulator-boot-on; @@ -441,7 +439,7 @@ buck4_reg: BUCK4 { // BUCK6 in datasheet - regulator-name = "BUCK4"; + regulator-name = "buck4"; regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -450,7 +448,7 @@ buck5_reg: BUCK5 { // BUCK7 in datasheet - regulator-name = "BUCK5"; + regulator-name = "buck5"; regulator-min-microvolt = <1605000>; regulator-max-microvolt = <1995000>; regulator-boot-on; @@ -459,7 +457,7 @@ buck6_reg: BUCK6 { // BUCK8 in datasheet - regulator-name = "BUCK6"; + regulator-name = "buck6"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1400000>; regulator-boot-on; @@ -467,7 +465,7 @@ }; ldo1_reg: LDO1 { - regulator-name = "LDO1"; + regulator-name = "ldo1"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <1900000>; regulator-boot-on; @@ -475,7 +473,7 @@ }; ldo2_reg: LDO2 { - regulator-name = "LDO2"; + regulator-name = "ldo2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; @@ -483,7 +481,7 @@ }; ldo3_reg: LDO3 { - regulator-name = "LDO3"; + regulator-name = "ldo3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -491,7 +489,7 @@ }; ldo4_reg: LDO4 { - regulator-name = "LDO4"; + regulator-name = "ldo4"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1800000>; regulator-boot-on; @@ -499,7 +497,7 @@ }; ldo6_reg: LDO6 { - regulator-name = "LDO6"; + regulator-name = "ldo6"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <1800000>; regulator-boot-on; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index df8e808ac473..e31ab8b4f54f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -380,6 +380,11 @@ }; }; + +&csi { + status = "okay"; +}; + &i2c3 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -393,12 +398,47 @@ #gpio-cells = <2>; vcc-supply = <&buck4_reg>; }; + + camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_camera>; + clocks = <&clk IMX8MM_CLK_CLKO1>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MM_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <24000000>; + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + + port { + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&imx8mm_mipi_csi_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; }; &lcdif { status = "okay"; }; +&mipi_csi { + status = "okay"; + + ports { + port@0 { + imx8mm_mipi_csi_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + }; +}; + &mipi_dsi { samsung,esc-clock-frequency = <10000000>; status = "okay"; @@ -684,4 +724,12 @@ MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 >; }; + + pinctrl_camera: cameragrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts index 479948f8a4b7..92e62fe31929 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phyboard-polis-rdk.dts @@ -140,6 +140,26 @@ }; }; +/* TPM */ +&ecspi2 { + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + tpm: tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm>; + reg = <0>; + spi-max-frequency = <43000000>; + }; +}; + &gpio1 { gpio-line-names = "", "LED_RED", "WDOG_INT", "X_RTC_INT", "", "", "", "RESET_ETHPHY", @@ -170,8 +190,11 @@ &i2c4 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; /* PCIe */ @@ -333,6 +356,15 @@ >; }; + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x80 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x80 + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x80 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00 + >; + }; + pinctrl_fan: fan0grp { fsl,pins = < MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x16 @@ -346,6 +378,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e2 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e2 + >; + }; + pinctrl_leds: leds1grp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16 @@ -368,6 +407,12 @@ >; }; + pinctrl_tpm: tpmgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x00 @@ -388,8 +433,8 @@ pinctrl_uart3: uart3grp { fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi index 847f08537b48..6069678244f3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-phycore-som.dtsi @@ -102,6 +102,8 @@ status = "okay"; som_flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <80000000>; @@ -149,7 +151,6 @@ regulator-max-microvolt = <3300000>; regulator-min-microvolt = <1800000>; regulator-name = "NVCC_SD2 (LDO2)"; - vselect-en; regulator-state-mem { regulator-off-in-suspend; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi index 2b83a5258ec6..d7830df5b6f9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som.dtsi @@ -142,7 +142,7 @@ rohm,reset-snvs-powered; #clock-cells = <0>; - clocks = <&osc_32k 0>; + clocks = <&osc_32k>; clock-output-names = "clk-32k-out"; regulators { diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rpidsi.dtso b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rpidsi.dtso new file mode 100644 index 000000000000..e0768d408c3b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x-rpidsi.dtso @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include <dt-bindings/gpio/gpio.h> + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm"; + + panel { + compatible = "powertip,ph800480t013-idf02"; + power-supply = <&attiny>; + backlight = <&attiny>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + + attiny: regulator@45 { + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + reg = <0x45>; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,burst-clock-frequency = <891000000>; + samsung,esc-clock-frequency = <54000000>; + samsung,pll-clock-frequency = <27000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + bridge@0 { + compatible = "toshiba,tc358762"; + reg = <0>; + vddc-supply = <&attiny>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rpidsi.dtso b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rpidsi.dtso new file mode 100644 index 000000000000..e0768d408c3b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rpidsi.dtso @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include <dt-bindings/gpio/gpio.h> + +#include "imx8mm-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mm-gw73xx-0x", "fsl,imx8mm"; + + panel { + compatible = "powertip,ph800480t013-idf02"; + power-supply = <&attiny>; + backlight = <&attiny>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + + attiny: regulator@45 { + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + reg = <0x45>; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,burst-clock-frequency = <891000000>; + samsung,esc-clock-frequency = <54000000>; + samsung,pll-clock-frequency = <27000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + bridge@0 { + compatible = "toshiba,tc358762"; + reg = <0>; + vddc-supply = <&attiny>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 0ec2ce3dd721..ed46d4f3e66f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -242,6 +242,22 @@ }; }; +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + &ddrc { operating-points-v2 = <&ddrc_opp_table>; @@ -496,7 +512,7 @@ interrupts = <20 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; #clock-cells = <0>; - clocks = <&osc_32k 0>; + clocks = <&osc_32k>; clock-output-names = "clk-32k-out"; regulators { @@ -511,7 +527,7 @@ }; /* vdd_arm: 0.805-1.0V (typ=0.9V) */ - BUCK2 { + buck2: BUCK2 { regulator-name = "buck2"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1300000>; @@ -773,12 +789,21 @@ /* SDIO WiFi */ &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <4>; non-removable; vmmc-supply = <®_wifi>; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + wifi@0 { + compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; + reg = <0>; + }; }; /* microSD */ @@ -1038,6 +1063,28 @@ >; }; + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 03cd29063312..b318c2d08038 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -431,7 +431,7 @@ interrupts = <8 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; #clock-cells = <0>; - clocks = <&osc_32k 0>; + clocks = <&osc_32k>; clock-output-names = "clk-32k-out"; regulators { @@ -714,12 +714,21 @@ /* SDIO WiFi */ &usdhc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; bus-width = <4>; non-removable; vmmc-supply = <®_wifi>; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + wifi@0 { + compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; + reg = <0>; + }; }; /* eMMC */ @@ -992,6 +1001,28 @@ >; }; + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts index 07b07dc954fd..0e102a12bca4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts @@ -416,7 +416,7 @@ interrupts = <8 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; #clock-cells = <0>; - clocks = <&osc_32k 0>; + clocks = <&osc_32k>; clock-output-names = "clk-32k-out"; regulators { diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts index d5b716855812..6afbabc89c02 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts @@ -460,7 +460,7 @@ interrupts = <8 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; #clock-cells = <0>; - clocks = <&osc_32k 0>; + clocks = <&osc_32k>; clock-output-names = "clk-32k-out"; regulators { @@ -640,6 +640,8 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + cts-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -650,13 +652,6 @@ status = "okay"; }; -/* off-board RS232 */ -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - &usbotg1 { dr_mode = "host"; disable-over-current; @@ -818,6 +813,8 @@ fsl,pins = < MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x140 /* CTS# in */ + MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x140 /* RTS# out */ >; }; @@ -828,13 +825,6 @@ >; }; - pinctrl_uart3: uart3grp { - fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 - >; - }; - pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7905-0x.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7905-0x.dts new file mode 100644 index 000000000000..914753f062cd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7905-0x.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mm.dtsi" +#include "imx8mm-venice-gw700x.dtsi" +#include "imx8mm-venice-gw7905.dtsi" + +/ { + model = "Gateworks Venice GW7905-0x i.MX8MM Development Kit"; + compatible = "gateworks,imx8mm-gw7905-0x", "fsl,imx8mm"; + + chosen { + stdout-path = &uart2; + }; +}; + +/* Disable SOM interfaces not used on baseboard */ +&fec1 { + status = "disabled"; +}; + +&usdhc1 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7905.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7905.dtsi new file mode 100644 index 000000000000..5eb92005195c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7905.dtsi @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> + +/ { + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pcie0_refclk: clock-pcie0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + regulator-name = "usb2_vbus"; + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "SD2_3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "gpioa", "gpiob", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "pci_usb_sel", + "", "", "", "pci_wdis#", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", + "gpioc", "gpiod", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + eeprom@52 { + compatible = "atmel,24c32"; + reg = <0x52>; + pagesize = <32>; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* USB1 - Type C front panel SINK port J14 */ +&usbotg1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +/* USB2 4-port USB3.0 HUB: + * P1 - USBC connector (host only) + * P2 - USB2 test connector + * P3 - miniPCIe full card + * P4 - miniPCIe half card + */ +&usbotg2 { + dr_mode = "host"; + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000040 /* GPIOA */ + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x40000040 /* GPIOB */ + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000106 /* PCI_USBSEL */ + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000106 /* PCIE_WDIS# */ + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000040 /* GPIOD */ + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */ + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x6 /* LEDR */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_pcie0: pciegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x106 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106 + >; + }; + + pinctrl_reg_usb2_en: regusb2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x6 /* USBHUB_RST# (ext p/u) */ + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x140 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x140 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x140 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 1a647d4072ba..236fe44f779d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1344,8 +1344,8 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ - 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ + <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; num-viewport = <4>; interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts index 1392ce02587b..35b8d2060cd9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-kit.dts @@ -16,4 +16,137 @@ chosen { stdout-path = &uart2; }; + + connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + + reg_hdmi: regulator-hdmi-dvdd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_hdmi>; + regulator-name = "hdmi_pwr_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <70000>; + regulator-always-on; + }; + + sound-hdmi { + compatible = "simple-audio-card"; + simple-audio-card,name = "sound-hdmi"; + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { + sound-dai = <&sai5>; + system-clock-direction-out; + }; + + simple-audio-card,codec { + sound-dai = <&adv_bridge>; + }; + }; +}; + +&i2c2 { + adv_bridge: hdmi@3d { + compatible = "adi,adv7535"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_bridge>; + reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; + reg-names = "main", "cec", "edid", "packet"; + adi,dsi-lanes = <4>; + avdd-supply = <®_hdmi>; + a2vdd-supply = <®_hdmi>; + dvdd-supply = <®_hdmi>; + pvdd-supply = <®_hdmi>; + v1p2-supply = <®_hdmi>; + v3p3-supply = <®_hdmi>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7535_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + adv7535_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&lcdif { + assigned-clocks = <&clk IMX8MN_VIDEO_PLL1>; + assigned-clock-rates = <594000000>; + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <20000000>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MN_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&iomuxc { + pinctrl_hdmi_bridge: hdmibridgegrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_reg_hdmi: reghdmigrp { + fsl,pins = < + MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index 8a4369d38903..90073b16536f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -121,7 +121,7 @@ interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; #clock-cells = <0>; - clocks = <&osc_32k 0>; + clocks = <&osc_32k>; clock-output-names = "clk-32k-out"; regulators { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi index 8e100e71b8d2..22a754d438f1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi @@ -92,7 +92,7 @@ rohm,reset-snvs-powered; #clock-cells = <0>; - clocks = <&osc_32k 0>; + clocks = <&osc_32k>; clock-output-names = "clk-32k-out"; regulators { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index 5110d59b719f..cc2ff59ac53b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -60,7 +60,7 @@ rohm,reset-snvs-powered; #clock-cells = <0>; - clocks = <&osc_32k 0>; + clocks = <&osc_32k>; clock-output-names = "clk-32k-out"; regulators { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index 4839a962a170..0b71f50d936e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -40,7 +40,7 @@ interrupts = <3 IRQ_TYPE_LEVEL_LOW>; regulators { - buck1: BUCK1{ + buck1: BUCK1 { regulator-name = "VDD_SOC"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <950000>; @@ -59,7 +59,7 @@ regulator-ramp-delay = <3125>; }; - buck4: BUCK4{ + buck4: BUCK4 { regulator-name = "VDD_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -67,7 +67,7 @@ regulator-always-on; }; - buck5: BUCK5{ + buck5: BUCK5 { regulator-name = "VDD_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 1443857bfa5f..0e60995a5727 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -23,6 +23,18 @@ }; }; + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7533_out>; + }; + }; + }; + memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0x80000000>; @@ -163,10 +175,45 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; - scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; + hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; + reg-names = "main", "cec", "edid", "packet"; + adi,dsi-lanes = <4>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7533_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + adv7533_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + + }; + }; + ptn5110: tcpc@50 { compatible = "nxp,ptn5110"; pinctrl-names = "default"; @@ -212,6 +259,65 @@ gpio-controller; #gpio-cells = <2>; }; + + camera@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_camera>; + clocks = <&clk IMX8MN_CLK_CLKO1>; + clock-names = "xclk"; + assigned-clocks = <&clk IMX8MN_CLK_CLKO1>; + assigned-clock-parents = <&clk IMX8MN_CLK_24M>; + assigned-clock-rates = <24000000>; + powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + + port { + ov5640_to_mipi_csi2: endpoint { + remote-endpoint = <&imx8mn_mipi_csi_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&isi { + status = "okay"; +}; + +&mipi_csi { + status = "okay"; + + ports { + port@0 { + imx8mn_mipi_csi_in: endpoint { + remote-endpoint = <&ov5640_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <10000000>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&adv7533_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; }; &sai2 { @@ -326,6 +432,14 @@ }; &iomuxc { + pinctrl_camera: cameragrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi index 31ae338b7ed9..391ca5516e4c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi @@ -208,12 +208,14 @@ read-only; reg = <0x53>; pagesize = <16>; + vcc-supply = <®_vcc3v3>; }; eeprom0: eeprom@57 { compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; + vcc-supply = <®_vcc3v3>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index 406a711486da..a7a57442cb81 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -1,11 +1,14 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* + * Supports Symphony evaluation board versions >= 1.4a. + * * Copyright 2019-2020 Variscite Ltd. * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org> */ /dts-v1/; +#include <dt-bindings/usb/pd.h> #include "imx8mn-var-som.dtsi" / { @@ -100,14 +103,26 @@ }; }; + /* + * For Symphony board version <= 1.4, the PTN5150 IRQ pin is connected + * to GPIO1_IO11 on the SoM (R106 present, R132 absent). From Symphony + * board version >= 1.4a, the PTN5150 ID pin is connected to GPIO1_IO11 + * on the SoM (R106 absent, R132 present). + */ extcon_usbotg1: typec@3d { compatible = "nxp,ptn5150"; reg = <0x3d>; interrupt-parent = <&gpio1>; - interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ptn5150>; status = "okay"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; }; }; @@ -148,8 +163,21 @@ }; &usbotg1 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; disable-over-current; - extcon = <&extcon_usbotg1>, <&extcon_usbotg1>; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + status = "okay"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&typec1_dr_sw>; + }; + }; }; &iomuxc { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 2ddba4213001..08746fb82561 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -429,7 +429,7 @@ interrupts = <8 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; #clock-cells = <0>; - clocks = <&osc_32k 0>; + clocks = <&osc_32k>; clock-output-names = "clk-32k-out"; regulators { @@ -667,12 +667,21 @@ /* SDIO WiFi */ &usdhc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; bus-width = <4>; non-removable; vmmc-supply = <®_wifi>; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + wifi@0 { + compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac"; + reg = <0>; + }; }; /* eMMC */ @@ -923,6 +932,28 @@ >; }; + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts index b4409349eb3f..28db9349ed62 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts @@ -129,7 +129,7 @@ nxp,dvs-standby-voltage = <850000>; }; - buck4: BUCK4{ + buck4: BUCK4 { regulator-name = "BUCK4"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; @@ -137,7 +137,7 @@ regulator-always-on; }; - buck5: BUCK5{ + buck5: BUCK5 { regulator-name = "BUCK5"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; @@ -226,7 +226,6 @@ compatible = "haoyu,hym8563"; reg = <0x51>; #clock-cells = <0>; - clock-frequency = <32768>; clock-output-names = "xin32k"; interrupt-parent = <&gpio2>; interrupts = <11 IRQ_TYPE_EDGE_FALLING>; @@ -355,28 +354,6 @@ >; }; - pinctrl_fec: fecgrp { - fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f - MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f - MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f - MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f - MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f - MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x1f - MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f - MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 - >; - }; - pinctrl_gpio_led: gpioledgrp { fsl,pins = < MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts new file mode 100644 index 000000000000..0b0c95432bdc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de> + */ + +/dts-v1/; + +#include "imx8mp-debix-som-a.dtsi" + +/ { + model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08"; + compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a", + "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + }; + + chosen { + stdout-path = &uart2; + }; + + reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "BB_VDD3V3"; + /* Required timings for ethernet phy's */ + startup-delay-us = <50000>; + off-on-delay-us = <110000>; + gpio = <&expander0 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_baseboard_vdd5v0: regulator-baseboard-vdd5v0 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "BB_VDD5V"; + gpio = <&expander0 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + regulator-som-vdd1v8 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "SOM_VDD1V8_SW"; + gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + regulator-som-vdd3v3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "SOM_VDD3V3_SW"; + gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + regulator-vbus-usb20 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "USB20_5V"; + gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_baseboard_vdd5v0>; + }; + + regulator-vbus-usb30 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "USB30_5V"; + gpio = <&expander1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_baseboard_vdd5v0>; + }; + + reg_vdd5v0: regulator-vdd5v0 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "VDD_5V"; + gpio = <&expander0 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + nvmem-cells = <ðmac1>; + nvmem-cell-names = "mac-address"; + phy-supply = <®_baseboard_vdd3v3>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + reset-assert-us = <20000>; + reset-deassert-us = <150000>; + eee-broken-1000t; + realtek,clkout-disable; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + nvmem-cells = <ðmac2>; + nvmem-cell-names = "mac-address"; + phy-supply = <®_baseboard_vdd3v3>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; + reset-assert-us = <20000>; + reset-deassert-us = <150000>; + eee-broken-1000t; + realtek,clkout-disable; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_vdd5v0>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_vdd5v0>; + status = "okay"; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&i2c4 { + expander0: gpio@20 { + compatible = "nxp,pca9535"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <0x02>; + }; + + expander1: gpio@23 { + compatible = "nxp,pca9535"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <0x02>; + + /* + * Since USB1 is bound to peripheral mode we need to ensure + * that VBUS is turned off. + */ + usb30-otg-hog { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "USB30_OTG_EN"; + }; + }; + + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + #clock-cells = <0>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + #address-cells = <1>; + #size-cells = <0>; + + /* MACs stored in ASCII */ + ethmac1: mac-address@0 { + reg = <0x0 0xc>; + }; + + ethmac2: mac-address@c { + reg = <0xc 0xc>; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* Debug */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* 2.x hub on port 1 */ + usb_hub_2_x: hub@1 { + compatible = "usb5e3,610"; + reg = <1>; + reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>; + vdd-supply = <®_vdd5v0>; + peer-hub = <&usb_hub_3_x>; + }; + + /* 3.x hub on port 2 */ + usb_hub_3_x: hub@2 { + compatible = "usb5e3,620"; + reg = <2>; + reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>; + vdd-supply = <®_vdd5v0>; + peer-hub = <&usb_hub_2_x>; + }; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +/* µSD Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + disable-wp; + no-sdio; + no-mmc; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + + MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x140 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi new file mode 100644 index 000000000000..bc312aa1bfc8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de> + */ + +#include "imx8mp.dtsi" + +/ { + model = "Polyhex i.MX8MPlus Debix SOM A"; + compatible = "polyhex,imx8mp-debix-som-a", "fsl,imx8mp"; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + adc@48 { + compatible = "ti,ads1115"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + + channel@4 { + reg = <4>; + ti,gain = <1>; + ti,datarate = <7>; + }; + + channel@5 { + reg = <5>; + ti,gain = <1>; + ti,datarate = <7>; + }; + + channel@6 { + reg = <6>; + ti,gain = <1>; + ti,datarate = <7>; + }; + + channel@7 { + reg = <7>; + ti,gain = <1>; + ti,datarate = <7>; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index fa37ce89f8d3..cc9d468b43ab 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -16,6 +16,18 @@ stdout-path = &uart2; }; + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&adv7533_out>; + }; + }; + }; + gpio-leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -378,6 +390,40 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; + reg-names = "main", "cec", "edid", "packet"; + adi,dsi-lanes = <4>; + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7533_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + adv7533_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + + }; + }; }; &i2c3 { @@ -443,6 +489,26 @@ */ }; +&lcdif1 { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <10000000>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&adv7533_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + &pcie_phy { fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; clocks = <&pcie0_refclk>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts index 64d522c71a44..e4215c83ee0f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts @@ -55,7 +55,6 @@ assigned-clock-parents = <&clk IMX8MP_CLK_24M>; assigned-clock-rates = <24000000>; clocks = <&clk IMX8MP_CLK_CLKOUT1>; - clock-names = "mclk"; #sound-dai-cells = <0>; VDDA-supply = <®_vcc_3v3_audio>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi index 5dbec71747c3..61c2a63efc6d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s.dtsi @@ -109,7 +109,7 @@ compatible = "linux,extcon-usb-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0_extcon>; - id-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; + id-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 6aa720bafe28..1e14c4cd3128 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -76,15 +76,15 @@ compatible = "nxp,pca9533"; reg = <0x62>; - led1 { + led-1 { type = <PCA9532_TYPE_LED>; }; - led2 { + led-2 { type = <PCA9532_TYPE_LED>; }; - led3 { + led-3 { type = <PCA9532_TYPE_LED>; }; }; @@ -103,6 +103,8 @@ /* SD-Card */ &usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <200000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index ecc4bce6db97..d8df97060e8f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -42,8 +42,8 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; fsl,magic-packet; status = "okay"; @@ -54,14 +54,12 @@ ethphy1: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; - interrupt-parent = <&gpio1>; - interrupts = <15 IRQ_TYPE_EDGE_FALLING>; - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + enet-phy-lane-no-swap; ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; ti,min-output-impedance; - enet-phy-lane-no-swap; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; }; }; }; @@ -75,8 +73,8 @@ compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <80000000>; - spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; }; }; @@ -85,89 +83,85 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic: pmic@25 { - reg = <0x25>; compatible = "nxp,pca9450c"; + reg = <0x25>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio4>; - interrupts = <18 IRQ_TYPE_LEVEL_LOW>; regulators { buck1: BUCK1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <805000>; + regulator-name = "VDD_SOC (BUCK1)"; regulator-ramp-delay = <3125>; }; buck2: BUCK2 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; nxp,dvs-run-voltage = <950000>; nxp,dvs-standby-voltage = <850000>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1050000>; + regulator-min-microvolt = <805000>; + regulator-name = "VDD_ARM (BUCK2)"; + regulator-ramp-delay = <3125>; }; buck4: BUCK4 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_3V3 (BUCK4)"; }; buck5: BUCK5 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDD_1V8 (BUCK5)"; }; buck6: BUCK6 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1155000>; + regulator-min-microvolt = <1045000>; + regulator-name = "NVCC_DRAM_1V1 (BUCK6)"; }; ldo1: LDO1 { - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; - }; - - ldo2: LDO2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; regulator-boot-on; - regulator-always-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1710000>; + regulator-name = "NVCC_SNVS_1V8 (LDO1)"; }; ldo3: LDO3 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; - }; - - ldo4: LDO4 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDDA_1V8 (LDO3)"; }; ldo5: LDO5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "NVCC_SD2 (LDO5)"; }; }; }; @@ -208,21 +202,20 @@ &iomuxc { pinctrl_fec: fecgrp { fsl,pins = < - MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 - MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 - MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 - MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 - MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 - MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 - MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 - MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 - MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 >; }; @@ -239,69 +232,69 @@ pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 >; }; pinctrl_i2c1_gpio: i2c1gpiogrp { fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3 - MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3 + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e2 >; }; pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141 + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x140 >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 >; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 >; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2 - MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx-2x.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx-2x.dts new file mode 100644 index 000000000000..53120fc9cd7f --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx-2x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mp.dtsi" +#include "imx8mp-venice-gw702x.dtsi" +#include "imx8mp-venice-gw71xx.dtsi" + +/ { + model = "Gateworks Venice GW71xx-2x i.MX8MP Development Kit"; + compatible = "gateworks,imx8mp-gw71xx-2x", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi new file mode 100644 index 000000000000..c531564c7ebb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> + +/ { + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pcie0_refclk: clock-pcie0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "dio1", "", "", "dio0", + "", "", "pci_usb_sel", "", + "", "", "", "", + "", "", "", "", + "dio3", "", "dio2", "", + "pci_wdis#", "", "", ""; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + accelerometer@19 { + compatible = "st,lis2de12"; + reg = <0x19>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio4>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + }; +}; + +&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* off-board header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* USB1 Type-C front panel */ +&usb3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + fsl,over-current-active-low; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + /* dual role is implemented but not a full featured OTG */ + adp-disable; + hnp-disable; + srp-disable; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + status = "okay"; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon1>; + type = "micro"; + label = "Type-C"; + id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + }; +}; + +/* USB2 - MiniPCIe socket */ +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ + MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ + MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ + MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x40000146 /* DIO2 */ + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x40000146 /* DIO3 */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ + >; + }; + + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ + MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ + >; + }; + + pinctrl_usbcon1: usbcon1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx-2x.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx-2x.dts new file mode 100644 index 000000000000..255e36f66b00 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx-2x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mp.dtsi" +#include "imx8mp-venice-gw702x.dtsi" +#include "imx8mp-venice-gw72xx.dtsi" + +/ { + model = "Gateworks Venice GW72xx-2x i.MX8MP Development Kit"; + compatible = "gateworks,imx8mp-gw72xx-2x", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi new file mode 100644 index 000000000000..f3bab22d5e68 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi @@ -0,0 +1,371 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> + +/ { + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pcie0_refclk: clock-pcie0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_usb1_vbus: regulator-usb1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_en>; + regulator-name = "usb1_vbus"; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb2_vbus: regulator-usb2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + regulator-name = "usb2_vbus"; + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; + regulator-name = "VDD_3V3_SD"; + enable-active-high; + gpio = <&gpio2 19 0>; /* SD2_RESET */ + off-on-delay-us = <12000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + startup-delay-us = <100>; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "dio1", "", "", "dio0", + "", "", "pci_usb_sel", "", + "", "", "", "", + "", "", "rs485_en", "rs485_term", + "", "", "", "rs485_half", + "pci_wdis#", "", "", ""; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + accelerometer@19 { + compatible = "st,lis2de12"; + reg = <0x19>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio4>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + }; +}; + +&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* off-board header */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* RS232 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +/* USB1 - OTG */ +&usb3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + fsl,over-current-active-low; + status = "okay"; +}; + +&usb3_phy0 { + vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usb_dwc3_0 { + /* dual role is implemented but not a full featured OTG */ + adp-disable; + hnp-disable; + srp-disable; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + status = "okay"; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon1>; + type = "micro"; + label = "otg"; + id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + }; +}; + +/* USB2 - USB3.0 Hub */ +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ + MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ + MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ + >; + }; + + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ + MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 + >; + }; + + pinctrl_reg_usb1_en: regusb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */ + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ + >; + }; + + pinctrl_usbcon1: usbcon1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ + >; + }; + + pinctrl_reg_usb2_en: regusb2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx-2x.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx-2x.dts new file mode 100644 index 000000000000..000fd15e0c07 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx-2x.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +/dts-v1/; + +#include "imx8mp.dtsi" +#include "imx8mp-venice-gw702x.dtsi" +#include "imx8mp-venice-gw73xx.dtsi" + +/ { + model = "Gateworks Venice GW73xx-2x i.MX8MP Development Kit"; + compatible = "gateworks,imx8mp-gw73xx-2x", "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi new file mode 100644 index 000000000000..68c62def4c06 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> + +/ { + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_RED>; + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pcie0_refclk: clock-pcie0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_usb1_vbus: regulator-usb1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_en>; + regulator-name = "usb1_vbus"; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb2_vbus: regulator-usb2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + regulator-name = "usb2_vbus"; + gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_wifi_en: regulator-wifi-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wl>; + regulator-name = "wl"; + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vmmc>; + regulator-name = "VDD_3V3_SD"; + enable-active-high; + gpio = <&gpio2 19 0>; /* SD2_RESET */ + off-on-delay-us = <12000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + startup-delay-us = <100>; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "dio1", "", "", "dio0", + "", "", "pci_usb_sel", "", + "", "", "", "", + "", "", "rs485_en", "rs485_term", + "", "", "", "rs485_half", + "pci_wdis#", "", "", ""; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + accelerometer@19 { + compatible = "st,lis2de12"; + reg = <0x19>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio4>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + }; +}; + +&pcie_phy { + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + fsl,clkreq-unsupported; + clocks = <&pcie0_refclk>; + clock-names = "ref"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* GPS */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* bluetooth HCI */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>; + cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4330-bt"; + shutdown-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + }; +}; + +/* RS232 */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +/* USB1 - OTG */ +&usb3_0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + fsl,over-current-active-low; + status = "okay"; +}; + +&usb3_phy0 { + vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usb_dwc3_0 { + /* dual role is implemented but not a full featured OTG */ + adp-disable; + hnp-disable; + srp-disable; + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + status = "okay"; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon1>; + type = "micro"; + label = "otg"; + id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + }; +}; + +/* USB2 - USB3.0 Hub */ +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* SDIO WiFi */ +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_wifi_en>; + status = "okay"; +}; + +/* microSD */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ + MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ + MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ + >; + }; + + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ + >; + }; + + pinctrl_bten: btengrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x146 + >; + }; + + pinctrl_gpio_leds: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ + MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 + >; + }; + + pinctrl_reg_wl: regwlgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x146 + >; + }; + + pinctrl_reg_usb1_en: regusb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */ + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ + >; + }; + + pinctrl_usbcon1: usbcon1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ + >; + }; + + pinctrl_reg_usb2_en: regusb2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-rpidsi.dtso b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-rpidsi.dtso new file mode 100644 index 000000000000..6a39f43435c2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-rpidsi.dtso @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp"; + + panel { + compatible = "powertip,ph800480t013-idf02"; + power-supply = <&attiny>; + backlight = <&attiny>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; +}; + +&i2c4 { + #address-cells = <1>; + #size-cells = <0>; + + attiny: regulator@45 { + compatible = "raspberrypi,7inch-touchscreen-panel-regulator"; + reg = <0x45>; + }; +}; + +&lcdif1 { + status = "okay"; +}; + +&mipi_dsi { + samsung,burst-clock-frequency = <891000000>; + samsung,esc-clock-frequency = <54000000>; + samsung,pll-clock-frequency = <27000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + bridge@0 { + compatible = "toshiba,tc358762"; + reg = <0>; + vddc-supply = <&attiny>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_out: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index 92514b71b5f4..faa370a5885f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -125,12 +125,22 @@ regulator-max-microvolt = <5000000>; }; + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can1>; + regulator-name = "can1_stby"; + gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_can2_stby: regulator-can2-stby { compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_can>; + pinctrl-0 = <&pinctrl_reg_can2>; regulator-name = "can2_stby"; - gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; + gpio = <&gpio5 5 GPIO_ACTIVE_LOW>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -164,6 +174,21 @@ cpu-supply = <®_arm>; }; +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@0 { + compatible = "tcg,tpm_tis-spi"; + #address-cells = <0x1>; + #size-cells = <0x1>; + reg = <0x0>; + spi-max-frequency = <36000000>; + }; +}; + /* off-board header */ &ecspi2 { pinctrl-names = "default"; @@ -204,6 +229,13 @@ }; }; +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; @@ -214,38 +246,38 @@ &gpio1 { gpio-line-names = "", "", "", "", "", "", "", "", - "", "", "dio0", "", "dio1", "", "", "", + "", "dio0", "", "dio1", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &gpio2 { gpio-line-names = - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "pcie3_wdis#", "", + "", "", "", "", "", "", "m2_pin20", "", + "", "", "", "", "", "pcie1_wdis#", "pcie3_wdis#", "", "", "", "pcie2_wdis#", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &gpio3 { gpio-line-names = - "m2_gdis#", "", "", "", "", "", "", "m2_rst#", + "", "", "", "", "", "", "m2_rst", "", + "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", - "m2_off#", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; }; &gpio4 { gpio-line-names = + "", "", "m2_off#", "", "", "", "", "", "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "m2_wdis#", "", "", "", - "", "", "", "", "", "", "", "uart_rs485"; + "", "", "m2_wdis#", "", "", "", "", "", + "", "", "", "", "", "", "", "rs485_en"; }; &gpio5 { gpio-line-names = - "uart_half", "uart_term", "", "", "", "", "", "", + "rs485_hd", "rs485_term", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""; @@ -268,6 +300,8 @@ interrupts = <20 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; adc { compatible = "gw,gsc-adc"; @@ -286,6 +320,12 @@ label = "vdd_bat"; }; + channel@16 { + gw,mode = <4>; + reg = <0x16>; + label = "fan_tach"; + }; + channel@82 { gw,mode = <2>; reg = <0x82>; @@ -358,6 +398,11 @@ gw,voltage-divider-ohms = <10000 10000>; }; }; + + fan-controller@a { + compatible = "gw,gsc-fan"; + reg = <0x0a>; + }; }; gpio: gpio@23 { @@ -369,85 +414,6 @@ interrupts = <4>; }; - pmic@25 { - compatible = "nxp,pca9450c"; - reg = <0x25>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio3>; - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - - regulators { - BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1000000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - reg_arm: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1025000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - BUCK4 { - regulator-name = "BUCK4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3600000>; - regulator-boot-on; - regulator-always-on; - }; - - BUCK5 { - regulator-name = "BUCK5"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - regulator-boot-on; - regulator-always-on; - }; - - BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <1045000>; - regulator-max-microvolt = <1155000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <1710000>; - regulator-max-microvolt = <1890000>; - regulator-boot-on; - regulator-always-on; - }; - - LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; @@ -559,7 +525,6 @@ }; }; -/* off-board header */ &i2c3 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -568,6 +533,85 @@ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + reg_arm: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1025000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1045000>; + regulator-max-microvolt = <1155000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; /* off-board header */ @@ -693,7 +737,7 @@ status = "okay"; wifi@0 { - compatible = "cypress,cyw4373-fmac"; + compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac"; reg = <0>; }; }; @@ -726,12 +770,14 @@ fsl,pins = < MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */ MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */ - MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */ - MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x40000040 /* M2SKT_OFF# */ + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */ + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x40000040 /* M2SKT_PIN20 */ + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x40000040 /* M2SKT_PIN22 */ + MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x40000150 /* PCIE1_WDIS# */ MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */ + MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */ MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */ - MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */ - MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000150 /* M2SKT_GDIS# */ MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ @@ -784,6 +830,13 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 @@ -869,7 +922,7 @@ pinctrl_pcie0: pciegrp { fsl,pins = < - MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x110 + MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x106 >; }; @@ -885,12 +938,18 @@ >; }; - pinctrl_reg_can: regcangrp { + pinctrl_reg_can1: regcan1grp { fsl,pins = < MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154 >; }; + pinctrl_reg_can2: regcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 + >; + }; + pinctrl_reg_usb2: regusb2grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140 @@ -903,12 +962,12 @@ >; }; - pinctrl_sai2: sai2grp { + pinctrl_spi1: spi1grp { fsl,pins = < - MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 - MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 - MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 - MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6 + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x82 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x82 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x82 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi index 56b0e4b865c9..7e9e4b13b5c5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -3,7 +3,36 @@ * Copyright 2022 Toradex */ -/* TODO: Audio Codec */ +/ { + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "imx8mp-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Headphone Jack", "MICBIAS", + "IN1L", "Headphone Jack"; + simple-audio-card,widgets = + "Microphone", "Headphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>; + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + }; +}; &backlight { power-supply = <®_3p3v>; @@ -64,7 +93,21 @@ &i2c4 { status = "okay"; - /* TODO: Audio Codec */ + /* Audio Codec */ + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + #sound-dai-cells = <0>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>; + clock-names = "mclk"; + AVDD-supply = <®_1p8v>; + CPVDD-supply = <®_1p8v>; + DBVDD-supply = <®_1p8v>; + DCVDD-supply = <®_1p8v>; + MICVDD-supply = <®_1p8v>; + }; }; /* Verdin PCIE_1 */ @@ -95,7 +138,14 @@ vin-supply = <®_3p3v>; }; -/* TODO: Verdin I2S_1 */ +/* Verdin I2S_1 */ +&sai1 { + assigned-clocks = <&clk IMX8MP_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; /* Verdin UART_1 */ &uart1 { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi index bdfdd4c782f1..a509b2b7fa85 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi @@ -4,8 +4,6 @@ */ / { - /* TODO: Audio Codec */ - reg_eth2phy: regulator-eth2phy { compatible = "regulator-fixed"; enable-active-high; @@ -17,6 +15,41 @@ startup-delay-us = <200000>; vin-supply = <®_3p3v>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "imx8mp-nau8822"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "Line Out", "AUXOUT1", + "Line Out", "AUXOUT2", + "LAUX", "Line In", + "RAUX", "Line In", + "LMICP", "Mic In", + "RMICP", "Mic In"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Line Out", "Line Out", + "Speaker", "Speaker", + "Microphone", "Mic In", + "Line", "Line In"; + + codec_dai: simple-audio-card,codec { + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>; + sound-dai = <&nau8822_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + }; }; &backlight { @@ -88,7 +121,14 @@ &i2c4 { status = "okay"; - /* TODO: Audio Codec */ + /* Audio Codec */ + nau8822_1a: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + #sound-dai-cells = <0>; + }; }; /* Verdin PCIE_1 */ @@ -119,7 +159,14 @@ vin-supply = <®_3p3v>; }; -/* TODO: Verdin I2C_1 with Audio Codec */ +/* Verdin I2S_1 */ +&sai1 { + assigned-clocks = <&clk IMX8MP_CLK_SAI1>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; /* Verdin UART_1, connector X50 through RS485 transceiver */ &uart1 { diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index cc406bb338fe..6f2f50e1639c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -306,8 +306,7 @@ etm0: etm@28440000 { compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x28440000 0x10000>; - arm,primecell-periphid = <0xbb95d>; + reg = <0x28440000 0x1000>; cpu = <&A53_0>; clocks = <&clk IMX8MP_CLK_MAIN_AXI>; clock-names = "apb_pclk"; @@ -323,8 +322,7 @@ etm1: etm@28540000 { compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x28540000 0x10000>; - arm,primecell-periphid = <0xbb95d>; + reg = <0x28540000 0x1000>; cpu = <&A53_1>; clocks = <&clk IMX8MP_CLK_MAIN_AXI>; clock-names = "apb_pclk"; @@ -340,8 +338,7 @@ etm2: etm@28640000 { compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x28640000 0x10000>; - arm,primecell-periphid = <0xbb95d>; + reg = <0x28640000 0x1000>; cpu = <&A53_2>; clocks = <&clk IMX8MP_CLK_MAIN_AXI>; clock-names = "apb_pclk"; @@ -357,8 +354,7 @@ etm3: etm@28740000 { compatible = "arm,coresight-etm4x", "arm,primecell"; - reg = <0x28740000 0x10000>; - arm,primecell-periphid = <0xbb95d>; + reg = <0x28740000 0x1000>; cpu = <&A53_3>; clocks = <&clk IMX8MP_CLK_MAIN_AXI>; clock-names = "apb_pclk"; @@ -701,7 +697,7 @@ snvs_rtc: snvs-rtc-lp { compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap =<&snvs>; + regmap = <&snvs>; offset = <0x34>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; @@ -854,7 +850,7 @@ pgc_vpumix: power-domain@19 { #power-domain-cells = <0>; reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; - clocks =<&clk IMX8MP_CLK_VPU_ROOT>; + clocks = <&clk IMX8MP_CLK_VPU_ROOT>; }; pgc_vpu_g1: power-domain@20 { @@ -1846,8 +1842,8 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ - <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ + <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; num-viewport = <4>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index ce7ce2ba855c..8055a2c23035 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -139,18 +139,6 @@ regulator-always-on; }; - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2_pwr>; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; - wwan_codec: sound-wwan-codec { compatible = "option,gtm601"; #sound-dai-cells = <0>; @@ -242,6 +230,13 @@ enable-active-high; regulator-always-on; }; + + wifi_pwr_seq: pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_rst>; + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; + }; }; &A53_0 { @@ -324,6 +319,7 @@ regulator-ramp-delay = <1250>; rohm,dvs-run-voltage = <1000000>; rohm,dvs-idle-voltage = <900000>; + regulator-always-on; }; buck3_reg: BUCK3 { @@ -561,9 +557,9 @@ reg = <0x6a>; vdd-supply = <®_3v3_p>; vddio-supply = <®_3v3_p>; - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; }; }; @@ -807,7 +803,7 @@ >; }; - pinctrl_usdhc2_pwr: usdhc2pwrgrp { + pinctrl_usdhc2_rst: usdhc2rstgrp { fsl,pins = < MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 >; @@ -1030,8 +1026,8 @@ pinctrl-1 = <&pinctrl_usdhc2_100mhz>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>; bus-width = <4>; - vmmc-supply = <®_usdhc2_vmmc>; - power-supply = <&wifi_pwr_en>; + vmmc-supply = <&wifi_pwr_en>; + mmc-pwrseq = <&wifi_pwr_seq>; broken-cd; disable-wp; cap-sdio-irq; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts index 2b3d437a642a..cf40025111c8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r2.dts @@ -13,9 +13,9 @@ }; &accel_gyro { - mount-matrix = "1", "0", "0", - "0", "-1", "0", - "0", "0", "1"; + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; }; &bq25895 { diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi index 7fd0176e4bd3..17f86496f8b0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r3.dtsi @@ -16,9 +16,9 @@ }; &accel_gyro { - mount-matrix = "1", "0", "0", - "0", "1", "0", - "0", "0", "-1"; + mount-matrix = "1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; }; &bq25895 { @@ -39,9 +39,9 @@ }; &magnetometer { - mount-matrix = "1", "0", "0", - "0", "-1", "0", - "0", "0", "-1"; + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "-1"; }; &proximity { diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts index 97577c0a7715..33f398b48119 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts @@ -23,5 +23,5 @@ }; &proximity { - proximity-near-level = <5>; + proximity-near-level = <7>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 38732579d13e..138a4d36a7ef 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -91,6 +91,7 @@ regulator-max-microvolt = <1800000>; gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; enable-active-high; + regulator-always-on; }; reg_mic_2v4: regulator-mic-2v4 { @@ -795,6 +796,8 @@ interrupt-parent = <&gpio1>; interrupts = <10 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; + extcon = <&usb3_phy0>; + wakeup-source; connector { compatible = "usb-c-connector"; @@ -1376,7 +1379,7 @@ pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <8>; vmmc-supply = <®_vdd_3v3>; - power-supply = <®_vdd_1v8>; + vqmmc-supply = <®_vdd_1v8>; non-removable; status = "okay"; }; @@ -1391,7 +1394,7 @@ bus-width = <4>; vmmc-supply = <®_wifi_3v3>; mmc-pwrseq = <&usdhc2_pwrseq>; - post-power-on-delay-ms = <1000>; + post-power-on-delay-ms = <20>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; max-frequency = <100000000>; disable-wp; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi index 0187890a90c5..efc00f4abeb1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi @@ -133,7 +133,7 @@ }; }; -&pgc_gpu{ +&pgc_gpu { power-supply = <&sw1a_reg>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts index afb3ceb06751..0d8def2766f5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts @@ -24,7 +24,7 @@ compatible = "linux,extcon-usb-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbcon0>; - id-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; pcie0_refclk: pcie0-refclk { diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 01eec424f7f7..35f07dfb4ca8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -330,6 +330,198 @@ nvmem-cells = <&imx8mq_uid>; nvmem-cell-names = "soc_unique_id"; + etm0: etm@28440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28440000 0x1000>; + cpu = <&A53_0>; + clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; + }; + }; + }; + + etm1: etm@28540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28540000 0x1000>; + cpu = <&A53_1>; + clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; + }; + }; + }; + + etm2: etm@28640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28640000 0x1000>; + cpu = <&A53_2>; + clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm2_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port2>; + }; + }; + }; + }; + + etm3: etm@28740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x28740000 0x1000>; + cpu = <&A53_3>; + clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + out-ports { + port { + etm3_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port3>; + }; + }; + }; + }; + + funnel { + /* + * non-configurable funnel don't show up on the AMBA + * bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + + ca_funnel_in_port1: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + + ca_funnel_in_port2: endpoint { + remote-endpoint = <&etm2_out_port>; + }; + }; + + port@3 { + reg = <3>; + + ca_funnel_in_port3: endpoint { + remote-endpoint = <&etm3_out_port>; + }; + }; + }; + + out-ports { + port { + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + }; + }; + + funnel@28c03000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x28c03000 0x1000>; + clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hugo_funnel_in_port0: endpoint { + remote-endpoint = <&ca_funnel_out_port0>; + }; + }; + + port@1 { + reg = <1>; + + hugo_funnel_in_port1: endpoint { + /* M4 input */ + }; + }; + /* the other input ports are not connect to anything */ + }; + + out-ports { + port { + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; + }; + }; + }; + + etf@28c04000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x28c04000 0x1000>; + clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + in-ports { + port { + etf_in_port: endpoint { + remote-endpoint = <&hugo_funnel_out_port0>; + }; + }; + }; + + out-ports { + port { + etf_out_port: endpoint { + remote-endpoint = <&etr_in_port>; + }; + }; + }; + }; + + etr@28c06000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x28c06000 0x1000>; + clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&etf_out_port>; + }; + }; + }; + }; + aips1: bus@30000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; @@ -631,9 +823,9 @@ compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x30370000 0x10000>; - snvs_rtc: snvs-rtc-lp{ + snvs_rtc: snvs-rtc-lp { compatible = "fsl,sec-v4.0-mon-rtc-lp"; - regmap =<&snvs>; + regmap = <&snvs>; offset = <0x34>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; @@ -1582,8 +1774,8 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ - <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ + <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 607cd6b4e972..0b34cc2250e1 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -22,6 +22,10 @@ /delete-node/ cpu@101; }; + thermal-zones { + /delete-node/ cpu1-thermal; + }; + memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0 0x40000000>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi index 9fff867709f0..31744fc1ab08 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/pads-imx8qm.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&gic>; @@ -23,9 +24,9 @@ serial1 = &lpuart1; serial2 = &lpuart2; serial3 = &lpuart3; - vpu_core0 = &vpu_core0; - vpu_core1 = &vpu_core1; - vpu_core2 = &vpu_core2; + vpu-core0 = &vpu_core0; + vpu-core1 = &vpu_core1; + vpu-core2 = &vpu_core2; }; cpus { @@ -62,6 +63,7 @@ device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x0>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -70,12 +72,15 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; }; A53_1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x1>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -84,12 +89,15 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; }; A53_2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x2>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -98,12 +106,15 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; }; A53_3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0 0x3>; + clocks = <&clk IMX_SC_R_A53 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; i-cache-size = <0x8000>; i-cache-line-size = <64>; @@ -112,12 +123,15 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; + #cooling-cells = <2>; }; A72_0: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x0 0x100>; + clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; i-cache-size = <0xC000>; i-cache-line-size = <64>; @@ -126,14 +140,19 @@ d-cache-line-size = <64>; d-cache-sets = <256>; next-level-cache = <&A72_L2>; + operating-points-v2 = <&a72_opp_table>; + #cooling-cells = <2>; }; A72_1: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a72"; reg = <0x0 0x101>; + clocks = <&clk IMX_SC_R_A72 IMX_SC_PM_CLK_CPU>; enable-method = "psci"; next-level-cache = <&A72_L2>; + operating-points-v2 = <&a72_opp_table>; + #cooling-cells = <2>; }; A53_L2: l2-cache0 { @@ -155,6 +174,66 @@ }; }; + a53_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + clock-latency-ns = <150000>; + }; + + opp-896000000 { + opp-hz = /bits/ 64 <896000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + + a72_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + }; + + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + }; + + opp-1596000000 { + opp-hz = /bits/ 64 <1596000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + gic: interrupt-controller@51a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ @@ -212,6 +291,133 @@ rtc: rtc { compatible = "fsl,imx8qxp-sc-rtc"; }; + + tsens: thermal-sensor { + compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; + #thermal-sensor-cells = <1>; + }; + }; + + thermal-zones { + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_A53>; + + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_A72>; + + trips { + cpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A72_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>; + + trips { + gpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>; + + trips { + gpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + drc0-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_DRC_0>; + + trips { + drc_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + + drc_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; }; /* sorted in register address */ diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts index 7d00e17f0447..50bf7919c863 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts @@ -180,7 +180,7 @@ >; }; - pinctrl_leds: ledsgrp{ + pinctrl_leds: ledsgrp { fsl,pins = < IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 0x00000021 IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 0x00000021 diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 85c0b1d2bac5..c80c85a4b405 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -46,9 +46,9 @@ serial1 = &lpuart1; serial2 = &lpuart2; serial3 = &lpuart3; - vpu_core0 = &vpu_core0; - vpu_core1 = &vpu_core1; - vpu_core2 = &vpu_core2; + vpu-core0 = &vpu_core0; + vpu-core1 = &vpu_core1; + vpu-core2 = &vpu_core2; }; cpus { diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts index f1c6d933a17c..69dd8e31027c 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -20,6 +20,55 @@ reg = <0x0 0x80000000 0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x28000000>; + linux,cma-default; + }; + + m33_reserved: noncacheable-section@a8600000 { + reg = <0 0xa8600000 0 0x1000000>; + no-map; + }; + + rsc_table: rsc-table@1fff8000{ + reg = <0 0x1fff8000 0 0x1000>; + no-map; + }; + + vdev0vring0: vdev0vring0@aff00000 { + reg = <0 0xaff00000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@aff08000 { + reg = <0 0xaff08000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@aff10000 { + reg = <0 0xaff10000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@aff18000 { + reg = <0 0xaff18000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xa8400000 0 0x100000>; + no-map; + }; + }; + clock_ext_rmii: clock-ext-rmii { compatible = "fixed-clock"; clock-frequency = <50000000>; @@ -36,6 +85,31 @@ }; }; +&cm33 { + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1>, + <&mu 1 1>, + <&mu 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + status = "okay"; +}; + +&flexspi2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexspi2_ptd>; + pinctrl-1 = <&pinctrl_flexspi2_ptd>; + status = "okay"; + + mx25uw51345gxdi00: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <200000000>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + }; +}; + &lpuart5 { /* console */ pinctrl-names = "default", "sleep"; @@ -44,10 +118,29 @@ status = "okay"; }; -&usdhc0 { +&lpi2c7 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c7>; + pinctrl-1 = <&pinctrl_lpi2c7>; + status = "okay"; + + pcal6408: gpio@21 { + compatible = "nxp,pcal9554b"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc0>; pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; non-removable; bus-width = <8>; status = "okay"; @@ -79,6 +172,10 @@ }; }; +&mu { + status = "okay"; +}; + &iomuxc1 { pinctrl_enet: enetgrp { fsl,pins = < @@ -96,6 +193,23 @@ >; }; + pinctrl_flexspi2_ptd: flexspi2ptdgrp { + fsl,pins = < + + MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x42 + MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x42 + MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x42 + MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x42 + MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x42 + MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x42 + MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x42 + MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x42 + MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x42 + MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x42 + MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42 + >; + }; + pinctrl_lpuart5: lpuart5grp { fsl,pins = < MX8ULP_PAD_PTF14__LPUART5_TX 0x3 @@ -103,19 +217,26 @@ >; }; + pinctrl_lpi2c7: lpi2c7grp { + fsl,pins = < + MX8ULP_PAD_PTE12__LPI2C7_SCL 0x20 + MX8ULP_PAD_PTE13__LPI2C7_SDA 0x20 + >; + }; + pinctrl_usdhc0: usdhc0grp { fsl,pins = < - MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 - MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 - MX8ULP_PAD_PTD10__SDHC0_D0 0x43 - MX8ULP_PAD_PTD9__SDHC0_D1 0x43 - MX8ULP_PAD_PTD8__SDHC0_D2 0x43 - MX8ULP_PAD_PTD7__SDHC0_D3 0x43 - MX8ULP_PAD_PTD6__SDHC0_D4 0x43 - MX8ULP_PAD_PTD5__SDHC0_D5 0x43 - MX8ULP_PAD_PTD4__SDHC0_D6 0x43 - MX8ULP_PAD_PTD3__SDHC0_D7 0x43 - MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 + MX8ULP_PAD_PTD1__SDHC0_CMD 0x3 + MX8ULP_PAD_PTD2__SDHC0_CLK 0x10002 + MX8ULP_PAD_PTD10__SDHC0_D0 0x3 + MX8ULP_PAD_PTD9__SDHC0_D1 0x3 + MX8ULP_PAD_PTD8__SDHC0_D2 0x3 + MX8ULP_PAD_PTD7__SDHC0_D3 0x3 + MX8ULP_PAD_PTD6__SDHC0_D4 0x3 + MX8ULP_PAD_PTD5__SDHC0_D5 0x3 + MX8ULP_PAD_PTD4__SDHC0_D6 0x3 + MX8ULP_PAD_PTD3__SDHC0_D7 0x3 + MX8ULP_PAD_PTD11__SDHC0_DQS 0x10002 >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 57627bdaa851..8a6596d5a581 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/imx8ulp-power.h> +#include <dt-bindings/thermal/thermal.h> #include "imx8ulp-pinfunc.h" @@ -39,6 +40,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&A35_L2>; + cpu-idle-states = <&cpu_sleep>; }; A35_1: cpu@1 { @@ -47,6 +49,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&A35_L2>; + cpu-idle-states = <&cpu_sleep>; }; A35_L2: l2-cache0 { @@ -54,6 +57,19 @@ cache-level = <2>; cache-unified; }; + + idle-states { + entry-method = "psci"; + + cpu_sleep: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + }; + }; }; gic: interrupt-controller@2d400000 { @@ -78,6 +94,28 @@ method = "smc"; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&scmi_sensor 0>; + + trips { + cpu_alert0: trip0 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit0: trip1 { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ @@ -148,11 +186,17 @@ }; }; + cm33: remoteproc-cm33 { + compatible = "fsl,imx8ulp-cm33"; + status = "disabled"; + }; + soc: soc@0 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x0 0x0 0x40000000>; + ranges = <0x0 0x0 0x0 0x40000000>, + <0x60000000 0x0 0x60000000 0x1000000>; s4muap: mailbox@27020000 { compatible = "fsl,imx8ulp-mu-s4"; @@ -307,6 +351,21 @@ #reset-cells = <1>; }; + flexspi2: spi@29810000 { + compatible = "nxp,imx8mm-fspi"; + reg = <0x29810000 0x10000>, <0x60000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>, + <&pcc4 IMX8ULP_CLK_FLEXSPI2>; + clock-names = "fspi", "fspi_en"; + assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>; + assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; + status = "disabled"; + }; + lpi2c6: i2c@29840000 { compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x29840000 0x10000>; @@ -365,6 +424,10 @@ <&pcc4 IMX8ULP_CLK_USDHC0>; clock-names = "ipg", "ahb", "per"; power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>, + <&pcc4 IMX8ULP_CLK_USDHC0>; + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV1>; + assigned-clock-rates = <389283840>, <389283840>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; bus-width = <4>; @@ -380,6 +443,10 @@ <&pcc4 IMX8ULP_CLK_USDHC1>; clock-names = "ipg", "ahb", "per"; power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>, + <&pcc4 IMX8ULP_CLK_USDHC1>; + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; + assigned-clock-rates = <194641920>, <194641920>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; bus-width = <4>; @@ -395,6 +462,10 @@ <&pcc4 IMX8ULP_CLK_USDHC2>; clock-names = "ipg", "ahb", "per"; power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>; + assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>, + <&pcc4 IMX8ULP_CLK_USDHC2>; + assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; + assigned-clock-rates = <194641920>, <194641920>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; bus-width = <4>; diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi index aab655931cde..bc659066e19a 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi @@ -35,7 +35,7 @@ /* Colibri UART_A */ &lpuart3 { - status= "okay"; + status = "okay"; }; /* Colibri SDCard */ diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi index f8953067bc3b..8d06925a8ebd 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi @@ -77,7 +77,7 @@ /* Colibri UART_A */ &lpuart3 { - status= "okay"; + status = "okay"; }; &lsio_gpio3 { diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index c50f46f06f62..cafd39130eb8 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -15,6 +15,52 @@ stdout-path = &lpuart1; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x80000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + + vdev0vring0: vdev0vring0@a4000000 { + reg = <0 0xa4000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@a4008000 { + reg = <0 0xa4008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@a4000000 { + reg = <0 0xa4010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@a4018000 { + reg = <0 0xa4018000 0 0x8000>; + no-map; + }; + + rsc_table: rsc-table@2021f000 { + reg = <0 0x2021f000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@a4020000 { + compatible = "shared-dma-pool"; + reg = <0 0xa4020000 0 0x100000>; + no-map; + }; + + }; + reg_vref_1v8: regulator-adc-vref { compatible = "regulator-fixed"; regulator-name = "vref_1v8"; @@ -39,6 +85,16 @@ status = "okay"; }; +&cm33 { + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu1 0 1>, + <&mu1 1 1>, + <&mu1 3 1>; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + status = "okay"; +}; + &mu1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts new file mode 100644 index 000000000000..f06139bdff97 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts @@ -0,0 +1,641 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + * Author: Alexander Stein + */ +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/usb/pd.h> +#include "imx93-tqma9352.dtsi" + +/{ + model = "TQ-Systems i.MX93 TQMa93xxLA on MBa93xxLA SBC"; + compatible = "tq,imx93-tqma9352-mba93xxla", + "tq,imx93-tqma9352", "fsl,imx93"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + eeprom0 = &eeprom0; + rtc0 = &pcf85063; + rtc1 = &bbnsm_rtc; + }; + + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pwms = <&tpm5 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_12v0>; + enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + clk_dp: clk-dp { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + switch-a { + label = "switcha"; + linux,code = <BTN_0>; + gpios = <&expander0 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-b { + label = "switchb"; + linux,code = <BTN_1>; + gpios = <&expander0 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&expander2 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-2 { + color = <LED_COLOR_ID_AMBER>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&expander2 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_3v8: regulator-3v8 { + compatible = "regulator-fixed"; + regulator-name = "V_3V8"; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* TODO: this is supply for IOT module */ + regulator-always-on; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "V_5V0_MB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "V_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc1 { + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_eqos>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy_eqos: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos_phy>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_fec>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy_fec: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&gpio1 { + expander-irq-hog { + gpio-hog; + gpios = <12 GPIO_ACTIVE_LOW>; + input; + line-name = "PEX_INT#"; + }; + + rtc-irq-hog { + gpio-hog; + gpios = <14 GPIO_ACTIVE_LOW>; + input; + line-name = "RTC_EVENT#"; + }; +}; + +&gpio3 { + ethphy-eqos-irq-hog { + gpio-hog; + gpios = <26 GPIO_ACTIVE_LOW>; + input; + line-name = "ENET0_IRQ#"; + }; + + ethphy-fec-irq-hog { + gpio-hog; + gpios = <27 GPIO_ACTIVE_LOW>; + input; + line-name = "ENET1_IRQ#"; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + temperature-sensor@1c { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1c>; + }; + + eeprom2: eeprom@54 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x54>; + pagesize = <16>; + vcc-supply = <®_3v3>; + }; + + expander0: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pexp_irq>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_3v3>; + gpio-line-names = "3V8_EN", "", + "", "IOT_PWRKEY", + "IOT_RESET", "IOT_W_DISABLE", + "BUTTON_A#", "BUTTON_B#"; + + /* + * Controls the IOT W_DISABLE pin which is low active + * as disable signal but inverted as seen from the CPU. + * The output-low states, the signal is + * inactive, e.g. not disabled + */ + iot_wdisable_hog: iot-wdisable-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "IOT_W_DISABLE"; + }; + }; + + expander1: gpio@71 { + compatible = "nxp,pca9538"; + reg = <0x71>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "ENET1_RESET#", "ENET2_RESET#", + "USB_RESET#", "", + "WLAN_PD#", "WLAN_W_DISABLE#", + "WLAN_PERST#", "12V_EN"; + + /* + * Controls the WiFi card PD pin which is low active + * as power down signal. The output-low states, the signal + * is inactive, e.g. not power down + */ + wlan-pd-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_PD#"; + }; + + /* + * Controls the WiFi card disable pin which is low active + * as disable signal. The output-low states, the signal + * is inactive, e.g. not disabled + */ + wlan-wdisable-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_W_DISABLE#"; + }; + + /* + * Controls the WiFi card reset pin which is low active + * as reset signal. The output-low states, the signal + * is inactive, e.g. not in reset + */ + wlan-perst-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-low; + line-name = "WLAN_PERST#"; + }; + }; + + expander2: gpio@72 { + compatible = "nxp,pca9538"; + reg = <0x72>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "LCD_RESET#", "LCD_PWR_EN", + "LCD_BL_EN", "DP_EN", + "MIPI_CSI_EN", "MIPI_CSI_RST#", + "USER_LED1", "USER_LED2"; + }; +}; + +&lpi2c5 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5>; + status = "okay"; + + dp_bridge: dp-bridge@f { + compatible = "toshiba,tc9595", "toshiba,tc358767"; + reg = <0x0f>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tc9595>; + clock-names = "ref"; + clocks = <&clk_dp>; + reset-gpios = <&expander2 3 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio4>; + interrupts = <29 IRQ_TYPE_EDGE_RISING>; + toshiba,hpd-pin = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dp_dsi_in: endpoint { + data-lanes = <1 2 3 4>; + }; + }; + }; + }; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* disabled per default, console for M33 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "disabled"; +}; + +&lpuart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +&lpuart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + status = "okay"; +}; + +&pcf85063 { + /* RTC_EVENT# is connected on MBa93xxLA */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcf85063>; + interrupt-parent = <&gpio1>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; +}; + +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm5>; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + no-sdio; + no-mmc; + disable-wp; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + /* PD | FSEL_2 | DSE X4 */ + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000051e + /* PD | FSEL_2 | DSE X6 */ + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + /* PD | FSEL_3 | DSE X6 */ + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + /* PD | FSEL_2 | DSE X4 */ + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e + /* PD | FSEL_3 | DSE X3 */ + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + >; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1306 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + /* PD | FSEL_2 | DSE X4 */ + MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000051e + /* PD | FSEL_2 | DSE X6 */ + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + /* PD | FSEL_3 | DSE X6 */ + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + /* PD | FSEL_2 | DSE X4 */ + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x51e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x51e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x51e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x51e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x51e + /* PD | FSEL_3 | DSE X3 */ + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e + >; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1306 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = < + MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e + MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e + >; + }; + + pinctrl_pcf85063: pcf85063grp { + fsl,pins = < + MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1306 + >; + }; + + pinctrl_pexp_irq: pexpirqgrp { + fsl,pins = < + MX93_PAD_SAI1_TXC__GPIO1_IO12 0x1306 + >; + }; + + pinctrl_tc9595: tc9595-grp { + fsl,pins = < + /* DP_IRQ */ + MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1306 + >; + }; + + pinctrl_tpm5: tpm5grp { + fsl,pins = < + MX93_PAD_GPIO_IO06__TPM5_CH0 0x57e + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + MX93_PAD_I2C2_SCL__GPIO1_IO02 0x1306 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX93_PAD_UART2_TXD__LPUART2_TX 0x31e + MX93_PAD_UART2_RXD__LPUART2_RX 0x31e + MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x31e + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX93_PAD_GPIO_IO14__LPUART3_TX 0x31e + MX93_PAD_GPIO_IO15__LPUART3_RX 0x31e + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e + MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins = < + MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e + MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2_hs: usdhc2hsgrp { + fsl,pins = < + /* HYS | PD | PU | FSEL_3 | DSE X5 */ + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17be + /* HYS | PD | PU | FSEL_3 | DSE X4 */ + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + /* HYS | PD | PU | FSEL_3 | DSE X3 */ + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + /* PD | PU | FSEL_2 | DSE X3 */ + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e + >; + }; + + pinctrl_usdhc2_uhs: usdhc2uhsgrp { + fsl,pins = < + /* HYS | PD | PU | FSEL_3 | DSE X6 */ + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe + /* HYS | PD | PU | FSEL_3 | DSE X4 */ + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + /* PD | PU | FSEL_2 | DSE X3 */ + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi new file mode 100644 index 000000000000..1c71c08becde --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + */ + +#include "imx93.dtsi" + +/{ + model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA SOM"; + compatible = "tq,imx93-tqma9352", "fsl,imx93"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + alloc-ranges = <0 0x60000000 0 0x40000000>; + size = <0 0x10000000>; + linux,cma-default; + }; + }; + + reg_v1v8: regulator-v1v8 { + compatible = "regulator-fixed"; + regulator-name = "V_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + /* SD2 RST# via PMIC SW_EN */ + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_v3v3>; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&adc1 { + vref-supply = <®_v1v8>; +}; + +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + /* + * no DQS, RXCLKSRC internal loop back, max 66 MHz + * clk framework uses CLK_DIVIDER_ROUND_CLOSEST + * selected value together with root from + * IMX93_CLK_SYS_PLL_PFD1 @ 800.000.000 Hz helps to + * respect the maximum value. + */ + spi-max-frequency = <62000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&gpio1 { + pmic-irq-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_LOW>; + input; + line-name = "PMIC_IRQ#"; + }; +}; + +&lpi2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c1>; + pinctrl-1 = <&pinctrl_lpi2c1>; + status = "okay"; + + se97_som: temperature-sensor@1b { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1b>; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <7000>; + }; + + eeprom0: eeprom@53 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + read-only; + vcc-supply = <®_v3v3>; + }; + + eeprom1: eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_v3v3>; + }; + + /* protectable identification memory (part of M24C64-D @57) */ + eeprom@5f { + compatible = "st,24c64", "atmel,24c64"; + reg = <0x5f>; + size = <32>; + pagesize = <32>; + vcc-supply = <®_v3v3>; + }; + + imu@6a { + compatible = "st,ism330dhcx"; + reg = <0x6a>; + vdd-supply = <®_v3v3>; + vddio-supply = <®_v3v3>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&wdog3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexspi1: flexspi1grp { + fsl,pins = < + MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x3fe + MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x3fe + MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x3fe + MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x3fe + MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x3fe + MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x3fe + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_pca9451: pca9451grp { + fsl,pins = < + MX93_PAD_I2C2_SDA__GPIO1_IO03 0x1306 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x1306 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + /* HYS | PU | PD | FSEL_3 | X5 */ + MX93_PAD_SD1_CLK__USDHC1_CLK 0x17be + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x17be + /* HYS | PU | FSEL_3 | X5 */ + MX93_PAD_SD1_CMD__USDHC1_CMD 0x13be + /* HYS | PU | FSEL_3 | X4 */ + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x139e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x139e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x139e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x139e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x139e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x139e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x139e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x139e + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x31e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 1d8dd14b65cf..6f85a05ee7e1 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/fsl,imx93-power.h> +#include <dt-bindings/thermal/thermal.h> #include "imx93-pinfunc.h" @@ -132,6 +133,44 @@ interrupt-parent = <&gic>; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <2000>; + + thermal-sensors = <&tmu 0>; + + trips { + cpu_alert: cpu-alert { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + cm33: remoteproc-cm33 { + compatible = "fsl,imx93-cm33"; + clocks = <&clk IMX93_CLK_CM33_GATE>; + status = "disabled"; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -252,7 +291,7 @@ }; lpuart1: serial@44380000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x44380000 0x1000>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART1_GATE>; @@ -261,7 +300,7 @@ }; lpuart2: serial@44390000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x44390000 0x1000>; interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART2_GATE>; @@ -343,6 +382,26 @@ reg = <0x44480000 0x2000>; }; + tmu: tmu@44482000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x44482000 0x1000>; + clocks = <&clk IMX93_CLK_TMC_GATE>; + little-endian; + fsl,tmu-range = <0x800000da 0x800000e9 + 0x80000102 0x8000012a + 0x80000166 0x800001a7 + 0x800001b6>; + fsl,tmu-calibration = <0x00000000 0x0000000e + 0x00000001 0x00000029 + 0x00000002 0x00000056 + 0x00000003 0x000000a2 + 0x00000004 0x00000116 + 0x00000005 0x00000195 + 0x00000006 0x000001b2>; + #thermal-sensor-cells = <1>; + }; + + adc1: adc@44530000 { compatible = "nxp,imx93-adc"; reg = <0x44530000 0x10000>; @@ -486,7 +545,7 @@ }; lpuart3: serial@42570000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42570000 0x1000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART3_GATE>; @@ -495,7 +554,7 @@ }; lpuart4: serial@42580000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42580000 0x1000>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART4_GATE>; @@ -504,7 +563,7 @@ }; lpuart5: serial@42590000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42590000 0x1000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART5_GATE>; @@ -513,7 +572,7 @@ }; lpuart6: serial@425a0000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x425a0000 0x1000>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART6_GATE>; @@ -551,7 +610,7 @@ }; lpuart7: serial@42690000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42690000 0x1000>; interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART7_GATE>; @@ -560,7 +619,7 @@ }; lpuart8: serial@426a0000 { - compatible = "fsl,imx93-lpuart", "fsl,imx7ulp-lpuart"; + compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x426a0000 0x1000>; interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART8_GATE>; @@ -683,7 +742,7 @@ clock-names = "ipg", "ahb", "per"; bus-width = <8>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; status = "disabled"; }; @@ -697,7 +756,7 @@ clock-names = "ipg", "ahb", "per"; bus-width = <4>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; status = "disabled"; }; @@ -760,7 +819,7 @@ clock-names = "ipg", "ahb", "per"; bus-width = <4>; fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; + fsl,tuning-step = <2>; status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi index a83b9d4f172e..ed1b5a7a6067 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi @@ -302,8 +302,8 @@ compatible = "snps,dw-mshc"; reg = <0x9820000 0x10000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&crg HISTB_SDIO0_CIU_CLK>, - <&crg HISTB_SDIO0_BIU_CLK>; + clocks = <&crg HISTB_SDIO0_BIU_CLK>, + <&crg HISTB_SDIO0_CIU_CLK>; clock-names = "biu", "ciu"; resets = <&crg 0x9c 4>; reset-names = "reset"; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index b7e2cbf466b3..be808bb2544e 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -861,7 +861,7 @@ #thermal-sensor-cells = <1>; }; - i2s0: i2s@f7118000{ + i2s0: i2s@f7118000 { compatible = "hisilicon,hi6210-i2s"; reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */ @@ -1032,17 +1032,17 @@ compatible = "hisilicon,hi6220-mali", "arm,mali-450"; reg = <0x0 0xf4080000 0x0 0x00040000>; interrupt-parent = <&gic>; - interrupts = <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, - <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "gp", "gpmmu", diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index c588848bfdeb..f46c33d10750 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -570,7 +570,7 @@ }; }; - eth0: ethernet-4{ + eth0: ethernet-4 { compatible = "hisilicon,hns-nic-v2"; ae-handle = <&dsaf0>; port-idx-in-ae = <4>; @@ -579,7 +579,7 @@ dma-coherent; }; - eth1: ethernet-5{ + eth1: ethernet-5 { compatible = "hisilicon,hns-nic-v2"; ae-handle = <&dsaf0>; port-idx-in-ae = <5>; @@ -588,7 +588,7 @@ dma-coherent; }; - eth2: ethernet-0{ + eth2: ethernet-0 { compatible = "hisilicon,hns-nic-v2"; ae-handle = <&dsaf0>; port-idx-in-ae = <0>; @@ -597,7 +597,7 @@ dma-coherent; }; - eth3: ethernet-1{ + eth3: ethernet-1 { compatible = "hisilicon,hns-nic-v2"; ae-handle = <&dsaf0>; port-idx-in-ae = <1>; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 595abe339c5d..81d907ef43ed 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1483,7 +1483,7 @@ }; }; - eth0: ethernet@4{ + eth0: ethernet@4 { compatible = "hisilicon,hns-nic-v2"; ae-handle = <&dsaf0>; port-idx-in-ae = <4>; @@ -1492,7 +1492,7 @@ dma-coherent; }; - eth1: ethernet@5{ + eth1: ethernet@5 { compatible = "hisilicon,hns-nic-v2"; ae-handle = <&dsaf0>; port-idx-in-ae = <5>; @@ -1501,7 +1501,7 @@ dma-coherent; }; - eth2: ethernet@0{ + eth2: ethernet@0 { compatible = "hisilicon,hns-nic-v2"; ae-handle = <&dsaf0>; port-idx-in-ae = <0>; @@ -1510,7 +1510,7 @@ dma-coherent; }; - eth3: ethernet@1{ + eth3: ethernet@1 { compatible = "hisilicon,hns-nic-v2"; ae-handle = <&dsaf0>; port-idx-in-ae = <1>; diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index c2a723838344..d39cfb723f5b 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -2,5 +2,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb \ + socfpga_agilex5_socdk.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index f9674cc46764..d3adb6a130ae 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -158,7 +158,7 @@ interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; @@ -176,7 +176,7 @@ interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; @@ -194,7 +194,7 @@ interrupt-names = "macirq"; mac-address = [00 00 00 00 00 00]; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; - reset-names = "stmmaceth", "stmmaceth-ocp"; + reset-names = "stmmaceth", "ahb"; tx-fifo-depth = <16384>; rx-fifo-depth = <16384>; snps,multicast-filter-bins = <256>; @@ -336,6 +336,9 @@ ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xffe00000 0x40000>; }; pdma: dma-controller@ffda0000 { @@ -373,9 +376,9 @@ }; rst: rstmgr@ffd11000 { - #reset-cells = <1>; - compatible = "altr,stratix10-rst-mgr"; + compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; reg = <0xffd11000 0x100>; + #reset-cells = <1>; }; smmu: iommu@fa000000 { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi new file mode 100644 index 000000000000..dcdaf7064953 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -0,0 +1,468 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, Intel Corporation + */ + +/dts-v1/; +#include <dt-bindings/reset/altr,rst-mgr-s10.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/intel,agilex5-clkmgr.h> + +/ { + compatible = "intel,socfpga-agilex5"; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + service_reserved: svcbuffer@0 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x2000000>; + alignment = <0x1000>; + no-map; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a76"; + reg = <0x200>; + device_type = "cpu"; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a76"; + reg = <0x300>; + device_type = "cpu"; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + intc: interrupt-controller@1d000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x1d000000 0 0x10000>, + <0x0 0x1d060000 0 0x100000>; + ranges; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells =<2>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + + its: msi-controller@1d040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x1d040000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + /* Clock tree 5 main sources*/ + clocks { + cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + cb_intosc_ls_clk: cb-intosc-ls-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + f2s_free_clk: f2s-free-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + qspi_clk: qspi-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + usbphy0: usbphy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + }; + + soc: soc@0 { + compatible = "simple-bus"; + ranges = <0 0 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + interrupt-parent = <&intc>; + + clkmgr: clock-controller@10d10000 { + compatible = "intel,agilex5-clkmgr"; + reg = <0x10d10000 0x1000>; + #clock-cells = <1>; + }; + + i2c0: i2c@10c02800 { + compatible = "snps,designware-i2c"; + reg = <0x10c02800 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst I2C0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c1: i2c@10c02900 { + compatible = "snps,designware-i2c"; + reg = <0x10c02900 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst I2C1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c2: i2c@10c02a00 { + compatible = "snps,designware-i2c"; + reg = <0x10c02a00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst I2C2_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c3: i2c@10c02b00 { + compatible = "snps,designware-i2c"; + reg = <0x10c02b00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst I2C3_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i2c4: i2c@10c02c00 { + compatible = "snps,designware-i2c"; + reg = <0x10c02c00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst I2C4_RESET>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + status = "disabled"; + }; + + i3c0: i3c-master@10da0000 { + compatible = "snps,dw-i3c-master-1.00a"; + reg = <0x10da0000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkmgr AGILEX5_L4_MP_CLK>; + status = "disabled"; + }; + + i3c1: i3c-master@10da1000 { + compatible = "snps,dw-i3c-master-1.00a"; + reg = <0x10da1000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkmgr AGILEX5_L4_MP_CLK>; + status = "disabled"; + }; + + gpio1: gpio@10c03300 { + compatible = "snps,dw-apb-gpio"; + reg = <0x10c03300 0x100>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&rst GPIO1_RESET>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + nand: nand-controller@10b80000 { + compatible = "cdns,hp-nfc"; + reg = <0x10b80000 0x10000>, + <0x10840000 0x10000>; + reg-names = "reg", "sdma"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkmgr AGILEX5_NAND_NF_CLK>; + cdns,board-delay-ps = <4830>; + status = "disabled"; + }; + + ocram: sram@0 { + compatible = "mmio-sram"; + reg = <0x00000000 0x80000>; + ranges = <0 0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + dmac0: dma-controller@10db0000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x10db0000 0x500>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <2>; + snps,block-size = <32767 32767 32767 32767>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <8>; + }; + + dmac1: dma-controller@10dc0000 { + compatible = "snps,axi-dma-1.01a"; + reg = <0x10dc0000 0x500>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, + <&clkmgr AGILEX5_L4_MP_CLK>; + clock-names = "core-clk", "cfgr-clk"; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <2>; + snps,block-size = <32767 32767 32767 32767>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <8>; + }; + + rst: rstmgr@10d11000 { + compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; + reg = <0x10d11000 0x1000>; + #reset-cells = <1>; + }; + + spi0: spi@10da4000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x10da4000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst SPIM0_RESET>; + reset-names = "spi"; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names ="tx", "rx"; + status = "disabled"; + + }; + + spi1: spi@10da5000 { + compatible = "snps,dw-apb-ssi"; + reg = <0x10da5000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst SPIM1_RESET>; + reset-names = "spi"; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; + status = "disabled"; + }; + + sysmgr: sysmgr@10d12000 { + compatible = "altr,sys-mgr-s10","altr,sys-mgr"; + reg = <0x10d12000 0x500>; + }; + + timer0: timer0@10c03000 { + compatible = "snps,dw-apb-timer"; + reg = <0x10c03000 0x100>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer1: timer1@10c03100 { + compatible = "snps,dw-apb-timer"; + reg = <0x10c03100 0x100>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer2: timer2@10d00000 { + compatible = "snps,dw-apb-timer"; + reg = <0x10d00000 0x100>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer3: timer3@10d00100 { + compatible = "snps,dw-apb-timer"; + reg = <0x10d00100 0x100>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + clock-names = "timer"; + }; + + uart0: serial@10c02000 { + compatible = "snps,dw-apb-uart"; + reg = <0x10c02000 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART0_RESET>; + status = "disabled"; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + }; + + uart1: serial@10c02100 { + compatible = "snps,dw-apb-uart"; + reg = <0x10c02100 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART1_RESET>; + status = "disabled"; + clocks = <&clkmgr AGILEX5_L4_SP_CLK>; + }; + + usb0: usb@10b00000 { + compatible = "snps,dwc2"; + reg = <0x10b00000 0x40000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; + reset-names = "dwc2", "dwc2-ecc"; + clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>; + clock-names = "otg"; + status = "disabled"; + }; + + watchdog0: watchdog@10d00200 { + compatible = "snps,dw-wdt"; + reg = <0x10d00200 0x100>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst WATCHDOG0_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog1: watchdog@10d00300 { + compatible = "snps,dw-wdt"; + reg = <0x10d00300 0x100>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst WATCHDOG1_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog2: watchdog@10d00400 { + compatible = "snps,dw-wdt"; + reg = <0x10d00400 0x100>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst WATCHDOG2_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog3: watchdog@10d00500 { + compatible = "snps,dw-wdt"; + reg = <0x10d00500 0x100>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst WATCHDOG3_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog4: watchdog@10d00600 { + compatible = "snps,dw-wdt"; + reg = <0x10d00600 0x100>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst WATCHDOG4_RESET>; + clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + qspi: spi@108d2000 { + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; + reg = <0x108d2000 0x100>, + <0x10900000 0x100000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts new file mode 100644 index 000000000000..c533e5a3a610 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, Intel Corporation + */ +#include "socfpga_agilex5.dtsi" + +/ { + model = "SoCFPGA Agilex5 SoCDK"; + compatible = "intel,socfpga-agilex5-socdk", "intel,socfpga-agilex5"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts index 6231a69204b1..1a32840c74e0 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts @@ -20,10 +20,10 @@ stdout-path = "serial0:115200n8"; }; - memory@0 { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0 0x80000000 0 0>; }; soc { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 07c3f8876613..053690657675 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -37,10 +37,10 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0 0x80000000 0 0>; }; }; @@ -128,12 +128,12 @@ qspi_boot: partition@0 { label = "Boot and fpga data"; - reg = <0x0 0x03FE0000>; + reg = <0x0 0x04200000>; }; - qspi_rootfs: partition@3FE0000 { - label = "Root Filesystem - JFFS2"; - reg = <0x03FE0000 0x0C020000>; + root: partition@4200000 { + label = "Root Filesystem - UBIFS"; + reg = <0x04200000 0x0BE00000>; }; }; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts index 51f83f96ec65..0f9020bd0c52 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts @@ -37,10 +37,10 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0 0x80000000 0 0>; }; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 08c088571270..5ddfdff37c25 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -19,10 +19,10 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@80000000 { device_type = "memory"; /* We expect the bootloader to fill in the reg */ - reg = <0 0 0 0>; + reg = <0 0x80000000 0 0>; }; soc { @@ -109,7 +109,7 @@ reg = <0x0 0x03FE0000>; }; - qspi_rootfs: partition@3FE0000 { + qspi_rootfs: partition@3fe0000 { label = "Root Filesystem - JFFS2"; reg = <0x03FE0000 0x0C020000>; }; diff --git a/arch/arm64/boot/dts/lg/lg1312.dtsi b/arch/arm64/boot/dts/lg/lg1312.dtsi index 78ae73d0cf36..48ec4ebec0a8 100644 --- a/arch/arm64/boot/dts/lg/lg1312.dtsi +++ b/arch/arm64/boot/dts/lg/lg1312.dtsi @@ -48,6 +48,8 @@ }; L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/lg/lg1313.dtsi b/arch/arm64/boot/dts/lg/lg1313.dtsi index 2173316573be..3869460aa5dc 100644 --- a/arch/arm64/boot/dts/lg/lg1313.dtsi +++ b/arch/arm64/boot/dts/lg/lg1313.dtsi @@ -48,6 +48,8 @@ }; L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index c9ce1010c415..62d03ffa9485 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -135,7 +135,7 @@ clocks = <&cnm_clock>; }; - i2c0: i2c@11000{ + i2c0: i2c@11000 { compatible = "marvell,mv78230-i2c"; reg = <0x11000 0x20>; #address-cells = <1>; @@ -154,7 +154,7 @@ status = "disabled"; }; - i2c1: i2c@11100{ + i2c1: i2c@11100 { compatible = "marvell,mv78230-i2c"; reg = <0x11100 0x20>; #address-cells = <1>; @@ -297,6 +297,16 @@ status = "disabled"; }; + nand: nand-controller@805b0000 { + compatible = "marvell,ac5-nand-controller"; + reg = <0x0 0x805b0000 0x0 0x00000054>; + #address-cells = <0x1>; + #size-cells = <0x0>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&nand_clock>; + status = "disabled"; + }; + gic: interrupt-controller@80600000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -319,5 +329,11 @@ #clock-cells = <0>; clock-frequency = <200000000>; }; + + nand_clock: nand-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts index 39ce6e25a8ef..48202810bf78 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts @@ -149,7 +149,7 @@ }; /* SPI-NOR */ -&cp0_spi1{ +&cp0_spi1 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index e4605d23fdc8..86cedb0bf1a9 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -585,11 +585,11 @@ }; &sata { - status = "disable"; + status = "disabled"; }; &sata_phy { - status = "disable"; + status = "disabled"; }; &spi0 { diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 4996499cc738..24075cd91420 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -469,14 +469,14 @@ switch: switch@600000000 { compatible = "microchip,sparx5-switch"; - reg = <0x6 0 0x401000>, - <0x6 0x10004000 0x7fc000>, - <0x6 0x11010000 0xaf0000>; + reg = <0x6 0 0x401000>, + <0x6 0x10004000 0x7fc000>, + <0x6 0x11010000 0xaf0000>; reg-names = "cpu", "dev", "gcb"; interrupt-names = "xtr", "fdma", "ptp"; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; resets = <&reset 0>; reset-names = "switch"; }; diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi index 12118b75c0e6..383938dcd3ce 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi @@ -49,6 +49,8 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index d4c034ac1244..bbc2e9bef08d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -531,6 +531,8 @@ }; serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 7e4c496fd91c..2b3bb5d0af17 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -135,7 +135,8 @@ clocks = <&bpmp TEGRA186_CLK_AHUB>; clock-names = "ahub"; assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; - assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; + assigned-clock-rates = <81600000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x02900800 0x02900800 0x11800>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 154fc8c0eb6d..33f92b77cd9d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -231,7 +231,8 @@ clocks = <&bpmp TEGRA194_CLK_AHUB>; clock-names = "ahub"; assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; - assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLP_OUT0>; + assigned-clock-rates = <81600000>; status = "disabled"; #address-cells = <2>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 92163b680980..0ae5a44f7d07 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -28,6 +28,8 @@ /* debug port */ serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 38f4ff229bef..a6a58e51822d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -58,19 +58,17 @@ dev-ctrl = /bits/ 8 <0x80>; init-brt = /bits/ 8 <0xff>; - pwm-period = <29334>; - pwms = <&pwm 0 29334>; pwm-names = "lp8557"; /* boost frequency 1 MHz */ - rom_13h { + rom-13h { rom-addr = /bits/ 8 <0x13>; rom-val = /bits/ 8 <0x01>; }; /* 3 LED string */ - rom_14h { + rom-14h { rom-addr = /bits/ 8 <0x14>; rom-val = /bits/ 8 <0x87>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi index 0a70daeffd85..f0d53f0b4117 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi @@ -21,6 +21,8 @@ /* debug port */ serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi index 1f263fd32a7a..bbd6ff0564da 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2894.dtsi @@ -1321,6 +1321,8 @@ }; serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index c9f488e14f37..c56824d7f4d8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -126,6 +126,8 @@ /* debug port */ serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 5a1ce432c1fb..53805555dd2d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1312,11 +1312,15 @@ }; serial@70006000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; uartd: serial@70006300 { compatible = "nvidia,tegra30-hsuart"; + reset-names = "serial"; + /delete-property/ reg-shift; status = "okay"; bluetooth { @@ -1391,7 +1395,6 @@ maxim,dvs-default-state = <1>; maxim,enable-active-discharge; maxim,enable-bias-control; - maxim,disable-etr; maxim,enable-gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; maxim,externally-enable; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 617583ff2736..47f8268e46bf 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -916,9 +916,7 @@ pd_vic: vic { clocks = <&tegra_car TEGRA210_CLK_VIC03>; - clock-names = "vic"; resets = <&tegra_car 178>; - reset-names = "vic"; #power-domain-cells = <0>; }; @@ -1386,7 +1384,8 @@ clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; clock-names = "ahub"; assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; - assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>; + assigned-clock-rates = <81600000>; #address-cells = <1>; #size-cells = <1>; ranges = <0x702d0000 0x702d0000 0x0000e400>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index 319b3a9cff24..cb792041fc62 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "tegra234.dtsi" +#include "tegra234-p3701.dtsi" / { model = "NVIDIA Jetson AGX Orin"; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi index e468352b8b7f..62c4fdad0b60 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0008.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "tegra234.dtsi" +#include "tegra234-p3701.dtsi" / { compatible = "nvidia,p3701-0008", "nvidia,tegra234"; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi new file mode 100644 index 000000000000..5e7797df50c2 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi @@ -0,0 +1,1991 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + compatible = "nvidia,p3701", "nvidia,tegra234"; + + bus@0 { + aconnect@2900000 { + status = "okay"; + + ahub@2900800 { + status = "okay"; + + i2s@2901000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s1_cif: endpoint { + remote-endpoint = <&xbar_i2s1>; + }; + }; + + i2s1_port: port@1 { + reg = <1>; + + i2s1_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + i2s@2901100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s2_cif: endpoint { + remote-endpoint = <&xbar_i2s2>; + }; + }; + + i2s2_port: port@1 { + reg = <1>; + + i2s2_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + i2s@2901300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s4_cif: endpoint { + remote-endpoint = <&xbar_i2s4>; + }; + }; + + i2s4_port: port@1 { + reg = <1>; + + i2s4_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + i2s@2901500 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2s6_cif: endpoint { + remote-endpoint = <&xbar_i2s6>; + }; + }; + + i2s6_port: port@1 { + reg = <1>; + + i2s6_dap: endpoint { + dai-format = "i2s"; + /* placeholder for external codec */ + }; + }; + }; + }; + + sfc@2902000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc1_cif_in: endpoint { + remote-endpoint = <&xbar_sfc1_in>; + }; + }; + + sfc1_out_port: port@1 { + reg = <1>; + + sfc1_cif_out: endpoint { + remote-endpoint = <&xbar_sfc1_out>; + }; + }; + }; + }; + + sfc@2902200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc2_cif_in: endpoint { + remote-endpoint = <&xbar_sfc2_in>; + }; + }; + + sfc2_out_port: port@1 { + reg = <1>; + + sfc2_cif_out: endpoint { + remote-endpoint = <&xbar_sfc2_out>; + }; + }; + }; + }; + + sfc@2902400 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc3_cif_in: endpoint { + remote-endpoint = <&xbar_sfc3_in>; + }; + }; + + sfc3_out_port: port@1 { + reg = <1>; + + sfc3_cif_out: endpoint { + remote-endpoint = <&xbar_sfc3_out>; + }; + }; + }; + }; + + sfc@2902600 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sfc4_cif_in: endpoint { + remote-endpoint = <&xbar_sfc4_in>; + }; + }; + + sfc4_out_port: port@1 { + reg = <1>; + + sfc4_cif_out: endpoint { + remote-endpoint = <&xbar_sfc4_out>; + }; + }; + }; + }; + + amx@2903000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx1_in1: endpoint { + remote-endpoint = <&xbar_amx1_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx1_in2: endpoint { + remote-endpoint = <&xbar_amx1_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx1_in3: endpoint { + remote-endpoint = <&xbar_amx1_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx1_in4: endpoint { + remote-endpoint = <&xbar_amx1_in4>; + }; + }; + + amx1_out_port: port@4 { + reg = <4>; + + amx1_out: endpoint { + remote-endpoint = <&xbar_amx1_out>; + }; + }; + }; + }; + + amx@2903100 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx2_in1: endpoint { + remote-endpoint = <&xbar_amx2_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx2_in2: endpoint { + remote-endpoint = <&xbar_amx2_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx2_in3: endpoint { + remote-endpoint = <&xbar_amx2_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx2_in4: endpoint { + remote-endpoint = <&xbar_amx2_in4>; + }; + }; + + amx2_out_port: port@4 { + reg = <4>; + + amx2_out: endpoint { + remote-endpoint = <&xbar_amx2_out>; + }; + }; + }; + }; + + amx@2903200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx3_in1: endpoint { + remote-endpoint = <&xbar_amx3_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx3_in2: endpoint { + remote-endpoint = <&xbar_amx3_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx3_in3: endpoint { + remote-endpoint = <&xbar_amx3_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx3_in4: endpoint { + remote-endpoint = <&xbar_amx3_in4>; + }; + }; + + amx3_out_port: port@4 { + reg = <4>; + + amx3_out: endpoint { + remote-endpoint = <&xbar_amx3_out>; + }; + }; + }; + }; + + amx@2903300 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + amx4_in1: endpoint { + remote-endpoint = <&xbar_amx4_in1>; + }; + }; + + port@1 { + reg = <1>; + + amx4_in2: endpoint { + remote-endpoint = <&xbar_amx4_in2>; + }; + }; + + port@2 { + reg = <2>; + + amx4_in3: endpoint { + remote-endpoint = <&xbar_amx4_in3>; + }; + }; + + port@3 { + reg = <3>; + + amx4_in4: endpoint { + remote-endpoint = <&xbar_amx4_in4>; + }; + }; + + amx4_out_port: port@4 { + reg = <4>; + + amx4_out: endpoint { + remote-endpoint = <&xbar_amx4_out>; + }; + }; + }; + }; + + adx@2903800 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx1_in: endpoint { + remote-endpoint = <&xbar_adx1_in>; + }; + }; + + adx1_out1_port: port@1 { + reg = <1>; + + adx1_out1: endpoint { + remote-endpoint = <&xbar_adx1_out1>; + }; + }; + + adx1_out2_port: port@2 { + reg = <2>; + + adx1_out2: endpoint { + remote-endpoint = <&xbar_adx1_out2>; + }; + }; + + adx1_out3_port: port@3 { + reg = <3>; + + adx1_out3: endpoint { + remote-endpoint = <&xbar_adx1_out3>; + }; + }; + + adx1_out4_port: port@4 { + reg = <4>; + + adx1_out4: endpoint { + remote-endpoint = <&xbar_adx1_out4>; + }; + }; + }; + }; + + adx@2903900 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx2_in: endpoint { + remote-endpoint = <&xbar_adx2_in>; + }; + }; + + adx2_out1_port: port@1 { + reg = <1>; + + adx2_out1: endpoint { + remote-endpoint = <&xbar_adx2_out1>; + }; + }; + + adx2_out2_port: port@2 { + reg = <2>; + + adx2_out2: endpoint { + remote-endpoint = <&xbar_adx2_out2>; + }; + }; + + adx2_out3_port: port@3 { + reg = <3>; + + adx2_out3: endpoint { + remote-endpoint = <&xbar_adx2_out3>; + }; + }; + + adx2_out4_port: port@4 { + reg = <4>; + + adx2_out4: endpoint { + remote-endpoint = <&xbar_adx2_out4>; + }; + }; + }; + }; + + adx@2903a00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx3_in: endpoint { + remote-endpoint = <&xbar_adx3_in>; + }; + }; + + adx3_out1_port: port@1 { + reg = <1>; + + adx3_out1: endpoint { + remote-endpoint = <&xbar_adx3_out1>; + }; + }; + + adx3_out2_port: port@2 { + reg = <2>; + + adx3_out2: endpoint { + remote-endpoint = <&xbar_adx3_out2>; + }; + }; + + adx3_out3_port: port@3 { + reg = <3>; + + adx3_out3: endpoint { + remote-endpoint = <&xbar_adx3_out3>; + }; + }; + + adx3_out4_port: port@4 { + reg = <4>; + + adx3_out4: endpoint { + remote-endpoint = <&xbar_adx3_out4>; + }; + }; + }; + }; + + adx@2903b00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adx4_in: endpoint { + remote-endpoint = <&xbar_adx4_in>; + }; + }; + + adx4_out1_port: port@1 { + reg = <1>; + + adx4_out1: endpoint { + remote-endpoint = <&xbar_adx4_out1>; + }; + }; + + adx4_out2_port: port@2 { + reg = <2>; + + adx4_out2: endpoint { + remote-endpoint = <&xbar_adx4_out2>; + }; + }; + + adx4_out3_port: port@3 { + reg = <3>; + + adx4_out3: endpoint { + remote-endpoint = <&xbar_adx4_out3>; + }; + }; + + adx4_out4_port: port@4 { + reg = <4>; + + adx4_out4: endpoint { + remote-endpoint = <&xbar_adx4_out4>; + }; + }; + }; + }; + + dmic@2904200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dmic3_cif: endpoint { + remote-endpoint = <&xbar_dmic3>; + }; + }; + + dmic3_port: port@1 { + reg = <1>; + + dmic3_dap: endpoint { + /* placeholder for external codec */ + }; + }; + }; + }; + + processing-engine@2908000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + ope1_cif_in_ep: endpoint { + remote-endpoint = <&xbar_ope1_in_ep>; + }; + }; + + ope1_out_port: port@1 { + reg = <0x1>; + + ope1_cif_out_ep: endpoint { + remote-endpoint = <&xbar_ope1_out_ep>; + }; + }; + }; + }; + + mvc@290a000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc1_cif_in: endpoint { + remote-endpoint = <&xbar_mvc1_in>; + }; + }; + + mvc1_out_port: port@1 { + reg = <1>; + + mvc1_cif_out: endpoint { + remote-endpoint = <&xbar_mvc1_out>; + }; + }; + }; + }; + + mvc@290a200 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mvc2_cif_in: endpoint { + remote-endpoint = <&xbar_mvc2_in>; + }; + }; + + mvc2_out_port: port@1 { + reg = <1>; + + mvc2_cif_out: endpoint { + remote-endpoint = <&xbar_mvc2_out>; + }; + }; + }; + }; + + amixer@290bb00 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + mix_in1: endpoint { + remote-endpoint = <&xbar_mix_in1>; + }; + }; + + port@1 { + reg = <0x1>; + + mix_in2: endpoint { + remote-endpoint = <&xbar_mix_in2>; + }; + }; + + port@2 { + reg = <0x2>; + + mix_in3: endpoint { + remote-endpoint = <&xbar_mix_in3>; + }; + }; + + port@3 { + reg = <0x3>; + + mix_in4: endpoint { + remote-endpoint = <&xbar_mix_in4>; + }; + }; + + port@4 { + reg = <0x4>; + + mix_in5: endpoint { + remote-endpoint = <&xbar_mix_in5>; + }; + }; + + port@5 { + reg = <0x5>; + + mix_in6: endpoint { + remote-endpoint = <&xbar_mix_in6>; + }; + }; + + port@6 { + reg = <0x6>; + + mix_in7: endpoint { + remote-endpoint = <&xbar_mix_in7>; + }; + }; + + port@7 { + reg = <0x7>; + + mix_in8: endpoint { + remote-endpoint = <&xbar_mix_in8>; + }; + }; + + port@8 { + reg = <0x8>; + + mix_in9: endpoint { + remote-endpoint = <&xbar_mix_in9>; + }; + }; + + port@9 { + reg = <0x9>; + + mix_in10: endpoint { + remote-endpoint = <&xbar_mix_in10>; + }; + }; + + mix_out1_port: port@a { + reg = <0xa>; + + mix_out1: endpoint { + remote-endpoint = <&xbar_mix_out1>; + }; + }; + + mix_out2_port: port@b { + reg = <0xb>; + + mix_out2: endpoint { + remote-endpoint = <&xbar_mix_out2>; + }; + }; + + mix_out3_port: port@c { + reg = <0xc>; + + mix_out3: endpoint { + remote-endpoint = <&xbar_mix_out3>; + }; + }; + + mix_out4_port: port@d { + reg = <0xd>; + + mix_out4: endpoint { + remote-endpoint = <&xbar_mix_out4>; + }; + }; + + mix_out5_port: port@e { + reg = <0xe>; + + mix_out5: endpoint { + remote-endpoint = <&xbar_mix_out5>; + }; + }; + }; + }; + + admaif@290f000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + admaif0_port: port@0 { + reg = <0x0>; + + admaif0: endpoint { + remote-endpoint = <&xbar_admaif0>; + }; + }; + + admaif1_port: port@1 { + reg = <0x1>; + + admaif1: endpoint { + remote-endpoint = <&xbar_admaif1>; + }; + }; + + admaif2_port: port@2 { + reg = <0x2>; + + admaif2: endpoint { + remote-endpoint = <&xbar_admaif2>; + }; + }; + + admaif3_port: port@3 { + reg = <0x3>; + + admaif3: endpoint { + remote-endpoint = <&xbar_admaif3>; + }; + }; + + admaif4_port: port@4 { + reg = <0x4>; + + admaif4: endpoint { + remote-endpoint = <&xbar_admaif4>; + }; + }; + + admaif5_port: port@5 { + reg = <0x5>; + + admaif5: endpoint { + remote-endpoint = <&xbar_admaif5>; + }; + }; + + admaif6_port: port@6 { + reg = <0x6>; + + admaif6: endpoint { + remote-endpoint = <&xbar_admaif6>; + }; + }; + + admaif7_port: port@7 { + reg = <0x7>; + + admaif7: endpoint { + remote-endpoint = <&xbar_admaif7>; + }; + }; + + admaif8_port: port@8 { + reg = <0x8>; + + admaif8: endpoint { + remote-endpoint = <&xbar_admaif8>; + }; + }; + + admaif9_port: port@9 { + reg = <0x9>; + + admaif9: endpoint { + remote-endpoint = <&xbar_admaif9>; + }; + }; + + admaif10_port: port@a { + reg = <0xa>; + + admaif10: endpoint { + remote-endpoint = <&xbar_admaif10>; + }; + }; + + admaif11_port: port@b { + reg = <0xb>; + + admaif11: endpoint { + remote-endpoint = <&xbar_admaif11>; + }; + }; + + admaif12_port: port@c { + reg = <0xc>; + + admaif12: endpoint { + remote-endpoint = <&xbar_admaif12>; + }; + }; + + admaif13_port: port@d { + reg = <0xd>; + + admaif13: endpoint { + remote-endpoint = <&xbar_admaif13>; + }; + }; + + admaif14_port: port@e { + reg = <0xe>; + + admaif14: endpoint { + remote-endpoint = <&xbar_admaif14>; + }; + }; + + admaif15_port: port@f { + reg = <0xf>; + + admaif15: endpoint { + remote-endpoint = <&xbar_admaif15>; + }; + }; + + admaif16_port: port@10 { + reg = <0x10>; + + admaif16: endpoint { + remote-endpoint = <&xbar_admaif16>; + }; + }; + + admaif17_port: port@11 { + reg = <0x11>; + + admaif17: endpoint { + remote-endpoint = <&xbar_admaif17>; + }; + }; + + admaif18_port: port@12 { + reg = <0x12>; + + admaif18: endpoint { + remote-endpoint = <&xbar_admaif18>; + }; + }; + + admaif19_port: port@13 { + reg = <0x13>; + + admaif19: endpoint { + remote-endpoint = <&xbar_admaif19>; + }; + }; + }; + }; + + asrc@2910000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = <&xbar_asrc_out6_ep>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + xbar_admaif0: endpoint { + remote-endpoint = <&admaif0>; + }; + }; + + port@1 { + reg = <0x1>; + + xbar_admaif1: endpoint { + remote-endpoint = <&admaif1>; + }; + }; + + port@2 { + reg = <0x2>; + + xbar_admaif2: endpoint { + remote-endpoint = <&admaif2>; + }; + }; + + port@3 { + reg = <0x3>; + + xbar_admaif3: endpoint { + remote-endpoint = <&admaif3>; + }; + }; + + port@4 { + reg = <0x4>; + + xbar_admaif4: endpoint { + remote-endpoint = <&admaif4>; + }; + }; + + port@5 { + reg = <0x5>; + + xbar_admaif5: endpoint { + remote-endpoint = <&admaif5>; + }; + }; + + port@6 { + reg = <0x6>; + + xbar_admaif6: endpoint { + remote-endpoint = <&admaif6>; + }; + }; + + port@7 { + reg = <0x7>; + + xbar_admaif7: endpoint { + remote-endpoint = <&admaif7>; + }; + }; + + port@8 { + reg = <0x8>; + + xbar_admaif8: endpoint { + remote-endpoint = <&admaif8>; + }; + }; + + port@9 { + reg = <0x9>; + + xbar_admaif9: endpoint { + remote-endpoint = <&admaif9>; + }; + }; + + port@a { + reg = <0xa>; + + xbar_admaif10: endpoint { + remote-endpoint = <&admaif10>; + }; + }; + + port@b { + reg = <0xb>; + + xbar_admaif11: endpoint { + remote-endpoint = <&admaif11>; + }; + }; + + port@c { + reg = <0xc>; + + xbar_admaif12: endpoint { + remote-endpoint = <&admaif12>; + }; + }; + + port@d { + reg = <0xd>; + + xbar_admaif13: endpoint { + remote-endpoint = <&admaif13>; + }; + }; + + port@e { + reg = <0xe>; + + xbar_admaif14: endpoint { + remote-endpoint = <&admaif14>; + }; + }; + + port@f { + reg = <0xf>; + + xbar_admaif15: endpoint { + remote-endpoint = <&admaif15>; + }; + }; + + port@10 { + reg = <0x10>; + + xbar_admaif16: endpoint { + remote-endpoint = <&admaif16>; + }; + }; + + port@11 { + reg = <0x11>; + + xbar_admaif17: endpoint { + remote-endpoint = <&admaif17>; + }; + }; + + port@12 { + reg = <0x12>; + + xbar_admaif18: endpoint { + remote-endpoint = <&admaif18>; + }; + }; + + port@13 { + reg = <0x13>; + + xbar_admaif19: endpoint { + remote-endpoint = <&admaif19>; + }; + }; + + xbar_i2s1_port: port@14 { + reg = <0x14>; + + xbar_i2s1: endpoint { + remote-endpoint = <&i2s1_cif>; + }; + }; + + xbar_i2s2_port: port@15 { + reg = <0x15>; + + xbar_i2s2: endpoint { + remote-endpoint = <&i2s2_cif>; + }; + }; + + xbar_i2s4_port: port@17 { + reg = <0x17>; + + xbar_i2s4: endpoint { + remote-endpoint = <&i2s4_cif>; + }; + }; + + xbar_i2s6_port: port@19 { + reg = <0x19>; + + xbar_i2s6: endpoint { + remote-endpoint = <&i2s6_cif>; + }; + }; + + xbar_dmic3_port: port@1c { + reg = <0x1c>; + + xbar_dmic3: endpoint { + remote-endpoint = <&dmic3_cif>; + }; + }; + + xbar_sfc1_in_port: port@20 { + reg = <0x20>; + + xbar_sfc1_in: endpoint { + remote-endpoint = <&sfc1_cif_in>; + }; + }; + + port@21 { + reg = <0x21>; + + xbar_sfc1_out: endpoint { + remote-endpoint = <&sfc1_cif_out>; + }; + }; + + xbar_sfc2_in_port: port@22 { + reg = <0x22>; + + xbar_sfc2_in: endpoint { + remote-endpoint = <&sfc2_cif_in>; + }; + }; + + port@23 { + reg = <0x23>; + + xbar_sfc2_out: endpoint { + remote-endpoint = <&sfc2_cif_out>; + }; + }; + + xbar_sfc3_in_port: port@24 { + reg = <0x24>; + + xbar_sfc3_in: endpoint { + remote-endpoint = <&sfc3_cif_in>; + }; + }; + + port@25 { + reg = <0x25>; + + xbar_sfc3_out: endpoint { + remote-endpoint = <&sfc3_cif_out>; + }; + }; + + xbar_sfc4_in_port: port@26 { + reg = <0x26>; + + xbar_sfc4_in: endpoint { + remote-endpoint = <&sfc4_cif_in>; + }; + }; + + port@27 { + reg = <0x27>; + + xbar_sfc4_out: endpoint { + remote-endpoint = <&sfc4_cif_out>; + }; + }; + + xbar_mvc1_in_port: port@28 { + reg = <0x28>; + + xbar_mvc1_in: endpoint { + remote-endpoint = <&mvc1_cif_in>; + }; + }; + + port@29 { + reg = <0x29>; + + xbar_mvc1_out: endpoint { + remote-endpoint = <&mvc1_cif_out>; + }; + }; + + xbar_mvc2_in_port: port@2a { + reg = <0x2a>; + + xbar_mvc2_in: endpoint { + remote-endpoint = <&mvc2_cif_in>; + }; + }; + + port@2b { + reg = <0x2b>; + + xbar_mvc2_out: endpoint { + remote-endpoint = <&mvc2_cif_out>; + }; + }; + + xbar_amx1_in1_port: port@2c { + reg = <0x2c>; + + xbar_amx1_in1: endpoint { + remote-endpoint = <&amx1_in1>; + }; + }; + + xbar_amx1_in2_port: port@2d { + reg = <0x2d>; + + xbar_amx1_in2: endpoint { + remote-endpoint = <&amx1_in2>; + }; + }; + + xbar_amx1_in3_port: port@2e { + reg = <0x2e>; + + xbar_amx1_in3: endpoint { + remote-endpoint = <&amx1_in3>; + }; + }; + + xbar_amx1_in4_port: port@2f { + reg = <0x2f>; + + xbar_amx1_in4: endpoint { + remote-endpoint = <&amx1_in4>; + }; + }; + + port@30 { + reg = <0x30>; + + xbar_amx1_out: endpoint { + remote-endpoint = <&amx1_out>; + }; + }; + + xbar_amx2_in1_port: port@31 { + reg = <0x31>; + + xbar_amx2_in1: endpoint { + remote-endpoint = <&amx2_in1>; + }; + }; + + xbar_amx2_in2_port: port@32 { + reg = <0x32>; + + xbar_amx2_in2: endpoint { + remote-endpoint = <&amx2_in2>; + }; + }; + + xbar_amx2_in3_port: port@33 { + reg = <0x33>; + + xbar_amx2_in3: endpoint { + remote-endpoint = <&amx2_in3>; + }; + }; + + xbar_amx2_in4_port: port@34 { + reg = <0x34>; + + xbar_amx2_in4: endpoint { + remote-endpoint = <&amx2_in4>; + }; + }; + + port@35 { + reg = <0x35>; + + xbar_amx2_out: endpoint { + remote-endpoint = <&amx2_out>; + }; + }; + + xbar_amx3_in1_port: port@36 { + reg = <0x36>; + + xbar_amx3_in1: endpoint { + remote-endpoint = <&amx3_in1>; + }; + }; + + xbar_amx3_in2_port: port@37 { + reg = <0x37>; + + xbar_amx3_in2: endpoint { + remote-endpoint = <&amx3_in2>; + }; + }; + + xbar_amx3_in3_port: port@38 { + reg = <0x38>; + + xbar_amx3_in3: endpoint { + remote-endpoint = <&amx3_in3>; + }; + }; + + xbar_amx3_in4_port: port@39 { + reg = <0x39>; + + xbar_amx3_in4: endpoint { + remote-endpoint = <&amx3_in4>; + }; + }; + + port@3a { + reg = <0x3a>; + + xbar_amx3_out: endpoint { + remote-endpoint = <&amx3_out>; + }; + }; + + xbar_amx4_in1_port: port@3b { + reg = <0x3b>; + + xbar_amx4_in1: endpoint { + remote-endpoint = <&amx4_in1>; + }; + }; + + xbar_amx4_in2_port: port@3c { + reg = <0x3c>; + + xbar_amx4_in2: endpoint { + remote-endpoint = <&amx4_in2>; + }; + }; + + xbar_amx4_in3_port: port@3d { + reg = <0x3d>; + + xbar_amx4_in3: endpoint { + remote-endpoint = <&amx4_in3>; + }; + }; + + xbar_amx4_in4_port: port@3e { + reg = <0x3e>; + + xbar_amx4_in4: endpoint { + remote-endpoint = <&amx4_in4>; + }; + }; + + port@3f { + reg = <0x3f>; + + xbar_amx4_out: endpoint { + remote-endpoint = <&amx4_out>; + }; + }; + + xbar_adx1_in_port: port@40 { + reg = <0x40>; + + xbar_adx1_in: endpoint { + remote-endpoint = <&adx1_in>; + }; + }; + + port@41 { + reg = <0x41>; + + xbar_adx1_out1: endpoint { + remote-endpoint = <&adx1_out1>; + }; + }; + + port@42 { + reg = <0x42>; + + xbar_adx1_out2: endpoint { + remote-endpoint = <&adx1_out2>; + }; + }; + + port@43 { + reg = <0x43>; + + xbar_adx1_out3: endpoint { + remote-endpoint = <&adx1_out3>; + }; + }; + + port@44 { + reg = <0x44>; + + xbar_adx1_out4: endpoint { + remote-endpoint = <&adx1_out4>; + }; + }; + + xbar_adx2_in_port: port@45 { + reg = <0x45>; + + xbar_adx2_in: endpoint { + remote-endpoint = <&adx2_in>; + }; + }; + + port@46 { + reg = <0x46>; + + xbar_adx2_out1: endpoint { + remote-endpoint = <&adx2_out1>; + }; + }; + + port@47 { + reg = <0x47>; + + xbar_adx2_out2: endpoint { + remote-endpoint = <&adx2_out2>; + }; + }; + + port@48 { + reg = <0x48>; + + xbar_adx2_out3: endpoint { + remote-endpoint = <&adx2_out3>; + }; + }; + + port@49 { + reg = <0x49>; + + xbar_adx2_out4: endpoint { + remote-endpoint = <&adx2_out4>; + }; + }; + + xbar_adx3_in_port: port@4a { + reg = <0x4a>; + + xbar_adx3_in: endpoint { + remote-endpoint = <&adx3_in>; + }; + }; + + port@4b { + reg = <0x4b>; + + xbar_adx3_out1: endpoint { + remote-endpoint = <&adx3_out1>; + }; + }; + + port@4c { + reg = <0x4c>; + + xbar_adx3_out2: endpoint { + remote-endpoint = <&adx3_out2>; + }; + }; + + port@4d { + reg = <0x4d>; + + xbar_adx3_out3: endpoint { + remote-endpoint = <&adx3_out3>; + }; + }; + + port@4e { + reg = <0x4e>; + + xbar_adx3_out4: endpoint { + remote-endpoint = <&adx3_out4>; + }; + }; + + xbar_adx4_in_port: port@4f { + reg = <0x4f>; + + xbar_adx4_in: endpoint { + remote-endpoint = <&adx4_in>; + }; + }; + + port@50 { + reg = <0x50>; + + xbar_adx4_out1: endpoint { + remote-endpoint = <&adx4_out1>; + }; + }; + + port@51 { + reg = <0x51>; + + xbar_adx4_out2: endpoint { + remote-endpoint = <&adx4_out2>; + }; + }; + + port@52 { + reg = <0x52>; + + xbar_adx4_out3: endpoint { + remote-endpoint = <&adx4_out3>; + }; + }; + + port@53 { + reg = <0x53>; + + xbar_adx4_out4: endpoint { + remote-endpoint = <&adx4_out4>; + }; + }; + + xbar_mix_in1_port: port@54 { + reg = <0x54>; + + xbar_mix_in1: endpoint { + remote-endpoint = <&mix_in1>; + }; + }; + + xbar_mix_in2_port: port@55 { + reg = <0x55>; + + xbar_mix_in2: endpoint { + remote-endpoint = <&mix_in2>; + }; + }; + + xbar_mix_in3_port: port@56 { + reg = <0x56>; + + xbar_mix_in3: endpoint { + remote-endpoint = <&mix_in3>; + }; + }; + + xbar_mix_in4_port: port@57 { + reg = <0x57>; + + xbar_mix_in4: endpoint { + remote-endpoint = <&mix_in4>; + }; + }; + + xbar_mix_in5_port: port@58 { + reg = <0x58>; + + xbar_mix_in5: endpoint { + remote-endpoint = <&mix_in5>; + }; + }; + + xbar_mix_in6_port: port@59 { + reg = <0x59>; + + xbar_mix_in6: endpoint { + remote-endpoint = <&mix_in6>; + }; + }; + + xbar_mix_in7_port: port@5a { + reg = <0x5a>; + + xbar_mix_in7: endpoint { + remote-endpoint = <&mix_in7>; + }; + }; + + xbar_mix_in8_port: port@5b { + reg = <0x5b>; + + xbar_mix_in8: endpoint { + remote-endpoint = <&mix_in8>; + }; + }; + + xbar_mix_in9_port: port@5c { + reg = <0x5c>; + + xbar_mix_in9: endpoint { + remote-endpoint = <&mix_in9>; + }; + }; + + xbar_mix_in10_port: port@5d { + reg = <0x5d>; + + xbar_mix_in10: endpoint { + remote-endpoint = <&mix_in10>; + }; + }; + + port@5e { + reg = <0x5e>; + + xbar_mix_out1: endpoint { + remote-endpoint = <&mix_out1>; + }; + }; + + port@5f { + reg = <0x5f>; + + xbar_mix_out2: endpoint { + remote-endpoint = <&mix_out2>; + }; + }; + + port@60 { + reg = <0x60>; + + xbar_mix_out3: endpoint { + remote-endpoint = <&mix_out3>; + }; + }; + + port@61 { + reg = <0x61>; + + xbar_mix_out4: endpoint { + remote-endpoint = <&mix_out4>; + }; + }; + + port@62 { + reg = <0x62>; + + xbar_mix_out5: endpoint { + remote-endpoint = <&mix_out5>; + }; + }; + + xbar_asrc_in1_port: port@63 { + reg = <0x63>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@64 { + reg = <0x64>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@65 { + reg = <0x65>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@67 { + reg = <0x67>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@69 { + reg = <0x69>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@6b { + reg = <0x6b>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@6d { + reg = <0x6d>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@6e { + reg = <0x6e>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@6f { + reg = <0x6f>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; + + xbar_ope1_in_port: port@70 { + reg = <0x70>; + + xbar_ope1_in_ep: endpoint { + remote-endpoint = <&ope1_cif_in_ep>; + }; + }; + + port@71 { + reg = <0x71>; + + xbar_ope1_out_ep: endpoint { + remote-endpoint = <&ope1_cif_out_ep>; + }; + }; + }; + }; + + dma-controller@2930000 { + status = "okay"; + }; + + interrupt-controller@2a40000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index cd13cf2381dd..4413a9b6da87 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -3,7 +3,6 @@ #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/input/gpio-keys.h> -#include <dt-bindings/sound/rt5640.h> #include "tegra234-p3701-0000.dtsi" #include "tegra234-p3737-0000.dtsi" @@ -24,2024 +23,16 @@ }; bus@0 { - aconnect@2900000 { - status = "okay"; - - ahub@2900800 { - status = "okay"; - - i2s@2901000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s1_cif: endpoint { - remote-endpoint = <&xbar_i2s1>; - }; - }; - - i2s1_port: port@1 { - reg = <1>; - - i2s1_dap: endpoint { - dai-format = "i2s"; - remote-endpoint = <&rt5640_ep>; - }; - }; - }; - }; - - i2s@2901100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s2_cif: endpoint { - remote-endpoint = <&xbar_i2s2>; - }; - }; - - i2s2_port: port@1 { - reg = <1>; - - i2s2_dap: endpoint { - dai-format = "i2s"; - /* placeholder for external codec */ - }; - }; - }; - }; - - i2s@2901300 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s4_cif: endpoint { - remote-endpoint = <&xbar_i2s4>; - }; - }; - - i2s4_port: port@1 { - reg = <1>; - - i2s4_dap: endpoint { - dai-format = "i2s"; - /* placeholder for external codec */ - }; - }; - }; - }; - - i2s@2901500 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - i2s6_cif: endpoint { - remote-endpoint = <&xbar_i2s6>; - }; - }; - - i2s6_port: port@1 { - reg = <1>; - - i2s6_dap: endpoint { - dai-format = "i2s"; - /* placeholder for external codec */ - }; - }; - }; - }; - - sfc@2902000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc1_cif_in: endpoint { - remote-endpoint = <&xbar_sfc1_in>; - }; - }; - - sfc1_out_port: port@1 { - reg = <1>; - - sfc1_cif_out: endpoint { - remote-endpoint = <&xbar_sfc1_out>; - }; - }; - }; - }; - - sfc@2902200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc2_cif_in: endpoint { - remote-endpoint = <&xbar_sfc2_in>; - }; - }; - - sfc2_out_port: port@1 { - reg = <1>; - - sfc2_cif_out: endpoint { - remote-endpoint = <&xbar_sfc2_out>; - }; - }; - }; - }; - - sfc@2902400 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc3_cif_in: endpoint { - remote-endpoint = <&xbar_sfc3_in>; - }; - }; - - sfc3_out_port: port@1 { - reg = <1>; - - sfc3_cif_out: endpoint { - remote-endpoint = <&xbar_sfc3_out>; - }; - }; - }; - }; - - sfc@2902600 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - sfc4_cif_in: endpoint { - remote-endpoint = <&xbar_sfc4_in>; - }; - }; - - sfc4_out_port: port@1 { - reg = <1>; - - sfc4_cif_out: endpoint { - remote-endpoint = <&xbar_sfc4_out>; - }; - }; - }; - }; - - amx@2903000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx1_in1: endpoint { - remote-endpoint = <&xbar_amx1_in1>; - }; - }; - - port@1 { - reg = <1>; - - amx1_in2: endpoint { - remote-endpoint = <&xbar_amx1_in2>; - }; - }; - - port@2 { - reg = <2>; - - amx1_in3: endpoint { - remote-endpoint = <&xbar_amx1_in3>; - }; - }; - - port@3 { - reg = <3>; - - amx1_in4: endpoint { - remote-endpoint = <&xbar_amx1_in4>; - }; - }; - - amx1_out_port: port@4 { - reg = <4>; - - amx1_out: endpoint { - remote-endpoint = <&xbar_amx1_out>; - }; - }; - }; - }; - - amx@2903100 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx2_in1: endpoint { - remote-endpoint = <&xbar_amx2_in1>; - }; - }; - - port@1 { - reg = <1>; - - amx2_in2: endpoint { - remote-endpoint = <&xbar_amx2_in2>; - }; - }; - - port@2 { - reg = <2>; - - amx2_in3: endpoint { - remote-endpoint = <&xbar_amx2_in3>; - }; - }; - - port@3 { - reg = <3>; - - amx2_in4: endpoint { - remote-endpoint = <&xbar_amx2_in4>; - }; - }; - - amx2_out_port: port@4 { - reg = <4>; - - amx2_out: endpoint { - remote-endpoint = <&xbar_amx2_out>; - }; - }; - }; - }; - - amx@2903200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx3_in1: endpoint { - remote-endpoint = <&xbar_amx3_in1>; - }; - }; - - port@1 { - reg = <1>; - - amx3_in2: endpoint { - remote-endpoint = <&xbar_amx3_in2>; - }; - }; - - port@2 { - reg = <2>; - - amx3_in3: endpoint { - remote-endpoint = <&xbar_amx3_in3>; - }; - }; - - port@3 { - reg = <3>; - - amx3_in4: endpoint { - remote-endpoint = <&xbar_amx3_in4>; - }; - }; - - amx3_out_port: port@4 { - reg = <4>; - - amx3_out: endpoint { - remote-endpoint = <&xbar_amx3_out>; - }; - }; - }; - }; - - amx@2903300 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - amx4_in1: endpoint { - remote-endpoint = <&xbar_amx4_in1>; - }; - }; - - port@1 { - reg = <1>; - - amx4_in2: endpoint { - remote-endpoint = <&xbar_amx4_in2>; - }; - }; - - port@2 { - reg = <2>; - - amx4_in3: endpoint { - remote-endpoint = <&xbar_amx4_in3>; - }; - }; - - port@3 { - reg = <3>; - - amx4_in4: endpoint { - remote-endpoint = <&xbar_amx4_in4>; - }; - }; - - amx4_out_port: port@4 { - reg = <4>; - - amx4_out: endpoint { - remote-endpoint = <&xbar_amx4_out>; - }; - }; - }; - }; - - adx@2903800 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx1_in: endpoint { - remote-endpoint = <&xbar_adx1_in>; - }; - }; - - adx1_out1_port: port@1 { - reg = <1>; - - adx1_out1: endpoint { - remote-endpoint = <&xbar_adx1_out1>; - }; - }; - - adx1_out2_port: port@2 { - reg = <2>; - - adx1_out2: endpoint { - remote-endpoint = <&xbar_adx1_out2>; - }; - }; - - adx1_out3_port: port@3 { - reg = <3>; - - adx1_out3: endpoint { - remote-endpoint = <&xbar_adx1_out3>; - }; - }; - - adx1_out4_port: port@4 { - reg = <4>; - - adx1_out4: endpoint { - remote-endpoint = <&xbar_adx1_out4>; - }; - }; - }; - }; - - adx@2903900 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx2_in: endpoint { - remote-endpoint = <&xbar_adx2_in>; - }; - }; - - adx2_out1_port: port@1 { - reg = <1>; - - adx2_out1: endpoint { - remote-endpoint = <&xbar_adx2_out1>; - }; - }; - - adx2_out2_port: port@2 { - reg = <2>; - - adx2_out2: endpoint { - remote-endpoint = <&xbar_adx2_out2>; - }; - }; - - adx2_out3_port: port@3 { - reg = <3>; - - adx2_out3: endpoint { - remote-endpoint = <&xbar_adx2_out3>; - }; - }; - - adx2_out4_port: port@4 { - reg = <4>; - - adx2_out4: endpoint { - remote-endpoint = <&xbar_adx2_out4>; - }; - }; - }; - }; - - adx@2903a00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx3_in: endpoint { - remote-endpoint = <&xbar_adx3_in>; - }; - }; - - adx3_out1_port: port@1 { - reg = <1>; - - adx3_out1: endpoint { - remote-endpoint = <&xbar_adx3_out1>; - }; - }; - - adx3_out2_port: port@2 { - reg = <2>; - - adx3_out2: endpoint { - remote-endpoint = <&xbar_adx3_out2>; - }; - }; - - adx3_out3_port: port@3 { - reg = <3>; - - adx3_out3: endpoint { - remote-endpoint = <&xbar_adx3_out3>; - }; - }; - - adx3_out4_port: port@4 { - reg = <4>; - - adx3_out4: endpoint { - remote-endpoint = <&xbar_adx3_out4>; - }; - }; - }; - }; - - adx@2903b00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - adx4_in: endpoint { - remote-endpoint = <&xbar_adx4_in>; - }; - }; - - adx4_out1_port: port@1 { - reg = <1>; - - adx4_out1: endpoint { - remote-endpoint = <&xbar_adx4_out1>; - }; - }; - - adx4_out2_port: port@2 { - reg = <2>; - - adx4_out2: endpoint { - remote-endpoint = <&xbar_adx4_out2>; - }; - }; - - adx4_out3_port: port@3 { - reg = <3>; - - adx4_out3: endpoint { - remote-endpoint = <&xbar_adx4_out3>; - }; - }; - - adx4_out4_port: port@4 { - reg = <4>; - - adx4_out4: endpoint { - remote-endpoint = <&xbar_adx4_out4>; - }; - }; - }; - }; - - dmic@2904200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - dmic3_cif: endpoint { - remote-endpoint = <&xbar_dmic3>; - }; - }; - - dmic3_port: port@1 { - reg = <1>; - - dmic3_dap: endpoint { - /* placeholder for external codec */ - }; - }; - }; - }; - - processing-engine@2908000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - ope1_cif_in_ep: endpoint { - remote-endpoint = <&xbar_ope1_in_ep>; - }; - }; - - ope1_out_port: port@1 { - reg = <0x1>; - - ope1_cif_out_ep: endpoint { - remote-endpoint = <&xbar_ope1_out_ep>; - }; - }; - }; - }; - - mvc@290a000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc1_cif_in: endpoint { - remote-endpoint = <&xbar_mvc1_in>; - }; - }; - - mvc1_out_port: port@1 { - reg = <1>; - - mvc1_cif_out: endpoint { - remote-endpoint = <&xbar_mvc1_out>; - }; - }; - }; - }; - - mvc@290a200 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - mvc2_cif_in: endpoint { - remote-endpoint = <&xbar_mvc2_in>; - }; - }; - - mvc2_out_port: port@1 { - reg = <1>; - - mvc2_cif_out: endpoint { - remote-endpoint = <&xbar_mvc2_out>; - }; - }; - }; - }; - - amixer@290bb00 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - mix_in1: endpoint { - remote-endpoint = <&xbar_mix_in1>; - }; - }; - - port@1 { - reg = <0x1>; - - mix_in2: endpoint { - remote-endpoint = <&xbar_mix_in2>; - }; - }; - - port@2 { - reg = <0x2>; - - mix_in3: endpoint { - remote-endpoint = <&xbar_mix_in3>; - }; - }; - - port@3 { - reg = <0x3>; - - mix_in4: endpoint { - remote-endpoint = <&xbar_mix_in4>; - }; - }; - - port@4 { - reg = <0x4>; - - mix_in5: endpoint { - remote-endpoint = <&xbar_mix_in5>; - }; - }; - - port@5 { - reg = <0x5>; - - mix_in6: endpoint { - remote-endpoint = <&xbar_mix_in6>; - }; - }; - - port@6 { - reg = <0x6>; - - mix_in7: endpoint { - remote-endpoint = <&xbar_mix_in7>; - }; - }; - - port@7 { - reg = <0x7>; - - mix_in8: endpoint { - remote-endpoint = <&xbar_mix_in8>; - }; - }; - - port@8 { - reg = <0x8>; - - mix_in9: endpoint { - remote-endpoint = <&xbar_mix_in9>; - }; - }; - - port@9 { - reg = <0x9>; - - mix_in10: endpoint { - remote-endpoint = <&xbar_mix_in10>; - }; - }; - - mix_out1_port: port@a { - reg = <0xa>; - - mix_out1: endpoint { - remote-endpoint = <&xbar_mix_out1>; - }; - }; - - mix_out2_port: port@b { - reg = <0xb>; - - mix_out2: endpoint { - remote-endpoint = <&xbar_mix_out2>; - }; - }; - - mix_out3_port: port@c { - reg = <0xc>; - - mix_out3: endpoint { - remote-endpoint = <&xbar_mix_out3>; - }; - }; - - mix_out4_port: port@d { - reg = <0xd>; - - mix_out4: endpoint { - remote-endpoint = <&xbar_mix_out4>; - }; - }; - - mix_out5_port: port@e { - reg = <0xe>; - - mix_out5: endpoint { - remote-endpoint = <&xbar_mix_out5>; - }; - }; - }; - }; - - admaif@290f000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - admaif0_port: port@0 { - reg = <0x0>; - - admaif0: endpoint { - remote-endpoint = <&xbar_admaif0>; - }; - }; - - admaif1_port: port@1 { - reg = <0x1>; - - admaif1: endpoint { - remote-endpoint = <&xbar_admaif1>; - }; - }; - - admaif2_port: port@2 { - reg = <0x2>; - - admaif2: endpoint { - remote-endpoint = <&xbar_admaif2>; - }; - }; - - admaif3_port: port@3 { - reg = <0x3>; - - admaif3: endpoint { - remote-endpoint = <&xbar_admaif3>; - }; - }; - - admaif4_port: port@4 { - reg = <0x4>; - - admaif4: endpoint { - remote-endpoint = <&xbar_admaif4>; - }; - }; - - admaif5_port: port@5 { - reg = <0x5>; - - admaif5: endpoint { - remote-endpoint = <&xbar_admaif5>; - }; - }; - - admaif6_port: port@6 { - reg = <0x6>; - - admaif6: endpoint { - remote-endpoint = <&xbar_admaif6>; - }; - }; - - admaif7_port: port@7 { - reg = <0x7>; - - admaif7: endpoint { - remote-endpoint = <&xbar_admaif7>; - }; - }; - - admaif8_port: port@8 { - reg = <0x8>; - - admaif8: endpoint { - remote-endpoint = <&xbar_admaif8>; - }; - }; - - admaif9_port: port@9 { - reg = <0x9>; - - admaif9: endpoint { - remote-endpoint = <&xbar_admaif9>; - }; - }; - - admaif10_port: port@a { - reg = <0xa>; - - admaif10: endpoint { - remote-endpoint = <&xbar_admaif10>; - }; - }; - - admaif11_port: port@b { - reg = <0xb>; - - admaif11: endpoint { - remote-endpoint = <&xbar_admaif11>; - }; - }; - - admaif12_port: port@c { - reg = <0xc>; - - admaif12: endpoint { - remote-endpoint = <&xbar_admaif12>; - }; - }; - - admaif13_port: port@d { - reg = <0xd>; - - admaif13: endpoint { - remote-endpoint = <&xbar_admaif13>; - }; - }; - - admaif14_port: port@e { - reg = <0xe>; - - admaif14: endpoint { - remote-endpoint = <&xbar_admaif14>; - }; - }; - - admaif15_port: port@f { - reg = <0xf>; - - admaif15: endpoint { - remote-endpoint = <&xbar_admaif15>; - }; - }; - - admaif16_port: port@10 { - reg = <0x10>; - - admaif16: endpoint { - remote-endpoint = <&xbar_admaif16>; - }; - }; - - admaif17_port: port@11 { - reg = <0x11>; - - admaif17: endpoint { - remote-endpoint = <&xbar_admaif17>; - }; - }; - - admaif18_port: port@12 { - reg = <0x12>; - - admaif18: endpoint { - remote-endpoint = <&xbar_admaif18>; - }; - }; - - admaif19_port: port@13 { - reg = <0x13>; - - admaif19: endpoint { - remote-endpoint = <&xbar_admaif19>; - }; - }; - }; - }; - - asrc@2910000 { - status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - asrc_in1_ep: endpoint { - remote-endpoint = <&xbar_asrc_in1_ep>; - }; - }; - - port@1 { - reg = <0x1>; - - asrc_in2_ep: endpoint { - remote-endpoint = <&xbar_asrc_in2_ep>; - }; - }; - - port@2 { - reg = <0x2>; - - asrc_in3_ep: endpoint { - remote-endpoint = <&xbar_asrc_in3_ep>; - }; - }; - - port@3 { - reg = <0x3>; - - asrc_in4_ep: endpoint { - remote-endpoint = <&xbar_asrc_in4_ep>; - }; - }; - - port@4 { - reg = <0x4>; - - asrc_in5_ep: endpoint { - remote-endpoint = <&xbar_asrc_in5_ep>; - }; - }; - - port@5 { - reg = <0x5>; - - asrc_in6_ep: endpoint { - remote-endpoint = <&xbar_asrc_in6_ep>; - }; - }; - - port@6 { - reg = <0x6>; - - asrc_in7_ep: endpoint { - remote-endpoint = <&xbar_asrc_in7_ep>; - }; - }; - - asrc_out1_port: port@7 { - reg = <0x7>; - - asrc_out1_ep: endpoint { - remote-endpoint = <&xbar_asrc_out1_ep>; - }; - }; - - asrc_out2_port: port@8 { - reg = <0x8>; - - asrc_out2_ep: endpoint { - remote-endpoint = <&xbar_asrc_out2_ep>; - }; - }; - - asrc_out3_port: port@9 { - reg = <0x9>; - - asrc_out3_ep: endpoint { - remote-endpoint = <&xbar_asrc_out3_ep>; - }; - }; - - asrc_out4_port: port@a { - reg = <0xa>; - - asrc_out4_ep: endpoint { - remote-endpoint = <&xbar_asrc_out4_ep>; - }; - }; - - asrc_out5_port: port@b { - reg = <0xb>; - - asrc_out5_ep: endpoint { - remote-endpoint = <&xbar_asrc_out5_ep>; - }; - }; - - asrc_out6_port: port@c { - reg = <0xc>; - - asrc_out6_ep: endpoint { - remote-endpoint = <&xbar_asrc_out6_ep>; - }; - }; - }; - }; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0x0>; - - xbar_admaif0: endpoint { - remote-endpoint = <&admaif0>; - }; - }; - - port@1 { - reg = <0x1>; - - xbar_admaif1: endpoint { - remote-endpoint = <&admaif1>; - }; - }; - - port@2 { - reg = <0x2>; - - xbar_admaif2: endpoint { - remote-endpoint = <&admaif2>; - }; - }; - - port@3 { - reg = <0x3>; - - xbar_admaif3: endpoint { - remote-endpoint = <&admaif3>; - }; - }; - - port@4 { - reg = <0x4>; - - xbar_admaif4: endpoint { - remote-endpoint = <&admaif4>; - }; - }; - - port@5 { - reg = <0x5>; - - xbar_admaif5: endpoint { - remote-endpoint = <&admaif5>; - }; - }; - - port@6 { - reg = <0x6>; - - xbar_admaif6: endpoint { - remote-endpoint = <&admaif6>; - }; - }; - - port@7 { - reg = <0x7>; - - xbar_admaif7: endpoint { - remote-endpoint = <&admaif7>; - }; - }; - - port@8 { - reg = <0x8>; - - xbar_admaif8: endpoint { - remote-endpoint = <&admaif8>; - }; - }; - - port@9 { - reg = <0x9>; - - xbar_admaif9: endpoint { - remote-endpoint = <&admaif9>; - }; - }; - - port@a { - reg = <0xa>; - - xbar_admaif10: endpoint { - remote-endpoint = <&admaif10>; - }; - }; - - port@b { - reg = <0xb>; - - xbar_admaif11: endpoint { - remote-endpoint = <&admaif11>; - }; - }; - - port@c { - reg = <0xc>; - - xbar_admaif12: endpoint { - remote-endpoint = <&admaif12>; - }; - }; - - port@d { - reg = <0xd>; - - xbar_admaif13: endpoint { - remote-endpoint = <&admaif13>; - }; - }; - - port@e { - reg = <0xe>; - - xbar_admaif14: endpoint { - remote-endpoint = <&admaif14>; - }; - }; - - port@f { - reg = <0xf>; - - xbar_admaif15: endpoint { - remote-endpoint = <&admaif15>; - }; - }; - - port@10 { - reg = <0x10>; - - xbar_admaif16: endpoint { - remote-endpoint = <&admaif16>; - }; - }; - - port@11 { - reg = <0x11>; - - xbar_admaif17: endpoint { - remote-endpoint = <&admaif17>; - }; - }; - - port@12 { - reg = <0x12>; - - xbar_admaif18: endpoint { - remote-endpoint = <&admaif18>; - }; - }; - - port@13 { - reg = <0x13>; - - xbar_admaif19: endpoint { - remote-endpoint = <&admaif19>; - }; - }; - - xbar_i2s1_port: port@14 { - reg = <0x14>; - - xbar_i2s1: endpoint { - remote-endpoint = <&i2s1_cif>; - }; - }; - - xbar_i2s2_port: port@15 { - reg = <0x15>; - - xbar_i2s2: endpoint { - remote-endpoint = <&i2s2_cif>; - }; - }; - - xbar_i2s4_port: port@17 { - reg = <0x17>; - - xbar_i2s4: endpoint { - remote-endpoint = <&i2s4_cif>; - }; - }; - - xbar_i2s6_port: port@19 { - reg = <0x19>; - - xbar_i2s6: endpoint { - remote-endpoint = <&i2s6_cif>; - }; - }; - - xbar_dmic3_port: port@1c { - reg = <0x1c>; - - xbar_dmic3: endpoint { - remote-endpoint = <&dmic3_cif>; - }; - }; - - xbar_sfc1_in_port: port@20 { - reg = <0x20>; - - xbar_sfc1_in: endpoint { - remote-endpoint = <&sfc1_cif_in>; - }; - }; - - port@21 { - reg = <0x21>; - - xbar_sfc1_out: endpoint { - remote-endpoint = <&sfc1_cif_out>; - }; - }; - - xbar_sfc2_in_port: port@22 { - reg = <0x22>; - - xbar_sfc2_in: endpoint { - remote-endpoint = <&sfc2_cif_in>; - }; - }; - - port@23 { - reg = <0x23>; - - xbar_sfc2_out: endpoint { - remote-endpoint = <&sfc2_cif_out>; - }; - }; - - xbar_sfc3_in_port: port@24 { - reg = <0x24>; - - xbar_sfc3_in: endpoint { - remote-endpoint = <&sfc3_cif_in>; - }; - }; - - port@25 { - reg = <0x25>; - - xbar_sfc3_out: endpoint { - remote-endpoint = <&sfc3_cif_out>; - }; - }; - - xbar_sfc4_in_port: port@26 { - reg = <0x26>; - - xbar_sfc4_in: endpoint { - remote-endpoint = <&sfc4_cif_in>; - }; - }; - - port@27 { - reg = <0x27>; - - xbar_sfc4_out: endpoint { - remote-endpoint = <&sfc4_cif_out>; - }; - }; - - xbar_mvc1_in_port: port@28 { - reg = <0x28>; - - xbar_mvc1_in: endpoint { - remote-endpoint = <&mvc1_cif_in>; - }; - }; - - port@29 { - reg = <0x29>; - - xbar_mvc1_out: endpoint { - remote-endpoint = <&mvc1_cif_out>; - }; - }; - - xbar_mvc2_in_port: port@2a { - reg = <0x2a>; - - xbar_mvc2_in: endpoint { - remote-endpoint = <&mvc2_cif_in>; - }; - }; - - port@2b { - reg = <0x2b>; - - xbar_mvc2_out: endpoint { - remote-endpoint = <&mvc2_cif_out>; - }; - }; - - xbar_amx1_in1_port: port@2c { - reg = <0x2c>; - - xbar_amx1_in1: endpoint { - remote-endpoint = <&amx1_in1>; - }; - }; - - xbar_amx1_in2_port: port@2d { - reg = <0x2d>; - - xbar_amx1_in2: endpoint { - remote-endpoint = <&amx1_in2>; - }; - }; - - xbar_amx1_in3_port: port@2e { - reg = <0x2e>; - - xbar_amx1_in3: endpoint { - remote-endpoint = <&amx1_in3>; - }; - }; - - xbar_amx1_in4_port: port@2f { - reg = <0x2f>; - - xbar_amx1_in4: endpoint { - remote-endpoint = <&amx1_in4>; - }; - }; - - port@30 { - reg = <0x30>; - - xbar_amx1_out: endpoint { - remote-endpoint = <&amx1_out>; - }; - }; - - xbar_amx2_in1_port: port@31 { - reg = <0x31>; - - xbar_amx2_in1: endpoint { - remote-endpoint = <&amx2_in1>; - }; - }; - - xbar_amx2_in2_port: port@32 { - reg = <0x32>; - - xbar_amx2_in2: endpoint { - remote-endpoint = <&amx2_in2>; - }; - }; - - xbar_amx2_in3_port: port@33 { - reg = <0x33>; - - xbar_amx2_in3: endpoint { - remote-endpoint = <&amx2_in3>; - }; - }; - - xbar_amx2_in4_port: port@34 { - reg = <0x34>; - - xbar_amx2_in4: endpoint { - remote-endpoint = <&amx2_in4>; - }; - }; - - port@35 { - reg = <0x35>; - - xbar_amx2_out: endpoint { - remote-endpoint = <&amx2_out>; - }; - }; - - xbar_amx3_in1_port: port@36 { - reg = <0x36>; - - xbar_amx3_in1: endpoint { - remote-endpoint = <&amx3_in1>; - }; - }; - - xbar_amx3_in2_port: port@37 { - reg = <0x37>; - - xbar_amx3_in2: endpoint { - remote-endpoint = <&amx3_in2>; - }; - }; - - xbar_amx3_in3_port: port@38 { - reg = <0x38>; - - xbar_amx3_in3: endpoint { - remote-endpoint = <&amx3_in3>; - }; - }; - - xbar_amx3_in4_port: port@39 { - reg = <0x39>; - - xbar_amx3_in4: endpoint { - remote-endpoint = <&amx3_in4>; - }; - }; - - port@3a { - reg = <0x3a>; - - xbar_amx3_out: endpoint { - remote-endpoint = <&amx3_out>; - }; - }; - - xbar_amx4_in1_port: port@3b { - reg = <0x3b>; - - xbar_amx4_in1: endpoint { - remote-endpoint = <&amx4_in1>; - }; - }; - - xbar_amx4_in2_port: port@3c { - reg = <0x3c>; - - xbar_amx4_in2: endpoint { - remote-endpoint = <&amx4_in2>; - }; - }; - - xbar_amx4_in3_port: port@3d { - reg = <0x3d>; - - xbar_amx4_in3: endpoint { - remote-endpoint = <&amx4_in3>; - }; - }; - - xbar_amx4_in4_port: port@3e { - reg = <0x3e>; - - xbar_amx4_in4: endpoint { - remote-endpoint = <&amx4_in4>; - }; - }; - - port@3f { - reg = <0x3f>; - - xbar_amx4_out: endpoint { - remote-endpoint = <&amx4_out>; - }; - }; - - xbar_adx1_in_port: port@40 { - reg = <0x40>; - - xbar_adx1_in: endpoint { - remote-endpoint = <&adx1_in>; - }; - }; - - port@41 { - reg = <0x41>; - - xbar_adx1_out1: endpoint { - remote-endpoint = <&adx1_out1>; - }; - }; - - port@42 { - reg = <0x42>; - - xbar_adx1_out2: endpoint { - remote-endpoint = <&adx1_out2>; - }; - }; - - port@43 { - reg = <0x43>; - - xbar_adx1_out3: endpoint { - remote-endpoint = <&adx1_out3>; - }; - }; - - port@44 { - reg = <0x44>; - - xbar_adx1_out4: endpoint { - remote-endpoint = <&adx1_out4>; - }; - }; - - xbar_adx2_in_port: port@45 { - reg = <0x45>; - - xbar_adx2_in: endpoint { - remote-endpoint = <&adx2_in>; - }; - }; - - port@46 { - reg = <0x46>; - - xbar_adx2_out1: endpoint { - remote-endpoint = <&adx2_out1>; - }; - }; - - port@47 { - reg = <0x47>; - - xbar_adx2_out2: endpoint { - remote-endpoint = <&adx2_out2>; - }; - }; - - port@48 { - reg = <0x48>; - - xbar_adx2_out3: endpoint { - remote-endpoint = <&adx2_out3>; - }; - }; - - port@49 { - reg = <0x49>; - - xbar_adx2_out4: endpoint { - remote-endpoint = <&adx2_out4>; - }; - }; - - xbar_adx3_in_port: port@4a { - reg = <0x4a>; - - xbar_adx3_in: endpoint { - remote-endpoint = <&adx3_in>; - }; - }; - - port@4b { - reg = <0x4b>; - - xbar_adx3_out1: endpoint { - remote-endpoint = <&adx3_out1>; - }; - }; - - port@4c { - reg = <0x4c>; - - xbar_adx3_out2: endpoint { - remote-endpoint = <&adx3_out2>; - }; - }; - - port@4d { - reg = <0x4d>; - - xbar_adx3_out3: endpoint { - remote-endpoint = <&adx3_out3>; - }; - }; - - port@4e { - reg = <0x4e>; - - xbar_adx3_out4: endpoint { - remote-endpoint = <&adx3_out4>; - }; - }; - - xbar_adx4_in_port: port@4f { - reg = <0x4f>; - - xbar_adx4_in: endpoint { - remote-endpoint = <&adx4_in>; - }; - }; - - port@50 { - reg = <0x50>; - - xbar_adx4_out1: endpoint { - remote-endpoint = <&adx4_out1>; - }; - }; - - port@51 { - reg = <0x51>; - - xbar_adx4_out2: endpoint { - remote-endpoint = <&adx4_out2>; - }; - }; - - port@52 { - reg = <0x52>; - - xbar_adx4_out3: endpoint { - remote-endpoint = <&adx4_out3>; - }; - }; - - port@53 { - reg = <0x53>; - - xbar_adx4_out4: endpoint { - remote-endpoint = <&adx4_out4>; - }; - }; - - xbar_mix_in1_port: port@54 { - reg = <0x54>; - - xbar_mix_in1: endpoint { - remote-endpoint = <&mix_in1>; - }; - }; - - xbar_mix_in2_port: port@55 { - reg = <0x55>; - - xbar_mix_in2: endpoint { - remote-endpoint = <&mix_in2>; - }; - }; - - xbar_mix_in3_port: port@56 { - reg = <0x56>; - - xbar_mix_in3: endpoint { - remote-endpoint = <&mix_in3>; - }; - }; - - xbar_mix_in4_port: port@57 { - reg = <0x57>; - - xbar_mix_in4: endpoint { - remote-endpoint = <&mix_in4>; - }; - }; - - xbar_mix_in5_port: port@58 { - reg = <0x58>; - - xbar_mix_in5: endpoint { - remote-endpoint = <&mix_in5>; - }; - }; - - xbar_mix_in6_port: port@59 { - reg = <0x59>; - - xbar_mix_in6: endpoint { - remote-endpoint = <&mix_in6>; - }; - }; - - xbar_mix_in7_port: port@5a { - reg = <0x5a>; - - xbar_mix_in7: endpoint { - remote-endpoint = <&mix_in7>; - }; - }; - - xbar_mix_in8_port: port@5b { - reg = <0x5b>; - - xbar_mix_in8: endpoint { - remote-endpoint = <&mix_in8>; - }; - }; - - xbar_mix_in9_port: port@5c { - reg = <0x5c>; - - xbar_mix_in9: endpoint { - remote-endpoint = <&mix_in9>; - }; - }; - - xbar_mix_in10_port: port@5d { - reg = <0x5d>; - - xbar_mix_in10: endpoint { - remote-endpoint = <&mix_in10>; - }; - }; - - port@5e { - reg = <0x5e>; - - xbar_mix_out1: endpoint { - remote-endpoint = <&mix_out1>; - }; - }; - - port@5f { - reg = <0x5f>; - - xbar_mix_out2: endpoint { - remote-endpoint = <&mix_out2>; - }; - }; - - port@60 { - reg = <0x60>; - - xbar_mix_out3: endpoint { - remote-endpoint = <&mix_out3>; - }; - }; - - port@61 { - reg = <0x61>; - - xbar_mix_out4: endpoint { - remote-endpoint = <&mix_out4>; - }; - }; - - port@62 { - reg = <0x62>; - - xbar_mix_out5: endpoint { - remote-endpoint = <&mix_out5>; - }; - }; - - xbar_asrc_in1_port: port@63 { - reg = <0x63>; - - xbar_asrc_in1_ep: endpoint { - remote-endpoint = <&asrc_in1_ep>; - }; - }; - - port@64 { - reg = <0x64>; - - xbar_asrc_out1_ep: endpoint { - remote-endpoint = <&asrc_out1_ep>; - }; - }; - - xbar_asrc_in2_port: port@65 { - reg = <0x65>; - - xbar_asrc_in2_ep: endpoint { - remote-endpoint = <&asrc_in2_ep>; - }; - }; - - port@66 { - reg = <0x66>; - - xbar_asrc_out2_ep: endpoint { - remote-endpoint = <&asrc_out2_ep>; - }; - }; - - xbar_asrc_in3_port: port@67 { - reg = <0x67>; - - xbar_asrc_in3_ep: endpoint { - remote-endpoint = <&asrc_in3_ep>; - }; - }; - - port@68 { - reg = <0x68>; - - xbar_asrc_out3_ep: endpoint { - remote-endpoint = <&asrc_out3_ep>; - }; - }; - - xbar_asrc_in4_port: port@69 { - reg = <0x69>; - - xbar_asrc_in4_ep: endpoint { - remote-endpoint = <&asrc_in4_ep>; - }; - }; - - port@6a { - reg = <0x6a>; - - xbar_asrc_out4_ep: endpoint { - remote-endpoint = <&asrc_out4_ep>; - }; - }; - - xbar_asrc_in5_port: port@6b { - reg = <0x6b>; - - xbar_asrc_in5_ep: endpoint { - remote-endpoint = <&asrc_in5_ep>; - }; - }; - - port@6c { - reg = <0x6c>; - - xbar_asrc_out5_ep: endpoint { - remote-endpoint = <&asrc_out5_ep>; - }; - }; - - xbar_asrc_in6_port: port@6d { - reg = <0x6d>; - - xbar_asrc_in6_ep: endpoint { - remote-endpoint = <&asrc_in6_ep>; - }; - }; - - port@6e { - reg = <0x6e>; - - xbar_asrc_out6_ep: endpoint { - remote-endpoint = <&asrc_out6_ep>; - }; - }; - - xbar_asrc_in7_port: port@6f { - reg = <0x6f>; - - xbar_asrc_in7_ep: endpoint { - remote-endpoint = <&asrc_in7_ep>; - }; - }; - - xbar_ope1_in_port: port@70 { - reg = <0x70>; - - xbar_ope1_in_ep: endpoint { - remote-endpoint = <&ope1_cif_in_ep>; - }; - }; - - port@71 { - reg = <0x71>; - - xbar_ope1_out_ep: endpoint { - remote-endpoint = <&ope1_cif_out_ep>; - }; - }; - }; - }; - - dma-controller@2930000 { - status = "okay"; - }; - - interrupt-controller@2a40000 { - status = "okay"; - }; - }; - serial@3100000 { compatible = "nvidia,tegra194-hsuart"; + reset-names = "serial"; status = "okay"; }; serial@31d0000 { - current-speed = <115200>; status = "okay"; }; - i2c@31e0000 { - status = "okay"; - - audio-codec@1c { - compatible = "realtek,rt5640"; - reg = <0x1c>; - interrupt-parent = <&gpio>; - interrupts = <TEGRA234_MAIN_GPIO(AC, 5) GPIO_ACTIVE_HIGH>; - clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>; - clock-names = "mclk"; - realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>; - realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>; - realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>; - sound-name-prefix = "CVB-RT"; - - port { - rt5640_ep: endpoint { - remote-endpoint = <&i2s1_dap>; - mclk-fs = <256>; - }; - }; - }; - }; - pwm@32a0000 { assigned-clocks = <&bpmp TEGRA234_CLK_PWM3>; assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; @@ -2099,6 +90,7 @@ mode = "otg"; usb-role-switch; status = "okay"; + port { hs_typec_p1: endpoint { remote-endpoint = <&hs_ucsi_ccg_p1>; @@ -2109,6 +101,7 @@ usb2-1 { mode = "host"; status = "okay"; + port { hs_typec_p0: endpoint { remote-endpoint = <&hs_ucsi_ccg_p0>; @@ -2129,6 +122,7 @@ usb3-0 { nvidia,usb2-companion = <1>; status = "okay"; + port { ss_typec_p0: endpoint { remote-endpoint = <&ss_ucsi_ccg_p0>; @@ -2139,6 +133,7 @@ usb3-1 { nvidia,usb2-companion = <0>; status = "okay"; + port { ss_typec_p1: endpoint { remote-endpoint = <&ss_ucsi_ccg_p1>; @@ -2194,57 +189,6 @@ }; }; - pcie@14100000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - - phys = <&p2u_hsio_3>; - phy-names = "p2u-0"; - }; - - pcie@14160000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - - phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>, - <&p2u_hsio_7>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; - }; - - pcie@141a0000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8_ls>; - vpcie3v3-supply = <&vdd_3v3_pcie>; - vpcie12v-supply = <&vdd_12v_pcie>; - - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; - - pcie-ep@141a0000 { - status = "disabled"; - - vddio-pex-ctl-supply = <&vdd_1v8_ls>; - - reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>; - - nvidia,refclk-select-gpios = <&gpio_aon - TEGRA234_AON_GPIO(AA, 4) - GPIO_ACTIVE_HIGH>; - - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; - }; - i2c@c240000 { status = "okay"; @@ -2271,6 +215,7 @@ port@0 { reg = <0>; + hs_ucsi_ccg_p0: endpoint { remote-endpoint = <&hs_typec_p0>; }; @@ -2278,6 +223,7 @@ port@1 { reg = <1>; + ss_ucsi_ccg_p0: endpoint { remote-endpoint = <&ss_typec_p0>; }; @@ -2297,6 +243,7 @@ port@0 { reg = <0>; + hs_ucsi_ccg_p1: endpoint { remote-endpoint = <&hs_typec_p1>; }; @@ -2304,6 +251,7 @@ port@1 { reg = <1>; + ss_ucsi_ccg_p1: endpoint { remote-endpoint = <&ss_typec_p1>; }; @@ -2312,6 +260,57 @@ }; }; }; + + pcie@14100000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + + phys = <&p2u_hsio_3>; + phy-names = "p2u-0"; + }; + + pcie@14160000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + + phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>, + <&p2u_hsio_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; + }; + + pcie@141a0000 { + status = "okay"; + + vddio-pex-ctl-supply = <&vdd_1v8_ls>; + vpcie3v3-supply = <&vdd_3v3_pcie>; + vpcie12v-supply = <&vdd_12v_pcie>; + + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; + + pcie-ep@141a0000 { + status = "disabled"; + + vddio-pex-ctl-supply = <&vdd_1v8_ls>; + + reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>; + + nvidia,refclk-select-gpios = <&gpio_aon + TEGRA234_AON_GPIO(AA, 4) + GPIO_ACTIVE_HIGH>; + + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; + }; }; gpio-keys { diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi index d94147f22ebf..eb79e80a9852 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000.dtsi @@ -1,9 +1,26 @@ // SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/sound/rt5640.h> + / { compatible = "nvidia,p3737-0000"; bus@0 { + aconnect@2900000 { + ahub@2900800 { + i2s@2901000 { + ports { + port@1 { + endpoint { + dai-format = "i2s"; + remote-endpoint = <&rt5640_ep>; + }; + }; + }; + }; + }; + }; + i2c@3160000 { status = "okay"; @@ -20,6 +37,30 @@ }; }; + i2c@31e0000 { + status = "okay"; + + audio-codec@1c { + compatible = "realtek,rt5640"; + reg = <0x1c>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA234_MAIN_GPIO(AC, 5) GPIO_ACTIVE_HIGH>; + clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>; + clock-names = "mclk"; + realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>; + realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>; + realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>; + sound-name-prefix = "CVB-RT"; + + port { + rt5640_ep: endpoint { + remote-endpoint = <&i2s1_dap>; + mclk-fs = <256>; + }; + }; + }; + }; + pwm@3280000 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts index 43d797e5544f..bac611d735c5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts @@ -12,6 +12,7 @@ aliases { serial0 = &tcu; + serial1 = &uarta; }; chosen { @@ -19,104 +20,102 @@ }; bus@0 { - host1x@13e00000 { - nvdec@15480000 { - status = "okay"; - }; - }; - - pcie@140e0000 { + serial@3100000 { + compatible = "nvidia,tegra194-hsuart"; + reset-names = "serial"; status = "okay"; - vddio-pex-ctl-supply = <&vdd_1v8_ls>; - phys = <&p2u_gbe_4>, <&p2u_gbe_5>; - phy-names = "p2u-0", "p2u-1"; }; - pcie@14100000 { + i2c@3160000 { status = "okay"; - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - phys = <&p2u_hsio_3>; - phy-names = "p2u-0"; }; - pcie@14160000 { + i2c@3180000 { status = "okay"; - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - phys = <&p2u_hsio_7>, <&p2u_hsio_6>, <&p2u_hsio_5>, - <&p2u_hsio_4>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; }; - pcie@141a0000 { + i2c@3190000 { status = "okay"; - vddio-pex-ctl-supply = <&vdd_1v8_ls>; - phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, - <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, - <&p2u_nvhs_6>, <&p2u_nvhs_7>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", - "p2u-5", "p2u-6", "p2u-7"; }; - pcie@141e0000 { + i2c@31b0000 { status = "okay"; - vddio-pex-ctl-supply = <&vdd_1v8_ls>; - phys = <&p2u_gbe_0>, <&p2u_gbe_1>; - phy-names = "p2u-0", "p2u-1"; }; - aconnect@2900000 { + i2c@31c0000 { status = "okay"; + }; - serial@3100000 { - compatible = "nvidia,tegra194-hsuart"; + i2c@31e0000 { status = "okay"; }; - i2c@3160000 { + spi@3270000 { status = "okay"; }; - i2c@3180000 { + hda@3510000 { + nvidia,model = "NVIDIA IGX Orin HDA"; status = "okay"; }; - i2c@3190000 { + fuse@3810000 { status = "okay"; }; - i2c@31b0000 { + i2c@c240000 { status = "okay"; }; - i2c@31c0000 { + i2c@c250000 { status = "okay"; - }; - i2c@31e0000 { - status = "okay"; + host1x@13e00000 { + nvdec@15480000 { + status = "okay"; + }; }; - spi@3270000 { + pcie@140e0000 { status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8_ls>; + phys = <&p2u_gbe_4>, <&p2u_gbe_5>; + phy-names = "p2u-0", "p2u-1"; }; - hda@3510000 { - nvidia,model = "NVIDIA IGX HDA"; + pcie@14100000 { status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + vpcie3v3-supply = <&vdd_3v3_wifi>; + phys = <&p2u_hsio_3>; + phy-names = "p2u-0"; }; - fuse@3810000 { + pcie@14160000 { status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + phys = <&p2u_hsio_7>, <&p2u_hsio_6>, <&p2u_hsio_5>, + <&p2u_hsio_4>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; }; - i2c@c240000 { + pcie@141a0000 { status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8_ls>; + phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, + <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, + <&p2u_nvhs_6>, <&p2u_nvhs_7>; + phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", + "p2u-5", "p2u-6", "p2u-7"; }; - i2c@c250000 { + pcie@141e0000 { status = "okay"; + vddio-pex-ctl-supply = <&vdd_1v8_ls>; + phys = <&p2u_gbe_0>, <&p2u_gbe_1>; + phy-names = "p2u-0", "p2u-1"; }; }; @@ -151,4 +150,89 @@ serial { status = "okay"; }; + + sound { + status = "okay"; + + compatible = "nvidia,tegra186-audio-graph-card"; + + dais = /* ADMAIF (FE) Ports */ + <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>, + <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>, + <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>, + <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>, + <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>, + /* XBAR Ports */ + <&xbar_i2s1_port>, <&xbar_i2s2_port>, <&xbar_i2s4_port>, + <&xbar_i2s6_port>, <&xbar_dmic3_port>, + <&xbar_sfc1_in_port>, <&xbar_sfc2_in_port>, + <&xbar_sfc3_in_port>, <&xbar_sfc4_in_port>, + <&xbar_mvc1_in_port>, <&xbar_mvc2_in_port>, + <&xbar_amx1_in1_port>, <&xbar_amx1_in2_port>, + <&xbar_amx1_in3_port>, <&xbar_amx1_in4_port>, + <&xbar_amx2_in1_port>, <&xbar_amx2_in2_port>, + <&xbar_amx2_in3_port>, <&xbar_amx2_in4_port>, + <&xbar_amx3_in1_port>, <&xbar_amx3_in2_port>, + <&xbar_amx3_in3_port>, <&xbar_amx3_in4_port>, + <&xbar_amx4_in1_port>, <&xbar_amx4_in2_port>, + <&xbar_amx4_in3_port>, <&xbar_amx4_in4_port>, + <&xbar_adx1_in_port>, <&xbar_adx2_in_port>, + <&xbar_adx3_in_port>, <&xbar_adx4_in_port>, + <&xbar_mix_in1_port>, <&xbar_mix_in2_port>, + <&xbar_mix_in3_port>, <&xbar_mix_in4_port>, + <&xbar_mix_in5_port>, <&xbar_mix_in6_port>, + <&xbar_mix_in7_port>, <&xbar_mix_in8_port>, + <&xbar_mix_in9_port>, <&xbar_mix_in10_port>, + <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>, + <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, + <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, + <&xbar_asrc_in7_port>, + <&xbar_ope1_in_port>, + /* HW accelerators */ + <&sfc1_out_port>, <&sfc2_out_port>, + <&sfc3_out_port>, <&sfc4_out_port>, + <&mvc1_out_port>, <&mvc2_out_port>, + <&amx1_out_port>, <&amx2_out_port>, + <&amx3_out_port>, <&amx4_out_port>, + <&adx1_out1_port>, <&adx1_out2_port>, + <&adx1_out3_port>, <&adx1_out4_port>, + <&adx2_out1_port>, <&adx2_out2_port>, + <&adx2_out3_port>, <&adx2_out4_port>, + <&adx3_out1_port>, <&adx3_out2_port>, + <&adx3_out3_port>, <&adx3_out4_port>, + <&adx4_out1_port>, <&adx4_out2_port>, + <&adx4_out3_port>, <&adx4_out4_port>, + <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>, + <&mix_out4_port>, <&mix_out5_port>, + <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, + <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, + <&ope1_out_port>, + /* BE I/O Ports */ + <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>, + <&dmic3_port>; + + label = "NVIDIA IGX Orin APE"; + + widgets = "Microphone", "CVB-RT MIC Jack", + "Microphone", "CVB-RT MIC", + "Headphone", "CVB-RT HP Jack", + "Speaker", "CVB-RT SPK"; + + routing = /* I2S4 <-> RT5640 */ + "CVB-RT AIF1 Playback", "I2S4 DAP-Playback", + "I2S4 DAP-Capture", "CVB-RT AIF1 Capture", + /* RT5640 codec controls */ + "CVB-RT HP Jack", "CVB-RT HPOL", + "CVB-RT HP Jack", "CVB-RT HPOR", + "CVB-RT IN1P", "CVB-RT MIC Jack", + "CVB-RT IN2P", "CVB-RT MIC Jack", + "CVB-RT IN2N", "CVB-RT MIC Jack", + "CVB-RT IN3P", "CVB-RT MIC Jack", + "CVB-RT SPK", "CVB-RT SPOLP", + "CVB-RT SPK", "CVB-RT SPORP", + "CVB-RT SPK", "CVB-RT LOUTL", + "CVB-RT SPK", "CVB-RT LOUTR", + "CVB-RT DMIC1", "CVB-RT MIC", + "CVB-RT DMIC2", "CVB-RT MIC"; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002.dtsi index c95063b19321..527f2f3aee3a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002.dtsi @@ -1,10 +1,60 @@ // SPDX-License-Identifier: GPL-2.0 +#include <dt-bindings/sound/rt5640.h> + / { compatible = "nvidia,p3740-0002"; bus@0 { + aconnect@2900000 { + ahub@2900800 { + i2s@2901300 { + ports { + port@1 { + endpoint { + dai-format = "i2s"; + remote-endpoint = <&rt5640_ep>; + }; + }; + }; + }; + + i2s@2901500 { + ports { + port@1 { + endpoint { + bitclock-master; + frame-master; + }; + }; + }; + }; + }; + }; + i2c@31c0000 { + rt5640: audio-codec@1c { + compatible = "realtek,rt5640"; + reg = <0x1c>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA234_MAIN_GPIO(F, 3) GPIO_ACTIVE_HIGH>; + clocks = <&bpmp TEGRA234_CLK_AUD_MCLK>; + clock-names = "mclk"; + + realtek,dmic1-data-pin = <RT5640_DMIC1_DATA_PIN_NONE>; + realtek,dmic2-data-pin = <RT5640_DMIC2_DATA_PIN_NONE>; + realtek,jack-detect-source = <RT5640_JD_SRC_HDA_HEADER>; + + sound-name-prefix = "CVB-RT"; + + port { + rt5640_ep: endpoint { + remote-endpoint = <&i2s4_dap>; + mclk-fs = <256>; + }; + }; + }; + /* carrier board ID EEPROM */ eeprom@55 { compatible = "atmel,24c02"; @@ -134,4 +184,32 @@ "usb3-0", "usb3-1", "usb3-2"; }; }; + + vdd_3v3_dp: regulator-vdd-3v3-dp { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_DP"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_sys>; + gpio = <&gpio TEGRA234_MAIN_GPIO(H, 6) 0>; + enable-active-high; + regulator-always-on; + }; + + vdd_3v3_sys: regulator-vdd-3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_3v3_wifi: regulator-vdd-3v3-wifi { + compatible = "regulator-fixed"; + regulator-name = "VDD_3V3_WIFI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio TEGRA234_MAIN_GPIO(G, 3) GPIO_ACTIVE_HIGH>; + regulator-boot-on; + enable-active-high; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi index a8aa6e7d8fbc..5f592f1d81e2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi @@ -106,12 +106,18 @@ trips { tj_trip_active0: active-0 { - temperature = <74000>; + temperature = <35000>; hysteresis = <4000>; type = "active"; }; tj_trip_active1: active-1 { + temperature = <74000>; + hysteresis = <4000>; + type = "active"; + }; + + tj_trip_active2: active-2 { temperature = <95000>; hysteresis = <4000>; type = "active"; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts index 65e4b51b79c1..e9460aedd47c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0000.dts @@ -13,6 +13,8 @@ aliases { serial0 = &tcu; + serial1 = &uarta; + serial2 = &uarte; }; chosen { @@ -20,8 +22,19 @@ }; bus@0 { + serial@3100000 { + compatible = "nvidia,tegra194-hsuart"; + reset-names = "serial"; + status = "okay"; + }; + + serial@3140000 { + compatible = "nvidia,tegra194-hsuart"; + reset-names = "serial"; + status = "okay"; + }; + serial@31d0000 { - current-speed = <115200>; status = "okay"; }; @@ -39,50 +52,6 @@ padctl@3520000 { status = "okay"; }; - - /* C1 - M.2 Key-E */ - pcie@14100000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - - phys = <&p2u_hsio_3>; - phy-names = "p2u-0"; - }; - - /* C4 - M.2 Key-M */ - pcie@14160000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - - phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>, - <&p2u_hsio_7>; - phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; - }; - - /* C8 - Ethernet */ - pcie@140a0000 { - status = "okay"; - - num-lanes = <2>; - - phys = <&p2u_gbe_2>, <&p2u_gbe_3>; - phy-names = "p2u-0", "p2u-1"; - - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - vpcie3v3-supply = <&vdd_3v3_pcie>; - }; - - /* C7 - M.2 Key-M */ - pcie@141e0000 { - status = "okay"; - - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - - phys = <&p2u_gbe_0>, <&p2u_gbe_1>; - phy-names = "p2u-0", "p2u-1"; - }; }; gpio-keys { @@ -113,7 +82,7 @@ }; pwm-fan { - cooling-levels = <0 187 255>; + cooling-levels = <0 88 187 255>; }; vdd_3v3_pcie: regulator-vdd-3v3-pcie { @@ -141,6 +110,11 @@ cooling-device = <&fan 1 2>; trip = <&tj_trip_active1>; }; + + map-active-2 { + cooling-device = <&fan 2 3>; + trip = <&tj_trip_active2>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts index 9b86aa6f7dbe..9e9bb9ca8be4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767-0005.dts @@ -12,7 +12,7 @@ model = "NVIDIA Jetson Orin Nano Developer Kit"; pwm-fan { - cooling-levels = <0 187 255>; + cooling-levels = <0 88 187 255>; }; thermal-zones { @@ -27,6 +27,11 @@ cooling-device = <&fan 1 2>; trip = <&tj_trip_active1>; }; + + map-active-2 { + cooling-device = <&fan 2 3>; + trip = <&tj_trip_active2>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi index c7291ba27cfa..39110c1232e0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000.dtsi @@ -29,7 +29,6 @@ }; serial@31d0000 { - current-speed = <115200>; status = "okay"; }; @@ -134,6 +133,19 @@ "usb3-1"; }; + /* C8 - Ethernet */ + pcie@140a0000 { + status = "okay"; + + num-lanes = <2>; + + phys = <&p2u_gbe_2>, <&p2u_gbe_3>; + phy-names = "p2u-0", "p2u-1"; + + vddio-pex-ctl-supply = <&vdd_1v8_ao>; + vpcie3v3-supply = <&vdd_3v3_pcie>; + }; + /* C1 - M.2 Key-E */ pcie@14100000 { status = "okay"; @@ -155,19 +167,6 @@ phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; }; - /* C8 - Ethernet */ - pcie@140a0000 { - status = "okay"; - - num-lanes = <2>; - - phys = <&p2u_gbe_2>, <&p2u_gbe_3>; - phy-names = "p2u-0", "p2u-1"; - - vddio-pex-ctl-supply = <&vdd_1v8_ao>; - vpcie3v3-supply = <&vdd_3v3_pcie>; - }; - /* C7 - M.2 Key-M */ pcie@141e0000 { status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts b/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts index 5804acfc428a..9f3e9f30c3f7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts @@ -19,6 +19,8 @@ bus@0 { serial@3100000 { + /delete-property/ dmas; + /delete-property/ dma-names; status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index f4974e81dd4b..95524e5bce82 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -180,7 +180,8 @@ clocks = <&bpmp TEGRA234_CLK_AHUB>; clock-names = "ahub"; assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>; - assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + assigned-clock-rates = <81600000>; status = "disabled"; #address-cells = <2>; @@ -687,6 +688,15 @@ status = "disabled"; }; + uarte: serial@3140000 { + compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; + reg = <0x0 0x03140000 0x0 0x10000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bpmp TEGRA234_CLK_UARTE>; + resets = <&bpmp TEGRA234_RESET_UARTE>; + status = "disabled"; + }; + gen1_i2c: i2c@3160000 { compatible = "nvidia,tegra194-i2c"; reg = <0x0 0x3160000 0x0 0x100>; @@ -808,6 +818,44 @@ dma-names = "rx", "tx"; }; + spi@3210000 { + compatible = "nvidia,tegra210-spi"; + reg = <0x0 0x03210000 0x0 0x1000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA234_CLK_SPI1>; + assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + clock-names = "spi"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + resets = <&bpmp TEGRA234_RESET_SPI1>; + reset-names = "spi"; + dmas = <&gpcdma 15>, <&gpcdma 15>; + dma-names = "rx", "tx"; + dma-coherent; + status = "disabled"; + }; + + spi@3230000 { + compatible = "nvidia,tegra210-spi"; + reg = <0x0 0x03230000 0x0 0x1000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA234_CLK_SPI3>; + clock-names = "spi"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_SPI3>; + reset-names = "spi"; + dmas = <&gpcdma 17>, <&gpcdma 17>; + dma-names = "rx", "tx"; + dma-coherent; + status = "disabled"; + }; + spi@3270000 { compatible = "nvidia,tegra234-qspi"; reg = <0x0 0x3270000 0x0 0x1000>; @@ -1733,6 +1781,25 @@ dma-names = "rx", "tx"; }; + spi@c260000 { + compatible = "nvidia,tegra210-spi"; + reg = <0x0 0x0c260000 0x0 0x1000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA234_CLK_SPI2>; + clock-names = "spi"; + iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>; + assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>; + resets = <&bpmp TEGRA234_RESET_SPI2>; + reset-names = "spi"; + dmas = <&gpcdma 19>, <&gpcdma 19>; + dma-names = "rx", "tx"; + dma-coherent; + status = "disabled"; + }; + rtc@c2a0000 { compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; reg = <0x0 0x0c2a0000 0x0 0x10000>; @@ -3589,72 +3656,142 @@ opp-peak-kBps = <816000>; }; - cl0_ch1_opp2: opp-268800000 { + cl0_ch1_opp2: opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp3: opp-268800000 { opp-hz = /bits/ 64 <268800000>; opp-peak-kBps = <816000>; }; - cl0_ch1_opp3: opp-422400000 { + cl0_ch1_opp4: opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp5: opp-422400000 { opp-hz = /bits/ 64 <422400000>; opp-peak-kBps = <816000>; }; - cl0_ch1_opp4: opp-576000000 { + cl0_ch1_opp6: opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp7: opp-576000000 { opp-hz = /bits/ 64 <576000000>; opp-peak-kBps = <816000>; }; - cl0_ch1_opp5: opp-729600000 { + cl0_ch1_opp8: opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp9: opp-729600000 { opp-hz = /bits/ 64 <729600000>; opp-peak-kBps = <816000>; }; - cl0_ch1_opp6: opp-883200000 { + cl0_ch1_opp10: opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp11: opp-883200000 { opp-hz = /bits/ 64 <883200000>; opp-peak-kBps = <816000>; }; - cl0_ch1_opp7: opp-1036800000 { + cl0_ch1_opp12: opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-peak-kBps = <816000>; + }; + + cl0_ch1_opp13: opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; opp-peak-kBps = <816000>; }; - cl0_ch1_opp8: opp-1190400000 { + cl0_ch1_opp14: opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <1632000>; + }; + + cl0_ch1_opp15: opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; - opp-peak-kBps = <816000>; + opp-peak-kBps = <1632000>; + }; + + cl0_ch1_opp16: opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <1632000>; }; - cl0_ch1_opp9: opp-1344000000 { + cl0_ch1_opp17: opp-1344000000 { opp-hz = /bits/ 64 <1344000000>; opp-peak-kBps = <1632000>; }; - cl0_ch1_opp10: opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; + cl0_ch1_opp18: opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; opp-peak-kBps = <1632000>; }; - cl0_ch1_opp11: opp-1651200000 { + cl0_ch1_opp19: opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <3200000>; + }; + + cl0_ch1_opp20: opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + opp-peak-kBps = <3200000>; + }; + + cl0_ch1_opp21: opp-1651200000 { opp-hz = /bits/ 64 <1651200000>; - opp-peak-kBps = <2660000>; + opp-peak-kBps = <3200000>; }; - cl0_ch1_opp12: opp-1804800000 { + cl0_ch1_opp22: opp-1728000000 { + opp-hz = /bits/ 64 <1728000000>; + opp-peak-kBps = <3200000>; + }; + + cl0_ch1_opp23: opp-1804800000 { opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <2660000>; + opp-peak-kBps = <3200000>; }; - cl0_ch1_opp13: opp-1958400000 { + cl0_ch1_opp24: opp-1881600000 { + opp-hz = /bits/ 64 <1881600000>; + opp-peak-kBps = <3200000>; + }; + + cl0_ch1_opp25: opp-1958400000 { opp-hz = /bits/ 64 <1958400000>; opp-peak-kBps = <3200000>; }; - cl0_ch1_opp14: opp-2112000000 { + cl0_ch1_opp26: opp-2035200000 { + opp-hz = /bits/ 64 <2035200000>; + opp-peak-kBps = <3200000>; + }; + + cl0_ch1_opp27: opp-2112000000 { opp-hz = /bits/ 64 <2112000000>; opp-peak-kBps = <6400000>; }; - cl0_ch1_opp15: opp-2201600000 { + cl0_ch1_opp28: opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <6400000>; + }; + + cl0_ch1_opp29: opp-2201600000 { opp-hz = /bits/ 64 <2201600000>; opp-peak-kBps = <6400000>; }; @@ -3669,72 +3806,142 @@ opp-peak-kBps = <816000>; }; - cl1_ch1_opp2: opp-268800000 { + cl1_ch1_opp2: opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp3: opp-268800000 { opp-hz = /bits/ 64 <268800000>; opp-peak-kBps = <816000>; }; - cl1_ch1_opp3: opp-422400000 { + cl1_ch1_opp4: opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp5: opp-422400000 { opp-hz = /bits/ 64 <422400000>; opp-peak-kBps = <816000>; }; - cl1_ch1_opp4: opp-576000000 { + cl1_ch1_opp6: opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp7: opp-576000000 { opp-hz = /bits/ 64 <576000000>; opp-peak-kBps = <816000>; }; - cl1_ch1_opp5: opp-729600000 { + cl1_ch1_opp8: opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp9: opp-729600000 { opp-hz = /bits/ 64 <729600000>; opp-peak-kBps = <816000>; }; - cl1_ch1_opp6: opp-883200000 { + cl1_ch1_opp10: opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp11: opp-883200000 { opp-hz = /bits/ 64 <883200000>; opp-peak-kBps = <816000>; }; - cl1_ch1_opp7: opp-1036800000 { + cl1_ch1_opp12: opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-peak-kBps = <816000>; + }; + + cl1_ch1_opp13: opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; opp-peak-kBps = <816000>; }; - cl1_ch1_opp8: opp-1190400000 { + cl1_ch1_opp14: opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <1632000>; + }; + + cl1_ch1_opp15: opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; - opp-peak-kBps = <816000>; + opp-peak-kBps = <1632000>; + }; + + cl1_ch1_opp16: opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <1632000>; }; - cl1_ch1_opp9: opp-1344000000 { + cl1_ch1_opp17: opp-1344000000 { opp-hz = /bits/ 64 <1344000000>; opp-peak-kBps = <1632000>; }; - cl1_ch1_opp10: opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; + cl1_ch1_opp18: opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; opp-peak-kBps = <1632000>; }; - cl1_ch1_opp11: opp-1651200000 { + cl1_ch1_opp19: opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <3200000>; + }; + + cl1_ch1_opp20: opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + opp-peak-kBps = <3200000>; + }; + + cl1_ch1_opp21: opp-1651200000 { opp-hz = /bits/ 64 <1651200000>; - opp-peak-kBps = <2660000>; + opp-peak-kBps = <3200000>; }; - cl1_ch1_opp12: opp-1804800000 { + cl1_ch1_opp22: opp-1728000000 { + opp-hz = /bits/ 64 <1728000000>; + opp-peak-kBps = <3200000>; + }; + + cl1_ch1_opp23: opp-1804800000 { opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <2660000>; + opp-peak-kBps = <3200000>; + }; + + cl1_ch1_opp24: opp-1881600000 { + opp-hz = /bits/ 64 <1881600000>; + opp-peak-kBps = <3200000>; }; - cl1_ch1_opp13: opp-1958400000 { + cl1_ch1_opp25: opp-1958400000 { opp-hz = /bits/ 64 <1958400000>; opp-peak-kBps = <3200000>; }; - cl1_ch1_opp14: opp-2112000000 { + cl1_ch1_opp26: opp-2035200000 { + opp-hz = /bits/ 64 <2035200000>; + opp-peak-kBps = <3200000>; + }; + + cl1_ch1_opp27: opp-2112000000 { opp-hz = /bits/ 64 <2112000000>; opp-peak-kBps = <6400000>; }; - cl1_ch1_opp15: opp-2201600000 { + cl1_ch1_opp28: opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <6400000>; + }; + + cl1_ch1_opp29: opp-2201600000 { opp-hz = /bits/ 64 <2201600000>; opp-peak-kBps = <6400000>; }; @@ -3749,72 +3956,142 @@ opp-peak-kBps = <816000>; }; - cl2_ch1_opp2: opp-268800000 { + cl2_ch1_opp2: opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp3: opp-268800000 { opp-hz = /bits/ 64 <268800000>; opp-peak-kBps = <816000>; }; - cl2_ch1_opp3: opp-422400000 { + cl2_ch1_opp4: opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp5: opp-422400000 { opp-hz = /bits/ 64 <422400000>; opp-peak-kBps = <816000>; }; - cl2_ch1_opp4: opp-576000000 { + cl2_ch1_opp6: opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp7: opp-576000000 { opp-hz = /bits/ 64 <576000000>; opp-peak-kBps = <816000>; }; - cl2_ch1_opp5: opp-729600000 { + cl2_ch1_opp8: opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp9: opp-729600000 { opp-hz = /bits/ 64 <729600000>; opp-peak-kBps = <816000>; }; - cl2_ch1_opp6: opp-883200000 { + cl2_ch1_opp10: opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp11: opp-883200000 { opp-hz = /bits/ 64 <883200000>; opp-peak-kBps = <816000>; }; - cl2_ch1_opp7: opp-1036800000 { + cl2_ch1_opp12: opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + opp-peak-kBps = <816000>; + }; + + cl2_ch1_opp13: opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; opp-peak-kBps = <816000>; }; - cl2_ch1_opp8: opp-1190400000 { + cl2_ch1_opp14: opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <1632000>; + }; + + cl2_ch1_opp15: opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; - opp-peak-kBps = <816000>; + opp-peak-kBps = <1632000>; }; - cl2_ch1_opp9: opp-1344000000 { + cl2_ch1_opp16: opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + opp-peak-kBps = <1632000>; + }; + + cl2_ch1_opp17: opp-1344000000 { opp-hz = /bits/ 64 <1344000000>; opp-peak-kBps = <1632000>; }; - cl2_ch1_opp10: opp-1497600000 { - opp-hz = /bits/ 64 <1497600000>; + cl2_ch1_opp18: opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; opp-peak-kBps = <1632000>; }; - cl2_ch1_opp11: opp-1651200000 { + cl2_ch1_opp19: opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + opp-peak-kBps = <3200000>; + }; + + cl2_ch1_opp20: opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + opp-peak-kBps = <3200000>; + }; + + cl2_ch1_opp21: opp-1651200000 { opp-hz = /bits/ 64 <1651200000>; - opp-peak-kBps = <2660000>; + opp-peak-kBps = <3200000>; + }; + + cl2_ch1_opp22: opp-1728000000 { + opp-hz = /bits/ 64 <1728000000>; + opp-peak-kBps = <3200000>; }; - cl2_ch1_opp12: opp-1804800000 { + cl2_ch1_opp23: opp-1804800000 { opp-hz = /bits/ 64 <1804800000>; - opp-peak-kBps = <2660000>; + opp-peak-kBps = <3200000>; }; - cl2_ch1_opp13: opp-1958400000 { + cl2_ch1_opp24: opp-1881600000 { + opp-hz = /bits/ 64 <1881600000>; + opp-peak-kBps = <3200000>; + }; + + cl2_ch1_opp25: opp-1958400000 { opp-hz = /bits/ 64 <1958400000>; opp-peak-kBps = <3200000>; }; - cl2_ch1_opp14: opp-2112000000 { + cl2_ch1_opp26: opp-2035200000 { + opp-hz = /bits/ 64 <2035200000>; + opp-peak-kBps = <3200000>; + }; + + cl2_ch1_opp27: opp-2112000000 { opp-hz = /bits/ 64 <2112000000>; opp-peak-kBps = <6400000>; }; - cl2_ch1_opp15: opp-2201600000 { + cl2_ch1_opp28: opp-2188800000 { + opp-hz = /bits/ 64 <2188800000>; + opp-peak-kBps = <6400000>; + }; + + cl2_ch1_opp29: opp-2201600000 { opp-hz = /bits/ 64 <2201600000>; opp-peak-kBps = <6400000>; }; diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 337abc4ceb17..2cca20563a1d 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -1,9 +1,11 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb +dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-d3-camera-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8039-t2.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb +dtb-$(CONFIG_ARCH_QCOM) += ipq5018-rdp432-c2.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb @@ -39,6 +41,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8939-samsung-a7.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8939-sony-xperia-kanuti-tulip.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb @@ -186,6 +189,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115p-lenovo-j606f.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dts new file mode 100644 index 000000000000..c08b4be5cc7e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-d3-camera-mezzanine.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Ltd. + */ + +/dts-v1/; + +#include "apq8016-sbc.dts" + +/ { + camera_vdddo_1v8: camera-vdddo-1v8 { + compatible = "regulator-fixed"; + regulator-name = "camera_vdddo"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + camera_vdda_2v8: camera-vdda-2v8 { + compatible = "regulator-fixed"; + regulator-name = "camera_vdda"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + camera_vddd_1v5: camera-vddd-1v5 { + compatible = "regulator-fixed"; + regulator-name = "camera_vddd"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; +}; + +&camss { + status = "okay"; + + ports { + port@0 { + reg = <0>; + csiphy0_ep: endpoint { + data-lanes = <0 2>; + remote-endpoint = <&ov5640_ep>; + }; + }; + }; +}; + +&cci { + status = "okay"; +}; + +&cci_i2c0 { + camera_rear@3b { + compatible = "ovti,ov5640"; + reg = <0x3b>; + + powerdown-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_rear_default>; + + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "xclk"; + assigned-clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + assigned-clock-rates = <23880000>; + + DOVDD-supply = <&camera_vdddo_1v8>; + AVDD-supply = <&camera_vdda_2v8>; + DVDD-supply = <&camera_vddd_1v5>; + + port { + ov5640_ep: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&csiphy0_ep>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts index f3d65a606194..4f5541e9be0e 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dts +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dts @@ -34,30 +34,6 @@ stdout-path = "serial0"; }; - camera_vdddo_1v8: camera-vdddo-1v8 { - compatible = "regulator-fixed"; - regulator-name = "camera_vdddo"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - camera_vdda_2v8: camera-vdda-2v8 { - compatible = "regulator-fixed"; - regulator-name = "camera_vdda"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - }; - - camera_vddd_1v5: camera-vddd-1v5 { - compatible = "regulator-fixed"; - regulator-name = "camera_vddd"; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-always-on; - }; - reserved-memory { ramoops@bff00000 { compatible = "ramoops"; @@ -77,7 +53,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 121 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 121 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; @@ -172,15 +148,13 @@ }; &blsp_i2c2 { - /* On Low speed expansion */ + /* On Low speed expansion: LS-I2C0 */ status = "okay"; - label = "LS-I2C0"; }; &blsp_i2c4 { - /* On High speed expansion */ + /* On High speed expansion: HS-I2C2 */ status = "okay"; - label = "HS-I2C2"; adv_bridge: bridge@39 { status = "okay"; @@ -228,21 +202,18 @@ }; &blsp_i2c6 { - /* On Low speed expansion */ + /* On Low speed expansion: LS-I2C1 */ status = "okay"; - label = "LS-I2C1"; }; &blsp_spi3 { - /* On High speed expansion */ + /* On High speed expansion: HS-SPI1 */ status = "okay"; - label = "HS-SPI1"; }; &blsp_spi5 { - /* On Low speed expansion */ + /* On Low speed expansion: LS-SPI0 */ status = "okay"; - label = "LS-SPI0"; }; &blsp_uart1 { @@ -257,50 +228,6 @@ &camss { status = "okay"; - ports { - port@0 { - reg = <0>; - csiphy0_ep: endpoint { - data-lanes = <0 2>; - remote-endpoint = <&ov5640_ep>; - status = "okay"; - }; - }; - }; -}; - -&cci { - status = "okay"; -}; - -&cci_i2c0 { - camera_rear@3b { - compatible = "ovti,ov5640"; - reg = <0x3b>; - - enable-gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>; - reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&camera_rear_default>; - - clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; - clock-names = "xclk"; - clock-frequency = <23880000>; - - vdddo-supply = <&camera_vdddo_1v8>; - vdda-supply = <&camera_vdda_2v8>; - vddd-supply = <&camera_vddd_1v5>; - - /* No camera mezzanine by default */ - status = "disabled"; - - port { - ov5640_ep: endpoint { - data-lanes = <0 2>; - remote-endpoint = <&csiphy0_ep>; - }; - }; - }; }; &lpass { diff --git a/arch/arm64/boot/dts/qcom/apq8039-t2.dts b/arch/arm64/boot/dts/qcom/apq8039-t2.dts index 40644c242fb7..027d1da7e81d 100644 --- a/arch/arm64/boot/dts/qcom/apq8039-t2.dts +++ b/arch/arm64/boot/dts/qcom/apq8039-t2.dts @@ -366,7 +366,6 @@ function = "gpio"; pins = "gpio107"; bias-pull-up; - input-enable; }; }; @@ -375,7 +374,6 @@ pinctrl-0 = <&pinctrl_otg_default>; pinctrl-1 = <&pinctrl_otg_host>; pinctrl-2 = <&pinctrl_otg_device>; - pin-switch-delay-us = <100000>; usb-role-switch; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 537547b97459..385b178314db 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -99,14 +99,14 @@ usb2_id: usb2-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>; + id-gpios = <&pmi8994_gpios 6 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb2_vbus_det_gpio>; }; usb3_id: usb3-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>; + id-gpios = <&pm8994_gpios 22 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb3_vbus_det_gpio>; }; @@ -138,8 +138,7 @@ }; &blsp1_i2c3 { - /* On Low speed expansion */ - label = "LS-I2C0"; + /* On Low speed expansion: LS-I2C0 */ status = "okay"; }; @@ -168,14 +167,12 @@ }; &blsp2_i2c1 { - /* On High speed expansion */ - label = "HS-I2C2"; + /* On High speed expansion: HS-I2C2 */ status = "okay"; }; &blsp2_i2c1 { - /* On Low speed expansion */ - label = "LS-I2C1"; + /* On Low speed expansion: LS-I2C1 */ status = "okay"; }; @@ -236,8 +233,8 @@ status = "okay"; pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mdss_hdmi_hpd_active &mdss_hdmi_ddc_active>; - pinctrl-1 = <&mdss_hdmi_hpd_suspend &mdss_hdmi_ddc_suspend>; + pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>; + pinctrl-1 = <&hdmi_hpd_suspend &hdmi_ddc_suspend>; core-vdda-supply = <&vreg_l12a_1p8>; core-vcc-supply = <&vreg_s4a_1p8>; @@ -433,28 +430,28 @@ drive-strength = <2>; }; - mdss_hdmi_hpd_active: mdss_hdmi-hpd-active-state { + hdmi_hpd_active: hdmi-hpd-active-state { pins = "gpio34"; function = "hdmi_hot"; bias-pull-down; drive-strength = <16>; }; - mdss_hdmi_hpd_suspend: mdss_hdmi-hpd-suspend-state { + hdmi_hpd_suspend: hdmi-hpd-suspend-state { pins = "gpio34"; function = "hdmi_hot"; bias-pull-down; drive-strength = <2>; }; - mdss_hdmi_ddc_active: mdss_hdmi-ddc-active-state { + hdmi_ddc_active: hdmi-ddc-active-state { pins = "gpio32", "gpio33"; function = "hdmi_ddc"; drive-strength = <2>; bias-pull-up; }; - mdss_hdmi_ddc_suspend: mdss_hdmi-ddc-suspend-state { + hdmi_ddc_suspend: hdmi-ddc-suspend-state { pins = "gpio32", "gpio33"; function = "hdmi_ddc"; drive-strength = <2>; @@ -1043,7 +1040,7 @@ }; }; - mdss_hdmi-dai-link { + hdmi-dai-link { link-name = "HDMI"; cpu { sound-dai = <&q6afedai HDMI_RX>; diff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts new file mode 100644 index 000000000000..e636a1cb9b77 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * IPQ5018 MP03.1-C2 board device tree source + * + * Copyright (c) 2023 The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "ipq5018.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2"; + compatible = "qcom,ipq5018-rdp432-c2", "qcom,ipq5018"; + + aliases { + serial0 = &blsp1_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&blsp1_uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc_default_state>; + pinctrl-names = "default"; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + max-frequency = <192000000>; + bus-width = <4>; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + sdc_default_state: sdc-default-state { + clk-pins { + pins = "gpio9"; + function = "sdc1_clk"; + drive-strength = <8>; + bias-disable; + }; + + cmd-pins { + pins = "gpio8"; + function = "sdc1_cmd"; + drive-strength = <8>; + bias-pull-up; + }; + + data-pins { + pins = "gpio4", "gpio5", "gpio6", "gpio7"; + function = "sdc1_data"; + drive-strength = <8>; + bias-disable; + }; + }; +}; + +&xo_board_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi new file mode 100644 index 000000000000..9f13d2dcdfd5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -0,0 +1,250 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * IPQ5018 SoC device tree source + * + * Copyright (c) 2023 The Linux Foundation. All rights reserved. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-ipq5018.h> +#include <dt-bindings/reset/qcom,gcc-ipq5018.h> + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-unified; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-ipq5018", "qcom,scm"; + }; + }; + + memory@40000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x40000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + tz_region: tz@4ac00000 { + reg = <0x0 0x4ac00000 0x0 0x200000>; + no-map; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq5018-tlmm"; + reg = <0x01000000 0x300000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 47>; + interrupt-controller; + #interrupt-cells = <2>; + + uart1_pins: uart1-state { + pins = "gpio31", "gpio32", "gpio33", "gpio34"; + function = "blsp1_uart1"; + drive-strength = <8>; + bias-pull-down; + }; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-ipq5018"; + reg = <0x01800000 0x80000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + sdhc_1: mmc@7804000 { + compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x7804000 0x1000>; + reg-names = "hc"; + + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board_clk>; + clock-names = "iface", "core", "xo"; + non-removable; + status = "disabled"; + }; + + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + reg = <0x0b000000 0x1000>, /* GICD */ + <0x0b002000 0x2000>, /* GICC */ + <0x0b001000 0x1000>, /* GICH */ + <0x0b004000 0x2000>; /* GICV */ + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0b00a000 0x1ffa>; + + v2m0: v2m@0 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00000000 0xff8>; + msi-controller; + }; + + v2m1: v2m@1000 { + compatible = "arm,gic-v2m-frame"; + reg = <0x00001000 0xff8>; + msi-controller; + }; + }; + + timer@b120000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0b120000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + frame@b120000 { + reg = <0x0b121000 0x1000>, + <0x0b122000 0x1000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <0>; + }; + + frame@b123000 { + reg = <0xb123000 0x1000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <1>; + status = "disabled"; + }; + + frame@b124000 { + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0b124000 0x1000>; + status = "disabled"; + }; + + frame@b125000 { + reg = <0x0b125000 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <3>; + status = "disabled"; + }; + + frame@b126000 { + reg = <0x0b126000 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <4>; + status = "disabled"; + }; + + frame@b127000 { + reg = <0x0b127000 0x1000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <5>; + status = "disabled"; + }; + + frame@b128000 { + reg = <0x0b128000 0x1000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <6>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi new file mode 100644 index 000000000000..4870cdb764d0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp-common.dtsi @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * IPQ5332 RDP board common device tree source + * + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include "ipq5332.dtsi" + +/ { + aliases { + serial0 = &blsp1_uart0; + }; + + chosen { + stdout-path = "serial0"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + button-wps { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&gpio_leds_default>; + pinctrl-names = "default"; + + led-0 { + gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + }; +}; + +&blsp1_uart0 { + pinctrl-0 = <&serial_0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&xo_board { + clock-frequency = <24000000>; +}; + +/* PINCTRL */ +&tlmm { + gpio_keys_default: gpio-keys-default-state { + pins = "gpio35"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + gpio_leds_default: gpio-leds-default-state { + pins = "gpio36"; + function = "gpio"; + drive-strength = <8>; + bias-pull-down; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts index 3af1d5556950..e89e2e948603 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -7,25 +7,11 @@ /dts-v1/; -#include "ipq5332.dtsi" +#include "ipq5332-rdp-common.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; - - aliases { - serial0 = &blsp1_uart0; - }; - - chosen { - stdout-path = "serial0"; - }; -}; - -&blsp1_uart0 { - pinctrl-0 = <&serial_0_pins>; - pinctrl-names = "default"; - status = "okay"; }; &blsp1_i2c1 { @@ -46,16 +32,6 @@ status = "okay"; }; -&sleep_clk { - clock-frequency = <32000>; -}; - -&xo_board { - clock-frequency = <24000000>; -}; - -/* PINCTRL */ - &tlmm { i2c_1_pins: i2c-1-state { pins = "gpio29", "gpio30"; diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts index bcf3b31c20e3..efd480a7afdf 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp442.dts @@ -7,25 +7,11 @@ /dts-v1/; -#include "ipq5332.dtsi" +#include "ipq5332-rdp-common.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ5332 MI01.3"; compatible = "qcom,ipq5332-ap-mi01.3", "qcom,ipq5332"; - - aliases { - serial0 = &blsp1_uart0; - }; - - chosen { - stdout-path = "serial0"; - }; -}; - -&blsp1_uart0 { - pinctrl-0 = <&serial_0_pins>; - pinctrl-names = "default"; - status = "okay"; }; &blsp1_i2c1 { @@ -60,16 +46,6 @@ status = "okay"; }; -&sleep_clk { - clock-frequency = <32000>; -}; - -&xo_board { - clock-frequency = <24000000>; -}; - -/* PINCTRL */ - &tlmm { i2c_1_pins: i2c-1-state { pins = "gpio29", "gpio30"; diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts index 3b6a5cb8bf07..f96b0c8c908b 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp468.dts @@ -7,25 +7,11 @@ /dts-v1/; -#include "ipq5332.dtsi" +#include "ipq5332-rdp-common.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ5332 MI01.6"; compatible = "qcom,ipq5332-ap-mi01.6", "qcom,ipq5332"; - - aliases { - serial0 = &blsp1_uart0; - }; - - chosen { - stdout-path = "serial0"; - }; -}; - -&blsp1_uart0 { - pinctrl-0 = <&serial_0_pins>; - pinctrl-names = "default"; - status = "okay"; }; &blsp1_spi0 { @@ -53,14 +39,6 @@ status = "okay"; }; -&sleep_clk { - clock-frequency = <32000>; -}; - -&xo_board { - clock-frequency = <24000000>; -}; - /* PINCTRL */ &tlmm { diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts index 53c68d8c5e5d..eb1fa33d6fe4 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp474.dts @@ -7,41 +7,11 @@ /dts-v1/; -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include "ipq5332.dtsi" +#include "ipq5332-rdp-common.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ5332 MI01.9"; compatible = "qcom,ipq5332-ap-mi01.9", "qcom,ipq5332"; - - aliases { - serial0 = &blsp1_uart0; - }; - - chosen { - stdout-path = "serial0"; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&gpio_keys_default_state>; - pinctrl-names = "default"; - - button-wps { - label = "wps"; - linux,code = <KEY_WPS_BUTTON>; - gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; - debounce-interval = <60>; - }; - }; -}; - -&blsp1_uart0 { - pinctrl-0 = <&serial_0_pins>; - pinctrl-names = "default"; - status = "okay"; }; &blsp1_i2c1 { @@ -62,24 +32,9 @@ status = "okay"; }; -&sleep_clk { - clock-frequency = <32000>; -}; - -&xo_board { - clock-frequency = <24000000>; -}; - /* PINCTRL */ &tlmm { - gpio_keys_default_state: gpio-keys-default-state { - pins = "gpio35"; - function = "gpio"; - drive-strength = <8>; - bias-pull-up; - }; - i2c_1_pins: i2c-1-state { pins = "gpio29", "gpio30"; function = "blsp1_i2c0"; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 7355f266742a..47b8b1d6730a 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -146,6 +146,32 @@ method = "smc"; }; + rpm: remoteproc { + compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-ipq6018"; + qcom,glink-channels = "rpm_requests"; + + regulators { + compatible = "qcom,rpm-mp5496-regulators"; + + ipq6018_s2: s2 { + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1062500>; + regulator-always-on; + }; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -182,28 +208,6 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-ipq6018"; - qcom,glink-channels = "rpm_requests"; - - regulators { - compatible = "qcom,rpm-mp5496-regulators"; - - ipq6018_s2: s2 { - regulator-min-microvolt = <725000>; - regulator-max-microvolt = <1062500>; - regulator-always-on; - }; - }; - }; - }; - smem { compatible = "qcom,smem"; memory-region = <&smem_region>; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 68839acbd613..00ed71936b47 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -794,10 +794,10 @@ pcie1: pci@10000000 { compatible = "qcom,pcie-ipq8074"; - reg = <0x10000000 0xf1d>, - <0x10000f20 0xa8>, - <0x00088000 0x2000>, - <0x10100000 0x1000>; + reg = <0x10000000 0xf1d>, + <0x10000f20 0xa8>, + <0x00088000 0x2000>, + <0x10100000 0x1000>; reg-names = "dbi", "elbi", "parf", "config"; device_type = "pci"; linux,pci-domain = <1>; diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 2b3ed8d351f7..877026ccc6e2 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -21,6 +21,24 @@ chosen { stdout-path = "serial0:115200n8"; }; + + regulator_fixed_3p3: s3300 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "fixed_3p3"; + }; + + regulator_fixed_0p925: s0925 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-boot-on; + regulator-always-on; + regulator-name = "fixed_0p925"; + }; }; &blsp1_uart2 { @@ -45,6 +63,13 @@ regulator-min-microvolt = <725000>; regulator-max-microvolt = <1075000>; }; + + mp5496_l2: l2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; }; }; @@ -98,6 +123,29 @@ }; }; +&usb_0_dwc3 { + dr_mode = "host"; +}; + +&usb_0_qmpphy { + vdda-pll-supply = <&mp5496_l2>; + vdda-phy-supply = <®ulator_fixed_0p925>; + + status = "okay"; +}; + +&usb_0_qusbphy { + vdd-supply = <®ulator_fixed_0p925>; + vdda-pll-supply = <&mp5496_l2>; + vdda-phy-dpdm-supply = <®ulator_fixed_3p3>; + + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + &xo_board_clk { clock-frequency = <24000000>; }; diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index f120c7c52351..51aba071c1eb 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/clock/qcom,ipq9574-gcc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset/qcom,ipq9574-gcc.h> +#include <dt-bindings/thermal/thermal.h> / { interrupt-parent = <&intc>; @@ -42,6 +43,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; cpu-supply = <&ipq9574_s1>; + #cooling-cells = <2>; }; CPU1: cpu@1 { @@ -54,6 +56,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; cpu-supply = <&ipq9574_s1>; + #cooling-cells = <2>; }; CPU2: cpu@2 { @@ -66,6 +69,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; cpu-supply = <&ipq9574_s1>; + #cooling-cells = <2>; }; CPU3: cpu@3 { @@ -78,6 +82,7 @@ clock-names = "cpu"; operating-points-v2 = <&cpu_opp_table>; cpu-supply = <&ipq9574_s1>; + #cooling-cells = <2>; }; L2_0: l2-cache { @@ -151,6 +156,22 @@ method = "smc"; }; + rpm: remoteproc { + compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-ipq9574"; + qcom,glink-channels = "rpm_requests"; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -179,18 +200,6 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-ipq9574"; - qcom,glink-channels = "rpm_requests"; - }; - }; - soc: soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -401,6 +410,8 @@ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + assigned-clock-rates = <50000000>; dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; status = "disabled"; @@ -429,6 +440,8 @@ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + assigned-clock-rates = <50000000>; dmas = <&blsp_dma 16>, <&blsp_dma 17>; dma-names = "tx", "rx"; status = "disabled"; @@ -457,6 +470,8 @@ clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + assigned-clock-rates = <50000000>; dmas = <&blsp_dma 18>, <&blsp_dma 19>; dma-names = "tx", "rx"; status = "disabled"; @@ -486,6 +501,8 @@ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; + assigned-clock-rates = <50000000>; dmas = <&blsp_dma 20>, <&blsp_dma 21>; dma-names = "tx", "rx"; status = "disabled"; @@ -505,6 +522,91 @@ status = "disabled"; }; + usb_0_qusbphy: phy@7b000 { + compatible = "qcom,ipq9574-qusb2-phy"; + reg = <0x0007b000 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo_board_clk>; + clock-names = "cfg_ahb", + "ref"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + status = "disabled"; + }; + + usb_0_qmpphy: phy@7d000 { + compatible = "qcom,ipq9574-qmp-usb3-phy"; + reg = <0x0007d000 0xa00>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_AUX_CLK>, + <&xo_board_clk>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets = <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names = "phy", + "phy_phy"; + + #clock-cells = <0>; + clock-output-names = "usb0_pipe_clk"; + + status = "disabled"; + }; + + usb3: usb@8af8800 { + compatible = "qcom,ipq9574-dwc3", "qcom,dwc3"; + reg = <0x08af8800 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_SNOC_USB_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_ANOC_USB_AXI_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <200000000>, + <24000000>; + + interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pwr_event"; + + resets = <&gcc GCC_USB_BCR>; + status = "disabled"; + + usb_0_dwc3: usb@8a00000 { + compatible = "snps,dwc3"; + reg = <0x8a00000 0xcd00>; + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "ref"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb_0_qusbphy>, <&usb_0_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + }; + }; + intc: interrupt-controller@b000000 { compatible = "qcom,msm-qgic2"; reg = <0x0b000000 0x1000>, /* GICD */ @@ -727,18 +829,28 @@ thermal-sensors = <&tsens 10>; trips { - cpu-critical { + cpu0_crit: cpu-critical { temperature = <120000>; hysteresis = <10000>; type = "critical"; }; - cpu-passive { + cpu0_alert: cpu-passive { temperature = <110000>; hysteresis = <1000>; type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&cpu0_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu1-thermal { @@ -747,18 +859,28 @@ thermal-sensors = <&tsens 11>; trips { - cpu-critical { + cpu1_crit: cpu-critical { temperature = <120000>; hysteresis = <10000>; type = "critical"; }; - cpu-passive { + cpu1_alert: cpu-passive { temperature = <110000>; hysteresis = <1000>; type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&cpu1_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu2-thermal { @@ -767,18 +889,28 @@ thermal-sensors = <&tsens 12>; trips { - cpu-critical { + cpu2_crit: cpu-critical { temperature = <120000>; hysteresis = <10000>; type = "critical"; }; - cpu-passive { + cpu2_alert: cpu-passive { temperature = <110000>; hysteresis = <1000>; type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&cpu2_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu3-thermal { @@ -787,18 +919,28 @@ thermal-sensors = <&tsens 13>; trips { - cpu-critical { + cpu3_crit: cpu-critical { temperature = <120000>; hysteresis = <10000>; type = "critical"; }; - cpu-passive { + cpu3_alert: cpu-passive { temperature = <110000>; hysteresis = <1000>; type = "passive"; }; }; + + cooling-maps { + map0 { + trip = <&cpu3_alert>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; wcss-phyb-thermal { diff --git a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts index 5ad49fe999db..84723c9b73b4 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts @@ -48,7 +48,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts index 1c43f3d6a0b4..47da738661bf 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts @@ -52,7 +52,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 69 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts index f4dbc515c47a..4aeeee24cedc 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts @@ -75,7 +75,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&usb_id_default>; pinctrl-names = "default"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 4239c8fda11b..484e488a5eca 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -80,7 +80,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 117 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 97262b8519b3..3892ad4f639a 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -165,7 +165,7 @@ pinctrl-0 = <&light_int_default>; vdd-supply = <&pm8916_l17>; - vio-supply = <&pm8916_l6>; + vddio-supply = <&pm8916_l6>; }; gyroscope@68 { diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts index 9757182fba3e..d73294af1a06 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts @@ -68,7 +68,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts index 438eb1faee1d..ac527a3a0826 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dts @@ -10,6 +10,7 @@ / { model = "Qualcomm Technologies, Inc. MSM 8916 MTP"; compatible = "qcom,msm8916-mtp", "qcom,msm8916-mtp/1", "qcom,msm8916"; + chassis-type = "handset"; aliases { serial0 = &blsp_uart2; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi index 0cdd6af7817f..6f65fd4b3ed3 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi @@ -42,10 +42,27 @@ &blsp_i2c2 { /* lis2hh12 accelerometer instead of BMC150 */ - status = "disabled"; - /delete-node/ accelerometer@10; /delete-node/ magnetometer@12; + + accelerometer@1d { + compatible = "st,lis2hh12"; + reg = <0x1d>; + + interrupt-parent = <&tlmm>; + interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; + + vdd-supply = <&pm8916_l5>; + vddio-supply = <&pm8916_l5>; + + st,drdy-int-pin = <1>; + mount-matrix = "1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + }; }; ®_motor_vdd { diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts index 777eb934eb4b..fad2535255f7 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-e5.dts @@ -22,3 +22,23 @@ compatible = "samsung,e5", "qcom,msm8916"; chassis-type = "handset"; }; + +&blsp_i2c5 { + status = "okay"; + + touchscreen@48 { + compatible = "melfas,mms345l"; + reg = <0x48>; + + interrupts-extended = <&tlmm 13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + + avdd-supply = <®_vdd_tsp_a>; + vdd-supply = <&pm8916_l6>; + + pinctrl-0 = <&ts_int_default>; + pinctrl-names = "default"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi index 7943bb619116..54d648972d35 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi @@ -101,7 +101,6 @@ interrupt-parent = <&tlmm>; interrupts = <115 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "INT1"; st,drdy-int-pin = <1>; mount-matrix = "0", "1", "0", diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi index f4fd5d72b28b..cb0e4a7faf91 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi @@ -86,6 +86,26 @@ }; }; +&blsp_i2c5 { + status = "okay"; + + touchscreen: touchscreen@50 { + compatible = "imagis,ist3038c"; + reg = <0x50>; + + interrupt-parent = <&tlmm>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + + vddio-supply = <&pm8916_l6>; + + pinctrl-0 = <&tsp_int_default>; + pinctrl-names = "default"; + }; +}; + &blsp_uart2 { status = "okay"; }; @@ -162,6 +182,15 @@ sdc2_cd_default: sdc2-cd-default-state { pins = "gpio38"; function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + tsp_int_default: tsp-int-default-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; bias-disable; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts index 0a32d33e9778..3e1ff5b4d2d7 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts @@ -10,6 +10,14 @@ chassis-type = "handset"; }; +&blsp_i2c5 { + status = "disabled"; +}; + +&touchscreen { + /* FIXME: Missing sm5703-mfd driver to power up vdd-supply */ +}; + &usb_hs_phy { qcom,init-seq = /bits/ 8 <0x1 0x19 0x2 0x0b>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts index 7e1326cc13c5..b2fe109723d8 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-j5x.dts @@ -8,12 +8,38 @@ model = "Samsung Galaxy J5 (2016)"; compatible = "samsung,j5x", "qcom,msm8916"; chassis-type = "handset"; + + reg_vdd_tsp_a: regulator-vdd-tsp-a { + compatible = "regulator-fixed"; + regulator-name = "vdd_tsp_a"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + gpio = <&tlmm 108 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tsp_ldo_en_default>; + pinctrl-names = "default"; + }; }; &muic { interrupts = <121 IRQ_TYPE_EDGE_FALLING>; }; +&touchscreen { + vdd-supply = <®_vdd_tsp_a>; +}; + +&tlmm { + tsp_ldo_en_default: tsp-ldo-en-default-state { + pins = "gpio108"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + &muic_int_default { pins = "gpio121"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts index 15dc246e84e2..eaf877378937 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts @@ -142,6 +142,12 @@ pinctrl-names = "default"; pinctrl-0 = <&muic_irq_default>; + + usb_con: connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; }; }; @@ -199,6 +205,15 @@ pinctrl-0 = <&nfc_default>; }; }; + + battery: battery { + compatible = "simple-battery"; + precharge-current-microamp = <450000>; + constant-charge-current-max-microamp = <1000000>; + charge-term-current-microamp = <150000>; + precharge-upper-limit-microvolt = <3500000>; + constant-charge-voltage-max-microvolt = <4350000>; + }; }; &blsp_i2c2 { @@ -219,16 +234,16 @@ compatible = "yamaha,yas537"; reg = <0x2e>; - mount-matrix = "0", "1", "0", - "1", "0", "0", - "0", "0", "-1"; + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; }; }; &blsp_i2c4 { status = "okay"; - battery@35 { + fuel-gauge@35 { compatible = "richtek,rt5033-battery"; reg = <0x35>; @@ -237,6 +252,8 @@ pinctrl-names = "default"; pinctrl-0 = <&fg_alert_default>; + + power-supplies = <&rt5033_charger>; }; }; @@ -261,6 +278,43 @@ }; }; +&blsp_i2c6 { + status = "okay"; + + pmic@34 { + compatible = "richtek,rt5033"; + reg = <0x34>; + + interrupt-parent = <&tlmm>; + interrupts = <62 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_default>; + + regulators { + rt5033_reg_safe_ldo: SAFE_LDO { + regulator-min-microvolt = <4900000>; + regulator-max-microvolt = <4900000>; + regulator-always-on; + }; + rt5033_reg_ldo: LDO { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + rt5033_reg_buck: BUCK { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; + + rt5033_charger: charger { + compatible = "richtek,rt5033-charger"; + monitored-battery = <&battery>; + richtek,usb-connector = <&usb_con>; + }; + }; +}; + &blsp_uart2 { status = "okay"; }; @@ -387,6 +441,14 @@ bias-disable; }; + pmic_int_default: pmic-int-default-state { + pins = "gpio62"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + tkey_default: tkey-default-state { pins = "gpio98"; function = "gpio"; diff --git a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts index c94d36b38651..8e238976ab1c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts @@ -56,7 +56,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb_id_default>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 7582c7d748fe..33fb65d73104 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -282,10 +282,10 @@ }; }; - smd { - compatible = "qcom,smd"; + rpm: remoteproc { + compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc"; - rpm { + smd-edge { interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; @@ -1712,6 +1712,14 @@ ports { #address-cells = <1>; #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts new file mode 100644 index 000000000000..ba652909d162 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8939-samsung-a7.dts @@ -0,0 +1,495 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/dts-v1/; + +#include "msm8939-pm8916.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "Samsung Galaxy A7 (2015)"; + compatible = "samsung,a7", "qcom,msm8939"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + serial0 = &blsp_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; + + reserved-memory { + /* Additional memory used by Samsung firmware modifications */ + tz-apps@85500000 { + reg = <0x0 0x85500000 0x0 0xb00000>; + no-map; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_hall_sensor_default>; + pinctrl-names = "default"; + + label = "GPIO Hall Effect Sensor"; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 52 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + linux,can-disable; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + label = "GPIO Buttons"; + + button-volume-up { + label = "Volume Up"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + + button-home { + label = "Home"; + gpios = <&tlmm 109 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOMEPAGE>; + }; + }; + + i2c-fg { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 106 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 105 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&fg_i2c_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + battery@35 { + compatible = "richtek,rt5033-battery"; + reg = <0x35>; + + interrupt-parent = <&tlmm>; + interrupts = <121 IRQ_TYPE_EDGE_BOTH>; + + pinctrl-0 = <&fg_alert_default>; + pinctrl-names = "default"; + }; + }; + + i2c-nfc { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&nfc_i2c_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + nfc@2b { + compatible = "nxp,pn547", "nxp,nxp-nci-i2c"; + reg = <0x2b>; + + interrupt-parent = <&tlmm>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&nfc_default>; + pinctrl-names = "default"; + }; + }; + + i2c-sensor { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 84 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 85 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&sensor_i2c_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + accelerometer: accelerometer@10 { + compatible = "bosch,bmc150_accel"; + reg = <0x10>; + interrupt-parent = <&tlmm>; + interrupts = <115 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l5>; + + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + + mount-matrix = "-1", "0", "0", + "0", "-1", "0", + "0", "0", "1"; + }; + + magnetometer@12 { + compatible = "bosch,bmc150_magn"; + reg = <0x12>; + + vdd-supply = <&pm8916_l17>; + vddio-supply = <&pm8916_l5>; + }; + }; + + i2c-tkey { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&tkey_i2c_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + touchkey@20 { + /* Note: Actually an ABOV MCU that implements same interface */ + compatible = "coreriver,tc360-touchkey"; + reg = <0x20>; + + interrupt-parent = <&tlmm>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + + vcc-supply = <®_touch_key>; + vdd-supply = <®_keyled>; + vddio-supply = <&pm8916_l6>; + + linux,keycodes = <KEY_APPSELECT KEY_BACK>; + + pinctrl-0 = <&tkey_default>; + pinctrl-names = "default"; + }; + }; + + pwm_vibrator: pwm-vibrator { + compatible = "clk-pwm"; + #pwm-cells = <2>; + + clocks = <&gcc GCC_GP2_CLK>; + + pinctrl-0 = <&motor_pwm_default>; + pinctrl-names = "default"; + }; + + reg_keyled: regulator-keyled { + compatible = "regulator-fixed"; + regulator-name = "keyled"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + /* NOTE: On some variants e.g. SM-A700FD it's GPIO 91 */ + gpio = <&tlmm 100 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tkey_led_en_default>; + pinctrl-names = "default"; + }; + + reg_touch_key: regulator-touch-key { + compatible = "regulator-fixed"; + regulator-name = "touch_key"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + gpio = <&tlmm 56 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tkey_en_default>; + pinctrl-names = "default"; + }; + + reg_tsp_vdd: regulator-tsp-vdd { + compatible = "regulator-fixed"; + regulator-name = "tsp_vdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&pm8916_s4>; + + gpio = <&tlmm 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <®_tsp_io_en_default>; + pinctrl-names = "default"; + }; + + reg_vdd_tsp: regulator-vdd-tsp { + compatible = "regulator-fixed"; + regulator-name = "vdd_tsp"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <®_tsp_en_default>; + pinctrl-names = "default"; + }; + + reg_vibrator: regulator-vibrator { + compatible = "regulator-fixed"; + regulator-name = "motor_en"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&motor_en_default>; + pinctrl-names = "default"; + }; + + vibrator { + compatible = "pwm-vibrator"; + + pwms = <&pwm_vibrator 0 100000>; + pwm-names = "enable"; + + vcc-supply = <®_vibrator>; + }; +}; + +&blsp_i2c1 { + status = "okay"; + + muic: extcon@25 { + compatible = "siliconmitus,sm5502-muic"; + reg = <0x25>; + + interrupt-parent = <&tlmm>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&muic_int_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_i2c5 { + status = "okay"; + + touchscreen@24 { + compatible = "cypress,tt21000"; + + reg = <0x24>; + interrupt-parent = <&tlmm>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <®_vdd_tsp>; + vddio-supply = <®_tsp_vdd>; + + pinctrl-0 = <&tsp_int_default>; + pinctrl-names = "default"; + }; +}; + +&blsp_uart2 { + status = "okay"; +}; + +&pm8916_resin { + linux,code = <KEY_VOLUMEDOWN>; + status = "okay"; +}; + +&pm8916_rpm_regulators { + pm8916_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_default &sdc2_cd_default>; + pinctrl-1 = <&sdc2_sleep &sdc2_cd_default>; + pinctrl-names = "default", "sleep"; + + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&usb { + extcon = <&muic>, <&muic>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&muic>; +}; + +&wcnss { + status = "okay"; +}; + +&wcnss_iris { + compatible = "qcom,wcn3660b"; +}; + +&tlmm { + accel_int_default: accel-int-default-state { + pins = "gpio115"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + fg_alert_default: fg-alert-default-state { + pins = "gpio121"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + fg_i2c_default: fg-i2c-default-state { + pins = "gpio105", "gpio106"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins = "gpio52"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio107", "gpio109"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + motor_en_default: motor-en-default-state { + pins = "gpio86"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + motor_pwm_default: motor-pwm-default-state { + pins = "gpio50"; + function = "gcc_gp2_clk_a"; + }; + + muic_int_default: muic-int-default-state { + pins = "gpio12"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + nfc_default: nfc-default-state { + irq-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + nfc-pins { + pins = "gpio49", "gpio116"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + + nfc_i2c_default: nfc-i2c-default-state { + pins = "gpio0", "gpio1"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + reg_tsp_en_default: reg-tsp-en-default-state { + pins = "gpio73"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + reg_tsp_io_en_default: reg-tsp-io-en-default-state { + pins = "gpio8"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_cd_default: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sensor_i2c_default: sensor-i2c-default-state { + pins = "gpio84", "gpio85"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tkey_default: tkey-default-state { + pins = "gpio20"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tkey_en_default: tkey-en-default-state { + pins = "gpio56"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tkey_i2c_default: tkey-i2c-default-state { + pins = "gpio16", "gpio17"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tkey_led_en_default: tkey-led-en-default-state { + pins = "gpio100"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_default: tsp-int-default-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts index 8613cf93dac5..89b6aebba404 100644 --- a/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts +++ b/arch/arm64/boot/dts/qcom/msm8939-sony-xperia-kanuti-tulip.dts @@ -16,6 +16,7 @@ / { model = "Sony Xperia M4 Aqua"; compatible = "sony,kanuti-tulip", "qcom,msm8939"; + chassis-type = "handset"; qcom,board-id = <QCOM_BOARD_ID_MTP 0>; qcom,msm-id = <QCOM_ID_MSM8939 0>, <QCOM_ID_MSM8939 0x30000>; @@ -32,7 +33,7 @@ usb_id: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 110 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; pinctrl-0 = <&usb_id_default>; pinctrl-names = "default"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi index 895cafc11480..6e24f0f2374f 100644 --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi @@ -55,6 +55,7 @@ L2_1: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; @@ -111,6 +112,7 @@ L2_0: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; @@ -155,7 +157,7 @@ idle-states { CPU_SLEEP_0: cpu-sleep-0 { - compatible ="qcom,idle-state-spc", "arm,idle-state"; + compatible = "arm,idle-state"; entry-latency-us = <130>; exit-latency-us = <150>; min-residency-us = <2000>; @@ -240,6 +242,62 @@ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; }; + rpm: remoteproc { + compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs1_mbox 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8936"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8939-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -308,62 +366,6 @@ }; }; - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs1_mbox 8 0>; - qcom,smd-edge = <15>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8936"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc"; - #clock-cells = <1>; - clock-names = "xo"; - clocks = <&xo_board>; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8939-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <1>; - }; - - rpmpd_opp_svs_krait: opp2 { - opp-level = <2>; - }; - - rpmpd_opp_svs_soc: opp3 { - opp-level = <3>; - }; - - rpmpd_opp_nom: opp4 { - opp-level = <4>; - }; - - rpmpd_opp_turbo: opp5 { - opp-level = <5>; - }; - - rpmpd_opp_super_turbo: opp6 { - opp-level = <6>; - }; - }; - }; - }; - }; - }; - smp2p-hexagon { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; @@ -386,8 +388,6 @@ interrupt-controller; #interrupt-cells = <2>; - #address-cells = <0>; - #size-cells = <0>; }; }; @@ -1644,7 +1644,7 @@ clocks = <&gcc GCC_SDCC2_AHB_CLK>, <&gcc GCC_SDCC2_APPS_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; - clock-names = "iface", "core", "xo"; + clock-names = "iface", "core", "xo"; resets = <&gcc GCC_SDCC2_BCR>; pinctrl-0 = <&sdc2_default>; pinctrl-1 = <&sdc2_sleep>; @@ -1731,7 +1731,7 @@ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; + clock-names = "core", "iface"; dmas = <&blsp_dma 6>, <&blsp_dma 7>; dma-names = "tx", "rx"; pinctrl-0 = <&blsp_i2c2_default>; @@ -1765,7 +1765,7 @@ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; + clock-names = "core", "iface"; dmas = <&blsp_dma 8>, <&blsp_dma 9>; dma-names = "tx", "rx"; pinctrl-0 = <&blsp_i2c3_default>; @@ -1799,7 +1799,7 @@ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; + clock-names = "core", "iface"; dmas = <&blsp_dma 10>, <&blsp_dma 11>; dma-names = "tx", "rx"; pinctrl-0 = <&blsp_i2c4_default>; @@ -1833,7 +1833,7 @@ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; + clock-names = "core", "iface"; dmas = <&blsp_dma 12>, <&blsp_dma 13>; dma-names = "tx", "rx"; pinctrl-0 = <&blsp_i2c5_default>; @@ -1867,7 +1867,7 @@ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; - clock-names = "core", "iface"; + clock-names = "core", "iface"; dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; pinctrl-0 = <&blsp_i2c6_default>; @@ -1975,7 +1975,7 @@ }; smd-edge { - interrupts = <GIC_SPI 142 1>; + interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; qcom,ipc = <&apcs1_mbox 8 17>; qcom,smd-edge = <6>; qcom,remote-pid = <4>; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts index 1d672e608653..a5957e79b818 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-daisy.dts @@ -17,7 +17,7 @@ compatible = "xiaomi,daisy", "qcom,msm8953"; chassis-type = "handset"; qcom,msm-id = <293 0>; - qcom,board-id= <0x1000b 0x9>; + qcom,board-id = <0x1000b 0x9>; chosen { #address-cells = <2>; @@ -125,7 +125,7 @@ vmon-slot-no = <1>; imon-slot-no = <1>; - interleave_mode = <0>; + maxim,interleave-mode; #sound-dai-cells = <0>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts index 831d3a42b583..61ff629c9bf3 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-tissot.dts @@ -96,7 +96,7 @@ vmon-slot-no = <1>; imon-slot-no = <1>; - #sound-dai-cells = <1>; + #sound-dai-cells = <0>; }; led-controller@45 { diff --git a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts index b5be55034fd3..1a1d3f92a511 100644 --- a/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts +++ b/arch/arm64/boot/dts/qcom/msm8953-xiaomi-vince.dts @@ -20,7 +20,7 @@ compatible = "xiaomi,vince", "qcom,msm8953"; chassis-type = "handset"; qcom,msm-id = <293 0>; - qcom,board-id= <0x1000b 0x08>; + qcom,board-id = <0x1000b 0x08>; gpio-keys { compatible = "gpio-keys"; @@ -132,7 +132,6 @@ touchscreen@20 { reg = <0x20>; compatible = "syna,rmi4-i2c"; - interrupts-parent = <&tlmm>; interrupts-extended = <&tlmm 65 IRQ_TYPE_EDGE_FALLING>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index b711cf9a6dc0..e7de7632669a 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -190,6 +190,74 @@ method = "smc"; }; + rpm: remoteproc { + compatible = "qcom,msm8953-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8953"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8953-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <RPM_SMD_LEVEL_RETENTION>; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = <RPM_SMD_LEVEL_MIN_SVS>; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = <RPM_SMD_LEVEL_LOW_SVS>; + }; + + rpmpd_opp_svs: opp5 { + opp-level = <RPM_SMD_LEVEL_SVS>; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; + }; + + rpmpd_opp_nom: opp7 { + opp-level = <RPM_SMD_LEVEL_NOM>; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = <RPM_SMD_LEVEL_TURBO>; + }; + }; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -263,74 +331,6 @@ }; }; - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8953"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc"; - clocks = <&xo_board>; - clock-names = "xo"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8953-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <RPM_SMD_LEVEL_RETENTION>; - }; - - rpmpd_opp_ret_plus: opp2 { - opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; - }; - - rpmpd_opp_min_svs: opp3 { - opp-level = <RPM_SMD_LEVEL_MIN_SVS>; - }; - - rpmpd_opp_low_svs: opp4 { - opp-level = <RPM_SMD_LEVEL_LOW_SVS>; - }; - - rpmpd_opp_svs: opp5 { - opp-level = <RPM_SMD_LEVEL_SVS>; - }; - - rpmpd_opp_svs_plus: opp6 { - opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; - }; - - rpmpd_opp_nom: opp7 { - opp-level = <RPM_SMD_LEVEL_NOM>; - }; - - rpmpd_opp_nom_plus: opp8 { - opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; - }; - - rpmpd_opp_turbo: opp9 { - opp-level = <RPM_SMD_LEVEL_TURBO>; - }; - }; - }; - }; - }; - }; - smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 753b9a2105ed..f9f5afbcc52b 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -232,6 +232,82 @@ method = "smc"; }; + rpm: remoteproc { + compatible = "qcom,msm8976-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8976"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8976-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <RPM_SMD_LEVEL_RETENTION>; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = <RPM_SMD_LEVEL_MIN_SVS>; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = <RPM_SMD_LEVEL_LOW_SVS>; + }; + + rpmpd_opp_svs: opp5 { + opp-level = <RPM_SMD_LEVEL_SVS>; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; + }; + + rpmpd_opp_nom: opp7 { + opp-level = <RPM_SMD_LEVEL_NOM>; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = <RPM_SMD_LEVEL_TURBO>; + }; + + rpmpd_opp_turbo_no_cpr: opp10 { + opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; + }; + + rpmpd_opp_turbo_high: opp111 { + opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>; + }; + }; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -346,82 +422,6 @@ }; }; - smd { - compatible = "qcom,smd"; - - rpm { - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8976"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc"; - clocks = <&xo_board>; - clock-names = "xo"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8976-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <RPM_SMD_LEVEL_RETENTION>; - }; - - rpmpd_opp_ret_plus: opp2 { - opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; - }; - - rpmpd_opp_min_svs: opp3 { - opp-level = <RPM_SMD_LEVEL_MIN_SVS>; - }; - - rpmpd_opp_low_svs: opp4 { - opp-level = <RPM_SMD_LEVEL_LOW_SVS>; - }; - - rpmpd_opp_svs: opp5 { - opp-level = <RPM_SMD_LEVEL_SVS>; - }; - - rpmpd_opp_svs_plus: opp6 { - opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; - }; - - rpmpd_opp_nom: opp7 { - opp-level = <RPM_SMD_LEVEL_NOM>; - }; - - rpmpd_opp_nom_plus: opp8 { - opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; - }; - - rpmpd_opp_turbo: opp9 { - opp-level = <RPM_SMD_LEVEL_TURBO>; - }; - - rpmpd_opp_turbo_no_cpr: opp10 { - opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; - }; - - rpmpd_opp_turbo_high: opp111 { - opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>; - }; - }; - }; - }; - }; - }; - smsm { compatible = "qcom,smsm"; @@ -439,7 +439,7 @@ hexagon_smsm: hexagon@1 { reg = <1>; - interrupts = <0 290 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 5a7923d7c62a..c3262571520d 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -178,6 +178,56 @@ method = "hvc"; }; + rpm: remoteproc { + compatible = "qcom,msm8994-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + qcom,remote-pid = <6>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8994"; + qcom,smd-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8994-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <1>; + }; + rpmpd_opp_svs_krait: opp2 { + opp-level = <2>; + }; + rpmpd_opp_svs_soc: opp3 { + opp-level = <3>; + }; + rpmpd_opp_nom: opp4 { + opp-level = <4>; + }; + rpmpd_opp_turbo: opp5 { + opp-level = <5>; + }; + rpmpd_opp_super_turbo: opp6 { + opp-level = <6>; + }; + }; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -237,55 +287,6 @@ }; }; - smd { - compatible = "qcom,smd"; - rpm { - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 0>; - qcom,smd-edge = <15>; - qcom,remote-pid = <6>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8994"; - qcom,smd-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8994-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <1>; - }; - rpmpd_opp_svs_krait: opp2 { - opp-level = <2>; - }; - rpmpd_opp_svs_soc: opp3 { - opp-level = <3>; - }; - rpmpd_opp_nom: opp4 { - opp-level = <4>; - }; - rpmpd_opp_turbo: opp5 { - opp-level = <5>; - }; - rpmpd_opp_super_turbo: opp6 { - opp-level = <6>; - }; - }; - }; - }; - }; - }; - smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; @@ -455,7 +456,7 @@ usb@f9200000 { compatible = "snps,dwc3"; reg = <0xf9200000 0xcc00>; - interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; maximum-speed = "high-speed"; diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts index 495d45a16e63..6e9c9caf25b1 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts @@ -10,6 +10,7 @@ / { model = "Qualcomm Technologies, Inc. MSM 8996 MTP"; compatible = "qcom,msm8996-mtp", "qcom,msm8996"; + chassis-type = "handset"; aliases { serial0 = &blsp2_uart2; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts index 4a0645db0ae1..6374c5f53d9a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone-dora.dts @@ -24,5 +24,5 @@ }; &usb3_id { - id-gpio = <&tlmm 24 GPIO_ACTIVE_LOW>; + id-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index b4b770a9277d..d55e4075040f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -71,7 +71,7 @@ usb3_id: usb3-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 25 GPIO_ACTIVE_LOW>; + id-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&usb_detect>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 47f55c7311e9..bcd2397eb373 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -187,10 +187,9 @@ &blsp2_i2c2 { status = "okay"; - label = "NFC_I2C"; clock-frequency = <400000>; - nfc: pn548@28 { + nfc: nfc@28 { compatible = "nxp,nxp-nci-i2c"; reg = <0x28>; @@ -208,9 +207,8 @@ &blsp2_i2c3 { status = "okay"; - label = "TYPEC_I2C"; - typec: tusb320l@47 { + typec: typec@47 { compatible = "ti,tusb320l"; reg = <0x47>; interrupt-parent = <&tlmm>; @@ -220,7 +218,7 @@ &blsp2_i2c6 { status = "okay"; - label = "MSM_TS_I2C"; + /* MSM_TS */ }; &blsp1_uart2 { diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index bdedcf9dff03..d1066edaea47 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -82,7 +82,7 @@ #size-cells = <0>; interrupt-parent = <&tlmm>; interrupts = <125 IRQ_TYPE_LEVEL_LOW>; - vdda-supply = <&vreg_l6a_1p8>; + vio-supply = <&vreg_l6a_1p8>; vdd-supply = <&vdd_3v2_tp>; reset-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 0cb2d4f08c3a..c8e0986425ab 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/qcom,mmcc-msm8996.h> #include <dt-bindings/clock/qcom,rpmcc.h> #include <dt-bindings/interconnect/qcom,msm8996.h> +#include <dt-bindings/interconnect/qcom,msm8996-cbf.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,apr.h> @@ -49,6 +50,7 @@ cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; clocks = <&kryocc 0>; + interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; next-level-cache = <&L2_0>; @@ -67,6 +69,7 @@ cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; clocks = <&kryocc 0>; + interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; operating-points-v2 = <&cluster0_opp>; #cooling-cells = <2>; next-level-cache = <&L2_0>; @@ -80,6 +83,7 @@ cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; clocks = <&kryocc 1>; + interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; operating-points-v2 = <&cluster1_opp>; #cooling-cells = <2>; next-level-cache = <&L2_1>; @@ -98,6 +102,7 @@ cpu-idle-states = <&CPU_SLEEP_0>; capacity-dmips-mhz = <1024>; clocks = <&kryocc 1>; + interconnects = <&cbf MASTER_CBF_M4M &cbf SLAVE_CBF_M4M>; operating-points-v2 = <&cluster1_opp>; #cooling-cells = <2>; next-level-cache = <&L2_1>; @@ -149,91 +154,109 @@ opp-hz = /bits/ 64 <307200000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-422400000 { opp-hz = /bits/ 64 <422400000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-556800000 { opp-hz = /bits/ 64 <556800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-652800000 { opp-hz = /bits/ 64 <652800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <384000>; }; opp-729600000 { opp-hz = /bits/ 64 <729600000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <460800>; }; opp-844800000 { opp-hz = /bits/ 64 <844800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <537600>; }; opp-960000000 { opp-hz = /bits/ 64 <960000000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <672000>; }; opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <672000>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <825600>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <825600>; }; opp-1228800000 { opp-hz = /bits/ 64 <1228800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <902400>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; opp-supported-hw = <0xd>; clock-latency-ns = <200000>; + opp-peak-kBps = <1056000>; }; opp-1363200000 { opp-hz = /bits/ 64 <1363200000>; opp-supported-hw = <0x2>; clock-latency-ns = <200000>; + opp-peak-kBps = <1132800>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; opp-supported-hw = <0xd>; clock-latency-ns = <200000>; + opp-peak-kBps = <1132800>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; opp-supported-hw = <0x9>; clock-latency-ns = <200000>; + opp-peak-kBps = <1190400>; }; opp-1497600000 { opp-hz = /bits/ 64 <1497600000>; opp-supported-hw = <0x04>; clock-latency-ns = <200000>; + opp-peak-kBps = <1305600>; }; opp-1593600000 { opp-hz = /bits/ 64 <1593600000>; opp-supported-hw = <0x9>; clock-latency-ns = <200000>; + opp-peak-kBps = <1382400>; }; }; @@ -247,136 +270,163 @@ opp-hz = /bits/ 64 <307200000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-403200000 { opp-hz = /bits/ 64 <403200000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-480000000 { opp-hz = /bits/ 64 <480000000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-556800000 { opp-hz = /bits/ 64 <556800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-652800000 { opp-hz = /bits/ 64 <652800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-729600000 { opp-hz = /bits/ 64 <729600000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <307200>; }; opp-806400000 { opp-hz = /bits/ 64 <806400000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <384000>; }; opp-883200000 { opp-hz = /bits/ 64 <883200000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <460800>; }; opp-940800000 { opp-hz = /bits/ 64 <940800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <537600>; }; opp-1036800000 { opp-hz = /bits/ 64 <1036800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <595200>; }; opp-1113600000 { opp-hz = /bits/ 64 <1113600000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <672000>; }; opp-1190400000 { opp-hz = /bits/ 64 <1190400000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <672000>; }; opp-1248000000 { opp-hz = /bits/ 64 <1248000000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <748800>; }; opp-1324800000 { opp-hz = /bits/ 64 <1324800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <825600>; }; opp-1401600000 { opp-hz = /bits/ 64 <1401600000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <902400>; }; opp-1478400000 { opp-hz = /bits/ 64 <1478400000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <979200>; }; opp-1555200000 { opp-hz = /bits/ 64 <1555200000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <1056000>; }; opp-1632000000 { opp-hz = /bits/ 64 <1632000000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <1190400>; }; opp-1708800000 { opp-hz = /bits/ 64 <1708800000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <1228800>; }; opp-1785600000 { opp-hz = /bits/ 64 <1785600000>; opp-supported-hw = <0xf>; clock-latency-ns = <200000>; + opp-peak-kBps = <1305600>; }; opp-1804800000 { opp-hz = /bits/ 64 <1804800000>; opp-supported-hw = <0xe>; clock-latency-ns = <200000>; + opp-peak-kBps = <1305600>; }; opp-1824000000 { opp-hz = /bits/ 64 <1824000000>; opp-supported-hw = <0x1>; clock-latency-ns = <200000>; + opp-peak-kBps = <1382400>; }; opp-1900800000 { opp-hz = /bits/ 64 <1900800000>; opp-supported-hw = <0x4>; clock-latency-ns = <200000>; + opp-peak-kBps = <1305600>; }; opp-1920000000 { opp-hz = /bits/ 64 <1920000000>; opp-supported-hw = <0x1>; clock-latency-ns = <200000>; + opp-peak-kBps = <1459200>; }; opp-1996800000 { opp-hz = /bits/ 64 <1996800000>; opp-supported-hw = <0x1>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; opp-2073600000 { opp-hz = /bits/ 64 <2073600000>; opp-supported-hw = <0x1>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; opp-2150400000 { opp-hz = /bits/ 64 <2150400000>; opp-supported-hw = <0x1>; clock-latency-ns = <200000>; + opp-peak-kBps = <1593600>; }; }; @@ -398,6 +448,63 @@ method = "smc"; }; + rpm: remoteproc { + compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8996"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + rpmpd: power-controller { + compatible = "qcom,msm8996-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp1: opp1 { + opp-level = <1>; + }; + + rpmpd_opp2: opp2 { + opp-level = <2>; + }; + + rpmpd_opp3: opp3 { + opp-level = <3>; + }; + + rpmpd_opp4: opp4 { + opp-level = <4>; + }; + + rpmpd_opp5: opp5 { + opp-level = <5>; + }; + + rpmpd_opp6: opp6 { + opp-level = <6>; + }; + }; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -472,62 +579,6 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - - qcom,rpm-msg-ram = <&rpm_msg_ram>; - - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8996"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; - #clock-cells = <1>; - clocks = <&xo_board>; - clock-names = "xo"; - }; - - rpmpd: power-controller { - compatible = "qcom,msm8996-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp1: opp1 { - opp-level = <1>; - }; - - rpmpd_opp2: opp2 { - opp-level = <2>; - }; - - rpmpd_opp3: opp3 { - opp-level = <3>; - }; - - rpmpd_opp4: opp4 { - opp-level = <4>; - }; - - rpmpd_opp5: opp5 { - opp-level = <5>; - }; - - rpmpd_opp6: opp6 { - opp-level = <6>; - }; - }; - }; - }; - }; - smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; @@ -538,7 +589,7 @@ compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; - interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; + interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; mboxes = <&apcs_glb 10>; @@ -1075,7 +1126,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <4>; + interrupts = <5>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_BYTE1_CLK>, @@ -1136,11 +1187,11 @@ status = "disabled"; }; - mdss_hdmi: mdss_hdmi-tx@9a0000 { - compatible = "qcom,mdss_hdmi-tx-8996"; - reg = <0x009a0000 0x50c>, - <0x00070000 0x6158>, - <0x009e0000 0xfff>; + mdss_hdmi: hdmi-tx@9a0000 { + compatible = "qcom,hdmi-tx-8996"; + reg = <0x009a0000 0x50c>, + <0x00070000 0x6158>, + <0x009e0000 0xfff>; reg-names = "core_physical", "qfprom_physical", "hdcp_physical"; @@ -1180,7 +1231,7 @@ mdss_hdmi_phy: phy@9a0600 { #phy-cells = <0>; - compatible = "qcom,mdss_hdmi-phy-8996"; + compatible = "qcom,hdmi-phy-8996"; reg = <0x009a0600 0x1c4>, <0x009a0a00 0x124>, <0x009a0c00 0x124>, @@ -1213,7 +1264,7 @@ reg = <0x00b00000 0x3f000>; reg-names = "kgsl_3d0_reg_memory"; - interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mmcc GPU_GX_GFX3D_CLK>, <&mmcc GPU_AHB_CLK>, @@ -3003,7 +3054,7 @@ usb3_dwc3: usb@6a00000 { compatible = "snps,dwc3"; reg = <0x06a00000 0xcc00>; - interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; phys = <&hsusb_phy1>, <&ssusb_phy_0>; phy-names = "usb2-phy", "usb3-phy"; snps,hird-threshold = /bits/ 8 <0>; @@ -3336,6 +3387,9 @@ #size-cells = <1>; ranges; + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq"; + clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, <&gcc GCC_USB20_MASTER_CLK>, <&gcc GCC_USB20_MOCK_UTMI_CLK>, @@ -3358,7 +3412,7 @@ usb2_dwc3: usb@7600000 { compatible = "snps,dwc3"; reg = <0x07600000 0xcc00>; - interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; phys = <&hsusb_phy2>; phy-names = "usb2-phy"; maximum-speed = "high-speed"; @@ -3372,7 +3426,7 @@ qcom,controlled-remotely; reg = <0x09184000 0x32000>; num-channels = <31>; - interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; qcom,ee = <1>; qcom,num-ees = <2>; @@ -3381,7 +3435,7 @@ slim_msm: slim-ngd@91c0000 { compatible = "qcom,slim-ngd-v1.5.0"; reg = <0x091c0000 0x2c000>; - interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; dmas = <&slimbam 3>, <&slimbam 4>; dma-names = "rx", "tx"; #address-cells = <1>; @@ -3551,6 +3605,7 @@ reg = <0x09a11000 0x10000>; clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&apcs_glb>; #clock-cells = <0>; + #interconnect-cells = <1>; }; intc: interrupt-controller@9bc0000 { diff --git a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts index 7957c8823f0d..5e3fd1637f44 100644 --- a/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts +++ b/arch/arm64/boot/dts/qcom/msm8996pro-xiaomi-natrium.dts @@ -106,7 +106,7 @@ &sound { compatible = "qcom,apq8096-sndcard"; model = "natrium"; - audio-routing = "RX_BIAS", "MCLK"; + audio-routing = "RX_BIAS", "MCLK"; mm1-dai-link { link-name = "MultiMedia1"; diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index b35e2d9f428c..b6a214bea70f 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -31,7 +31,7 @@ */ extcon_usb: extcon-usb { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; }; gpio-hall-sensors { diff --git a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts index 453a1c9e9808..4319f4da8996 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-mtp.dts @@ -11,6 +11,7 @@ / { model = "Qualcomm Technologies, Inc. MSM8998 v1 MTP"; compatible = "qcom,msm8998-mtp", "qcom,msm8998"; + chassis-type = "handset"; qcom,board-id = <8 0>; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 687e96068cb2..876c6921ddf0 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -89,8 +89,8 @@ extcon_usb: extcon-usb { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>; - vbus-gpio = <&tlmm 128 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; + vbus-gpios = <&tlmm 128 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cc_dir_default &usb_detect_en>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts index 2444b87fddf7..437b30cc8bdc 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-xiaomi-sagit.dts @@ -213,7 +213,6 @@ rmi4-f1a@1a { reg = <0x1a>; - syna,codes = <KEY_BACK KEY_APPSELECT>; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index f0e943ff0046..f180047cacb0 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -316,73 +316,98 @@ }; }; + dsi_opp_table: opp-table-dsi { + compatible = "operating-points-v2"; + + opp-131250000 { + opp-hz = /bits/ 64 <131250000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-210000000 { + opp-hz = /bits/ 64 <210000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-312500000 { + opp-hz = /bits/ 64 <312500000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; }; - rpm-glink { - compatible = "qcom,glink-rpm"; + rpm: remoteproc { + compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc"; - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; + glink-edge { + compatible = "qcom,glink-rpm"; - rpm_requests: rpm-requests { - compatible = "qcom,rpm-msm8998"; - qcom,glink-channels = "rpm_requests"; + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; - rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; - #clock-cells = <1>; - }; + rpm_requests: rpm-requests { + compatible = "qcom,rpm-msm8998"; + qcom,glink-channels = "rpm_requests"; - rpmpd: power-controller { - compatible = "qcom,msm8998-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; + clocks = <&xo>; + clock-names = "xo"; + #clock-cells = <1>; + }; - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; + rpmpd: power-controller { + compatible = "qcom,msm8998-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; - rpmpd_opp_ret: opp1 { - opp-level = <RPM_SMD_LEVEL_RETENTION>; - }; + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; - rpmpd_opp_ret_plus: opp2 { - opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; - }; + rpmpd_opp_ret: opp1 { + opp-level = <RPM_SMD_LEVEL_RETENTION>; + }; - rpmpd_opp_min_svs: opp3 { - opp-level = <RPM_SMD_LEVEL_MIN_SVS>; - }; + rpmpd_opp_ret_plus: opp2 { + opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; + }; - rpmpd_opp_low_svs: opp4 { - opp-level = <RPM_SMD_LEVEL_LOW_SVS>; - }; + rpmpd_opp_min_svs: opp3 { + opp-level = <RPM_SMD_LEVEL_MIN_SVS>; + }; - rpmpd_opp_svs: opp5 { - opp-level = <RPM_SMD_LEVEL_SVS>; - }; + rpmpd_opp_low_svs: opp4 { + opp-level = <RPM_SMD_LEVEL_LOW_SVS>; + }; - rpmpd_opp_svs_plus: opp6 { - opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; - }; + rpmpd_opp_svs: opp5 { + opp-level = <RPM_SMD_LEVEL_SVS>; + }; - rpmpd_opp_nom: opp7 { - opp-level = <RPM_SMD_LEVEL_NOM>; - }; + rpmpd_opp_svs_plus: opp6 { + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; + }; - rpmpd_opp_nom_plus: opp8 { - opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; - }; + rpmpd_opp_nom: opp7 { + opp-level = <RPM_SMD_LEVEL_NOM>; + }; - rpmpd_opp_turbo: opp9 { - opp-level = <RPM_SMD_LEVEL_TURBO>; - }; + rpmpd_opp_nom_plus: opp8 { + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; + }; - rpmpd_opp_turbo_plus: opp10 { - opp-level = <RPM_SMD_LEVEL_BINNING>; + rpmpd_opp_turbo: opp9 { + opp-level = <RPM_SMD_LEVEL_TURBO>; + }; + + rpmpd_opp_turbo_plus: opp10 { + opp-level = <RPM_SMD_LEVEL_BINNING>; + }; }; }; }; @@ -909,10 +934,10 @@ pcie0: pci@1c00000 { compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996"; - reg = <0x01c00000 0x2000>, - <0x1b000000 0xf1d>, - <0x1b000f20 0xa8>, - <0x1b100000 0x100000>; + reg = <0x01c00000 0x2000>, + <0x1b000000 0xf1d>, + <0x1b000f20 0xa8>, + <0x1b100000 0x100000>; reg-names = "parf", "dbi", "elbi", "config"; device_type = "pci"; linux,pci-domain = <0>; @@ -1488,7 +1513,7 @@ "rbcpr", "core"; - interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; iommus = <&adreno_smmu 0>; operating-points-v2 = <&gpu_opp_table>; power-domains = <&rpmpd MSM8998_VDDMX>; @@ -1574,7 +1599,7 @@ reg = <0x05065000 0x9000>; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, - <&gcc GPLL0_OUT_MAIN>; + <&gcc GCC_GPU_GPLL0_CLK>; clock-names = "xo", "gpll0"; }; @@ -2074,11 +2099,11 @@ spmi_bus: spmi@800f000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x0800f000 0x1000>, - <0x08400000 0x1000000>, - <0x09400000 0x1000000>, - <0x0a400000 0x220000>, - <0x0800a000 0x3000>; + reg = <0x0800f000 0x1000>, + <0x08400000 0x1000000>, + <0x09400000 0x1000000>, + <0x0a400000 0x220000>, + <0x0800a000 0x3000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; @@ -2718,16 +2743,274 @@ "dsi1byte", "hdmipll", "dplink", - "dpvco"; + "dpvco", + "gpll0_div"; clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GCC_MMSS_GPLL0_CLK>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>, <0>, <0>, <0>, - <0>, - <0>, - <0>, - <0>; + <&gcc GCC_MMSS_GPLL0_DIV_CLK>; + }; + + mdss: display-subsystem@c900000 { + compatible = "qcom,msm8998-mdss"; + reg = <0x0c900000 0x1000>; + reg-names = "mdss"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "core"; + + power-domains = <&mmcc MDSS_GDSC>; + iommus = <&mmss_smmu 0>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@c901000 { + compatible = "qcom,msm8998-dpu"; + reg = <0x0c901000 0x8f000>, + <0x0c9a8e00 0xf0>, + <0x0c9b0000 0x2008>, + <0x0c9b8000 0x1040>; + reg-names = "mdp", + "regdma", + "vbif", + "vbif_nrt"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MNOC_AHB_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "mnoc", + "core", + "vsync"; + + assigned-clocks = <&mmcc MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd MSM8998_VDDMX>; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-171430000 { + opp-hz = /bits/ 64 <171430000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-330000000 { + opp-hz = /bits/ 64 <330000000>; + required-opps = <&rpmpd_opp_nom>; + }; + + opp-412500000 { + opp-hz = /bits/ 64 <412500000>; + required-opps = <&rpmpd_opp_turbo>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@c994000 { + compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0c994000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_BYTE0_INTF_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd MSM8998_VDDCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@c994400 { + compatible = "qcom,dsi-phy-10nm-8998"; + reg = <0x0c994400 0x200>, + <0x0c994600 0x280>, + <0x0c994a00 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dsi1: dsi@c996000 { + compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0c996000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&mmcc MDSS_BYTE1_CLK>, + <&mmcc MDSS_BYTE1_INTF_CLK>, + <&mmcc MDSS_PCLK1_CLK>, + <&mmcc MDSS_ESC1_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, + <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd MSM8998_VDDCX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@c996400 { + compatible = "qcom,dsi-phy-10nm-8998"; + reg = <0x0c996400 0x200>, + <0x0c996600 0x280>, + <0x0c996a00 0x10e>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; }; mmss_smmu: iommu@cd00000 { @@ -2737,10 +3020,10 @@ clocks = <&mmcc MNOC_AHB_CLK>, <&mmcc BIMC_SMMU_AHB_CLK>, - <&rpmcc RPM_SMD_MMAXI_CLK>, <&mmcc BIMC_SMMU_AXI_CLK>; - clock-names = "iface-mm", "iface-smmu", - "bus-mm", "bus-smmu"; + clock-names = "iface-mm", + "iface-smmu", + "bus-smmu"; #global-interrupts = <0>; interrupts = @@ -2764,6 +3047,8 @@ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + + power-domains = <&mmcc BIMC_SMMU_GDSC>; }; remoteproc_adsp: remoteproc@17300000 { diff --git a/arch/arm64/boot/dts/qcom/pm6125.dtsi b/arch/arm64/boot/dts/qcom/pm6125.dtsi index 59092a551a16..99369a0cdb61 100644 --- a/arch/arm64/boot/dts/qcom/pm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6125.dtsi @@ -85,36 +85,42 @@ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; #io-channel-cells = <1>; - ref-gnd@0 { + channel@0 { reg = <ADC5_REF_GND>; qcom,pre-scaling = <1 1>; + label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = <ADC5_1P25VREF>; qcom,pre-scaling = <1 1>; + label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = <ADC5_DIE_TEMP>; qcom,pre-scaling = <1 1>; + label = "die_temp"; }; - vph-pwr@83 { + channel@83 { reg = <ADC5_VPH_PWR>; qcom,pre-scaling = <1 3>; + label = "vph_pwr"; }; - vcoin@85 { + channel@85 { reg = <ADC5_VCOIN>; qcom,pre-scaling = <1 3>; + label = "vcoin"; }; - xo-therm@4c { + channel@4c { reg = <ADC5_XO_THERM_100K_PU>; qcom,pre-scaling = <1 1>; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "xo_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm6150.dtsi b/arch/arm64/boot/dts/qcom/pm6150.dtsi index 2e6afa296141..7d4d1f2767ed 100644 --- a/arch/arm64/boot/dts/qcom/pm6150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150.dtsi @@ -72,7 +72,7 @@ #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@6 { + channel@6 { reg = <ADC5_DIE_TEMP>; label = "die_temp"; }; diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index 6f7aa67501e2..d13a1ab7c20b 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -60,25 +60,25 @@ #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@0 { + channel@0 { reg = <ADC5_REF_GND>; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - adc-chan@1 { + channel@1 { reg = <ADC5_1P25VREF>; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - adc-chan@6 { + channel@6 { reg = <ADC5_DIE_TEMP>; qcom,pre-scaling = <1 1>; label = "die_temp"; }; - adc-chan@83 { + channel@83 { reg = <ADC5_VPH_PWR>; qcom,pre-scaling = <1 3>; label = "vph_pwr"; @@ -121,8 +121,9 @@ pm6150l_wled: leds@d800 { compatible = "qcom,pm6150l-wled"; reg = <0xd800>, <0xd900>; - interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ovp"; + interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x5 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp", "short"; label = "backlight"; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index 4bc717917f44..98dc04962fe3 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -91,82 +91,93 @@ #size-cells = <0>; #io-channel-cells = <1>; - ref_gnd: ref_gnd@0 { + channel@0 { reg = <ADC5_REF_GND>; qcom,decimation = <1024>; qcom,pre-scaling = <1 1>; + label = "ref_gnd"; }; - vref_1p25: vref_1p25@1 { + channel@1 { reg = <ADC5_1P25VREF>; qcom,decimation = <1024>; qcom,pre-scaling = <1 1>; + label = "vref_1p25"; }; - die_temp: die_temp@6 { + channel@6 { reg = <ADC5_DIE_TEMP>; qcom,decimation = <1024>; qcom,pre-scaling = <1 1>; + label = "die_temp"; }; - xo_therm: xo_therm@4c { + channel@4c { reg = <ADC5_XO_THERM_100K_PU>; qcom,pre-scaling = <1 1>; qcom,decimation = <1024>; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "xo_therm"; }; - msm_therm: msm_therm@4d { + channel@4d { reg = <ADC5_AMUX_THM1_100K_PU>; qcom,pre-scaling = <1 1>; qcom,decimation = <1024>; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "msm_therm"; }; - emmc_therm: emmc_therm@4e { + channel@4e { reg = <ADC5_AMUX_THM2_100K_PU>; qcom,pre-scaling = <1 1>; qcom,decimation = <1024>; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "emmc_therm"; }; - pa_therm0: thermistor0@4f { + channel@4f { reg = <ADC5_AMUX_THM3_100K_PU>; qcom,pre-scaling = <1 1>; qcom,decimation = <1024>; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "pa_therm0"; }; - pa_therm1: thermistor1@50 { + channel@50 { reg = <ADC5_AMUX_THM4_100K_PU>; qcom,pre-scaling = <1 1>; qcom,decimation = <1024>; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "pa_therm1"; }; - quiet_therm: quiet_therm@51 { + channel@51 { reg = <ADC5_AMUX_THM5_100K_PU>; qcom,pre-scaling = <1 1>; qcom,decimation = <1024>; qcom,hw-settle-time = <200>; qcom,ratiometric; + label = "quiet_therm"; }; - vadc_vph_pwr: vph_pwr@83 { + channel@83 { reg = <ADC5_VPH_PWR>; qcom,decimation = <1024>; qcom,pre-scaling = <1 3>; + label = "vph_pwr"; }; - vcoin: vcoin@85 { + channel@85 { reg = <ADC5_VCOIN>; qcom,decimation = <1024>; qcom,pre-scaling = <1 3>; + label = "vcoin"; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm660l.dtsi b/arch/arm64/boot/dts/qcom/pm660l.dtsi index 87b71b7205b8..6fdbf507c262 100644 --- a/arch/arm64/boot/dts/qcom/pm660l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660l.dtsi @@ -74,8 +74,9 @@ pm660l_wled: leds@d800 { compatible = "qcom,pm660l-wled"; reg = <0xd800>, <0xd900>; - interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ovp"; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp", "short"; label = "backlight"; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/qcom/pm7250b.dtsi index daa6f1d30efa..e8540c36bd99 100644 --- a/arch/arm64/boot/dts/qcom/pm7250b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm7250b.dtsi @@ -62,56 +62,56 @@ #io-channel-cells = <1>; interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - adc-chan@0 { + channel@0 { reg = <ADC5_REF_GND>; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - adc-chan@1 { + channel@1 { reg = <ADC5_1P25VREF>; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - adc-chan@2 { + channel@2 { reg = <ADC5_DIE_TEMP>; qcom,pre-scaling = <1 1>; label = "die_temp"; }; - adc-chan@7 { + channel@7 { reg = <ADC5_USB_IN_I>; qcom,pre-scaling = <1 1>; label = "usb_in_i_uv"; }; - adc-chan@8 { + channel@8 { reg = <ADC5_USB_IN_V_16>; qcom,pre-scaling = <1 16>; label = "usb_in_v_div_16"; }; - adc-chan@9 { + channel@9 { reg = <ADC5_CHG_TEMP>; qcom,pre-scaling = <1 1>; label = "chg_temp"; }; - adc-chan@e { + channel@e { reg = <ADC5_AMUX_THM2>; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; label = "smb1390_therm"; }; - adc-chan@1e { + channel@1e { reg = <ADC5_MID_CHG_DIV6>; qcom,pre-scaling = <1 6>; label = "chg_mid"; }; - adc-chan@4b { + channel@4b { reg = <ADC5_BAT_ID_100K_PU>; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; @@ -119,19 +119,19 @@ label = "bat_id"; }; - adc-chan@83 { + channel@83 { reg = <ADC5_VPH_PWR>; qcom,pre-scaling = <1 3>; label = "vph_pwr"; }; - adc-chan@84 { + channel@84 { reg = <ADC5_VBAT_SNS>; qcom,pre-scaling = <1 3>; label = "vbat_sns"; }; - adc-chan@99 { + channel@99 { reg = <ADC5_SBUx>; qcom,pre-scaling = <1 3>; label = "chg_sbux"; @@ -147,6 +147,16 @@ #size-cells = <0>; status = "disabled"; }; + + pm7250b_gpios: pinctrl@c000 { + compatible = "qcom,pm7250b-gpio", "qcom,spmi-gpio"; + reg = <0xc000>; + gpio-controller; + gpio-ranges = <&pm7250b_gpios 0 0 12>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; }; pmic@3 { diff --git a/arch/arm64/boot/dts/qcom/pm7550ba.dtsi b/arch/arm64/boot/dts/qcom/pm7550ba.dtsi new file mode 100644 index 000000000000..8b00ece987d1 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm7550ba.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pm7550ba-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm7550ba_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pm7550ba: pmic@7 { + compatible = "qcom,pm7550ba", "qcom,spmi-pmic"; + reg = <7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm7550ba_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm7550ba_gpios: gpio@8800 { + compatible = "qcom,pm7550ba-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm7550ba_gpios 0 0 8>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pm7550ba_eusb2_repeater: phy@fd00 { + compatible = "qcom,pm7550ba-eusb2-repeater", "qcom,pm8550b-eusb2-repeater"; + reg = <0xfd00>; + #phy-cells = <0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index db90c55fa2cf..3ba3ba5d8fce 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -90,19 +90,19 @@ #io-channel-cells = <1>; interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = <ADC5_REF_GND>; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = <ADC5_1P25VREF>; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = <ADC5_DIE_TEMP>; qcom,pre-scaling = <1 1>; label = "die_temp"; diff --git a/arch/arm64/boot/dts/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/qcom/pm8150b.dtsi index 66752cc063d6..2b9123df5847 100644 --- a/arch/arm64/boot/dts/qcom/pm8150b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150b.dtsi @@ -76,25 +76,25 @@ #io-channel-cells = <1>; interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = <ADC5_REF_GND>; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = <ADC5_1P25VREF>; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = <ADC5_DIE_TEMP>; qcom,pre-scaling = <1 1>; label = "die_temp"; }; - chg-temp@9 { + channel@9 { reg = <ADC5_CHG_TEMP>; qcom,pre-scaling = <1 1>; label = "chg_temp"; diff --git a/arch/arm64/boot/dts/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/qcom/pm8150l.dtsi index cca45fad75ac..b1686e5777b8 100644 --- a/arch/arm64/boot/dts/qcom/pm8150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150l.dtsi @@ -70,19 +70,19 @@ #io-channel-cells = <1>; interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = <ADC5_REF_GND>; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = <ADC5_1P25VREF>; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = <ADC5_DIE_TEMP>; qcom,pre-scaling = <1 1>; label = "die_temp"; diff --git a/arch/arm64/boot/dts/qcom/pm8350.dtsi b/arch/arm64/boot/dts/qcom/pm8350.dtsi index 2dfeb99300d7..9ed9ba23e81e 100644 --- a/arch/arm64/boot/dts/qcom/pm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350.dtsi @@ -8,7 +8,7 @@ / { thermal-zones { - pm8350_thermal: pm8350c-thermal { + pm8350_thermal: pm8350-thermal { polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&pm8350_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pm8350b.dtsi b/arch/arm64/boot/dts/qcom/pm8350b.dtsi index f1c7bd9d079c..05c105898892 100644 --- a/arch/arm64/boot/dts/qcom/pm8350b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350b.dtsi @@ -8,7 +8,7 @@ / { thermal-zones { - pm8350b_thermal: pm8350c-thermal { + pm8350b_thermal: pm8350b-thermal { polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&pm8350b_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 1ea8920ff369..223442f909f1 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -66,27 +66,27 @@ #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@0 { + channel@0 { reg = <VADC_USBIN>; qcom,pre-scaling = <1 10>; }; - adc-chan@7 { + channel@7 { reg = <VADC_VSYS>; qcom,pre-scaling = <1 3>; }; - adc-chan@8 { + channel@8 { reg = <VADC_DIE_TEMP>; }; - adc-chan@9 { + channel@9 { reg = <VADC_REF_625MV>; }; - adc-chan@a { + channel@a { reg = <VADC_REF_1250MV>; }; - adc-chan@e { + channel@e { reg = <VADC_GND_REF>; }; - adc-chan@f { + channel@f { reg = <VADC_VDD_VADC>; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8950.dtsi b/arch/arm64/boot/dts/qcom/pm8950.dtsi index 5ec38b7e335a..f03095779de0 100644 --- a/arch/arm64/boot/dts/qcom/pm8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8950.dtsi @@ -50,77 +50,90 @@ #size-cells = <0>; #io-channel-cells = <1>; - vcoin@5 { + channel@5 { reg = <VADC_VCOIN>; qcom,pre-scaling = <1 1>; + label = "vcoin"; }; - vph-pwr@7 { + channel@7 { reg = <VADC_VSYS>; qcom,pre-scaling = <1 1>; + label = "vph_pwr"; }; - die-temp@8 { + channel@8 { reg = <VADC_DIE_TEMP>; qcom,pre-scaling = <1 1>; + label = "die_temp"; }; - ref-625mv@9 { + channel@9 { reg = <VADC_REF_625MV>; qcom,pre-scaling = <1 1>; + label = "ref_625mv"; }; - ref-1250mv@a { + channel@a { reg = <VADC_REF_1250MV>; qcom,pre-scaling = <1 1>; + label = "ref_1250mv"; }; - ref-buf-625mv@c { + channel@c { reg = <VADC_SPARE1>; qcom,pre-scaling = <1 1>; + label = "ref_buf_625mv"; }; - ref-gnd@e { + channel@e { reg = <VADC_GND_REF>; + label = "ref_gnd"; }; - ref-vdd@f { + channel@f { reg = <VADC_VDD_VADC>; + label = "ref_vdd"; }; - pa-therm1@11 { + channel@11 { reg = <VADC_P_MUX2_1_1>; qcom,pre-scaling = <1 1>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "pa_therm1"; }; - case-therm@13 { + channel@13 { reg = <VADC_P_MUX4_1_1>; qcom,pre-scaling = <1 1>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "case_therm"; }; - xo-therm@32 { + channel@32 { reg = <VADC_LR_MUX3_XO_THERM>; qcom,pre-scaling = <1 1>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "xo_therm"; }; - pa-therm0@36 { + channel@36 { reg = <VADC_LR_MUX7_HW_ID>; qcom,pre-scaling = <1 1>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "pa_therm0"; }; - xo-therm-buf@3c { + channel@3c { reg = <VADC_LR_MUX3_BUF_XO_THERM>; qcom,pre-scaling = <1 1>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "xo_therm_buf"; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8953.dtsi b/arch/arm64/boot/dts/qcom/pm8953.dtsi index 2268daf27fa7..1067e141be6c 100644 --- a/arch/arm64/boot/dts/qcom/pm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8953.dtsi @@ -6,6 +6,37 @@ #include <dt-bindings/input/linux-event-codes.h> #include <dt-bindings/spmi/spmi.h> +/ { + thermal-zones { + pm8953-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&pm8953_temp>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pmic@0 { compatible = "qcom,pm8953", "qcom,spmi-pmic"; @@ -36,7 +67,7 @@ }; }; - temp-alarm@2400 { + pm8953_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>; @@ -53,22 +84,22 @@ #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@8 { + channel@8 { reg = <VADC_DIE_TEMP>; }; - adc-chan@9 { + channel@9 { reg = <VADC_REF_625MV>; }; - adc-chan@a { + channel@a { reg = <VADC_REF_1250MV>; }; - adc-chan@c { + channel@c { reg = <VADC_SPARE1>; }; - adc-chan@e { + channel@e { reg = <VADC_GND_REF>; }; - adc-chan@f { + channel@f { reg = <VADC_VDD_VADC>; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8994.dtsi b/arch/arm64/boot/dts/qcom/pm8994.dtsi index 672094c8ca58..d44a95caf04a 100644 --- a/arch/arm64/boot/dts/qcom/pm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8994.dtsi @@ -83,27 +83,27 @@ #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@7 { + channel@7 { reg = <VADC_VSYS>; qcom,pre-scaling = <1 3>; label = "vph_pwr"; }; - adc-chan@8 { + channel@8 { reg = <VADC_DIE_TEMP>; label = "die_temp"; }; - adc-chan@9 { + channel@9 { reg = <VADC_REF_625MV>; label = "ref_625mv"; }; - adc-chan@a { + channel@a { reg = <VADC_REF_1250MV>; label = "ref_1250mv"; }; - adc-chan@e { + channel@e { reg = <VADC_GND_REF>; }; - adc-chan@f { + channel@f { reg = <VADC_VDD_VADC>; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8998.dtsi b/arch/arm64/boot/dts/qcom/pm8998.dtsi index 695d79116cde..3f82715392c6 100644 --- a/arch/arm64/boot/dts/qcom/pm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8998.dtsi @@ -86,7 +86,7 @@ #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@6 { + channel@6 { reg = <ADC5_DIE_TEMP>; label = "die_temp"; }; diff --git a/arch/arm64/boot/dts/qcom/pmi8950.dtsi b/arch/arm64/boot/dts/qcom/pmi8950.dtsi index 4891be3cd68a..1029f3b1bb9a 100644 --- a/arch/arm64/boot/dts/qcom/pmi8950.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8950.dtsi @@ -20,37 +20,37 @@ #size-cells = <0>; #io-channel-cells = <1>; - adc-chan@0 { + channel@0 { reg = <VADC_USBIN>; qcom,pre-scaling = <1 4>; label = "usbin"; }; - adc-chan@1 { + channel@1 { reg = <VADC_DCIN>; qcom,pre-scaling = <1 4>; label = "dcin"; }; - adc-chan@2 { + channel@2 { reg = <VADC_VCHG_SNS>; qcom,pre-scaling = <1 1>; label = "vchg_sns"; }; - adc-chan@9 { + channel@9 { reg = <VADC_REF_625MV>; qcom,pre-scaling = <1 1>; label = "ref_625mv"; }; - adc-chan@a { + channel@a { reg = <VADC_REF_1250MV>; qcom,pre-scaling = <1 1>; label = "ref_1250mv"; }; - adc-chan@d { + channel@d { reg = <VADC_SPARE2>; qcom,pre-scaling = <1 1>; label = "chg_temp"; @@ -87,8 +87,9 @@ pmi8950_wled: leds@d800 { compatible = "qcom,pmi8950-wled"; reg = <0xd800>, <0xd900>; - interrupts = <0x3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "short"; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp", "short"; label = "backlight"; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/pmi8994.dtsi b/arch/arm64/boot/dts/qcom/pmi8994.dtsi index 0192968f4d9b..36d6a1fb553a 100644 --- a/arch/arm64/boot/dts/qcom/pmi8994.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8994.dtsi @@ -54,8 +54,9 @@ pmi8994_wled: wled@d800 { compatible = "qcom,pmi8994-wled"; reg = <0xd800>, <0xd900>; - interrupts = <3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "short"; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp", "short"; qcom,cabc; qcom,external-pfet; status = "disabled"; diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index bc6297e7253e..1eb74017062d 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -59,7 +59,7 @@ }; pmk8350_adc_tm: adc-tm@3400 { - compatible = "qcom,adc-tm7"; + compatible = "qcom,spmi-adc-tm5-gen2"; reg = <0x3400>; interrupts = <PMK8350_SID 0x34 0x0 IRQ_TYPE_EDGE_RISING>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi index ee1e428d3a6e..dbd4b91dfe06 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_1.dtsi @@ -77,19 +77,19 @@ #io-channel-cells = <1>; interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = <ADC5_REF_GND>; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = <ADC5_1P25VREF>; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = <ADC5_DIE_TEMP>; qcom,pre-scaling = <1 1>; label = "die_temp"; diff --git a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi index 1da4606e8ee6..1cee20ac2c9c 100644 --- a/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi +++ b/arch/arm64/boot/dts/qcom/pmm8155au_2.dtsi @@ -69,19 +69,19 @@ #io-channel-cells = <1>; interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = <ADC5_REF_GND>; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = <ADC5_1P25VREF>; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = <ADC5_DIE_TEMP>; qcom,pre-scaling = <1 1>; label = "die_temp"; diff --git a/arch/arm64/boot/dts/qcom/pmp8074.dtsi b/arch/arm64/boot/dts/qcom/pmp8074.dtsi index 580684411d74..0d0a846ac8d9 100644 --- a/arch/arm64/boot/dts/qcom/pmp8074.dtsi +++ b/arch/arm64/boot/dts/qcom/pmp8074.dtsi @@ -18,57 +18,66 @@ #size-cells = <0>; #io-channel-cells = <1>; - ref-gnd@0 { + channel@0 { reg = <ADC5_REF_GND>; qcom,pre-scaling = <1 1>; + label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = <ADC5_1P25VREF>; qcom,pre-scaling = <1 1>; + label = "vref_1p25"; }; - vref-vadc@2 { + channel@2 { reg = <ADC5_VREF_VADC>; qcom,pre-scaling = <1 1>; + label = "vref_vadc"; }; - pmic_die: die-temp@6 { + channel@6 { reg = <ADC5_DIE_TEMP>; qcom,pre-scaling = <1 1>; + label = "pmic_die"; }; - xo_therm: xo-temp@76 { + channel@76 { reg = <ADC5_XO_THERM_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "xo_therm"; }; - pa_therm1: thermistor1@77 { + channel@77 { reg = <ADC5_AMUX_THM1_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "pa_therm1"; }; - pa_therm2: thermistor2@78 { + channel@78 { reg = <ADC5_AMUX_THM2_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "pa_therm2"; }; - pa_therm3: thermistor3@79 { + channel@79 { reg = <ADC5_AMUX_THM3_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "pa_therm3"; }; - vph-pwr@131 { + channel@131 { reg = <ADC5_VPH_PWR>; qcom,pre-scaling = <1 3>; + label = "vph_pwr"; }; }; diff --git a/arch/arm64/boot/dts/qcom/pmr735b.dtsi b/arch/arm64/boot/dts/qcom/pmr735b.dtsi index ec24c4478005..f7473e247322 100644 --- a/arch/arm64/boot/dts/qcom/pmr735b.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735b.dtsi @@ -8,7 +8,7 @@ / { thermal-zones { - pmr735a_thermal: pmr735a-thermal { + pmr735b_thermal: pmr735b-thermal { polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&pmr735b_temp_alarm>; diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi index 22edb47c6a84..461ad97032f7 100644 --- a/arch/arm64/boot/dts/qcom/pms405.dtsi +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi @@ -81,45 +81,52 @@ #size-cells = <0>; #io-channel-cells = <1>; - ref_gnd@0 { + channel@0 { reg = <ADC5_REF_GND>; qcom,pre-scaling = <1 1>; + label = "ref_gnd"; }; - vref_1p25@1 { + channel@1 { reg = <ADC5_1P25VREF>; qcom,pre-scaling = <1 1>; + label = "vref_1p25"; }; - pon_1: vph_pwr@131 { + channel@131 { reg = <ADC5_VPH_PWR>; qcom,pre-scaling = <1 3>; + label = "vph_pwr"; }; - die_temp@6 { + channel@6 { reg = <ADC5_DIE_TEMP>; qcom,pre-scaling = <1 1>; + label = "die_temp"; }; - pa_therm1: thermistor1@77 { + channel@77 { reg = <ADC5_AMUX_THM1_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "pa_therm1"; }; - pa_therm3: thermistor3@79 { + channel@79 { reg = <ADC5_AMUX_THM3_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "pa_therm3"; }; - xo_therm: xo_temp@76 { + channel@76 { reg = <ADC5_XO_THERM_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "xo_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/pmx75.dtsi b/arch/arm64/boot/dts/qcom/pmx75.dtsi new file mode 100644 index 000000000000..373e45f63dff --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmx75.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + thermal-zones { + pmx75-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pmx75_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + + trip2 { + temperature = <145000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&spmi_bus { + pmx75: pmic@1 { + compatible = "qcom,pmx75", "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmx75_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pmx75_gpios: gpio@8800 { + compatible = "qcom,pmx75-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pmx75_gpios 0 0 16>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi index 0ed11e80e5e2..d46e591e72b5 100644 --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi @@ -198,6 +198,71 @@ }; }; + rpm: remoteproc { + compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-qcm2290"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,qcm2290-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level = <RPM_SMD_LEVEL_MIN_SVS>; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level = <RPM_SMD_LEVEL_LOW_SVS>; + }; + + rpmpd_opp_svs: opp3 { + opp-level = <RPM_SMD_LEVEL_SVS>; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; + }; + + rpmpd_opp_nom: opp5 { + opp-level = <RPM_SMD_LEVEL_NOM>; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; + }; + + rpmpd_opp_turbo: opp7 { + opp-level = <RPM_SMD_LEVEL_TURBO>; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; + }; + }; + }; + }; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -288,67 +353,6 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-qcm2290"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; - clocks = <&xo_board>; - clock-names = "xo"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,qcm2290-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_min_svs: opp1 { - opp-level = <RPM_SMD_LEVEL_MIN_SVS>; - }; - - rpmpd_opp_low_svs: opp2 { - opp-level = <RPM_SMD_LEVEL_LOW_SVS>; - }; - - rpmpd_opp_svs: opp3 { - opp-level = <RPM_SMD_LEVEL_SVS>; - }; - - rpmpd_opp_svs_plus: opp4 { - opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; - }; - - rpmpd_opp_nom: opp5 { - opp-level = <RPM_SMD_LEVEL_NOM>; - }; - - rpmpd_opp_nom_plus: opp6 { - opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; - }; - - rpmpd_opp_turbo: opp7 { - opp-level = <RPM_SMD_LEVEL_TURBO>; - }; - - rpmpd_opp_turbo_plus: opp8 { - opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; - }; - }; - }; - }; - }; - smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; @@ -638,6 +642,32 @@ status = "disabled"; }; + usb_qmpphy: phy@1615000 { + compatible = "qcom,qcm2290-qmp-usb3-phy"; + reg = <0x0 0x01615000 0x0 0x1000>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "cfg_ahb", + "ref", + "com_aux", + "pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; + reset-names = "phy", + "phy_phy"; + + #clock-cells = <0>; + clock-output-names = "usb3_phy_pipe_clk_src"; + + #phy-cells = <0>; + + status = "disabled"; + }; + qfprom@1b44000 { compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; reg = <0x0 0x01b44000 0x0 0x3000>; @@ -790,7 +820,7 @@ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; - dma-channels = <10>; + dma-channels = <10>; dma-channel-mask = <0x1f>; iommus = <&apps_smmu 0xf6 0x0>; #dma-cells = <3>; @@ -1062,8 +1092,8 @@ compatible = "snps,dwc3"; reg = <0x0 0x04e00000 0x0 0xcd00>; interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; - phys = <&usb_hsphy>; - phy-names = "usb2-phy"; + phys = <&usb_hsphy>, <&usb_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; iommus = <&apps_smmu 0x120 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 972f753847e1..2721f32dfb71 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -166,6 +166,84 @@ method = "smc"; }; + rpm: remoteproc { + compatible = "qcom,qcs404-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-qcs404"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + + rpmpd: power-controller { + compatible = "qcom,qcs404-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <16>; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = <32>; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = <48>; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = <64>; + }; + + rpmpd_opp_svs: opp5 { + opp-level = <128>; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = <192>; + }; + + rpmpd_opp_nom: opp7 { + opp-level = <256>; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = <320>; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = <384>; + }; + + rpmpd_opp_turbo_no_cpr: opp10 { + opp-level = <416>; + }; + + rpmpd_opp_turbo_plus: opp11 { + opp-level = <512>; + }; + }; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -217,80 +295,6 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-qcs404"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; - #clock-cells = <1>; - clocks = <&xo_board>; - clock-names = "xo"; - }; - - rpmpd: power-controller { - compatible = "qcom,qcs404-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <16>; - }; - - rpmpd_opp_ret_plus: opp2 { - opp-level = <32>; - }; - - rpmpd_opp_min_svs: opp3 { - opp-level = <48>; - }; - - rpmpd_opp_low_svs: opp4 { - opp-level = <64>; - }; - - rpmpd_opp_svs: opp5 { - opp-level = <128>; - }; - - rpmpd_opp_svs_plus: opp6 { - opp-level = <192>; - }; - - rpmpd_opp_nom: opp7 { - opp-level = <256>; - }; - - rpmpd_opp_nom_plus: opp8 { - opp-level = <320>; - }; - - rpmpd_opp_turbo: opp9 { - opp-level = <384>; - }; - - rpmpd_opp_turbo_no_cpr: opp10 { - opp-level = <416>; - }; - - rpmpd_opp_turbo_plus: opp11 { - opp-level = <512>; - }; - }; - }; - }; - }; - smem { compatible = "qcom,smem"; @@ -1459,10 +1463,10 @@ pcie: pci@10000000 { compatible = "qcom,pcie-qcs404"; - reg = <0x10000000 0xf1d>, - <0x10000f20 0xa8>, - <0x07780000 0x2000>, - <0x10001000 0x2000>; + reg = <0x10000000 0xf1d>, + <0x10000f20 0xa8>, + <0x07780000 0x2000>, + <0x10001000 0x2000>; reg-names = "dbi", "elbi", "parf", "config"; device_type = "pci"; linux,pci-domain = <0>; diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts index 1d22f87fd238..5a25cdec969e 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts @@ -448,6 +448,28 @@ status = "okay"; }; +&reserved_memory { + ecc_meta_data_mem: ecc-meta-data@e0000000 { + reg = <0x0 0xe0000000 0x0 0x20000000>; + no-map; + }; + + harq_buffer_mem: harq-buffer@800000000 { + reg = <0x8 0x0 0x0 0x80000000>; + no-map; + }; + + tenx_sp_buffer_mem: tenx-sp-buffer@880000000 { + reg = <0x8 0x80000000 0x0 0x50000000>; + no-map; + }; + + fapi_buffer_mem: fapi-buffer@8d0000000 { + reg = <0x8 0xd0000000 0x0 0x20000000>; + no-map; + }; +}; + &sdhc { pinctrl-0 = <&sdc_on_state>; pinctrl-1 = <&sdc_off_state>; @@ -471,6 +493,10 @@ status = "okay"; }; +&tlmm { + gpio-reserved-ranges = <28 2>; +}; + &uart7 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts index ef3616093289..eadba066972e 100644 --- a/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts +++ b/arch/arm64/boot/dts/qcom/qrb2210-rb1.dts @@ -38,6 +38,91 @@ wakeup-source; }; }; + + vreg_hdmi_out_1p2: regulator-hdmi-out-1p2 { + compatible = "regulator-fixed"; + regulator-name = "VREG_HDMI_OUT_1P2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vdc_1v2>; + regulator-always-on; + regulator-boot-on; + }; + + lt9611_3v3: regulator-lt9611-3v3 { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdc_3v3>; + regulator-always-on; + regulator-boot-on; + }; + + /* Main barrel jack input */ + vdc_12v: regulator-vdc-12v { + compatible = "regulator-fixed"; + regulator-name = "DC_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* 1.2V supply stepped down from the barrel jack input */ + vdc_1v2: regulator-vdc-1v2 { + compatible = "regulator-fixed"; + regulator-name = "VDC_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vdc_12v>; + regulator-always-on; + regulator-boot-on; + }; + + /* 3.3V supply stepped down from the barrel jack input */ + vdc_3v3: regulator-vdc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdc_12v>; + regulator-always-on; + regulator-boot-on; + }; + + /* 5V supply stepped down from the barrel jack input */ + vdc_5v: regulator-vdc-5v { + compatible = "regulator-fixed"; + regulator-name = "VDC_5V"; + + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* "Battery" voltage for the SoM, stepped down from the barrel jack input */ + vdc_vbat_som: regulator-vdc-vbat { + compatible = "regulator-fixed"; + regulator-name = "VBAT_SOM"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + regulator-always-on; + regulator-boot-on; + }; + + /* PM2250 charger out, supplied by VBAT */ + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + vin-supply = <&vdc_vbat_som>; + + regulator-always-on; + regulator-boot-on; + }; }; &pm2250_resin { @@ -49,7 +134,183 @@ status = "okay"; }; +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm2250-regulators"; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_l1_l2_l3_l5_l6_l7_l8_l9_l10_l11_l12-supply = <&pm2250_s3>; + vdd_l4_l17_l18_l19_l20_l21_l22-supply = <&vph_pwr>; + vdd_l13_l14_l15_l16-supply = <&pm2250_s4>; + + /* + * S1 - VDD_APC + * S2 - VDD_CX + */ + + pm2250_s3: s3 { + /* 0.4V-1.6625V -> 1.3V (Power tree requirements) */ + regulator-min-microvolts = <1350000>; + regulator-max-microvolts = <1350000>; + regulator-boot-on; + }; + + pm2250_s4: s4 { + /* 1.2V-2.35V -> 2.05V (Power tree requirements) */ + regulator-min-microvolts = <2072000>; + regulator-max-microvolts = <2072000>; + regulator-boot-on; + }; + + /* L1 - VDD_MX */ + + pm2250_l2: l2 { + /* LPDDR4X VDD2 */ + regulator-min-microvolts = <1136000>; + regulator-max-microvolts = <1136000>; + regulator-always-on; + regulator-boot-on; + }; + + pm2250_l3: l3 { + /* LPDDR4X VDDQ */ + regulator-min-microvolts = <616000>; + regulator-max-microvolts = <616000>; + regulator-always-on; + regulator-boot-on; + }; + + pm2250_l4: l4 { + /* max = 3.05V -> max = just below 3V (SDHCI2) */ + regulator-min-microvolts = <1648000>; + regulator-max-microvolts = <2992000>; + regulator-allow-set-load; + }; + + pm2250_l5: l5 { + /* CSI/DSI */ + regulator-min-microvolts = <1232000>; + regulator-max-microvolts = <1232000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm2250_l6: l6 { + /* DRAM PLL */ + regulator-min-microvolts = <928000>; + regulator-max-microvolts = <928000>; + regulator-always-on; + regulator-boot-on; + }; + + pm2250_l7: l7 { + /* Wi-Fi CX/MX */ + regulator-min-microvolts = <664000>; + regulator-max-microvolts = <664000>; + }; + + /* + * L8 - VDD_LPI_CX + * L9 - VDD_LPI_MX + */ + + pm2250_l10: l10 { + /* Wi-Fi RFA */ + regulator-min-microvolts = <1300000>; + regulator-max-microvolts = <1300000>; + }; + + pm2250_l11: l11 { + /* GPS RF1 */ + regulator-min-microvolts = <1000000>; + regulator-max-microvolts = <1000000>; + regulator-boot-on; + }; + + pm2250_l12: l12 { + /* USB PHYs */ + regulator-min-microvolts = <928000>; + regulator-max-microvolts = <928000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm2250_l13: l13 { + /* USB/QFPROM/PLLs */ + regulator-min-microvolts = <1800000>; + regulator-max-microvolts = <1800000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm2250_l14: l14 { + /* SDHCI1 VQMMC */ + regulator-min-microvolts = <1800000>; + regulator-max-microvolts = <1800000>; + regulator-allow-set-load; + /* Broken hardware, never turn it off! */ + regulator-always-on; + }; + + pm2250_l15: l15 { + /* WCD/DSI/BT VDDIO */ + regulator-min-microvolts = <1800000>; + regulator-max-microvolts = <1800000>; + regulator-allow-set-load; + regulator-always-on; + regulator-boot-on; + }; + + pm2250_l16: l16 { + /* GPS RF2 */ + regulator-min-microvolts = <1800000>; + regulator-max-microvolts = <1800000>; + regulator-boot-on; + }; + + pm2250_l17: l17 { + regulator-min-microvolts = <3000000>; + regulator-max-microvolts = <3000000>; + }; + + pm2250_l18: l18 { + /* VDD_PXn */ + regulator-min-microvolts = <1800000>; + regulator-max-microvolts = <1800000>; + }; + + pm2250_l19: l19 { + /* VDD_PXn */ + regulator-min-microvolts = <1800000>; + regulator-max-microvolts = <1800000>; + }; + + pm2250_l20: l20 { + /* SDHCI1 VMMC */ + regulator-min-microvolts = <2856000>; + regulator-max-microvolts = <2856000>; + regulator-allow-set-load; + }; + + pm2250_l21: l21 { + /* SDHCI2 VMMC */ + regulator-min-microvolts = <2960000>; + regulator-max-microvolts = <3300000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm2250_l22: l22 { + /* Wi-Fi */ + regulator-min-microvolts = <3312000>; + regulator-max-microvolts = <3312000>; + }; + }; +}; + &sdhc_1 { + vmmc-supply = <&pm2250_l20>; + vqmmc-supply = <&pm2250_l14>; pinctrl-0 = <&sdc1_state_on>; pinctrl-1 = <&sdc1_state_off>; pinctrl-names = "default", "sleep"; @@ -61,6 +322,8 @@ }; &sdhc_2 { + vmmc-supply = <&pm2250_l21>; + vqmmc-supply = <&pm2250_l4>; cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; pinctrl-0 = <&sdc2_state_on &sd_det_in_on>; pinctrl-1 = <&sdc2_state_off &sd_det_in_off>; @@ -104,6 +367,9 @@ }; &usb_hsphy { + vdd-supply = <&pm2250_l12>; + vdda-pll-supply = <&pm2250_l13>; + vdda-phy-dpdm-supply = <&pm2250_l21>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts index e23a0406eacc..a7278a9472ed 100644 --- a/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts +++ b/arch/arm64/boot/dts/qcom/qrb4210-rb2.dts @@ -179,6 +179,14 @@ status = "okay"; }; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/qrb4210/a610_zap.mbn"; + }; +}; + &i2c2 { clock-frequency = <400000>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index a9e7b832c18c..dfa8ee5c75af 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -640,16 +640,18 @@ }; &pm8150_adc { - xo-therm@4c { + channel@4c { reg = <ADC5_XO_THERM_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "xo_therm"; }; - wifi-therm@4e { + channel@4e { reg = <ADC5_AMUX_THM2_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "wifi_therm"; }; }; @@ -717,10 +719,11 @@ }; &pm8150b_adc { - conn-therm@4f { + channel@4f { reg = <ADC5_AMUX_THM3_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "conn_therm"; }; }; @@ -752,16 +755,18 @@ }; &pm8150l_adc { - skin-msm-therm@4e { + channel@4e { reg = <ADC5_AMUX_THM2_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "skin_msm_therm"; }; - pm8150l-therm@4f { + channel@4f { reg = <ADC5_AMUX_THM3_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "pm8150l_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts index 2cc893ae4d10..2a862c83309e 100644 --- a/arch/arm64/boot/dts/qcom/qru1000-idp.dts +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts @@ -448,6 +448,22 @@ status = "okay"; }; +&reserved_memory { + ecc_meta_data_mem: ecc-meta-data@f0000000 { + reg = <0x0 0xf0000000 0x0 0x10000000>; + no-map; + }; + + tenx_sp_mem: tenx-sp-buffer@800000000 { + reg = <0x8 0x0 0x0 0x80000000>; + no-map; + }; +}; + +&tlmm { + gpio-reserved-ranges = <28 2>; +}; + &uart7 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi b/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi index 1221be89b3de..a1fbb477fafe 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p-pmics.dtsi @@ -14,7 +14,7 @@ #address-cells = <1>; #size-cells = <0>; - rtc@6000 { + pmm8540a_rtc: rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>, <0x6100>; reg-names = "rtc", "alarm"; @@ -39,6 +39,15 @@ #address-cells = <1>; #size-cells = <0>; + pmm8540c_sdam_2: nvram@b110 { + compatible = "qcom,spmi-sdam"; + reg = <0xb110>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xb110 0xb0>; + status = "disabled"; + }; + pmm8540c_gpios: gpio@c000 { compatible = "qcom,pm8150-gpio", "qcom,spmi-gpio"; reg = <0xc000>; diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 5a26974dcf8f..b04f72ec097c 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -407,6 +407,21 @@ status = "okay"; }; +&pmm8540a_rtc { + nvmem-cells = <&rtc_offset>; + nvmem-cell-names = "offset"; + + status = "okay"; +}; + +&pmm8540c_sdam_2 { + status = "okay"; + + rtc_offset: rtc-offset@a0 { + reg = <0xa0 0x4>; + }; +}; + &qup0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi index bacbdec56281..96b2c59ad02b 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi @@ -207,7 +207,7 @@ linux,pci-domain = <2>; - interrupts = <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "msi"; interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 26f5a4e0ffed..81a7eeb9cfcd 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -16,11 +16,13 @@ compatible = "qcom,sa8775p-ride", "qcom,sa8775p"; aliases { + ethernet0 = ðernet0; + ethernet1 = ðernet1; + i2c11 = &i2c11; + i2c18 = &i2c18; serial0 = &uart10; serial1 = &uart12; serial2 = &uart17; - i2c11 = &i2c11; - i2c18 = &i2c18; spi16 = &spi16; ufshc1 = &ufs_mem_hc; }; @@ -261,6 +263,173 @@ }; }; +ðernet0 { + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy0>; + + pinctrl-0 = <ðernet0_default>; + pinctrl-names = "default"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + snps,ps-speed = <1000>; + + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy0: phy@8 { + compatible = "ethernet-phy-id0141.0dd4"; + reg = <0x8>; + device_type = "ethernet-phy"; + reset-gpios = <&pmm8654au_2_gpios 8 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + + sgmii_phy1: phy@a { + compatible = "ethernet-phy-id0141.0dd4"; + reg = <0xa>; + device_type = "ethernet-phy"; + reset-gpios = <&pmm8654au_2_gpios 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + +ðernet1 { + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy1>; + + snps,mtl-rx-config = <&mtl_rx_setup1>; + snps,mtl-tx-config = <&mtl_tx_setup1>; + snps,ps-speed = <1000>; + + status = "okay"; + + mtl_rx_setup1: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xc>; + }; + }; + + mtl_tx_setup1: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + }; + + queue1 { + snps,dcb-algorithm; + }; + + queue2 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + + queue3 { + snps,avb-algorithm; + snps,send_slope = <0x1000>; + snps,idle_slope = <0x1000>; + snps,high_credit = <0x3e800>; + snps,low_credit = <0xffc18000>; + }; + }; +}; + &i2c11 { clock-frequency = <400000>; pinctrl-0 = <&qup_i2c11_default>; @@ -355,6 +524,16 @@ status = "okay"; }; +&serdes0 { + phy-supply = <&vreg_l5a>; + status = "okay"; +}; + +&serdes1 { + phy-supply = <&vreg_l5a>; + status = "okay"; +}; + &sleep_clk { clock-frequency = <32764>; }; @@ -366,6 +545,22 @@ }; &tlmm { + ethernet0_default: ethernet0-default-state { + ethernet0_mdc: ethernet0-mdc-pins { + pins = "gpio8"; + function = "emac0_mdc"; + drive-strength = <16>; + bias-pull-up; + }; + + ethernet0_mdio: ethernet0-mdio-pins { + pins = "gpio9"; + function = "emac0_mdio"; + drive-strength = <16>; + bias-pull-up; + }; + }; + qup_uart10_default: qup-uart10-state { pins = "gpio46", "gpio47"; function = "qup1_se3"; @@ -443,6 +638,86 @@ bias-pull-down; }; }; + + pcie0_default_state: pcie0-default-state { + perst-pins { + pins = "gpio2"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins = "gpio4"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio3"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&pcie0 { + perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; }; &uart10 { diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index b130136acffe..9f4f58e831a4 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -481,8 +481,8 @@ <0>, <0>, <0>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, <0>, <0>, <0>; @@ -1837,6 +1837,24 @@ <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; }; + serdes0: phy@8901000 { + compatible = "qcom,sa8775p-dwmac-sgmii-phy"; + reg = <0x0 0x08901000 0x0 0xe10>; + clocks = <&gcc GCC_SGMI_CLKREF_EN>; + clock-names = "sgmi_ref"; + #phy-cells = <0>; + status = "disabled"; + }; + + serdes1: phy@8902000 { + compatible = "qcom,sa8775p-dwmac-sgmii-phy"; + reg = <0x0 0x08902000 0x0 0xe10>; + clocks = <&gcc GCC_SGMI_CLKREF_EN>; + clock-names = "sgmi_ref"; + #phy-cells = <0>; + status = "disabled"; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sa8775p-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x30000>, @@ -1925,6 +1943,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 149>; + wakeup-parent = <&pdc>; }; apps_smmu: iommu@15000000 { @@ -2306,6 +2325,72 @@ #freq-domain-cells = <1>; }; + + ethernet1: ethernet@23000000 { + compatible = "qcom,sa8775p-ethqos"; + reg = <0x0 0x23000000 0x0 0x10000>, + <0x0 0x23016000 0x0 0x100>; + reg-names = "stmmaceth", "rgmii"; + + interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + + clocks = <&gcc GCC_EMAC1_AXI_CLK>, + <&gcc GCC_EMAC1_SLV_AHB_CLK>, + <&gcc GCC_EMAC1_PTP_CLK>, + <&gcc GCC_EMAC1_PHY_AUX_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "phyaux"; + + power-domains = <&gcc EMAC1_GDSC>; + + phys = <&serdes1>; + phy-names = "serdes"; + + iommus = <&apps_smmu 0x140 0xf>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <16384>; + + status = "disabled"; + }; + + ethernet0: ethernet@23040000 { + compatible = "qcom,sa8775p-ethqos"; + reg = <0x0 0x23040000 0x0 0x10000>, + <0x0 0x23056000 0x0 0x100>; + reg-names = "stmmaceth", "rgmii"; + + interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + + clocks = <&gcc GCC_EMAC0_AXI_CLK>, + <&gcc GCC_EMAC0_SLV_AHB_CLK>, + <&gcc GCC_EMAC0_PTP_CLK>, + <&gcc GCC_EMAC0_PHY_AUX_CLK>; + clock-names = "stmmaceth", + "pclk", + "ptp_ref", + "phyaux"; + + power-domains = <&gcc EMAC0_GDSC>; + + phys = <&serdes0>; + phy-names = "serdes"; + + iommus = <&apps_smmu 0x120 0xf>; + + snps,tso; + snps,pbl = <32>; + rx-fifo-depth = <16384>; + tx-fifo-depth = <16384>; + + status = "disabled"; + }; }; arch_timer: timer { @@ -2315,4 +2400,204 @@ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; + + pcie0: pci@1c00000{ + compatible = "qcom,pcie-sa8775p"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40100000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <0>; + num-lanes = <2>; + + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie0_phy: phy@1c04000 { + compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; + reg = <0x0 0x1c04000 0x0 0x2000>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, + <&gcc GCC_PCIE_0_PHY_AUX_CLK>; + + clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", + "pipediv2", "phy_aux"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie1: pci@1c10000{ + compatible = "qcom,pcie-sa8775p"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60100000 0x0 0x100000>, + <0x0 0x01c13000 0x0 0x1000>; + reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; + device_type = "pci"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; + bus-range = <0x00 0xff>; + + dma-coherent; + + linux,pci-domain = <1>; + num-lanes = <4>; + + interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, + <0x100 &pcie_smmu 0x0081 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + power-domains = <&gcc PCIE_1_GDSC>; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + status = "disabled"; + }; + + pcie1_phy: phy@1c14000 { + compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; + reg = <0x0 0x1c14000 0x0 0x4000>; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPEDIV2_CLK>, + <&gcc GCC_PCIE_1_PHY_AUX_CLK>; + + clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe", + "pipediv2", "phy_aux"; + + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts index b637b4270f88..dbb48934d499 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-acer-aspire1.dts @@ -314,16 +314,18 @@ }; &pm6150_adc { - thermistor@4e { + channel@4e { reg = <ADC5_AMUX_THM2_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "thermistor"; }; - charger-thermistor@4f { + channel@4f { reg = <ADC5_AMUX_THM3_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "charger_thermistor"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi b/arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi new file mode 100644 index 000000000000..ee35a454dbf6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-firmware-tfa.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/* + * Devices that use SC7180 with TrustedFirmware-A + * need PSCI PC mode instead of the OSI mode provided + * by Qualcomm firmware. + */ + +&CPU0 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU1 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU2 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU3 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU4 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU5 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + + cpu-idle-states = <&LITTLE_CPU_SLEEP_0 + &LITTLE_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU6 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +&CPU7 { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + + cpu-idle-states = <&BIG_CPU_SLEEP_0 + &BIG_CPU_SLEEP_1 + &CLUSTER_SLEEP_0>; +}; + +/delete-node/ &domain_idle_states; + +&idle_states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "cluster-power-down"; + arm,psci-suspend-param = <0x40003444>; + entry-latency-us = <3263>; + exit-latency-us = <6562>; + min-residency-us = <9926>; + local-timer-stop; + }; +}; + +/delete-node/ &CPU_PD0; +/delete-node/ &CPU_PD1; +/delete-node/ &CPU_PD2; +/delete-node/ &CPU_PD3; +/delete-node/ &CPU_PD4; +/delete-node/ &CPU_PD5; +/delete-node/ &CPU_PD6; +/delete-node/ &CPU_PD7; +/delete-node/ &CLUSTER_PD; + +&apps_rsc { + /delete-property/ power-domains; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index a1c50be4ad95..0146fb0036d4 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -11,6 +11,7 @@ #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> #include "sc7180.dtsi" +#include "sc7180-firmware-tfa.dtsi" #include "pm6150.dtsi" #include "pm6150l.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts index edfcd47e1a00..03d350dcec96 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts @@ -24,8 +24,8 @@ }; &pm6150_adc { - /delete-node/ skin-temp-thermistor@4e; - /delete-node/ charger-thermistor@4f; + /delete-node/ channel@4e; + /delete-node/ channel@4f; }; &pm6150_adc_tm { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 8b8ea8af165d..a532cc4aac47 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -119,10 +119,11 @@ ap_ts_pen_1v8: &i2c4 { }; &pm6150_adc { - skin-temp-thermistor@4e { + channel@4e { reg = <ADC5_AMUX_THM2_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "skin_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index b3ba23a88a0b..b27dcd2ec856 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -145,10 +145,11 @@ ap_ts_pen_1v8: &i2c4 { }; &pm6150_adc { - skin-temp-thermistor@4d { + channel@4d { reg = <ADC5_AMUX_THM1_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "skin_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 269007d73162..13339b723a93 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -55,7 +55,7 @@ ap_ts_pen_1v8: &i2c4 { }; &pm6150_adc { - /delete-node/ charger-thermistor@4f; + /delete-node/ channel@4f; }; &pm6150_adc_tm { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts index 8467ff41e6d5..ba222a60c4c6 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts @@ -27,7 +27,7 @@ }; &pm6150_adc { - /delete-node/ charger-thermistor@4f; + /delete-node/ channel@4f; }; &pm6150_adc_tm { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts index 88cf2246c18a..64d6172bf402 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts @@ -24,7 +24,7 @@ }; &pm6150_adc { - /delete-node/ charger-thermistor@4f; + /delete-node/ channel@4f; }; &pm6150_adc_tm { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index 6c5287bd27d6..fd944842dd6c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -148,10 +148,11 @@ ap_ts_pen_1v8: &i2c4 { }; &pm6150_adc { - 5v-choke-thermistor@4e { + channel@4e { reg = <ADC5_AMUX_THM2_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "5v_choke_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi index 2efa8a4bcda6..2f6a340ddd2a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi @@ -163,10 +163,11 @@ }; &pm6150_adc { - skin-temp-thermistor@4d { + channel@4d { reg = <ADC5_AMUX_THM1_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "skin_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 681637cf6c4a..5a33e16a8b67 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/sound/sc7180-lpass.h> #include "sc7180.dtsi" +#include "sc7180-firmware-tfa.dtsi" /* PMICs depend on spmi_bus label and so must come after sc7180.dtsi */ #include "pm6150.dtsi" #include "pm6150l.dtsi" @@ -837,10 +838,11 @@ hp_i2c: &i2c9 { }; &pm6150_adc { - charger-thermistor@4f { + channel@4f { reg = <ADC5_AMUX_THM3_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "charger_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 06df931d8cad..a79c0f2e1879 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,videocc-sc7180.h> +#include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sc7180.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -78,9 +79,8 @@ reg = <0x0 0x0>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; capacity-dmips-mhz = <415>; dynamic-power-coefficient = <137>; operating-points-v2 = <&cpu0_opp_table>; @@ -108,9 +108,8 @@ reg = <0x0 0x100>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; capacity-dmips-mhz = <415>; dynamic-power-coefficient = <137>; next-level-cache = <&L2_100>; @@ -133,9 +132,8 @@ reg = <0x0 0x200>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; capacity-dmips-mhz = <415>; dynamic-power-coefficient = <137>; next-level-cache = <&L2_200>; @@ -158,9 +156,8 @@ reg = <0x0 0x300>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; capacity-dmips-mhz = <415>; dynamic-power-coefficient = <137>; next-level-cache = <&L2_300>; @@ -183,9 +180,8 @@ reg = <0x0 0x400>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; capacity-dmips-mhz = <415>; dynamic-power-coefficient = <137>; next-level-cache = <&L2_400>; @@ -208,9 +204,8 @@ reg = <0x0 0x500>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - cpu-idle-states = <&LITTLE_CPU_SLEEP_0 - &LITTLE_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; capacity-dmips-mhz = <415>; dynamic-power-coefficient = <137>; next-level-cache = <&L2_500>; @@ -233,9 +228,8 @@ reg = <0x0 0x600>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <480>; next-level-cache = <&L2_600>; @@ -258,9 +252,8 @@ reg = <0x0 0x700>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; - cpu-idle-states = <&BIG_CPU_SLEEP_0 - &BIG_CPU_SLEEP_1 - &CLUSTER_SLEEP_0>; + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <480>; next-level-cache = <&L2_700>; @@ -313,7 +306,7 @@ }; }; - idle-states { + idle_states: idle-states { entry-method = "psci"; LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { @@ -355,15 +348,34 @@ min-residency-us = <5555>; local-timer-stop; }; + }; - CLUSTER_SLEEP_0: cluster-sleep-0 { - compatible = "arm,idle-state"; + domain_idle_states: domain-idle-states { + CLUSTER_SLEEP_PC: cluster-sleep-0 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-l3-power-collapse"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + }; + + CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { + compatible = "domain-idle-state"; + idle-state-name = "cluster-cx-retention"; + arm,psci-suspend-param = <0x41001244>; + entry-latency-us = <3638>; + exit-latency-us = <4562>; + min-residency-us = <8467>; + }; + + CLUSTER_AOSS_SLEEP: cluster-sleep-2 { + compatible = "domain-idle-state"; idle-state-name = "cluster-power-down"; - arm,psci-suspend-param = <0x40003444>; + arm,psci-suspend-param = <0x4100b244>; entry-latency-us = <3263>; exit-latency-us = <6562>; - min-residency-us = <9926>; - local-timer-stop; + min-residency-us = <9826>; }; }; }; @@ -566,6 +578,61 @@ psci { compatible = "arm,psci-1.0"; method = "smc"; + + CPU_PD0: cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD1: cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD2: cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD3: cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD4: cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD5: cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; + }; + + CPU_PD6: cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + }; + + CPU_PD7: cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; + }; + + CLUSTER_PD: cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_PC + &CLUSTER_SLEEP_CX_RET + &CLUSTER_AOSS_SLEEP>; + }; }; reserved_memory: reserved-memory { @@ -2773,6 +2840,90 @@ }; }; + pmu@90b6300 { + compatible = "qcom,sc7180-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x090b6300 0 0x600>; + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <2288000>; + }; + + opp-1 { + opp-peak-kBps = <4577000>; + }; + + opp-2 { + opp-peak-kBps = <7110000>; + }; + + opp-3 { + opp-peak-kBps = <9155000>; + }; + + opp-4 { + opp-peak-kBps = <12298000>; + }; + + opp-5 { + opp-peak-kBps = <14236000>; + }; + }; + }; + + pmu@90cd000 { + compatible = "qcom,sc7180-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0 0x090cd000 0 0x1000>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <1144000>; + }; + + opp-1 { + opp-peak-kBps = <1720000>; + }; + + opp-2 { + opp-peak-kBps = <2086000>; + }; + + opp-3 { + opp-peak-kBps = <2929000>; + }; + + opp-4 { + opp-peak-kBps = <3879000>; + }; + + opp-5 { + opp-peak-kBps = <5931000>; + }; + + opp-6 { + opp-peak-kBps = <6881000>; + }; + + opp-7 { + opp-peak-kBps = <8137000>; + }; + }; + }; + dc_noc: interconnect@9160000 { compatible = "qcom,sc7180-dc-noc"; reg = <0 0x09160000 0 0x03200>; @@ -3512,6 +3663,7 @@ <SLEEP_TCS 3>, <WAKE_TCS 3>, <CONTROL_TCS 1>; + power-domains = <&CLUSTER_PD>; rpmhcc: clock-controller { compatible = "qcom,sc7180-rpmh-clk"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi index 485f9942e128..a90c70b1b73e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi @@ -13,7 +13,7 @@ compatible = "google,sc7280-herobrine"; model = "sc7280-rt5682-max98360a-3mic"; - audio-routing = "VA DMIC0", "vdd-micb", + audio-routing = "VA DMIC0", "vdd-micb", "VA DMIC1", "vdd-micb", "VA DMIC2", "vdd-micb", "VA DMIC3", "vdd-micb", diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 15222e92e3f5..b5fe7356be48 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -73,7 +73,7 @@ }; &pmk8350_vadc { - pmr735a-die-temp@403 { + channel@403 { reg = <PMR735A_ADC7_DIE_TEMP>; label = "pmr735a_die_temp"; qcom,pre-scaling = <1 1>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 21027042cf13..2ff549f4dc7a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -432,7 +432,7 @@ }; &pmk8350_vadc { - pmk8350-die-temp@3 { + channel@3 { reg = <PMK8350_ADC7_DIE_TEMP>; label = "pmk8350_die_temp"; qcom,pre-scaling = <1 1>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index 9137db066d9e..f9b96bd2477e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -383,13 +383,13 @@ }; &pmk8350_vadc { - pmk8350-die-temp@3 { + channel@3 { reg = <PMK8350_ADC7_DIE_TEMP>; label = "pmk8350_die_temp"; qcom,pre-scaling = <1 1>; }; - pmr735a-die-temp@403 { + channel@403 { reg = <PMR735A_ADC7_DIE_TEMP>; label = "pmr735a_die_temp"; qcom,pre-scaling = <1 1>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index a0e8db8270e7..925428a5f6ae 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2449,7 +2449,7 @@ <&apps_smmu 0x1821 0>, <&apps_smmu 0x1832 0>; - power-domains = <&rpmhpd SC7280_LCX>; + power-domains = <&rpmhpd SC7280_LCX>; power-domain-names = "lcx"; required-opps = <&rpmhpd_opp_nom>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index fe3b366e1435..abc66613ccaa 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -36,7 +36,7 @@ pinctrl-0 = <&hall_int_active_state>; pinctrl-names = "default"; - lid { + lid-switch { gpios = <&tlmm 121 GPIO_ACTIVE_LOW>; linux,input-type = <EV_SW>; linux,code = <SW_LID>; @@ -45,6 +45,84 @@ }; }; + pmic-glink { + compatible = "qcom,sc8180x-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_con0_hs: endpoint { + remote-endpoint = <&usb_prim_role_switch>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_con0_ss: endpoint { + remote-endpoint = <&usb_prim_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_con0_sbu: endpoint { + remote-endpoint = <&usbprim_sbu_mux>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + pmic_glink_con1_hs: endpoint { + remote-endpoint = <&usb_sec_role_switch>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_con1_ss: endpoint { + remote-endpoint = <&usb_sec_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_con1_sbu: endpoint { + remote-endpoint = <&usbsec_sbu_mux>; + }; + }; + }; + }; + }; + reserved-memory { rmtfs_mem: rmtfs-region@85500000 { compatible = "qcom,rmtfs-mem"; @@ -100,6 +178,44 @@ vin-supply = <&vph_pwr>; }; + + usbprim-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usbprim_sbu_default>; + + mode-switch; + orientation-switch; + + port { + usbprim_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_con0_sbu>; + }; + }; + }; + + usbsec-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 188 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 187 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usbsec_sbu_default>; + + mode-switch; + orientation-switch; + + port { + usbsec_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_con1_sbu>; + }; + }; + }; }; &apps_rsc { @@ -283,6 +399,24 @@ status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_prim_qmpphy_dp_in>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_sec_qmpphy_dp_in>; +}; + &mdss_edp { data-lanes = <0 1 2 3>; @@ -298,11 +432,9 @@ backlight = <&backlight>; - ports { - port { - auo_b140han06_in: endpoint { - remote-endpoint = <&mdss_edp_out>; - }; + port { + auo_b140han06_in: endpoint { + remote-endpoint = <&mdss_edp_out>; }; }; }; @@ -419,6 +551,8 @@ vdda-phy-supply = <&vreg_l3c_1p2>; vdda-pll-supply = <&vreg_l5e_0p88>; + orientation-switch; + status = "okay"; }; @@ -430,6 +564,18 @@ dr_mode = "host"; }; +&usb_prim_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_prim_qmpphy_out { + remote-endpoint = <&pmic_glink_con0_ss>; +}; + +&usb_prim_role_switch { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_sec_hsphy { vdda-pll-supply = <&vreg_l5e_0p88>; vdda18-supply = <&vreg_l12a_1p8>; @@ -442,9 +588,23 @@ vdda-phy-supply = <&vreg_l3c_1p2>; vdda-pll-supply = <&vreg_l5e_0p88>; + orientation-switch; + status = "okay"; }; +&usb_sec_qmpphy_dp_in { + remote-endpoint = <&mdss_dp1_out>; +}; + +&usb_sec_qmpphy_out { + remote-endpoint = <&pmic_glink_con1_ss>; +}; + +&usb_sec_role_switch { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + &usb_sec { status = "okay"; }; @@ -497,7 +657,6 @@ pins = "gpio121"; function = "gpio"; - input-enable; bias-disable; }; @@ -513,7 +672,6 @@ pins = "gpio122"; function = "gpio"; - input-enable; bias-pull-up; drive-strength = <2>; }; @@ -530,7 +688,6 @@ pins = "gpio37", "gpio24"; function = "gpio"; - input-enable; bias-pull-up; drive-strength = <2>; }; @@ -560,6 +717,40 @@ }; }; + usbprim_sbu_default: usbprim-sbu-state { + oe-n-pins { + pins = "gpio152"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + output-high; + }; + + sel-pins { + pins = "gpio100"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + }; + + usbsec_sbu_default: usbsec-sbu-state { + oe-n-pins { + pins = "gpio188"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + output-high; + }; + + sel-pins { + pins = "gpio187"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + }; + uart13_state: uart13-state { cts-pins { pins = "gpio43"; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi index 8247af01c84a..ddc84282f142 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi @@ -74,7 +74,7 @@ #address-cells = <1>; #size-cells = <0>; - pon: power-on@800 { + pon: pon@800 { compatible = "qcom,pm8916-pon"; reg = <0x0800>; pwrkey { @@ -105,19 +105,19 @@ #io-channel-cells = <1>; interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = <ADC5_REF_GND>; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = <ADC5_1P25VREF>; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = <ADC5_DIE_TEMP>; qcom,pre-scaling = <1 1>; label = "die_temp"; @@ -142,9 +142,10 @@ }; pmc8180_gpios: gpio@c000 { - compatible = "qcom,pmc8180-gpio"; + compatible = "qcom,pmc8180-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pmc8180_gpios 0 0 10>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -172,19 +173,19 @@ #io-channel-cells = <1>; interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = <ADC5_REF_GND>; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = <ADC5_1P25VREF>; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - vcoin@85 { + channel@85 { reg = <0x85>; qcom,pre-scaling = <1 1>; label = "vcoin2"; @@ -220,19 +221,19 @@ #io-channel-cells = <1>; interrupts = <0xa 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = <ADC5_REF_GND>; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = <ADC5_1P25VREF>; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - vcoin@85 { + channel@85 { reg = <0x85>; qcom,pre-scaling = <1 1>; label = "vcoin"; @@ -246,7 +247,7 @@ #address-cells = <1>; #size-cells = <0>; - power-on@800 { + pon@800 { compatible = "qcom,pm8916-pon"; reg = <0x0800>; @@ -270,19 +271,19 @@ #io-channel-cells = <1>; interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>; - ref-gnd@0 { + channel@0 { reg = <ADC5_REF_GND>; qcom,pre-scaling = <1 1>; label = "ref_gnd"; }; - vref-1p25@1 { + channel@1 { reg = <ADC5_1P25VREF>; qcom,pre-scaling = <1 1>; label = "vref_1p25"; }; - die-temp@6 { + channel@6 { reg = <ADC5_DIE_TEMP>; qcom,pre-scaling = <1 1>; label = "die_temp"; @@ -300,9 +301,10 @@ }; pmc8180c_gpios: gpio@c000 { - compatible = "qcom,pmc8180c-gpio"; + compatible = "qcom,pmc8180c-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pmc8180c_gpios 0 0 12>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; @@ -313,7 +315,7 @@ compatible = "qcom,pmc8180c", "qcom,spmi-pmic"; reg = <0x5 SPMI_USID>; - pmc8180c_lpg: lpg { + pmc8180c_lpg: pwm { compatible = "qcom,pmc8180c-lpg"; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index fc038474cb71..834e6f9fb7c8 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -50,6 +50,84 @@ }; }; + pmic-glink { + compatible = "qcom,sc8180x-pmic-glink", "qcom,pmic-glink"; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_con0_hs: endpoint { + remote-endpoint = <&usb_prim_role_switch>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_con0_ss: endpoint { + remote-endpoint = <&usb_prim_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_con0_sbu: endpoint { + remote-endpoint = <&usbprim_sbu_mux>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + pmic_glink_con1_hs: endpoint { + remote-endpoint = <&usb_sec_role_switch>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_con1_ss: endpoint { + remote-endpoint = <&usb_sec_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_con1_sbu: endpoint { + remote-endpoint = <&usbsec_sbu_mux>; + }; + }; + }; + }; + }; + reserved-memory { rmtfs_mem: rmtfs-region@85500000 { compatible = "qcom,rmtfs-mem"; @@ -143,6 +221,44 @@ vin-supply = <&vph_pwr>; }; + + usbprim-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usbprim_sbu_default>; + + mode-switch; + orientation-switch; + + port { + usbprim_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_con0_sbu>; + }; + }; + }; + + usbsec-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + enable-gpios = <&tlmm 188 GPIO_ACTIVE_LOW>; + select-gpios = <&tlmm 187 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&usbsec_sbu_default>; + + mode-switch; + orientation-switch; + + port { + usbsec_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_con1_sbu>; + }; + }; + }; }; &apps_rsc { @@ -363,6 +479,24 @@ status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_prim_qmpphy_dp_in>; +}; + +&mdss_dp1 { + status = "okay"; +}; + +&mdss_dp1_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_sec_qmpphy_dp_in>; +}; + &mdss_edp { data-lanes = <0 1 2 3>; @@ -377,11 +511,9 @@ backlight = <&backlight>; - ports { - port { - auo_b133han05_in: endpoint { - remote-endpoint = <&mdss_edp_out>; - }; + port { + auo_b133han05_in: endpoint { + remote-endpoint = <&mdss_edp_out>; }; }; }; @@ -496,6 +628,8 @@ vdda-phy-supply = <&vreg_l3c_1p2>; vdda-pll-supply = <&vreg_l5e_0p88>; + orientation-switch; + status = "okay"; }; @@ -507,6 +641,18 @@ dr_mode = "host"; }; +&usb_prim_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_prim_qmpphy_out { + remote-endpoint = <&pmic_glink_con0_ss>; +}; + +&usb_prim_role_switch { + remote-endpoint = <&pmic_glink_con0_hs>; +}; + &usb_sec_hsphy { vdda-pll-supply = <&vreg_l5e_0p88>; vdda18-supply = <&vreg_l12a_1p8>; @@ -519,9 +665,23 @@ vdda-phy-supply = <&vreg_l3c_1p2>; vdda-pll-supply = <&vreg_l5e_0p88>; + orientation-switch; + status = "okay"; }; +&usb_sec_qmpphy_dp_in { + remote-endpoint = <&mdss_dp1_out>; +}; + +&usb_sec_qmpphy_out { + remote-endpoint = <&pmic_glink_con1_ss>; +}; + +&usb_sec_role_switch { + remote-endpoint = <&pmic_glink_con1_hs>; +}; + &usb_sec { status = "okay"; }; @@ -582,7 +742,6 @@ pins = "gpio121"; function = "gpio"; - input-enable; bias-disable; }; @@ -592,7 +751,6 @@ function = "gpio"; bias-pull-up; - intput-enable; }; kp-disable-pins { @@ -635,13 +793,46 @@ }; }; + usbprim_sbu_default: usbprim-sbu-state { + oe-n-pins { + pins = "gpio152"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + output-high; + }; + + sel-pins { + pins = "gpio100"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + }; + + usbsec_sbu_default: usbsec-sbu-state { + oe-n-pins { + pins = "gpio188"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + output-high; + }; + + sel-pins { + pins = "gpio187"; + function = "gpio"; + bias-disable; + drive-strength = <16>; + }; + }; + tp_int_active_state: tp-int-active-state { tp-int-pins { pins = "gpio24"; function = "gpio"; bias-disable; - input-enable; }; tp-close-n-pins { @@ -649,7 +840,6 @@ function = "gpio"; bias-disable; - input-enable; }; }; @@ -658,7 +848,6 @@ pins = "gpio122"; function = "gpio"; - input-enable; bias-disable; }; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index be78a933d8eb..486f7ffef43b 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -64,6 +64,7 @@ L3_0: l3-cache { compatible = "cache"; cache-level = <3>; + cache-unified; }; }; }; @@ -298,7 +299,7 @@ domain-idle-states { CLUSTER_SLEEP_0: cluster-sleep-0 { compatible = "domain-idle-state"; - arm,psci-suspend-param = <0x4100c244>; + arm,psci-suspend-param = <0x4100a344>; entry-latency-us = <3263>; exit-latency-us = <6562>; min-residency-us = <9987>; @@ -2252,7 +2253,7 @@ }; gmu: gmu@2c6a000 { - compatible="qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; + compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; reg = <0 0x02c6a000 0 0x30000>, <0 0x0b290000 0 0x10000>, @@ -2464,6 +2465,23 @@ status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_prim_qmpphy_out: endpoint {}; + }; + + port@2 { + reg = <2>; + + usb_prim_qmpphy_dp_in: endpoint {}; + }; + }; + usb_prim_ssphy: usb3-phy@88e9200 { reg = <0 0x088e9200 0 0x200>, <0 0x088e9400 0 0x200>, @@ -2513,6 +2531,23 @@ status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_sec_qmpphy_out: endpoint {}; + }; + + port@2 { + reg = <2>; + + usb_sec_qmpphy_dp_in: endpoint {}; + }; + }; + usb_sec_ssphy: usb3-phy@88e9200 { reg = <0 0x088ee200 0 0x200>, <0 0x088ee400 0 0x200>, @@ -2541,8 +2576,11 @@ system-cache-controller@9200000 { compatible = "qcom,sc8180x-llcc"; - reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; @@ -2604,6 +2642,11 @@ snps,dis_enblslpm_quirk; phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>; phy-names = "usb2-phy", "usb3-phy"; + + port { + usb_prim_role_switch: endpoint { + }; + }; }; }; @@ -2656,6 +2699,11 @@ snps,dis_enblslpm_quirk; phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>; phy-names = "usb2-phy", "usb3-phy"; + + port { + usb_sec_role_switch: endpoint { + }; + }; }; }; @@ -2983,6 +3031,8 @@ port@1 { reg = <1>; + mdss_dp0_out: endpoint { + }; }; }; @@ -3057,6 +3107,8 @@ port@1 { reg = <1>; + mdss_dp1_out: endpoint { + }; }; }; @@ -3429,7 +3481,7 @@ #size-cells = <1>; ranges = <0 0 0 0x20000000>; - frame@17c21000{ + frame@17c21000 { reg = <0x17c21000 0x1000>, <0x17c22000 0x1000>; frame-number = <0>; @@ -3856,7 +3908,7 @@ }; }; - gpu-thermal-top { + gpu-top-thermal { polling-delay-passive = <250>; polling-delay = <1000>; @@ -4006,7 +4058,7 @@ }; }; - gpu-thermal-bottom { + gpu-bottom-thermal { polling-delay-passive = <250>; polling-delay = <1000>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index b566e403d1db..e4861c61a65b 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -133,7 +133,7 @@ vreg_edp_bl: regulator-edp-bl { compatible = "regulator-fixed"; - regulator-name = "VBL9"; + regulator-name = "VREG_EDP_BL"; regulator-min-microvolt = <3600000>; regulator-max-microvolt = <3600000>; @@ -149,7 +149,7 @@ vreg_nvme: regulator-nvme { compatible = "regulator-fixed"; - regulator-name = "VCC3_SSD"; + regulator-name = "VREG_NVME_3P3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -163,11 +163,11 @@ vreg_misc_3p3: regulator-misc-3p3 { compatible = "regulator-fixed"; - regulator-name = "VCC3B"; + regulator-name = "VREG_MISC_3P3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&pmc8280_1_gpios 1 GPIO_ACTIVE_HIGH>; + gpio = <&pmc8280_1_gpios 2 GPIO_ACTIVE_HIGH>; enable-active-high; pinctrl-names = "default"; @@ -180,7 +180,7 @@ vreg_wlan: regulator-wlan { compatible = "regulator-fixed"; - regulator-name = "VCC_WLAN_3R9"; + regulator-name = "VPH_PWR_WLAN"; regulator-min-microvolt = <3900000>; regulator-max-microvolt = <3900000>; @@ -196,7 +196,7 @@ vreg_wwan: regulator-wwan { compatible = "regulator-fixed"; - regulator-name = "VCC3B_WAN"; + regulator-name = "SDX_VPH_PWR"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -234,7 +234,6 @@ mode-switch; orientation-switch; - svid = /bits/ 16 <0xff01>; port { usb0_sbu_mux: endpoint { @@ -254,7 +253,6 @@ mode-switch; orientation-switch; - svid = /bits/ 16 <0xff01>; port { usb1_sbu_mux: endpoint { @@ -757,7 +755,7 @@ }; misc_3p3_reg_en: misc-3p3-reg-en-state { - pins = "gpio1"; + pins = "gpio2"; function = "normal"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 7cc3028440b6..38edaf51aa34 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -12,6 +12,7 @@ #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h> #include <dt-bindings/input/gpio-keys.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sc8280xp.dtsi" @@ -78,6 +79,21 @@ }; }; + leds { + compatible = "gpio-leds"; + + led-camera-indicator { + label = "white:camera-indicator"; + function = LED_FUNCTION_INDICATOR; + color = <LED_COLOR_ID_WHITE>; + gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + /* Reuse as a panic indicator until we get a "camera on" trigger */ + panic-indicator; + }; + }; + pmic-glink { compatible = "qcom,sc8280xp-pmic-glink", "qcom,pmic-glink"; @@ -334,7 +350,6 @@ mode-switch; orientation-switch; - svid = /bits/ 16 <0xff01>; port { usb0_sbu_mux: endpoint { @@ -354,7 +369,6 @@ mode-switch; orientation-switch; - svid = /bits/ 16 <0xff01>; port { usb1_sbu_mux: endpoint { @@ -836,88 +850,88 @@ &pmk8280_vadc { status = "okay"; - pmic-die-temp@3 { + channel@3 { reg = <PMK8350_ADC7_DIE_TEMP>; qcom,pre-scaling = <1 1>; label = "pmk8350_die_temp"; }; - xo-therm@44 { + channel@44 { reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "pmk8350_xo_therm"; }; - pmic-die-temp@103 { + channel@103 { reg = <PM8350_ADC7_DIE_TEMP(1)>; qcom,pre-scaling = <1 1>; label = "pmc8280_1_die_temp"; }; - sys-therm@144 { + channel@144 { reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm1"; }; - sys-therm@145 { + channel@145 { reg = <PM8350_ADC7_AMUX_THM2_100K_PU(1)>; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm2"; }; - sys-therm@146 { + channel@146 { reg = <PM8350_ADC7_AMUX_THM3_100K_PU(1)>; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm3"; }; - sys-therm@147 { + channel@147 { reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm4"; }; - pmic-die-temp@303 { + channel@303 { reg = <PM8350_ADC7_DIE_TEMP(3)>; qcom,pre-scaling = <1 1>; label = "pmc8280_2_die_temp"; }; - sys-therm@344 { + channel@344 { reg = <PM8350_ADC7_AMUX_THM1_100K_PU(3)>; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm5"; }; - sys-therm@345 { + channel@345 { reg = <PM8350_ADC7_AMUX_THM2_100K_PU(3)>; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm6"; }; - sys-therm@346 { + channel@346 { reg = <PM8350_ADC7_AMUX_THM3_100K_PU(3)>; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm7"; }; - sys-therm@347 { + channel@347 { reg = <PM8350_ADC7_AMUX_THM4_100K_PU(3)>; qcom,hw-settle-time = <200>; qcom,ratiometric; label = "sys_therm8"; }; - pmic-die-temp@403 { + channel@403 { reg = <PMR735A_ADC7_DIE_TEMP>; qcom,pre-scaling = <1 1>; label = "pmr735a_die_temp"; @@ -1246,7 +1260,7 @@ }; &tlmm { - gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>; + gpio-reserved-ranges = <70 2>, <74 6>, <125 2>, <128 2>, <154 4>; bt_default: bt-default-state { hstp-bt-en-pins { diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi index a0ba535bb6c9..80ee12ded4f4 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi @@ -101,7 +101,7 @@ compatible = "qcom,pmk8350-rtc"; reg = <0x6100>, <0x6200>; reg-names = "rtc", "alarm"; - interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + interrupts-extended = <&spmi_bus 0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; wakeup-source; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index ac0596dfdbc4..cad59af7ccef 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -298,6 +298,7 @@ firmware { scm: scm { compatible = "qcom,scm-sc8280xp", "qcom,scm"; + interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; }; }; @@ -4058,6 +4059,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 230>; + wakeup-parent = <&pdc>; }; apps_smmu: iommu@15000000 { diff --git a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts index 0b23d5bb3f26..2ed39d402d3f 100644 --- a/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts +++ b/arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts @@ -43,7 +43,7 @@ */ extcon_usb: extcon-usb { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>; }; hdmi-out { diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 3033723fc6ff..87d0293c728d 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -150,7 +150,7 @@ */ extcon_usb: extcon-usb { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index bba0f366ef03..ec6003212c4d 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -359,6 +359,74 @@ method = "smc"; }; + rpm: remoteproc { + compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sdm660"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sdm660-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <RPM_SMD_LEVEL_RETENTION>; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = <RPM_SMD_LEVEL_MIN_SVS>; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = <RPM_SMD_LEVEL_LOW_SVS>; + }; + + rpmpd_opp_svs: opp5 { + opp-level = <RPM_SMD_LEVEL_SVS>; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; + }; + + rpmpd_opp_nom: opp7 { + opp-level = <RPM_SMD_LEVEL_NOM>; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = <RPM_SMD_LEVEL_TURBO>; + }; + }; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -440,70 +508,6 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-sdm660"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,sdm660-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <RPM_SMD_LEVEL_RETENTION>; - }; - - rpmpd_opp_ret_plus: opp2 { - opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; - }; - - rpmpd_opp_min_svs: opp3 { - opp-level = <RPM_SMD_LEVEL_MIN_SVS>; - }; - - rpmpd_opp_low_svs: opp4 { - opp-level = <RPM_SMD_LEVEL_LOW_SVS>; - }; - - rpmpd_opp_svs: opp5 { - opp-level = <RPM_SMD_LEVEL_SVS>; - }; - - rpmpd_opp_svs_plus: opp6 { - opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; - }; - - rpmpd_opp_nom: opp7 { - opp-level = <RPM_SMD_LEVEL_NOM>; - }; - - rpmpd_opp_nom_plus: opp8 { - opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; - }; - - rpmpd_opp_turbo: opp9 { - opp-level = <RPM_SMD_LEVEL_TURBO>; - }; - }; - }; - }; - }; - smem: smem { compatible = "qcom,smem"; memory-region = <&smem_region>; @@ -1030,7 +1034,7 @@ reg = <0x05000000 0x40000>; reg-names = "kgsl_3d0_reg_memory"; - interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, <&gpucc GPUCC_RBBMTIMER_CLK>, @@ -1196,11 +1200,11 @@ spmi_bus: spmi@800f000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x0800f000 0x1000>, - <0x08400000 0x1000000>, - <0x09400000 0x1000000>, - <0x0a400000 0x220000>, - <0x0800a000 0x3000>; + reg = <0x0800f000 0x1000>, + <0x08400000 0x1000000>, + <0x09400000 0x1000000>, + <0x0a400000 0x220000>, + <0x0800a000 0x3000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; @@ -2286,50 +2290,50 @@ frame@17921000 { frame-number = <0>; - interrupts = <0 8 0x4>, - <0 7 0x4>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17921000 0x1000>, <0x17922000 0x1000>; }; frame@17923000 { frame-number = <1>; - interrupts = <0 9 0x4>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17923000 0x1000>; status = "disabled"; }; frame@17924000 { frame-number = <2>; - interrupts = <0 10 0x4>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17924000 0x1000>; status = "disabled"; }; frame@17925000 { frame-number = <3>; - interrupts = <0 11 0x4>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17925000 0x1000>; status = "disabled"; }; frame@17926000 { frame-number = <4>; - interrupts = <0 12 0x4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17926000 0x1000>; status = "disabled"; }; frame@17927000 { frame-number = <5>; - interrupts = <0 13 0x4>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17927000 0x1000>; status = "disabled"; }; frame@17928000 { frame-number = <6>; - interrupts = <0 14 0x4>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; reg = <0x17928000 0x1000>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 8fb2d1788742..3c47410ba94c 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -85,7 +85,7 @@ */ extcon_usb: extcon-usb { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi index a1c207c0266d..84cd2e39266f 100644 --- a/arch/arm64/boot/dts/qcom/sdm670.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/phy/phy-qcom-qusb2.h> @@ -35,6 +36,12 @@ compatible = "qcom,kryo360"; reg = <0x0 0x0>; enable-method = "psci"; + capacity-dmips-mhz = <610>; + dynamic-power-coefficient = <203>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; next-level-cache = <&L2_0>; @@ -56,6 +63,12 @@ compatible = "qcom,kryo360"; reg = <0x0 0x100>; enable-method = "psci"; + capacity-dmips-mhz = <610>; + dynamic-power-coefficient = <203>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; next-level-cache = <&L2_100>; @@ -72,6 +85,12 @@ compatible = "qcom,kryo360"; reg = <0x0 0x200>; enable-method = "psci"; + capacity-dmips-mhz = <610>; + dynamic-power-coefficient = <203>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; next-level-cache = <&L2_200>; @@ -88,6 +107,12 @@ compatible = "qcom,kryo360"; reg = <0x0 0x300>; enable-method = "psci"; + capacity-dmips-mhz = <610>; + dynamic-power-coefficient = <203>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; next-level-cache = <&L2_300>; @@ -104,6 +129,12 @@ compatible = "qcom,kryo360"; reg = <0x0 0x400>; enable-method = "psci"; + capacity-dmips-mhz = <610>; + dynamic-power-coefficient = <203>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; next-level-cache = <&L2_400>; @@ -120,6 +151,12 @@ compatible = "qcom,kryo360"; reg = <0x0 0x500>; enable-method = "psci"; + capacity-dmips-mhz = <610>; + dynamic-power-coefficient = <203>; + qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; next-level-cache = <&L2_500>; @@ -136,6 +173,12 @@ compatible = "qcom,kryo360"; reg = <0x0 0x600>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <393>; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; next-level-cache = <&L2_600>; @@ -152,6 +195,12 @@ compatible = "qcom,kryo360"; reg = <0x0 0x700>; enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <393>; + qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; next-level-cache = <&L2_700>; @@ -246,6 +295,111 @@ reg = <0x0 0x80000000 0x0 0x0>; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + cpu0_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <400000 4800000>; + }; + + cpu0_opp2: opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <400000 4800000>; + }; + + cpu0_opp3: opp-748800000 { + opp-hz = /bits/ 64 <748800000>; + opp-peak-kBps = <1200000 4800000>; + }; + + cpu0_opp4: opp-998400000 { + opp-hz = /bits/ 64 <998400000>; + opp-peak-kBps = <1804000 8908800>; + }; + + cpu0_opp5: opp-1209600000 { + opp-hz = /bits/ 64 <1209600000>; + opp-peak-kBps = <2188000 8908800>; + }; + + cpu0_opp6: opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <2188000 13516800>; + }; + + cpu0_opp7: opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <3072000 15052800>; + }; + + cpu0_opp8: opp-1612800000 { + opp-hz = /bits/ 64 <1612800000>; + opp-peak-kBps = <3072000 22118400>; + }; + + cpu0_opp9: opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <4068000 23040000>; + }; + }; + + cpu6_opp_table: opp-table-cpu6 { + compatible = "operating-points-v2"; + opp-shared; + + cpu6_opp1: opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <400000 4800000>; + }; + + cpu6_opp2: opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + opp-peak-kBps = <400000 4800000>; + }; + + cpu6_opp3: opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + opp-peak-kBps = <1200000 4800000>; + }; + + cpu6_opp4: opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + opp-peak-kBps = <1200000 4800000>; + }; + + cpu6_opp5: opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + opp-peak-kBps = <2188000 8908800>; + }; + + cpu6_opp6: opp-1363200000 { + opp-hz = /bits/ 64 <1363200000>; + opp-peak-kBps = <4068000 12902400>; + }; + + cpu6_opp7: opp-1536000000 { + opp-hz = /bits/ 64 <1536000000>; + opp-peak-kBps = <4068000 12902400>; + }; + + cpu6_opp8: opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + opp-peak-kBps = <4068000 15052800>; + }; + + cpu6_opp9: opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + opp-peak-kBps = <4068000 15052800>; + }; + + cpu6_opp10: opp-1996800000 { + opp-hz = /bits/ 64 <1996800000>; + opp-peak-kBps = <6220000 19046400>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -969,6 +1123,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 151>; + wakeup-parent = <&pdc>; qup_i2c0_default: qup-i2c0-default-state { pins = "gpio0", "gpio1"; @@ -1169,6 +1324,16 @@ }; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,sdm670-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>; + qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>, + <54 534 24>, <79 559 30>, <115 630 7>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>, @@ -1354,5 +1519,26 @@ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <3>; }; + + osm_l3: interconnect@17d41000 { + compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3"; + reg = <0 0x17d41000 0 0x1400>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + }; + + cpufreq_hw: cpufreq@17d43000 { + compatible = "qcom,cpufreq-hw"; + reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; + reg-names = "freq-domain0", "freq-domain1"; + + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 1ce413263b7f..f86e7acdfd99 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -1071,27 +1071,27 @@ ap_ts_i2c: &i2c14 { }; &pm8998_adc { - adc-chan@4d { + channel@4d { reg = <ADC5_AMUX_THM1_100K_PU>; label = "sdm_temp"; }; - adc-chan@4e { + channel@4e { reg = <ADC5_AMUX_THM2_100K_PU>; label = "quiet_temp"; }; - adc-chan@4f { + channel@4f { reg = <ADC5_AMUX_THM3_100K_PU>; label = "lte_temp_1"; }; - adc-chan@50 { + channel@50 { reg = <ADC5_AMUX_THM4_100K_PU>; label = "lte_temp_2"; }; - adc-chan@51 { + channel@51 { reg = <ADC5_AMUX_THM5_100K_PU>; label = "charger_temp"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index d6b464cb61d6..c7eba6c491be 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -101,6 +101,14 @@ }; }; + reserved-memory { + /* Cont splash region set up by the bootloader */ + cont_splash_mem: framebuffer@9d400000 { + reg = <0x0 0x9d400000 0x0 0x2400000>; + no-map; + }; + }; + lt9611_1v8: lt9611-vdd18-regulator { compatible = "regulator-fixed"; regulator-name = "LT9611_1V8"; @@ -410,6 +418,13 @@ }; }; +&camss { + status = "okay"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; +}; + &cdsp_pas { status = "okay"; firmware-name = "qcom/sdm845/cdsp.mbn"; @@ -506,6 +521,7 @@ }; &mdss { + memory-region = <&cont_splash_mem>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index b2d4336e764b..b3c27a524742 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -15,6 +15,7 @@ / { model = "Qualcomm Technologies, Inc. SDM845 MTP"; compatible = "qcom,sdm845-mtp", "qcom,sdm845"; + chassis-type = "handset"; aliases { serial0 = &uart9; @@ -533,42 +534,42 @@ }; &pm8998_adc { - adc-chan@4c { + channel@4c { reg = <ADC5_XO_THERM_100K_PU>; label = "xo_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; }; - adc-chan@4d { + channel@4d { reg = <ADC5_AMUX_THM1_100K_PU>; label = "msm_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; }; - adc-chan@4f { + channel@4f { reg = <ADC5_AMUX_THM3_100K_PU>; label = "pa_therm1"; qcom,ratiometric; qcom,hw-settle-time = <200>; }; - adc-chan@51 { + channel@51 { reg = <ADC5_AMUX_THM5_100K_PU>; label = "quiet_therm"; qcom,ratiometric; qcom,hw-settle-time = <200>; }; - adc-chan@83 { + channel@83 { reg = <ADC5_VPH_PWR>; label = "vph_pwr"; qcom,ratiometric; qcom,hw-settle-time = <200>; }; - adc-chan@85 { + channel@85 { reg = <ADC5_VCOIN>; label = "vcoin"; qcom,ratiometric; diff --git a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts index 623a826b18a3..4005e04d998a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts @@ -39,7 +39,7 @@ max98927_codec: max98927@3a { compatible = "maxim,max98927"; reg = <0x3a>; - #sound-dai-cells = <1>; + #sound-dai-cells = <0>; pinctrl-0 = <&speaker_default>; pinctrl-names = "default"; @@ -57,7 +57,7 @@ &sound { model = "OnePlus 6"; - audio-routing = "RX_BIAS", "MCLK", + audio-routing = "RX_BIAS", "MCLK", "AMIC2", "MIC BIAS2", "AMIC3", "MIC BIAS4", "AMIC4", "MIC BIAS1", @@ -66,7 +66,7 @@ &speaker_playback_dai { codec { - sound-dai = <&max98927_codec 0>; + sound-dai = <&max98927_codec>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index dce0141f3719..fbb8655653fb 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -440,7 +440,7 @@ reg = <0x38>; wakeup-source; interrupt-parent = <&tlmm>; - interrupts = <125 0x2>; + interrupts = <125 IRQ_TYPE_EDGE_FALLING>; vdd-supply = <&vreg_l28a_3p0>; vcc-i2c-supply = <&vreg_l14a_1p88>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi index 3bc187a066ae..7ee61b20452e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sony-xperia-tama.dtsi @@ -15,6 +15,15 @@ qcom,msm-id = <321 0x20001>; /* SDM845 v2.1 */ qcom,board-id = <8 0>; + aliases { + serial0 = &uart6; + serial1 = &uart9; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + gpio-keys { compatible = "gpio-keys"; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 02a6ea0b8b2c..055ca80c0075 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1207,6 +1207,7 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + power-domains = <&rpmhpd SDM845_CX>; }; qfprom@784000 { @@ -2613,7 +2614,11 @@ <0 0>, <0 0>, <0 0>, - <0 300000000>; + <75000000 300000000>; + + interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mem_noc SLAVE_EBI1 0>, + <&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; + interconnect-names = "ufs-ddr", "cpu-ufs"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index cfbc4fc1eba9..92a812b5f423 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -33,7 +33,8 @@ chassis-type = "convertible"; aliases { - hsuart0 = &uart6; + serial0 = &uart9; + serial1 = &uart6; }; gpio-keys { @@ -80,6 +81,22 @@ }; }; + sw_edp_1p2: edp-1p2-regulator { + compatible = "regulator-fixed"; + regulator-name = "sw_edp_1p2"; + + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + pinctrl-0 = <&sw_edp_1p2_en>; + pinctrl-names = "default"; + + gpio = <&pm8998_gpios 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply = <&vreg_l2a_1p2>; + }; + sn65dsi86_refclk: sn65dsi86-refclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -87,6 +104,25 @@ clock-frequency = <19200000>; }; + vph_pwr: regulator-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vlcm_3v3: regulator-vlcm-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vlcm_3v3"; + + vin-supply = <&vph_pwr>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + backlight: backlight { compatible = "pwm-backlight"; pwms = <&sn65dsi86 1000000>; @@ -387,6 +423,8 @@ enable-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + vcca-supply = <&sw_edp_1p2>; + vcc-supply = <&sw_edp_1p2>; vpll-supply = <&vreg_l14a_1p88>; vccio-supply = <&vreg_l14a_1p88>; @@ -419,6 +457,7 @@ panel: panel { compatible = "boe,nv133fhm-n61"; backlight = <&backlight>; + power-supply = <&vlcm_3v3>; port { panel_in_edp: endpoint { @@ -480,6 +519,16 @@ firmware-name = "qcom/sdm850/LENOVO/81JL/qcdsp1v2850.mbn", "qcom/sdm850/LENOVO/81JL/qcdsp2850.mbn"; }; +&pm8998_gpios { + /* This pin is pulled down by a fixed resistor */ + sw_edp_1p2_en: pm8998-gpio9-state { + pins = "gpio9"; + function = "normal"; + bias-disable; + qcom,drive-strength = <0>; + }; +}; + &qup_i2c10_default { drive-strength = <2>; bias-disable; @@ -658,6 +707,10 @@ }; }; +&uart9 { + status = "okay"; +}; + &ufs_mem_hc { status = "okay"; @@ -779,5 +832,5 @@ &crypto { /* FIXME: qce_start triggers an SError */ - status = "disable"; + status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts index 41f59e32af64..543837316001 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts @@ -56,7 +56,7 @@ }; aliases { - hsuart0 = &uart6; + serial1 = &uart6; }; /* Reserved memory changes */ diff --git a/arch/arm64/boot/dts/qcom/sdx75-idp.dts b/arch/arm64/boot/dts/qcom/sdx75-idp.dts index cbe5cdf5a228..10d15871f2c4 100644 --- a/arch/arm64/boot/dts/qcom/sdx75-idp.dts +++ b/arch/arm64/boot/dts/qcom/sdx75-idp.dts @@ -5,7 +5,11 @@ /dts-v1/; +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sdx75.dtsi" +#include "pm7550ba.dtsi" +#include "pmk8550.dtsi" +#include "pmx75.dtsi" / { model = "Qualcomm Technologies, Inc. SDX75 IDP"; @@ -14,6 +18,232 @@ aliases { serial0 = &uart1; }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vph_ext: vph-ext-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_ext"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + }; + + vreg_bob_3p3: pmx75-bob { + compatible = "regulator-fixed"; + regulator-name = "vreg_bob_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vph_ext>; + }; +}; + +&apps_rsc { + pmx75-rpmh-regulators { + compatible = "qcom,pmx75-rpmh-regulators"; + qcom,pmic-id = "b"; + + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + vdd-s7-supply = <&vph_pwr>; + vdd-s8-supply = <&vph_pwr>; + vdd-s9-supply = <&vph_pwr>; + vdd-s10-supply = <&vph_pwr>; + vdd-l1-supply = <&vreg_s2b_1p224>; + vdd-l2-l18-supply = <&vreg_s2b_1p224>; + vdd-l3-supply = <&vreg_s7b_0p936>; + vdd-l4-l16-supply = <&vreg_s7b_0p936>; + vdd-l5-l6-supply = <&vreg_s4b_1p824>; + vdd-l7-supply = <&vreg_s7b_0p936>; + vdd-l8-l9-supply = <&vreg_s8b_0p824>; + vdd-l10-supply = <&vreg_bob_3p3>; + vdd-l11-l13-supply = <&vreg_bob_3p3>; + vdd-l12-supply = <&vreg_s2b_1p224>; + vdd-l14-supply = <&vreg_s3b_0p752>; + vdd-l15-supply = <&vreg_s2b_1p224>; + vdd-l17-supply = <&vreg_s8b_0p824>; + vdd-l19-supply = <&vreg_s7b_0p936>; + vdd-l20-l21-supply = <&vreg_s7b_0p936>; + + vreg_s2b_1p224: smps2 { + regulator-name = "vreg_s2b_1p224"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + }; + + vreg_s3b_0p752: smps3 { + regulator-name = "vreg_s3b_0p752"; + regulator-min-microvolt = <684000>; + regulator-max-microvolt = <904000>; + }; + + vreg_s4b_1p824: smps4 { + regulator-name = "vreg_s4b_1p824"; + regulator-min-microvolt = <1824000>; + regulator-max-microvolt = <1904000>; + }; + + vreg_s7b_0p936: smps7 { + regulator-name = "vreg_s7b_0p936"; + regulator-min-microvolt = <352000>; + regulator-max-microvolt = <1060000>; + }; + + vreg_s8b_0p824: smps8 { + regulator-name = "vreg_s8b_0p824"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1100000>; + }; + + vreg_l1b_1p2: ldo1 { + regulator-name = "vreg_l1b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_1p128: ldo2 { + regulator-name = "vreg_l2b_1p128"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1160000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3b_0p896: ldo3 { + regulator-name = "vreg_l3b_0p896"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1040000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l4b_0p88: ldo4 { + regulator-name = "vreg_l4b_0p88"; + regulator-min-microvolt = <864000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5b_1p776: ldo5 { + regulator-name = "vreg_l5b_1p776"; + regulator-min-microvolt = <1770000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_0p904: ldo7 { + regulator-name = "vreg_l7b_0p904"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_0p8: ldo8 { + regulator-name = "vreg_l8b_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_0p752: ldo9 { + regulator-name = "vreg_l9b_0p752"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l10b_3p08: ldo10 { + regulator-name = "vreg_l10b_3p08"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3088000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11b_1p8: ldo11 { + regulator-name = "vreg_l11b_1p8"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name = "vreg_l12b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13b_1p8: ldo13 { + regulator-name = "vreg_l13b_1p8"; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_0p624: ldo14 { + regulator-name = "vreg_l14b_0p624"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_1p2: ldo15 { + regulator-name = "vreg_l15b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16b_0p912: ldo16 { + regulator-name = "vreg_l16b_0p912"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_0p752: ldo17 { + regulator-name = "vreg_l17b_0p752"; + regulator-min-microvolt = <684000>; + regulator-max-microvolt = <957600>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l19b_0p952: ldo19 { + regulator-name = "vreg_l19b_0p952"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l20b_0p912: ldo20 { + regulator-name = "vreg_l20b_0p912"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <952000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l21b_0p856: ldo21 { + regulator-name = "vreg_l21b_0p856"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + }; }; &chosen { diff --git a/arch/arm64/boot/dts/qcom/sdx75.dtsi b/arch/arm64/boot/dts/qcom/sdx75.dtsi index 21d5d55da5eb..e180aa4023ec 100644 --- a/arch/arm64/boot/dts/qcom/sdx75.dtsi +++ b/arch/arm64/boot/dts/qcom/sdx75.dtsi @@ -9,6 +9,8 @@ #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sdx75-gcc.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/qcom,rpmhpd.h> +#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / { @@ -469,6 +471,29 @@ interrupt-controller; }; + spmi_bus: spmi@c400000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c500000 0x0 0x400000>, + <0x0 0x0c440000 0x0 0x80000>, + <0x0 0x0c4c0000 0x0 0x10000>, + <0x0 0x0c42d000 0x0 0x4000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + qcom,ee = <0>; + qcom,channel = <0>; + qcom,bus-id = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + tlmm: pinctrl@f000000 { compatible = "qcom,sdx75-tlmm"; reg = <0x0 0x0f000000 0x0 0x400000>; @@ -484,14 +509,14 @@ tx-pins { pins = "gpio12"; function = "qup_se1_l2_mira"; - drive-strength= <2>; + drive-strength = <2>; bias-disable; }; rx-pins { pins = "gpio13"; function = "qup_se1_l3_mira"; - drive-strength= <2>; + drive-strength = <2>; bias-disable; }; }; @@ -643,6 +668,56 @@ clock-names = "xo"; #clock-cells = <1>; }; + + rpmhpd: power-controller { + compatible = "qcom,sdx75-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp-48 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; }; cpufreq_hw: cpufreq@17d91000 { diff --git a/arch/arm64/boot/dts/qcom/sm4450-qrd.dts b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts new file mode 100644 index 000000000000..00a1c81ca397 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm4450-qrd.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "sm4450.dtsi" +/ { + model = "Qualcomm Technologies, Inc. SM4450 QRD"; + compatible = "qcom,sm4450-qrd", "qcom,sm4450"; + + aliases { }; + + chosen { + bootargs = "console=hvc0"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm4450.dtsi b/arch/arm64/boot/dts/qcom/sm4450.dtsi new file mode 100644 index 000000000000..c4e5b33f5169 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm4450.dtsi @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks{ + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <76800000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + L2_100: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + L2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + L2_300: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + L2_400: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + L2_500: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + L2_600: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + #cooling-cells = <2>; + + L2_700: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <800>; + exit-latency-us = <750>; + min-residency-us = <4090>; + local-timer-stop; + }; + + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <600>; + exit-latency-us = <1550>; + min-residency-us = <4791>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <1050>; + exit-latency-us = <2500>; + min-residency-us = <5309>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41003344>; + entry-latency-us = <1561>; + exit-latency-us = <2801>; + min-residency-us = <8550>; + }; + }; + }; + + memory@a0000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0xa0000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&LITTLE_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&BIG_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cpu-cluster0 { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; + }; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm4450-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + qcom,pdc-ranges = <0 480 94>, <94 494 31>, + <125 63 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + intc: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ + <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17420000 0x0 0x1000>; + ranges = <0 0 0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17421000 { + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + }; + + frame@17423000 { + reg = <0x17423000 0x1000>; + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@17425000 { + reg = <0x17425000 0x1000>; + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@17427000 { + reg = <0x17427000 0x1000>; + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@17429000 { + reg = <0x17429000 0x1000>; + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@1742b000 { + reg = <0x1742b000 0x1000>; + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@1742d000 { + reg = <0x1742d000 0x1000>; + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts index 3ce9875e932c..9b70a87906dc 100644 --- a/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts +++ b/arch/arm64/boot/dts/qcom/sm6115-fxtec-pro1x.dts @@ -44,7 +44,7 @@ gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>; debounce-interval = <15>; linux,can-disable; - gpio-key,wakeup; + wakeup-source; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 55118577bf92..839c60351240 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -341,6 +341,72 @@ }; }; + rpm: remoteproc { + compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + + interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6115"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sm6115-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level = <RPM_SMD_LEVEL_MIN_SVS>; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level = <RPM_SMD_LEVEL_LOW_SVS>; + }; + + rpmpd_opp_svs: opp3 { + opp-level = <RPM_SMD_LEVEL_SVS>; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; + }; + + rpmpd_opp_nom: opp5 { + opp-level = <RPM_SMD_LEVEL_NOM>; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; + }; + + rpmpd_opp_turbo: opp7 { + opp-level = <RPM_SMD_LEVEL_TURBO>; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; + }; + }; + }; + }; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -440,68 +506,6 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-sm6115"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; - clocks = <&xo_board>; - clock-names = "xo"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,sm6115-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_min_svs: opp1 { - opp-level = <RPM_SMD_LEVEL_MIN_SVS>; - }; - - rpmpd_opp_low_svs: opp2 { - opp-level = <RPM_SMD_LEVEL_LOW_SVS>; - }; - - rpmpd_opp_svs: opp3 { - opp-level = <RPM_SMD_LEVEL_SVS>; - }; - - rpmpd_opp_svs_plus: opp4 { - opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; - }; - - rpmpd_opp_nom: opp5 { - opp-level = <RPM_SMD_LEVEL_NOM>; - }; - - rpmpd_opp_nom_plus: opp6 { - opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; - }; - - rpmpd_opp_turbo: opp7 { - opp-level = <RPM_SMD_LEVEL_TURBO>; - }; - - rpmpd_opp_turbo_plus: opp8 { - opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; - }; - }; - }; - }; - }; - smp2p-adsp { compatible = "qcom,smp2p"; qcom,smem = <443>, <429>; @@ -865,6 +869,11 @@ reg = <0x25b 0x1>; bits = <1 4>; }; + + gpu_speed_bin: gpu-speed-bin@6006 { + reg = <0x6006 0x2>; + bits = <5 8>; + }; }; rng: rng@1b53000 { @@ -1052,7 +1061,7 @@ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; - dma-channels = <10>; + dma-channels = <10>; dma-channel-mask = <0xf>; iommus = <&apps_smmu 0xf6 0x0>; #dma-cells = <3>; @@ -1316,6 +1325,104 @@ }; }; + gpu: gpu@5900000 { + compatible = "qcom,adreno-610.0", "qcom,adreno"; + reg = <0x0 0x05900000 0x0 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */ + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_BIMC_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>; + clock-names = "core", + "iface", + "mem_iface", + "alt_mem_iface", + "gmu", + "xo"; + + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&adreno_smmu 0 1>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + qcom,gmu = <&gmu_wrapper>; + + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + status = "disabled"; + + zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-320000000 { + opp-hz = /bits/ 64 <320000000>; + required-opps = <&rpmpd_opp_low_svs>; + opp-supported-hw = <0x1f>; + }; + + opp-465000000 { + opp-hz = /bits/ 64 <465000000>; + required-opps = <&rpmpd_opp_svs>; + opp-supported-hw = <0x1f>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmpd_opp_svs_plus>; + opp-supported-hw = <0x1f>; + }; + + opp-745000000 { + opp-hz = /bits/ 64 <745000000>; + required-opps = <&rpmpd_opp_nom>; + opp-supported-hw = <0xf>; + }; + + opp-820000000 { + opp-hz = /bits/ 64 <820000000>; + required-opps = <&rpmpd_opp_nom_plus>; + opp-supported-hw = <0x7>; + }; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + required-opps = <&rpmpd_opp_turbo>; + opp-supported-hw = <0x7>; + }; + + /* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */ + opp-950000000 { + opp-hz = /bits/ 64 <950000000>; + required-opps = <&rpmpd_opp_turbo_plus>; + opp-supported-hw = <0x4>; + }; + + opp-980000000 { + opp-hz = /bits/ 64 <980000000>; + required-opps = <&rpmpd_opp_turbo_plus>; + opp-supported-hw = <0x3>; + }; + }; + }; + + gmu_wrapper: gmu@596a000 { + compatible = "qcom,adreno-gmu-wrapper"; + reg = <0x0 0x0596a000 0x0 0x30000>; + reg-names = "gmu"; + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", "gx"; + }; + gpucc: clock-controller@5990000 { compatible = "qcom,sm6115-gpucc"; reg = <0x0 0x05990000 0x0 0x9000>; diff --git a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts index 81fdcaf48926..c2d15fc6c96b 100644 --- a/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts +++ b/arch/arm64/boot/dts/qcom/sm6115p-lenovo-j606f.dts @@ -65,9 +65,49 @@ }; }; -&dispcc { - /* HACK: disable until a panel driver is ready to retain simplefb */ - status = "disabled"; +&gpu { + status = "okay"; + + zap-shader { + firmware-name = "qcom/sm6115/LENOVO/J606F/a610_zap.mbn"; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&pm6125_l18>; + status = "okay"; + + panel: panel@0 { + compatible = "lenovo,j606f-boe-nt36523w", "novatek,nt36523w"; + reg = <0>; + + reset-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; + vddio-supply = <&pm6125_l9>; + + pinctrl-names = "default"; + pinctrl-0 = <&te_active &mdss_dsi_active>; + + rotation = <180>; /* Yep, it's mounted upside down! */ + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; +}; + +&mdss_dsi0_phy { + status = "okay"; }; &pm6125_gpios { @@ -212,8 +252,9 @@ }; pm6125_l18: l18 { - regulator-min-microvolt = <1104000>; - regulator-max-microvolt = <1312000>; + /* 1.104V-1.312V fixed @ 1.232V for DSIPHY */ + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1232000>; }; pm6125_l19: l19 { @@ -282,6 +323,20 @@ bias-pull-up; output-high; }; + + te_active: te-active-state { + pins = "gpio81"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + mdss_dsi_active: dsi-active-state { + pins = "gpio82"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; }; &ufs_mem_hc { diff --git a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts index 9f8a9ef398a2..fb4cba004367 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dts @@ -42,7 +42,7 @@ extcon_usb: extcon-usb { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; }; gpio-keys { @@ -79,7 +79,7 @@ reg = <0x0 0xffc40000 0x0 0xc0000>; record-size = <0x1000>; console-size = <0x40000>; - msg-size = <0x20000 0x20000>; + pmsg-size = <0x20000>; }; cmdline_mem: memory@ffd00000 { @@ -183,39 +183,44 @@ pinctrl-names = "default"; pinctrl-0 = <&camera_flash_therm &emmc_ufs_therm &rf_pa1_therm>; - rf-pa0-therm@4d { + channel@4d { reg = <ADC5_AMUX_THM1_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "rf_pa0_therm"; }; - quiet-therm@4e { + channel@4e { reg = <ADC5_AMUX_THM2_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "quiet_therm"; }; - camera-flash-therm@52 { + channel@52 { reg = <ADC5_GPIO1_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "camera_flash_therm"; }; - emmc-ufs-therm@54 { + channel@54 { reg = <ADC5_GPIO3_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "emmc_ufs_therm"; }; - rf-pa1-therm@55 { + channel@55 { reg = <ADC5_GPIO4_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; qcom,pre-scaling = <1 1>; + label = "rf_pa1_therm"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts index a7f4aeae9c1a..272bc85f1719 100644 --- a/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts +++ b/arch/arm64/boot/dts/qcom/sm6125-xiaomi-laurel-sprout.dts @@ -52,7 +52,7 @@ reg = <0x0 0xffc40000 0x0 0xc0000>; record-size = <0x1000>; console-size = <0x40000>; - msg-size = <0x20000 0x20000>; + pmsg-size = <0x20000>; }; cmdline_mem: memory@ffd00000 { @@ -63,7 +63,7 @@ extcon_usb: usb-id { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; + id-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; }; gpio-keys { diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index a596baa6ce3e..d7c1a40617c6 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -181,6 +181,78 @@ method = "smc"; }; + rpm: remoteproc { + compatible = "qcom,sm6125-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + + interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6125"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,sm6125-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_ret: opp1 { + opp-level = <RPM_SMD_LEVEL_RETENTION>; + }; + + rpmpd_opp_ret_plus: opp2 { + opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; + }; + + rpmpd_opp_min_svs: opp3 { + opp-level = <RPM_SMD_LEVEL_MIN_SVS>; + }; + + rpmpd_opp_low_svs: opp4 { + opp-level = <RPM_SMD_LEVEL_LOW_SVS>; + }; + + rpmpd_opp_svs: opp5 { + opp-level = <RPM_SMD_LEVEL_SVS>; + }; + + rpmpd_opp_svs_plus: opp6 { + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; + }; + + rpmpd_opp_nom: opp7 { + opp-level = <RPM_SMD_LEVEL_NOM>; + }; + + rpmpd_opp_nom_plus: opp8 { + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; + }; + + rpmpd_opp_turbo: opp9 { + opp-level = <RPM_SMD_LEVEL_TURBO>; + }; + + rpmpd_opp_turbo_no_cpr: opp10 { + opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; + }; + }; + }; + }; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -292,74 +364,6 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - - interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&apcs_glb 0>; - - rpm_requests: rpm-requests { - compatible = "qcom,rpm-sm6125"; - qcom,glink-channels = "rpm_requests"; - - rpmcc: clock-controller { - compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; - #clock-cells = <1>; - }; - - rpmpd: power-controller { - compatible = "qcom,sm6125-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; - - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; - - rpmpd_opp_ret: opp1 { - opp-level = <RPM_SMD_LEVEL_RETENTION>; - }; - - rpmpd_opp_ret_plus: opp2 { - opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; - }; - - rpmpd_opp_min_svs: opp3 { - opp-level = <RPM_SMD_LEVEL_MIN_SVS>; - }; - - rpmpd_opp_low_svs: opp4 { - opp-level = <RPM_SMD_LEVEL_LOW_SVS>; - }; - - rpmpd_opp_svs: opp5 { - opp-level = <RPM_SMD_LEVEL_SVS>; - }; - - rpmpd_opp_svs_plus: opp6 { - opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; - }; - - rpmpd_opp_nom: opp7 { - opp-level = <RPM_SMD_LEVEL_NOM>; - }; - - rpmpd_opp_nom_plus: opp8 { - opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; - }; - - rpmpd_opp_turbo: opp9 { - opp-level = <RPM_SMD_LEVEL_TURBO>; - }; - - rpmpd_opp_turbo_no_cpr: opp10 { - opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; - }; - }; - }; - }; - }; - smem: smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 30e77010aed5..8fd6f4d03490 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -4,7 +4,9 @@ * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> */ +#include <dt-bindings/clock/qcom,dispcc-sm6350.h> #include <dt-bindings/clock/qcom,gcc-sm6350.h> +#include <dt-bindings/clock/qcom,gpucc-sm6350.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/clock/qcom,sm6350-camcc.h> #include <dt-bindings/dma/qcom-gpi.h> @@ -633,11 +635,6 @@ no-map; }; - pil_gpu_mem: memory@8b715400 { - reg = <0 0x8b715400 0 0x2000>; - no-map; - }; - pil_modem_mem: memory@8b800000 { reg = <0 0x8b800000 0 0xf800000>; no-map; @@ -658,6 +655,11 @@ no-map; }; + pil_gpu_mem: memory@f0d00000 { + reg = <0 0xf0d00000 0 0x1000>; + no-map; + }; + debug_region: memory@ffb00000 { reg = <0 0xffb00000 0 0xc0000>; no-map; @@ -673,7 +675,7 @@ reg = <0 0xffc00000 0 0x100000>; record-size = <0x1000>; console-size = <0x40000>; - msg-size = <0x20000 0x20000>; + pmsg-size = <0x20000>; ecc-size = <16>; no-map; }; @@ -804,6 +806,18 @@ #mbox-cells = <2>; }; + qfprom: qfprom@784000 { + compatible = "qcom,sm6350-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@2015 { + reg = <0x2015 0x1>; + bits = <0 8>; + }; + }; + rng: rng@793000 { compatible = "qcom,prng-ee"; reg = <0 0x00793000 0 0x1000>; @@ -1308,6 +1322,159 @@ }; }; + gpu: gpu@3d00000 { + compatible = "qcom,adreno-619.0", "qcom,adreno"; + reg = <0 0x03d00000 0 0x40000>, + <0 0x03d9e000 0 0x1000>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem"; + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&adreno_smmu 0>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + + status = "disabled"; + + zap-shader { + memory-region = <&pil_gpu_mem>; + }; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-850000000 { + opp-hz = /bits/ 64 <850000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + opp-supported-hw = <0x02>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + opp-supported-hw = <0x04>; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + opp-supported-hw = <0x08>; + }; + + opp-565000000 { + opp-hz = /bits/ 64 <565000000>; + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + opp-supported-hw = <0x10>; + }; + + opp-430000000 { + opp-hz = /bits/ 64 <430000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + opp-supported-hw = <0xff>; + }; + + opp-355000000 { + opp-hz = /bits/ 64 <355000000>; + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + opp-supported-hw = <0xff>; + }; + + opp-253000000 { + opp-hz = /bits/ 64 <253000000>; + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + opp-supported-hw = <0xff>; + }; + }; + }; + + adreno_smmu: iommu@3d40000 { + compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; + reg = <0 0x03d40000 0 0x10000>; + #iommu-cells = <1>; + #global-interrupts = <2>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "ahb", + "bus", + "iface"; + + power-domains = <&gpucc GPU_CX_GDSC>; + }; + + gmu: gmu@3d6a000 { + compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; + reg = <0 0x03d6a000 0 0x31000>, + <0 0x0b290000 0 0x10000>, + <0 0x0b490000 0 0x10000>; + reg-names = "gmu", + "gmu_pdc", + "gmu_pdc_seq"; + + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hfi", + "gmu"; + + clocks = <&gpucc GPU_CC_AHB_CLK>, + <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_CXO_CLK>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + clock-names = "ahb", + "gmu", + "cxo", + "axi", + "memnoc"; + + power-domains = <&gpucc GPU_CX_GDSC>, + <&gpucc GPU_GX_GDSC>; + power-domain-names = "cx", + "gx"; + + iommus = <&adreno_smmu 5>; + + operating-points-v2 = <&gmu_opp_table>; + + status = "disabled"; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + }; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm6350-gpucc"; + reg = <0 0x03d90000 0 0x9000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK>, + <&gcc GCC_GPU_GPLL0_DIV_CLK>; + clock-names = "bi_tcxo", + "gcc_gpu_gpll0_clk_src", + "gcc_gpu_gpll0_div_clk_src"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mpss: remoteproc@4080000 { compatible = "qcom,sm6350-mpss-pas"; reg = <0x0 0x04080000 0x0 0x4040>; @@ -1556,6 +1723,103 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + pmu@90b6300 { + compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon"; + reg = <0x0 0x090b6300 0x0 0x600>; + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + interconnects = <&clk_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <2288000>; + }; + + opp-1 { + opp-peak-kBps = <4577000>; + }; + + opp-2 { + opp-peak-kBps = <7110000>; + }; + + opp-3 { + opp-peak-kBps = <9155000>; + }; + + opp-4 { + opp-peak-kBps = <12298000>; + }; + + opp-5 { + opp-peak-kBps = <14236000>; + }; + + }; + }; + + pmu@90cd000 { + compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0x0 0x090cd000 0x0 0x1000>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <762000>; + }; + + opp-1 { + opp-peak-kBps = <1144000>; + }; + + opp-2 { + opp-peak-kBps = <1720000>; + }; + + opp-3 { + opp-peak-kBps = <2086000>; + }; + + opp-4 { + opp-peak-kBps = <2597000>; + }; + + opp-5 { + opp-peak-kBps = <2929000>; + }; + + opp-6 { + opp-peak-kBps = <3879000>; + }; + + opp-7 { + opp-peak-kBps = <5161000>; + }; + + opp-8 { + opp-peak-kBps = <5931000>; + }; + + opp-9 { + opp-peak-kBps = <6881000>; + }; + + opp-10 { + opp-peak-kBps = <7980000>; + }; + }; + }; + usb_1: usb@a6f8800 { compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; @@ -1703,6 +1967,223 @@ #power-domain-cells = <1>; }; + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm6350-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", + "bus", + "core"; + + power-domains = <&dispcc MDSS_GDSC>; + iommus = <&apps_smmu 0x800 0x2>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm6350-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&gcc GCC_DISP_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "iface", + "rot", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM6350_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-373333333 { + opp-hz = /bits/ 64 <373333333>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-448000000 { + opp-hz = /bits/ 64 <448000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-560000000 { + opp-hz = /bits/ 64 <560000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd SM6350_MX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-10nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94a00 0 0x1e0>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm6350-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_DISP_GPLL0_CLK>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; + clock-names = "bi_tcxo", + "gcc_disp_gpll0_clk", + "dsi0_phy_pll_out_byteclk", + "dsi0_phy_pll_out_dsiclk", + "dp_phy_pll_link_clk", + "dp_phy_pll_vco_div_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm6350-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; @@ -1780,6 +2261,7 @@ interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 157>; + wakeup-parent = <&pdc>; cci0_default: cci0-default-state { pins = "gpio39", "gpio40"; diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 3dba34210a6d..e7ff55443da7 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/qcom,sm6375-gpucc.h> #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/firmware/qcom,scm.h> +#include <dt-bindings/interconnect/qcom,osm-l3.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/power/qcom-rpmpd.h> @@ -45,6 +46,8 @@ enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -69,6 +72,8 @@ enable-method = "psci"; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -88,6 +93,8 @@ enable-method = "psci"; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -107,6 +114,8 @@ enable-method = "psci"; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -126,6 +135,8 @@ enable-method = "psci"; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -145,6 +156,8 @@ enable-method = "psci"; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 0>; + operating-points-v2 = <&cpu0_opp_table>; + interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -164,6 +177,8 @@ enable-method = "psci"; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -183,6 +198,8 @@ enable-method = "psci"; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1>; + operating-points-v2 = <&cpu6_opp_table>; + interconnects = <&cpucp_l3 MASTER_EPSS_L3_APPS &cpucp_l3 SLAVE_EPSS_L3_SHARED>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; #cooling-cells = <2>; @@ -300,6 +317,116 @@ reg = <0x0 0x80000000 0x0 0x0>; }; + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-peak-kBps = <(300000 * 32)>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + opp-peak-kBps = <(556800 * 32)>; + }; + + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <(652800 * 32)>; + }; + + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <(921600 * 32)>; + }; + + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + opp-peak-kBps = <(921600 * 32)>; + }; + + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + opp-peak-kBps = <(1171200 * 32)>; + }; + + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + + opp-1708800000 { + opp-hz = /bits/ 64 <1708800000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + }; + + cpu6_opp_table: opp-table-cpu6 { + compatible = "operating-points-v2"; + opp-shared; + + opp-691200000 { + opp-hz = /bits/ 64 <691200000>; + opp-peak-kBps = <(556800 * 32)>; + }; + + opp-940800000 { + opp-hz = /bits/ 64 <940800000>; + opp-peak-kBps = <(921600 * 32)>; + }; + + opp-1228800000 { + opp-hz = /bits/ 64 <1228800000>; + opp-peak-kBps = <(1171200 * 32)>; + }; + + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + opp-peak-kBps = <(1382400 * 32)>; + }; + + opp-1516800000 { + opp-hz = /bits/ 64 <1516800000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + + opp-2054400000 { + opp-hz = /bits/ 64 <2054400000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-peak-kBps = <(1497600 * 32)>; + }; + }; + pmu { compatible = "arm,armv8-pmuv3"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; @@ -494,67 +621,71 @@ }; }; - rpm-glink { - compatible = "qcom,glink-rpm"; - interrupts-extended = <&ipcc IPCC_CLIENT_AOP - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; - qcom,rpm-msg-ram = <&rpm_msg_ram>; - mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + rpm: remoteproc { + compatible = "qcom,sm6375-rpm-proc", "qcom,rpm-proc"; - rpm_requests: rpm-requests { - compatible = "qcom,rpm-sm6375"; - qcom,glink-channels = "rpm_requests"; + glink-edge { + compatible = "qcom,glink-rpm"; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; - rpmcc: clock-controller { - compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc"; - clocks = <&xo_board_clk>; - clock-names = "xo"; - #clock-cells = <1>; - }; + rpm_requests: rpm-requests { + compatible = "qcom,rpm-sm6375"; + qcom,glink-channels = "rpm_requests"; - rpmpd: power-controller { - compatible = "qcom,sm6375-rpmpd"; - #power-domain-cells = <1>; - operating-points-v2 = <&rpmpd_opp_table>; + rpmcc: clock-controller { + compatible = "qcom,rpmcc-sm6375", "qcom,rpmcc"; + clocks = <&xo_board_clk>; + clock-names = "xo"; + #clock-cells = <1>; + }; - rpmpd_opp_table: opp-table { - compatible = "operating-points-v2"; + rpmpd: power-controller { + compatible = "qcom,sm6375-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; - rpmpd_opp_ret: opp1 { - opp-level = <RPM_SMD_LEVEL_RETENTION>; - }; + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; - rpmpd_opp_min_svs: opp2 { - opp-level = <RPM_SMD_LEVEL_MIN_SVS>; - }; + rpmpd_opp_ret: opp1 { + opp-level = <RPM_SMD_LEVEL_RETENTION>; + }; - rpmpd_opp_low_svs: opp3 { - opp-level = <RPM_SMD_LEVEL_LOW_SVS>; - }; + rpmpd_opp_min_svs: opp2 { + opp-level = <RPM_SMD_LEVEL_MIN_SVS>; + }; - rpmpd_opp_svs: opp4 { - opp-level = <RPM_SMD_LEVEL_SVS>; - }; + rpmpd_opp_low_svs: opp3 { + opp-level = <RPM_SMD_LEVEL_LOW_SVS>; + }; - rpmpd_opp_svs_plus: opp5 { - opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; - }; + rpmpd_opp_svs: opp4 { + opp-level = <RPM_SMD_LEVEL_SVS>; + }; - rpmpd_opp_nom: opp6 { - opp-level = <RPM_SMD_LEVEL_NOM>; - }; + rpmpd_opp_svs_plus: opp5 { + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; + }; - rpmpd_opp_nom_plus: opp7 { - opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; - }; + rpmpd_opp_nom: opp6 { + opp-level = <RPM_SMD_LEVEL_NOM>; + }; - rpmpd_opp_turbo: opp8 { - opp-level = <RPM_SMD_LEVEL_TURBO>; - }; + rpmpd_opp_nom_plus: opp7 { + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; + }; + + rpmpd_opp_turbo: opp8 { + opp-level = <RPM_SMD_LEVEL_TURBO>; + }; - rpmpd_opp_turbo_no_cpr: opp9 { - opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; + rpmpd_opp_turbo_no_cpr: opp9 { + opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index e3dc49951523..18171c5d8a38 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -476,7 +476,7 @@ }; &pm7250b_adc { - adc-chan@4d { + channel@4d { reg = <ADC5_AMUX_THM1_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -484,7 +484,7 @@ label = "charger_skin_therm"; }; - adc-chan@4f { + channel@4f { reg = <ADC5_AMUX_THM3_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; @@ -516,7 +516,7 @@ }; &pmk8350_vadc { - adc-chan@644 { + channel@644 { reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts index c0200e7f3f74..bb161b536da4 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -15,6 +15,7 @@ / { model = "Qualcomm Technologies, Inc. SM8150 HDK"; compatible = "qcom,sm8150-hdk", "qcom,sm8150"; + chassis-type = "embedded"; aliases { serial0 = &uart2; diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts index 34ec84916bdd..286350ac7751 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts @@ -16,6 +16,7 @@ / { model = "Qualcomm Technologies, Inc. SM8150 MTP"; compatible = "qcom,sm8150-mtp", "qcom,sm8150"; + chassis-type = "handset"; aliases { serial0 = &uart2; diff --git a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi index baafea53770b..ae0ca48b89a5 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150-sony-xperia-kumano.dtsi @@ -222,7 +222,7 @@ reg = <0x0 0xffc00000 0x0 0x100000>; record-size = <0x1000>; console-size = <0x40000>; - msg-size = <0x20000 0x20000>; + pmsg-size = <0x20000>; ecc-size = <16>; no-map; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index b46e55bb8bde..a7c3020a5de4 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1231,7 +1231,7 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_default>; - interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -3840,7 +3840,7 @@ }; mdss_dsi0_phy: phy@ae94400 { - compatible = "qcom,dsi-phy-7nm"; + compatible = "qcom,dsi-phy-7nm-8150"; reg = <0 0x0ae94400 0 0x200>, <0 0x0ae94600 0 0x280>, <0 0x0ae94900 0 0x260>; @@ -3914,7 +3914,7 @@ }; mdss_dsi1_phy: phy@ae96400 { - compatible = "qcom,dsi-phy-7nm"; + compatible = "qcom,dsi-phy-7nm-8150"; reg = <0 0x0ae96400 0 0x200>, <0 0x0ae96600 0 0x280>, <0 0x0ae96900 0 0x260>; diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts index 0aee7f8658b4..1bbb71e1a4fc 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts @@ -14,6 +14,7 @@ / { model = "Qualcomm Technologies, Inc. SM8250 HDK"; compatible = "qcom,sm8250-hdk", "qcom,sm8250"; + chassis-type = "embedded"; aliases { serial0 = &uart12; diff --git a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts index 4c9de236676d..7ef99038cb37 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-mtp.dts @@ -18,6 +18,7 @@ / { model = "Qualcomm Technologies, Inc. SM8250 MTP"; compatible = "qcom,sm8250-mtp", "qcom,sm8250"; + chassis-type = "handset"; aliases { serial0 = &uart12; @@ -525,22 +526,25 @@ }; &pm8150_adc { - xo-therm@4c { + channel@4c { reg = <ADC5_XO_THERM_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "xo_therm"; }; - skin-therm@4d { + channel@4d { reg = <ADC5_AMUX_THM1_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "skin_therm"; }; - pa-therm1@4e { + channel@4e { reg = <ADC5_AMUX_THM2_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "pa_therm1"; }; }; @@ -570,10 +574,11 @@ }; &pm8150b_adc { - conn-therm@4f { + channel@4f { reg = <ADC5_AMUX_THM3_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "conn_therm"; }; }; @@ -614,22 +619,25 @@ }; &pm8150l_adc { - camera-flash-therm@4d { + channel@4d { reg = <ADC5_AMUX_THM1_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "camera_flash_therm"; }; - skin-msm-therm@4e { + channel@4e { reg = <ADC5_AMUX_THM2_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "skin_msm_therm"; }; - pa-therm2@4f { + channel@4f { reg = <ADC5_AMUX_THM3_100K_PU>; qcom,ratiometric; qcom,hw-settle-time = <200>; + label = "pa_therm2"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts index 356a81698731..b70bf9261ba9 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx203.dts @@ -14,3 +14,369 @@ }; /delete-node/ &vreg_l7f_1p8; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + pmic@75 { + compatible = "dlg,slg51000"; + reg = <0x75>; + dlg,cs-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>; + vin5-supply = <&vreg_s1f_1p2>; + vin6-supply = <&vreg_s1f_1p2>; + + pinctrl-0 = <&cam_pwr_b_cs>; + pinctrl-names = "default"; + + regulators { + slg51000_1_ldo1: ldo1 { + regulator-name = "slg51000_b_ldo1"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_1_ldo2: ldo2 { + regulator-name = "slg51000_b_ldo2"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_1_ldo3: ldo3 { + regulator-name = "slg51000_b_ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_1_ldo4: ldo4 { + regulator-name = "slg51000_b_ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_1_ldo5: ldo5 { + regulator-name = "slg51000_b_ldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_1_ldo6: ldo6 { + regulator-name = "slg51000_b_ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_1_ldo7: ldo7 { + regulator-name = "slg51000_b_ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + }; + }; +}; + +&i2c15 { + pmic@75 { + compatible = "dlg,slg51000"; + reg = <0x75>; + dlg,cs-gpios = <&tlmm 71 GPIO_ACTIVE_HIGH>; + vin5-supply = <&vreg_l2f_1p3>; + vin6-supply = <&vreg_l2f_1p3>; + + pinctrl-0 = <&cam_pwr_a_cs>; + pinctrl-names = "default"; + + regulators { + slg51000_0_ldo1: ldo1 { + regulator-name = "slg51000_a_ldo1"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_0_ldo2: ldo2 { + regulator-name = "slg51000_a_ldo2"; + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + slg51000_0_ldo3: ldo3 { + regulator-name = "slg51000_a_ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_0_ldo4: ldo4 { + regulator-name = "slg51000_a_ldo4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + + slg51000_0_ldo5: ldo5 { + regulator-name = "slg51000_a_ldo5"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_0_ldo6: ldo6 { + regulator-name = "slg51000_a_ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1200000>; + }; + + slg51000_0_ldo7: ldo7 { + regulator-name = "slg51000_a_ldo7"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3750000>; + }; + }; + }; +}; + +&pm8009_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "CAM_PWR_LD_EN", + "WIDEC_PWR_EN", + "NC"; +}; + +&pm8150_gpios { + gpio-line-names = "VOL_DOWN_N", /* GPIO_1 */ + "OPTION_2", + "NC", + "PM_SLP_CLK_IN", + "OPTION_1", + "NC", + "NC", + "SP_ARI_PWR_ALARM", + "NC", + "NC"; /* GPIO_10 */ +}; + +&pm8150b_gpios { + gpio-line-names = "SNAPSHOT_N", /* GPIO_1 */ + "FOCUS_N", + "NC", + "NC", + "RF_LCD_ID_EN", + "NC", + "NC", + "LCD_ID", + "NC", + "WLC_EN_N", /* GPIO_10 */ + "NC", + "RF_ID"; +}; + +&pm8150l_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "PM3003A_EN", + "NC", + "NC", + "NC", + "AUX2_THERM", + "BB_HP_EN", + "FP_LDO_EN", + "PMX_RESET_N", + "AUX3_THERM", /* GPIO_10 */ + "DTV_PWR_EN", + "PM3003A_MODE"; +}; + +&tlmm { + gpio-line-names = "AP_CTI_IN", /* GPIO_0 */ + "MDM2AP_ERR_FATAL", + "AP_CTI_OUT", + "MDM2AP_STATUS", + "NFC_I2C_SDA", + "NFC_I2C_SCL", + "NFC_EN", + "NFC_CLK_REQ", + "NFC_ESE_PWR_REQ", + "DVDT_WRT_DET_AND", + "SPK_AMP_RESET_N", /* GPIO_10 */ + "SPK_AMP_INT_N", + "APPS_I2C_1_SDA", + "APPS_I2C_1_SCL", + "NC", + "TX_GTR_THRES_IN", + "HST_BT_UART_CTS", + "HST_BT_UART_RFR", + "HST_BT_UART_TX", + "HST_BT_UART_RX", + "HST_WLAN_EN", /* GPIO_20 */ + "HST_BT_EN", + "RGBC_IR_PWR_EN", + "FP_INT_N", + "NC", + "NC", + "NC", + "NC", + "NFC_ESE_SPI_MISO", + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_SCLK", /* GPIO_30 */ + "NFC_ESE_SPI_CS_N", + "WCD_RST_N", + "NC", + "SDM_DEBUG_UART_TX", + "SDM_DEBUG_UART_RX", + "TS_I2C_SDA", + "TS_I2C_SCL", + "TS_INT_N", + "FP_SPI_MISO", /* GPIO_40 */ + "FP_SPI_MOSI", + "FP_SPI_SCLK", + "FP_SPI_CS_N", + "APPS_I2C_0_SDA", + "APPS_I2C_0_SCL", + "DISP_ERR_FG", + "UIM2_DETECT_EN", + "NC", + "NC", + "NC", /* GPIO_50 */ + "NC", + "MDM_UART_CTS", + "MDM_UART_RFR", + "MDM_UART_TX", + "MDM_UART_RX", + "AP2MDM_STATUS", + "AP2MDM_ERR_FATAL", + "MDM_IPC_HS_UART_TX", + "MDM_IPC_HS_UART_RX", + "NC", /* GPIO_60 */ + "NC", + "NC", + "NC", + "NC", + "USB_CC_DIR", + "DISP_VSYNC", + "NC", + "NC", + "CAM_PWR_B_CS", + "NC", /* GPIO_70 */ + "CAM_PWR_A_CS", + "SBU_SW_SEL", + "SBU_SW_OE", + "FP_RESET_N", + "FP_RESET_N", + "DISP_RESET_N", + "DEBUG_GPIO0", + "TRAY_DET", + "CAM2_RST_N", + "PCIE0_RST_N", + "PCIE0_CLK_REQ_N", /* GPIO_80 */ + "PCIE0_WAKE_N", + "DVDT_ENABLE", + "DVDT_WRT_DET_OR", + "NC", + "PCIE2_RST_N", + "PCIE2_CLK_REQ_N", + "PCIE2_WAKE_N", + "MDM_VFR_IRQ0", + "MDM_VFR_IRQ1", + "SW_SERVICE", /* GPIO_90 */ + "CAM_SOF", + "CAM1_RST_N", + "CAM0_RST_N", + "CAM0_MCLK", + "CAM1_MCLK", + "CAM2_MCLK", + "CAM3_MCLK", + "CAM4_MCLK", + "TOF_RST_N", + "NC", /* GPIO_100 */ + "CCI0_I2C_SDA", + "CCI0_I2C_SCL", + "CCI1_I2C_SDA", + "CCI1_I2C_SCL_", + "CCI2_I2C_SDA", + "CCI2_I2C_SCL", + "CCI3_I2C_SDA", + "CCI3_I2C_SCL", + "CAM3_RST_N", + "NFC_DWL_REQ", /* GPIO_110 */ + "NFC_IRQ", + "XVS", + "NC", + "RF_ID_EXTENSION", + "SPK_AMP_I2C_SDA", + "SPK_AMP_I2C_SCL", + "NC", + "NC", + "WLC_I2C_SDA", + "WLC_I2C_SCL", /* GPIO_120 */ + "ACC_COVER_OPEN", + "ALS_PROX_INT_N", + "ACCEL_INT", + "WLAN_SW_CTRL", + "CAMSENSOR_I2C_SDA", + "CAMSENSOR_I2C_SCL", + "UDON_SWITCH_SEL", + "WDOG_DISABLE", + "BAROMETER_INT", + "NC", /* GPIO_130 */ + "NC", + "FORCED_USB_BOOT", + "NC", + "NC", + "WLC_INT_N", + "NC", + "NC", + "RGBC_IR_INT", + "NC", + "NC", /* GPIO_140 */ + "NC", + "BT_SLIMBUS_CLK", + "BT_SLIMBUS_DATA", + "HW_ID_0", + "HW_ID_1", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", /* GPIO_150 */ + "WCD_SWR_RX_DATA1", + "SDM_DMIC_CLK1", + "SDM_DMIC_DATA1", + "SDM_DMIC_CLK2", + "SDM_DMIC_DATA2", + "SPK_AMP_I2S_CLK", + "SPK_AMP_I2S_WS", + "SPK_AMP_I2S_ASP_DIN", + "SPK_AMP_I2S_ASP_DOUT", + "COMPASS_I2C_SDA", /* GPIO_160 */ + "COMPASS_I2C_SCL", + "NC", + "NC", + "SSC_SPI_1_MISO", + "SSC_SPI_1_MOSI", + "SSC_SPI_1_CLK", + "SSC_SPI_1_CS_N", + "NC", + "NC", + "SSC_SENSOR_I2C_SDA", /* GPIO_170 */ + "SSC_SENSOR_I2C_SCL", + "NC", + "NC", + "NC", + "NC", + "HST_BLE_SNS_UART6_TX", + "HST_BLE_SNS_UART6_RX", + "HST_WLAN_UART_TX", + "HST_WLAN_UART_RX"; + + cam_pwr_b_cs: cam-pwr-b-state { + pins = "gpio69"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; + + cam_pwr_a_cs: cam-pwr-a-state { + pins = "gpio71"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-low; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts index 01fe3974ee72..58a521046f5f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo-pdx206.dts @@ -20,6 +20,8 @@ }; &gpio_keys { + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n &g_assist_n>; + g-assist-key { label = "Google Assistant Key"; linux,code = <KEY_LEFTMETA>; @@ -30,6 +32,247 @@ }; }; +&pm8009_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "NC", + "WIDEC_PWR_EN", + "NC"; +}; + +&pm8150_gpios { + gpio-line-names = "VOL_DOWN_N", /* GPIO_1 */ + "OPTION_2", + "NC", + "PM_SLP_CLK_IN", + "OPTION_1", + "G_ASSIST_N", + "NC", + "SP_ARI_PWR_ALARM", + "NC", + "NC"; /* GPIO_10 */ + + g_assist_n: g-assist-n-state { + pins = "gpio6"; + function = "normal"; + power-source = <1>; + bias-pull-up; + input-enable; + }; +}; + +&pm8150b_gpios { + gpio-line-names = "SNAPSHOT_N", /* GPIO_1 */ + "FOCUS_N", + "NC", + "NC", + "RF_LCD_ID_EN", + "NC", + "NC", + "LCD_ID", + "NC", + "NC", /* GPIO_10 */ + "NC", + "RF_ID"; +}; + +&pm8150l_gpios { + gpio-line-names = "NC", /* GPIO_1 */ + "PM3003A_EN", + "NC", + "NC", + "NC", + "AUX2_THERM", + "BB_HP_EN", + "FP_LDO_EN", + "PMX_RESET_N", + "NC", /* GPIO_10 */ + "NC", + "PM3003A_MODE"; +}; + +&tlmm { + gpio-line-names = "AP_CTI_IN", /* GPIO_0 */ + "MDM2AP_ERR_FATAL", + "AP_CTI_OUT", + "MDM2AP_STATUS", + "NFC_I2C_SDA", + "NFC_I2C_SCL", + "NFC_EN", + "NFC_CLK_REQ", + "NFC_ESE_PWR_REQ", + "DVDT_WRT_DET_AND", + "SPK_AMP_RESET_N", /* GPIO_10 */ + "SPK_AMP_INT_N", + "APPS_I2C_1_SDA", + "APPS_I2C_1_SCL", + "NC", + "TX_GTR_THRES_IN", + "HST_BT_UART_CTS", + "HST_BT_UART_RFR", + "HST_BT_UART_TX", + "HST_BT_UART_RX", + "HST_WLAN_EN", /* GPIO_20 */ + "HST_BT_EN", + "RGBC_IR_PWR_EN", + "FP_INT_N", + "NC", + "NC", + "NC", + "NC", + "NFC_ESE_SPI_MISO", + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_SCLK", /* GPIO_30 */ + "NFC_ESE_SPI_CS_N", + "WCD_RST_N", + "NC", + "SDM_DEBUG_UART_TX", + "SDM_DEBUG_UART_RX", + "TS_I2C_SDA", + "TS_I2C_SCL", + "TS_INT_N", + "FP_SPI_MISO", /* GPIO_40 */ + "FP_SPI_MOSI", + "FP_SPI_SCLK", + "FP_SPI_CS_N", + "APPS_I2C_0_SDA", + "APPS_I2C_0_SCL", + "DISP_ERR_FG", + "UIM2_DETECT_EN", + "NC", + "NC", + "NC", /* GPIO_50 */ + "NC", + "MDM_UART_CTS", + "MDM_UART_RFR", + "MDM_UART_TX", + "MDM_UART_RX", + "AP2MDM_STATUS", + "AP2MDM_ERR_FATAL", + "MDM_IPC_HS_UART_TX", + "MDM_IPC_HS_UART_RX", + "NC", /* GPIO_60 */ + "NC", + "NC", + "NC", + "NC", + "USB_CC_DIR", + "DISP_VSYNC", + "NC", + "NC", + "CAM_PWR_B_CS", + "NC", /* GPIO_70 */ + "FRONTC_PWR_EN", + "SBU_SW_SEL", + "SBU_SW_OE", + "FP_RESET_N", + "FP_RESET_N", + "DISP_RESET_N", + "DEBUG_GPIO0", + "TRAY_DET", + "CAM2_RST_N", + "PCIE0_RST_N", + "PCIE0_CLK_REQ_N", /* GPIO_80 */ + "PCIE0_WAKE_N", + "DVDT_ENABLE", + "DVDT_WRT_DET_OR", + "NC", + "PCIE2_RST_N", + "PCIE2_CLK_REQ_N", + "PCIE2_WAKE_N", + "MDM_VFR_IRQ0", + "MDM_VFR_IRQ1", + "SW_SERVICE", /* GPIO_90 */ + "CAM_SOF", + "CAM1_RST_N", + "CAM0_RST_N", + "CAM0_MCLK", + "CAM1_MCLK", + "CAM2_MCLK", + "CAM3_MCLK", + "NC", + "NC", + "NC", /* GPIO_100 */ + "CCI0_I2C_SDA", + "CCI0_I2C_SCL", + "CCI1_I2C_SDA", + "CCI1_I2C_SCL_", + "CCI2_I2C_SDA", + "CCI2_I2C_SCL", + "CCI3_I2C_SDA", + "CCI3_I2C_SCL", + "CAM3_RST_N", + "NFC_DWL_REQ", /* GPIO_110 */ + "NFC_IRQ", + "XVS", + "NC", + "RF_ID_EXTENSION", + "SPK_AMP_I2C_SDA", + "SPK_AMP_I2C_SCL", + "NC", + "NC", + "NC", + "NC", + "ACC_COVER_OPEN", + "ALS_PROX_INT_N", + "ACCEL_INT", + "WLAN_SW_CTRL", + "CAMSENSOR_I2C_SDA", + "CAMSENSOR_I2C_SCL", + "UDON_SWITCH_SEL", + "WDOG_DISABLE", + "BAROMETER_INT", + "NC", /* GPIO_130 */ + "NC", + "FORCED_USB_BOOT", + "NC", + "NC", + "NC", + "NC", + "NC", + "RGBC_IR_INT", + "NC", + "NC", /* GPIO_140 */ + "NC", + "BT_SLIMBUS_CLK", + "BT_SLIMBUS_DATA", + "HW_ID_0", + "HW_ID_1", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", /* GPIO_150 */ + "WCD_SWR_RX_DATA1", + "SDM_DMIC_CLK1", + "SDM_DMIC_DATA1", + "SDM_DMIC_CLK2", + "SDM_DMIC_DATA2", + "SPK_AMP_I2S_CLK", + "SPK_AMP_I2S_WS", + "SPK_AMP_I2S_ASP_DIN", + "SPK_AMP_I2S_ASP_DOUT", + "COMPASS_I2C_SDA", /* GPIO_160 */ + "COMPASS_I2C_SCL", + "NC", + "NC", + "SSC_SPI_1_MISO", + "SSC_SPI_1_MOSI", + "SSC_SPI_1_CLK", + "SSC_SPI_1_CS_N", + "NC", + "NC", + "SSC_SENSOR_I2C_SDA", /* GPIO_170 */ + "SSC_SENSOR_I2C_SCL", + "NC", + "NC", + "NC", + "NC", + "HST_BLE_SNS_UART6_TX", + "HST_BLE_SNS_UART6_RX", + "HST_WLAN_UART_TX", + "HST_WLAN_UART_RX"; +}; + &vreg_l2f_1p3 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index 8ab82bacba81..ecdc20bc10f5 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -51,12 +51,26 @@ gpio_keys: gpio-keys { compatible = "gpio-keys"; - /* - * Camera focus (light press) and camera snapshot (full press) - * seem not to work properly.. Adding the former one stalls the CPU - * and the latter kills the volume down key for whatever reason. In any - * case, they are both on &pm8150b_gpios: camera focus(2), camera snapshot(1). - */ + pinctrl-0 = <&focus_n &snapshot_n &vol_down_n>; + pinctrl-names = "default"; + + key-camera-focus { + label = "Camera Focus"; + linux,code = <KEY_CAMERA_FOCUS>; + gpios = <&pm8150b_gpios 2 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + + key-camera-snapshot { + label = "Camera Snapshot"; + linux,code = <KEY_CAMERA>; + gpios = <&pm8150b_gpios 1 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; key-vol-down { label = "Volume Down"; @@ -112,7 +126,7 @@ reg = <0x0 0xffc00000 0x0 0x100000>; record-size = <0x1000>; console-size = <0x40000>; - msg-size = <0x20000 0x20000>; + pmsg-size = <0x20000>; ecc-size = <16>; no-map; }; @@ -486,13 +500,6 @@ }; }; -&i2c5 { - status = "okay"; - clock-frequency = <400000>; - - /* Dialog SLG51000 CMIC @ 75 */ -}; - &i2c9 { status = "okay"; clock-frequency = <400000>; @@ -551,6 +558,34 @@ vdda-pll-supply = <&vreg_l9a_1p2>; }; +&pm8150_gpios { + vol_down_n: vol-down-n-state { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + +&pm8150b_gpios { + snapshot_n: snapshot-n-state { + pins = "gpio1"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; + + focus_n: focus-n-state { + pins = "gpio2"; + function = "normal"; + power-source = <0>; + bias-pull-up; + input-enable; + }; +}; + &pon_pwrkey { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index b841ea9192ae..85e5cf3dc91e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -565,7 +565,7 @@ }; }; - port@1{ + port@1 { reg = <1>; panel_in_1: endpoint { diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 1efa07f2caff..a4e58ad731c3 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -16,6 +16,7 @@ #include <dt-bindings/interconnect/qcom,sm8250.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/soc/qcom,apr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/sound/qcom,q6afe.h> @@ -100,7 +101,7 @@ clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <448>; - dynamic-power-coefficient = <205>; + dynamic-power-coefficient = <105>; next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; @@ -131,7 +132,7 @@ clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <448>; - dynamic-power-coefficient = <205>; + dynamic-power-coefficient = <105>; next-level-cache = <&L2_100>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; @@ -156,7 +157,7 @@ clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <448>; - dynamic-power-coefficient = <205>; + dynamic-power-coefficient = <105>; next-level-cache = <&L2_200>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; @@ -181,7 +182,7 @@ clocks = <&cpufreq_hw 0>; enable-method = "psci"; capacity-dmips-mhz = <448>; - dynamic-power-coefficient = <205>; + dynamic-power-coefficient = <105>; next-level-cache = <&L2_300>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; @@ -1036,7 +1037,7 @@ dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1068,7 +1069,7 @@ dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1100,7 +1101,7 @@ dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1132,7 +1133,7 @@ dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, <&gpi_dma2 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1147,7 +1148,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart17_default>; interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -1177,7 +1178,7 @@ dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, <&gpi_dma2 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1192,7 +1193,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart18_default>; interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -1222,7 +1223,7 @@ dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1290,7 +1291,7 @@ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, <&gpi_dma0 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1322,7 +1323,7 @@ dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, <&gpi_dma0 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1354,7 +1355,7 @@ dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, <&gpi_dma0 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1369,7 +1370,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart2_default>; interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -1399,7 +1400,7 @@ dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, <&gpi_dma0 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1431,7 +1432,7 @@ dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, <&gpi_dma0 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1463,7 +1464,7 @@ dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, <&gpi_dma0 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1495,7 +1496,7 @@ dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, <&gpi_dma0 1 6 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1510,7 +1511,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart6_default>; interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -1540,7 +1541,7 @@ dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, <&gpi_dma0 1 7 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1605,7 +1606,7 @@ dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1637,7 +1638,7 @@ dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1669,7 +1670,7 @@ dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1701,7 +1702,7 @@ dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1733,7 +1734,7 @@ dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1748,7 +1749,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart12_default>; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; status = "disabled"; }; @@ -1778,7 +1779,7 @@ dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; dma-names = "tx", "rx"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table>; #address-cells = <1>; #size-cells = <0>; @@ -1905,6 +1906,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; + dma-coherent; status = "disabled"; }; @@ -2011,6 +2013,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; + dma-coherent; status = "disabled"; }; @@ -2119,6 +2122,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; + dma-coherent; status = "disabled"; }; @@ -2204,6 +2208,10 @@ <0 0>, <0 0>; + interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>, + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>; + interconnect-names = "ufs-ddr", "cpu-ufs"; + status = "disabled"; }; @@ -2726,6 +2734,7 @@ clock-names = "ahb", "bus", "iface"; power-domains = <&gpucc GPU_CX_GDSC>; + dma-coherent; }; slpi: remoteproc@5c00000 { @@ -2743,8 +2752,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8250_LCX>, - <&rpmhpd SM8250_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&slpi_mem>; @@ -3059,7 +3068,7 @@ port@7 { reg = <7>; funnel_swao_in_funnel_merg: endpoint { - remote-endpoint= <&funnel_merg_out_funnel_swao>; + remote-endpoint = <&funnel_merg_out_funnel_swao>; }; }; }; @@ -3463,7 +3472,7 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; memory-region = <&cdsp_mem>; @@ -3660,7 +3669,7 @@ iommus = <&apps_smmu 0x4a0 0x0>; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc2_opp_table>; status = "disabled"; @@ -3690,6 +3699,128 @@ }; }; + pmu@9091000 { + compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0 0x09091000 0 0x1000>; + + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-800000 { + opp-peak-kBps = <(200 * 4 * 1000)>; + }; + + opp-1200000 { + opp-peak-kBps = <(300 * 4 * 1000)>; + }; + + opp-1804000 { + opp-peak-kBps = <(451 * 4 * 1000)>; + }; + + opp-2188000 { + opp-peak-kBps = <(547 * 4 * 1000)>; + }; + + opp-2724000 { + opp-peak-kBps = <(681 * 4 * 1000)>; + }; + + opp-3072000 { + opp-peak-kBps = <(768 * 4 * 1000)>; + }; + + opp-4068000 { + opp-peak-kBps = <(1017 * 4 * 1000)>; + }; + + /* 1353 MHz, LPDDR4X */ + + opp-6220000 { + opp-peak-kBps = <(1555 * 4 * 1000)>; + }; + + opp-7216000 { + opp-peak-kBps = <(1804 * 4 * 1000)>; + }; + + opp-8368000 { + opp-peak-kBps = <(2092 * 4 * 1000)>; + }; + + /* LPDDR5 */ + opp-10944000 { + opp-peak-kBps = <(2736 * 4 * 1000)>; + }; + }; + }; + + pmu@90b6400 { + compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x090b6400 0 0x600>; + + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>; + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-800000 { + opp-peak-kBps = <(200 * 4 * 1000)>; + }; + + opp-1804000 { + opp-peak-kBps = <(451 * 4 * 1000)>; + }; + + opp-2188000 { + opp-peak-kBps = <(547 * 4 * 1000)>; + }; + + opp-2724000 { + opp-peak-kBps = <(681 * 4 * 1000)>; + }; + + opp-3072000 { + opp-peak-kBps = <(768 * 4 * 1000)>; + }; + + /* 1017MHz, 1353 MHz, LPDDR4X */ + + opp-6220000 { + opp-peak-kBps = <(1555 * 4 * 1000)>; + }; + + opp-6832000 { + opp-peak-kBps = <(1708 * 4 * 1000)>; + }; + + opp-8368000 { + opp-peak-kBps = <(2092 * 4 * 1000)>; + }; + + /* 2133MHz, LPDDR4X */ + + /* LPDDR5 */ + opp-10944000 { + opp-peak-kBps = <(2736 * 4 * 1000)>; + }; + + /* LPDDR5 */ + opp-12784000 { + opp-peak-kBps = <(3196 * 4 * 1000)>; + }; + }; + }; + dc_noc: interconnect@90c0000 { compatible = "qcom,sm8250-dc-noc"; reg = <0 0x090c0000 0 0x4200>; @@ -3836,7 +3967,7 @@ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&videocc MVS0C_GDSC>, <&videocc MVS0_GDSC>, - <&rpmhpd SM8250_MX>; + <&rpmhpd RPMHPD_MX>; power-domain-names = "venus", "vcodec0", "mx"; operating-points-v2 = <&venus_opp_table>; @@ -3897,7 +4028,7 @@ clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; #clock-cells = <1>; @@ -4177,7 +4308,7 @@ <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; status = "disabled"; #clock-cells = <1>; @@ -4230,7 +4361,7 @@ assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; interrupt-parent = <&mdss>; interrupts = <0>; @@ -4305,7 +4436,7 @@ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&mdss_dsi0_phy>; @@ -4397,7 +4528,7 @@ assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&mdss_dsi1_phy>; @@ -4448,7 +4579,7 @@ dispcc: clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0 0x0af00000 0 0x10000>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&mdss_dsi0_phy 0>, @@ -5298,104 +5429,105 @@ reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <2>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; }; adsp: remoteproc@17300000 { @@ -5413,8 +5545,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8250_LCX>, - <&rpmhpd SM8250_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&adsp_mem>; diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 61dd9663fabe..4013d25a7df3 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -7,10 +7,12 @@ #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sm8350.dtsi" +#include "pmk8350.dtsi" / { model = "Qualcomm Technologies, Inc. SM8350 HDK"; compatible = "qcom,sm8350-hdk", "qcom,sm8350"; + chassis-type = "embedded"; aliases { serial0 = &uart2; @@ -348,18 +350,10 @@ vcc-supply = <&vreg_bob>; mode-switch; orientation-switch; - svid = /bits/ 16 <0xff01>; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - fsa4480_sbu_mux: endpoint { - remote-endpoint = <&pmic_glink_sbu>; - }; + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; }; }; }; @@ -474,6 +468,18 @@ status = "okay"; }; +&sdhc_2 { + cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>; + vmmc-supply = <&vreg_l9c_2p96>; + vqmmc-supply = <&vreg_l6c_1p8>; + no-sdio; + no-mmc; + status = "okay"; +}; + &slpi { status = "okay"; firmware-name = "qcom/sm8350/slpi.mbn"; @@ -732,6 +738,13 @@ bias-pull-up; }; }; + + sdc2_card_det_n: sd-card-det-n-state { + pins = "gpio92"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; }; &uart2 { diff --git a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts index d21d2aacf201..c5a6c8745606 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-mtp.dts @@ -17,6 +17,7 @@ / { model = "Qualcomm Technologies, Inc. sm8350 MTP"; compatible = "qcom,sm8350-mtp", "qcom,sm8350"; + chassis-type = "handset"; aliases { serial0 = &uart2; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index ec451c616f3e..00604bf7724f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -15,7 +15,10 @@ #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/phy/phy-qcom-qmp.h> #include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/power/qcom,rpmhpd.h> +#include <dt-bindings/soc/qcom,apr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/sound/qcom,q6afe.h> #include <dt-bindings/thermal/thermal.h> #include <dt-bindings/interconnect/qcom,sm8350.h> @@ -48,7 +51,7 @@ CPU0: cpu@0 { device_type = "cpu"; - compatible = "qcom,kryo685"; + compatible = "arm,cortex-a55"; reg = <0x0 0x0>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; @@ -72,7 +75,7 @@ CPU1: cpu@100 { device_type = "cpu"; - compatible = "qcom,kryo685"; + compatible = "arm,cortex-a55"; reg = <0x0 0x100>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; @@ -91,7 +94,7 @@ CPU2: cpu@200 { device_type = "cpu"; - compatible = "qcom,kryo685"; + compatible = "arm,cortex-a55"; reg = <0x0 0x200>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; @@ -110,7 +113,7 @@ CPU3: cpu@300 { device_type = "cpu"; - compatible = "qcom,kryo685"; + compatible = "arm,cortex-a55"; reg = <0x0 0x300>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; @@ -129,7 +132,7 @@ CPU4: cpu@400 { device_type = "cpu"; - compatible = "qcom,kryo685"; + compatible = "arm,cortex-a78"; reg = <0x0 0x400>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; @@ -148,7 +151,7 @@ CPU5: cpu@500 { device_type = "cpu"; - compatible = "qcom,kryo685"; + compatible = "arm,cortex-a78"; reg = <0x0 0x500>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; @@ -167,7 +170,7 @@ CPU6: cpu@600 { device_type = "cpu"; - compatible = "qcom,kryo685"; + compatible = "arm,cortex-a78"; reg = <0x0 0x600>; clocks = <&cpufreq_hw 1>; enable-method = "psci"; @@ -186,7 +189,7 @@ CPU7: cpu@700 { device_type = "cpu"; - compatible = "qcom,kryo685"; + compatible = "arm,cortex-x1"; reg = <0x0 0x700>; clocks = <&cpufreq_hw 2>; enable-method = "psci"; @@ -246,8 +249,8 @@ compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <355>; - exit-latency-us = <909>; + entry-latency-us = <360>; + exit-latency-us = <531>; min-residency-us = <3934>; local-timer-stop; }; @@ -256,15 +259,23 @@ compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; - entry-latency-us = <241>; - exit-latency-us = <1461>; + entry-latency-us = <702>; + exit-latency-us = <1061>; min-residency-us = <4488>; local-timer-stop; }; }; domain-idle-states { - CLUSTER_SLEEP_0: cluster-sleep-0 { + CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + }; + + CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { compatible = "domain-idle-state"; arm,psci-suspend-param = <0x4100c344>; entry-latency-us = <3263>; @@ -346,7 +357,7 @@ CLUSTER_PD: power-domain-cpu-cluster0 { #power-domain-cells = <0>; - domain-idle-states = <&CLUSTER_SLEEP_0>; + domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; }; }; @@ -737,7 +748,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, <&gpi_dma2 1 0 QCOM_GPI_SPI>; @@ -769,7 +780,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, <&gpi_dma2 1 1 QCOM_GPI_SPI>; @@ -801,7 +812,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, <&gpi_dma2 1 2 QCOM_GPI_SPI>; @@ -833,7 +844,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, <&gpi_dma2 1 3 QCOM_GPI_SPI>; @@ -851,7 +862,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, <&gpi_dma2 1 4 QCOM_GPI_SPI>; @@ -869,7 +880,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart18_default>; interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; @@ -896,7 +907,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, <&gpi_dma2 1 5 QCOM_GPI_SPI>; @@ -963,7 +974,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, <&gpi_dma0 1 0 QCOM_GPI_SPI>; @@ -995,7 +1006,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, <&gpi_dma0 1 1 QCOM_GPI_SPI>; @@ -1027,7 +1038,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, <&gpi_dma0 1 2 QCOM_GPI_SPI>; @@ -1045,7 +1056,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart3_default_state>; interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; @@ -1058,7 +1069,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, <&gpi_dma0 1 3 QCOM_GPI_SPI>; @@ -1090,7 +1101,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, <&gpi_dma0 1 4 QCOM_GPI_SPI>; @@ -1122,7 +1133,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, <&gpi_dma0 1 5 QCOM_GPI_SPI>; @@ -1154,7 +1165,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, <&gpi_dma0 1 6 QCOM_GPI_SPI>; @@ -1172,7 +1183,7 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_uart6_default>; interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; status = "disabled"; }; @@ -1199,7 +1210,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, <&gpi_dma0 1 7 QCOM_GPI_SPI>; @@ -1266,7 +1277,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, <&gpi_dma1 1 0 QCOM_GPI_SPI>; @@ -1298,7 +1309,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, <&gpi_dma1 1 1 QCOM_GPI_SPI>; @@ -1330,7 +1341,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, <&gpi_dma1 1 2 QCOM_GPI_SPI>; @@ -1362,7 +1373,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, <&gpi_dma1 1 3 QCOM_GPI_SPI>; @@ -1394,7 +1405,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, <&gpi_dma1 1 4 QCOM_GPI_SPI>; @@ -1426,7 +1437,7 @@ clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, <&gpi_dma1 1 5 QCOM_GPI_SPI>; @@ -1806,6 +1817,20 @@ #hwlock-cells = <1>; }; + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sm8350-lpass-lpi-pinctrl"; + reg = <0 0x033c0000 0 0x20000>, + <0 0x03550000 0 0x10000>; + + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + }; + gpu: gpu@3d00000 { compatible = "qcom,adreno-660.1", "qcom,adreno"; @@ -2007,8 +2032,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8350_CX>, - <&rpmhpd SM8350_MSS>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; power-domain-names = "cx", "mss"; interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; @@ -2048,8 +2073,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8350_LCX>, - <&rpmhpd SM8350_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&pil_slpi_mem>; @@ -2118,7 +2143,7 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; iommus = <&apps_smmu 0x4a0 0x0>; - power-domains = <&rpmhpd SM8350_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc2_opp_table>; bus-width = <4>; dma-coherent; @@ -2479,7 +2504,7 @@ assigned-clock-rates = <19200000>; operating-points-v2 = <&dpu_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; interrupt-parent = <&mdss>; interrupts = <0>; @@ -2542,7 +2567,7 @@ #sound-dai-cells = <0>; operating-points-v2 = <&dp_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; status = "disabled"; @@ -2610,7 +2635,7 @@ <&mdss_dsi0_phy 1>; operating-points-v2 = <&dsi0_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&mdss_dsi0_phy>; @@ -2708,7 +2733,7 @@ <&mdss_dsi1_phy 1>; operating-points-v2 = <&dsi1_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&mdss_dsi1_phy>; @@ -2799,7 +2824,7 @@ #reset-cells = <1>; #power-domain-cells = <1>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; }; pdc: interrupt-controller@b220000 { @@ -3077,104 +3102,104 @@ reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <2>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; }; adsp: remoteproc@17300000 { @@ -3192,8 +3217,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8350_LCX>, - <&rpmhpd SM8350_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&pil_adsp_mem>; @@ -3215,6 +3240,75 @@ label = "lpass"; qcom,remote-pid = <2>; + apr { + compatible = "qcom,apr-v2"; + qcom,glink-channels = "apr_audio_svc"; + qcom,domain = <APR_DOMAIN_ADSP>; + #address-cells = <1>; + #size-cells = <0>; + + service@3 { + reg = <APR_SVC_ADSP_CORE>; + compatible = "qcom,q6core"; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + }; + + q6afe: service@4 { + compatible = "qcom,q6afe"; + reg = <APR_SVC_AFE>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + q6afedai: dais { + compatible = "qcom,q6afe-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + }; + + q6afecc: clock-controller { + compatible = "qcom,q6afe-clocks"; + #clock-cells = <2>; + }; + }; + + q6asm: service@7 { + compatible = "qcom,q6asm"; + reg = <APR_SVC_ASM>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + q6asmdai: dais { + compatible = "qcom,q6asm-dais"; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <1>; + iommus = <&apps_smmu 0x1801 0x0>; + + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; + }; + }; + + q6adm: service@8 { + compatible = "qcom,q6adm"; + reg = <APR_SVC_ADM>; + qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; + + q6routing: routing { + compatible = "qcom,q6adm-routing"; + #sound-dai-cells = <0>; + }; + }; + }; + fastrpc { compatible = "qcom,fastrpc"; qcom,glink-channels = "fastrpcglink-apps-dsp"; @@ -3399,6 +3493,13 @@ <0 0x18593000 0 0x1000>; reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1", + "dcvsh-irq-2"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; @@ -3421,8 +3522,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8350_CX>, - <&rpmhpd SM8350_MXC>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>; power-domain-names = "cx", "mxc"; interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index bc4c125d1832..bd5e8181f2aa 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -6,6 +6,10 @@ /dts-v1/; #include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h> +#include <dt-bindings/iio/qcom,spmi-adc7-pm8350b.h> +#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> +#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h> #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> #include "sm8450.dtsi" #include "pm8350.dtsi" @@ -14,11 +18,11 @@ #include "pm8450.dtsi" #include "pmk8350.dtsi" #include "pmr735a.dtsi" -#include "pmr735b.dtsi" / { model = "Qualcomm Technologies, Inc. SM8450 HDK"; compatible = "qcom,sm8450-hdk", "qcom,sm8450"; + chassis-type = "embedded"; aliases { serial0 = &uart7; @@ -130,6 +134,120 @@ }; }; + thermal-zones { + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 2>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + rear-tof-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 5>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + skin-msm-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 1>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + therm1-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 3>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + therm2-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 6>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + usb-conn-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 7>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + wide-rfc-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 4>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + xo-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 0>; + + trips { + active-config0 { + temperature = <50000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -517,18 +635,10 @@ vcc-supply = <&vreg_bob>; mode-switch; orientation-switch; - svid = /bits/ 16 <0xff01>; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - fsa4480_sbu_mux: endpoint { - remote-endpoint = <&pmic_glink_sbu>; - }; + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; }; }; }; @@ -589,6 +699,175 @@ vdda-pll-supply = <&vreg_l6b_1p2>; }; +&pm8350_temp_alarm { + io-channels = <&pmk8350_vadc PM8350_ADC7_DIE_TEMP(1)>; + io-channel-names = "thermal"; +}; + +&pm8350b_temp_alarm { + io-channels = <&pmk8350_vadc PM8350B_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmr735a_temp_alarm { + io-channels = <&pmk8350_vadc PMR735A_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + skin-msm-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + camera-therm@2 { + reg = <2>; + io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + therm1-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + wide-rfc-therm@4 { + reg = <4>; + io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + rear-tof-therm@5 { + reg = <5>; + io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM5_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + therm2-therm@6 { + reg = <6>; + io-channels = <&pmk8350_vadc PM8350_ADC7_GPIO3_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + usb-conn-therm@7 { + reg = <7>; + io-channels = <&pmk8350_vadc PM8350B_ADC7_AMUX_THM5_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pmk8350_vadc { + status = "okay"; + + channel@3 { + reg = <PMK8350_ADC7_DIE_TEMP>; + label = "pmk8350_die_temp"; + }; + + channel@44 { + reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "pmk8350_xo_therm"; + }; + + channel@103 { + reg = <PM8350_ADC7_DIE_TEMP(1)>; + label = "pm8350_die_temp"; + }; + + channel@144 { + reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "skin_msm_temp"; + }; + + channel@145 { + reg = <PM8350_ADC7_AMUX_THM2_100K_PU(1)>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "camera_temp"; + }; + + channel@146 { + reg = <PM8350_ADC7_AMUX_THM3_100K_PU(1)>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "therm1_temp"; + }; + + channel@147 { + reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "wide_rfc_temp"; + }; + + channel@148 { + reg = <PM8350_ADC7_AMUX_THM5_100K_PU(1)>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "rear_tof_temp"; + }; + + channel@14c { + reg = <PM8350_ADC7_GPIO3_100K_PU(1)>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "therm2_temp"; + }; + + channel@303 { + reg = <PM8350B_ADC7_DIE_TEMP>; + label = "pm8350b_die_temp"; + }; + + channel@348 { + reg = <PM8350B_ADC7_AMUX_THM5_100K_PU>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "usb_conn_temp"; + }; + + channel@403 { + reg = <PMR735A_ADC7_DIE_TEMP>; + label = "pmr735a_die_temp"; + }; + + channel@44a { + reg = <PMR735A_ADC7_GPIO1_100K_PU>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "qtm_w_temp"; + }; + + channel@44b { + reg = <PMR735A_ADC7_GPIO2_100K_PU>; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "qtm_n_temp"; + }; +}; + &remoteproc_adsp { status = "okay"; firmware-name = "qcom/sm8450/adsp.mbn"; diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 65a94dfaf5ae..37479327707f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -18,6 +18,7 @@ / { model = "Qualcomm Technologies, Inc. SM8450 QRD"; compatible = "qcom,sm8450-qrd", "qcom,sm8450"; + chassis-type = "handset"; aliases { serial0 = &uart7; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 5cd7296c7660..2a60cf8bd891 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -13,7 +13,9 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/phy/phy-qcom-qmp.h> +#include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/interconnect/qcom,icc.h> #include <dt-bindings/interconnect/qcom,sm8450.h> #include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> @@ -1149,7 +1151,7 @@ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; - power-domains = <&rpmhpd SM8450_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, @@ -1312,7 +1314,7 @@ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; - power-domains = <&rpmhpd SM8450_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, @@ -1736,6 +1738,11 @@ }; }; + rng: rng@10c3000 { + compatible = "qcom,sm8450-prng-ee", "qcom,prng-ee"; + reg = <0 0x010c3000 0 0x1000>; + }; + pcie0: pci@1c00000 { compatible = "qcom,pcie-sm8450-pcie0"; reg = <0 0x01c00000 0 0x3000>, @@ -2097,8 +2104,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8450_LCX>, - <&rpmhpd SM8450_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&slpi_mem>; @@ -2372,8 +2379,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8450_LCX>, - <&rpmhpd SM8450_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; memory-region = <&adsp_mem>; @@ -2477,8 +2484,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8450_CX>, - <&rpmhpd SM8450_MXC>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>; power-domain-names = "cx", "mxc"; memory-region = <&cdsp_mem>; @@ -2584,8 +2591,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8450_CX>, - <&rpmhpd SM8450_MSS>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; power-domain-names = "cx", "mss"; memory-region = <&mpss_mem>; @@ -2613,7 +2620,7 @@ reg = <0 0x0aaf0000 0 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; @@ -2705,7 +2712,7 @@ <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; @@ -2720,8 +2727,12 @@ /* same path used twice */ interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, - <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; - interconnect-names = "mdp0-mem", "mdp1-mem"; + <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; @@ -2767,7 +2778,7 @@ assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; interrupt-parent = <&mdss>; interrupts = <0>; @@ -2859,7 +2870,7 @@ #sound-dai-cells = <0>; operating-points-v2 = <&dp_opp_table>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; status = "disabled"; @@ -2925,7 +2936,7 @@ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; operating-points-v2 = <&mdss_dsi_opp_table>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&mdss_dsi0_phy>; phy-names = "dsi"; @@ -3017,7 +3028,7 @@ assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; operating-points-v2 = <&mdss_dsi_opp_table>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&mdss_dsi1_phy>; phy-names = "dsi"; @@ -3085,7 +3096,7 @@ <0>, <0>, /* dp3 */ <0>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; @@ -3135,6 +3146,11 @@ #clock-cells = <0>; }; + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0 0x0c3f0000 0 0x400>; + }; + spmi_bus: spmi@c400000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c400000 0 0x00003000>, @@ -3810,103 +3826,103 @@ reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <1>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; }; intc: interrupt-controller@17100000 { @@ -4120,9 +4136,7 @@ ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8450-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x3000>, - <0 0x01d88000 0 0x8000>; - reg-names = "std", "ice"; + reg = <0 0x01d84000 0 0x3000>; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -4147,8 +4161,7 @@ "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk", - "ice_core_clk"; + "rx_lane1_sync_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, @@ -4157,8 +4170,7 @@ <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, - <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; freq-table-hz = <75000000 300000000>, <0 0>, @@ -4167,8 +4179,9 @@ <75000000 300000000>, <0 0>, <0 0>, - <0 0>, - <75000000 300000000>; + <0 0>; + qcom,ice = <&ice>; + status = "disabled"; }; @@ -4198,6 +4211,13 @@ }; }; + ice: crypto@1d88000 { + compatible = "qcom,sm8450-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d88000 0 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x28000>; @@ -4212,7 +4232,7 @@ <&apps_smmu 0x59f 0x0>; }; - crypto: crypto@1de0000 { + crypto: crypto@1dfa000 { compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; reg = <0 0x01dfa000 0 0x6000>; dmas = <&cryptobam 4>, <&cryptobam 5>; @@ -4243,7 +4263,7 @@ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; iommus = <&apps_smmu 0x4a0 0x0>; - power-domains = <&rpmhpd SM8450_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc2_opp_table>; bus-width = <4>; dma-coherent; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index ec86c5f38045..f29cce5186ac 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -18,6 +18,7 @@ / { model = "Qualcomm Technologies, Inc. SM8550 MTP"; compatible = "qcom,sm8550-mtp", "qcom,sm8550"; + chassis-type = "handset"; aliases { serial0 = &uart7; @@ -80,7 +81,15 @@ reg = <1>; pmic_glink_ss_in: endpoint { - remote-endpoint = <&usb_1_dwc3_ss>; + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; }; }; }; @@ -186,6 +195,7 @@ vdd-bob1-supply = <&vph_pwr>; vdd-bob2-supply = <&vph_pwr>; + vdd-l1-l4-l10-supply = <&vreg_s6g_1p8>; vdd-l2-l13-l14-supply = <&vreg_bob1>; vdd-l3-supply = <&vreg_s4g_1p3>; vdd-l5-l16-supply = <&vreg_bob1>; @@ -500,6 +510,30 @@ }; }; +&i2c_master_hub_0 { + status = "okay"; +}; + +&i2c_hub_2 { + status = "okay"; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + vcc-supply = <&vreg_bob1>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; +}; + &lpass_tlmm { spkr_1_sd_n_active: spkr-1-sd-n-active-state { pins = "gpio17"; @@ -558,6 +592,15 @@ status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_dp_qmpphy_dp_in>; +}; + &pcie_1_phy_aux_clk { clock-frequency = <1000>; }; @@ -781,7 +824,7 @@ }; &usb_1_dwc3_ss { - remote-endpoint = <&pmic_glink_ss_in>; + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; &usb_1_hsphy { @@ -797,9 +840,23 @@ vdda-phy-supply = <&vreg_l3e_1p2>; vdda-pll-supply = <&vreg_l3f_0p91>; + orientation-switch; + status = "okay"; }; +&usb_dp_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&pmic_glink_ss_in>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + &xo_board { clock-frequency = <76800000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index ec4feee6837d..2c09ce8aeafd 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -19,6 +19,7 @@ / { model = "Qualcomm Technologies, Inc. SM8550 QRD"; compatible = "qcom,sm8550-qrd", "qcom,sm8550"; + chassis-type = "handset"; aliases { serial0 = &uart7; @@ -97,7 +98,15 @@ reg = <1>; pmic_glink_ss_in: endpoint { - remote-endpoint = <&usb_1_dwc3_ss>; + remote-endpoint = <&redriver_ss_out>; + }; + }; + + port@2 { + reg = <2>; + + pmic_glink_sbu: endpoint { + remote-endpoint = <&fsa4480_sbu_mux>; }; }; }; @@ -517,6 +526,62 @@ }; }; +&i2c_master_hub_0 { + status = "okay"; +}; + +&i2c_hub_2 { + status = "okay"; + + typec-retimer@1c { + compatible = "onnn,nb7vpq904m"; + reg = <0x1c>; + + vcc-supply = <&vreg_l15b_1p8>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + redriver_ss_out: endpoint { + remote-endpoint = <&pmic_glink_ss_in>; + }; + }; + + port@1 { + reg = <1>; + + redriver_ss_in: endpoint { + data-lanes = <3 2 1 0>; + remote-endpoint = <&usb_dp_qmpphy_out>; + }; + }; + }; + }; + + typec-mux@42 { + compatible = "fcs,fsa4480"; + reg = <0x42>; + + vcc-supply = <&vreg_bob1>; + + mode-switch; + orientation-switch; + + port { + fsa4480_sbu_mux: endpoint { + remote-endpoint = <&pmic_glink_sbu>; + }; + }; + }; +}; + &gcc { clocks = <&bi_tcxo_div2>, <&sleep_clk>, <&pcie0_phy>, @@ -586,6 +651,15 @@ status = "okay"; }; +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + data-lanes = <0 1>; + remote-endpoint = <&usb_dp_qmpphy_dp_in>; +}; + &pcie_1_phy_aux_clk { status = "disabled"; }; @@ -842,7 +916,7 @@ }; &usb_1_dwc3_ss { - remote-endpoint = <&pmic_glink_ss_in>; + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; }; &usb_1_hsphy { @@ -858,9 +932,23 @@ vdda-phy-supply = <&vreg_l3e_1p2>; vdda-pll-supply = <&vreg_l3f_0p88>; + orientation-switch; + status = "okay"; }; +&usb_dp_qmpphy_dp_in { + remote-endpoint = <&mdss_dp0_out>; +}; + +&usb_dp_qmpphy_out { + remote-endpoint = <&redriver_ss_in>; +}; + +&usb_dp_qmpphy_usb_ss_in { + remote-endpoint = <&usb_1_dwc3_ss>; +}; + &xo_board { clock-frequency = <76800000>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 41d60af93692..d115960bdeec 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -15,6 +15,7 @@ #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/power/qcom,rpmhpd.h> #include <dt-bindings/soc/qcom,gpr.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> @@ -1600,7 +1601,7 @@ pinctrl-0 = <&qup_uart7_default>; interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; interconnect-names = "qup-core", "qup-config"; - interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>; status = "disabled"; }; @@ -1989,8 +1990,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8550_CX>, - <&rpmhpd SM8550_MSS>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; power-domain-names = "cx", "mss"; interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; @@ -2368,7 +2369,7 @@ iommus = <&apps_smmu 0x540 0>; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; - power-domains = <&rpmhpd SM8550_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc2_opp_table>; interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, @@ -2412,7 +2413,7 @@ reg = <0 0x0aaf0000 0 0x10000>; clocks = <&bi_tcxo_div2>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; @@ -2471,7 +2472,7 @@ "core", "vsync"; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; assigned-clock-rates = <19200000>; @@ -2560,7 +2561,7 @@ #sound-dai-cells = <0>; operating-points-v2 = <&dp_opp_table>; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; status = "disabled"; @@ -2628,7 +2629,7 @@ "iface", "bus"; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; @@ -2723,7 +2724,7 @@ "iface", "bus"; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; @@ -2798,7 +2799,7 @@ <0>, <0>, /* dp3 */ <0>; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; @@ -2838,6 +2839,32 @@ #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; }; usb_1: usb@a6f8800 { @@ -3517,103 +3544,103 @@ reg = <0 0x15000000 0 0x100000>; #iommu-cells = <2>; #global-interrupts = <1>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; }; intc: interrupt-controller@17100000 { @@ -3933,8 +3960,8 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8550_LCX>, - <&rpmhpd SM8550_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>; @@ -4065,9 +4092,9 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&rpmhpd SM8550_CX>, - <&rpmhpd SM8550_MXC>, - <&rpmhpd SM8550_NSP>; + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP>; power-domain-names = "cx", "mxc", "nsp"; interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; diff --git a/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi b/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi index d45f072f8cdf..e0930d1ba3aa 100644 --- a/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi +++ b/arch/arm64/boot/dts/renesas/gmsl-cameras.dtsi @@ -100,7 +100,7 @@ #ifdef GMSL_CAMERA_1 port@1 { - max9286_in1: endpoint{ + max9286_in1: endpoint { remote-endpoint = <&fakra_con1>; }; @@ -233,7 +233,7 @@ #ifdef GMSL_CAMERA_5 port@1 { - max9286_in5: endpoint{ + max9286_in5: endpoint { remote-endpoint = <&fakra_con5>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index c2b65f8de547..e36999e91af5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -145,7 +145,7 @@ status = "okay"; clock-frequency = <400000>; - hdmi@39{ + hdmi@39 { compatible = "adi,adv7511w"; #sound-dai-cells = <0>; reg = <0x39>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980a.dtsi b/arch/arm64/boot/dts/renesas/r8a77980a.dtsi index 25b2d27b6167..83f5e21111c9 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980a.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980a.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car V3H2 (R8A77980A) SoC * diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 1be0b99c15ed..4c545eff9b42 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -76,7 +76,7 @@ enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; dynamic-power-coefficient = <277>; - clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; + clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; }; @@ -88,7 +88,7 @@ next-level-cache = <&L2_CA53>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; - clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>; + clocks = <&cpg CPG_CORE R8A77990_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index dd8e0e159526..5cbde8e8fcd5 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the Spider CPU board * @@ -6,6 +6,8 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + #include "r8a779f0.dtsi" / { @@ -22,6 +24,24 @@ stdout-path = "serial0:1843200n8"; }; + leds { + compatible = "gpio-leds"; + + led-7 { + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <7>; + }; + + led-8 { + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <8>; + }; + }; + memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts index 7aac3f4d319c..f139cc4feb37 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the Spider CPU and BreakOut boards * diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 1d5426e6293c..ecdd5a523fa3 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC * @@ -466,6 +466,21 @@ #thermal-sensor-cells = <1>; }; + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a779f0", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_CORE R8A779F0_CLK_CL16M>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + }; + tmu0: timer@e61e0000 { compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; reg = <0 0xe61e0000 0 0x30>; diff --git a/arch/arm64/boot/dts/renesas/r8a779m0.dtsi b/arch/arm64/boot/dts/renesas/r8a779m0.dtsi index 6fb1979cc041..38978360e722 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779m0.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car H3e (R8A779M0) SoC * diff --git a/arch/arm64/boot/dts/renesas/r8a779m1-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a779m1-salvator-xs.dts index 084b75b04680..74b0ac04ffe1 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m1-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a779m1-salvator-xs.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the Salvator-X 2nd version board with R-Car H3e-2G * diff --git a/arch/arm64/boot/dts/renesas/r8a779m1-ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a779m1-ulcb-kf.dts index 0baebc5c58b0..d2089e1d7100 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m1-ulcb-kf.dts +++ b/arch/arm64/boot/dts/renesas/r8a779m1-ulcb-kf.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the H3ULCB Kingfisher board with R-Car H3e-2G * diff --git a/arch/arm64/boot/dts/renesas/r8a779m1-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a779m1-ulcb.dts index e294b6bda28c..705ea047ef62 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m1-ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a779m1-ulcb.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) with R-Car H3e-2G * diff --git a/arch/arm64/boot/dts/renesas/r8a779m1.dtsi b/arch/arm64/boot/dts/renesas/r8a779m1.dtsi index 1064a87a0c77..be0219defe3a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779m1.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car H3e-2G (R8A779M1) SoC * diff --git a/arch/arm64/boot/dts/renesas/r8a779m2.dtsi b/arch/arm64/boot/dts/renesas/r8a779m2.dtsi index 324627340b86..bced12764c69 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m2.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779m2.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car M3e (R8A779M2) SoC * diff --git a/arch/arm64/boot/dts/renesas/r8a779m3-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a779m3-salvator-xs.dts index 4ab26fd7233d..e53a6e88ccfa 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m3-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a779m3-salvator-xs.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the Salvator-X 2nd version board with R-Car M3e-2G * diff --git a/arch/arm64/boot/dts/renesas/r8a779m3-ulcb-kf.dts b/arch/arm64/boot/dts/renesas/r8a779m3-ulcb-kf.dts index 6bacee1d2ef5..587e8764bcd2 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m3-ulcb-kf.dts +++ b/arch/arm64/boot/dts/renesas/r8a779m3-ulcb-kf.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the M3ULCB Kingfisher board with R-Car M3e-2G * diff --git a/arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dts index 8f215a0b771b..413f000b4630 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a779m3-ulcb.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) with R-Car M3e-2G * diff --git a/arch/arm64/boot/dts/renesas/r8a779m3.dtsi b/arch/arm64/boot/dts/renesas/r8a779m3.dtsi index 7fdbdd97ed4b..ffde141137df 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m3.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779m3.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car M3e-2G (R8A779M3) SoC * diff --git a/arch/arm64/boot/dts/renesas/r8a779m4.dtsi b/arch/arm64/boot/dts/renesas/r8a779m4.dtsi index d7fbb6c05502..ae8486056962 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m4.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779m4.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car M3Ne (R8A779M4) SoC * diff --git a/arch/arm64/boot/dts/renesas/r8a779m5-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a779m5-salvator-xs.dts index c0341a88d641..6efc23171a66 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m5-salvator-xs.dts +++ b/arch/arm64/boot/dts/renesas/r8a779m5-salvator-xs.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the Salvator-X 2nd version board with R-Car M3Ne-2G * diff --git a/arch/arm64/boot/dts/renesas/r8a779m5.dtsi b/arch/arm64/boot/dts/renesas/r8a779m5.dtsi index df51e0ff5986..aded03ad31a1 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m5.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779m5.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car M3Ne-2G (R8A779M5) SoC * diff --git a/arch/arm64/boot/dts/renesas/r8a779m6.dtsi b/arch/arm64/boot/dts/renesas/r8a779m6.dtsi index afe3cabfb898..94d6a6cf503e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m6.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779m6.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car E3e (R8A779M6) SoC * diff --git a/arch/arm64/boot/dts/renesas/r8a779m7.dtsi b/arch/arm64/boot/dts/renesas/r8a779m7.dtsi index 4958babc52fd..0580fa614034 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m7.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779m7.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car D3e (R8A779M7) SoC * diff --git a/arch/arm64/boot/dts/renesas/r8a779m8.dtsi b/arch/arm64/boot/dts/renesas/r8a779m8.dtsi index 750bd8ccdb7f..dfccc080fb3e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779m8.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779m8.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car H3Ne (R8A779M8) SoC * diff --git a/arch/arm64/boot/dts/renesas/r8a779mb.dtsi b/arch/arm64/boot/dts/renesas/r8a779mb.dtsi index 40d1dce2f350..181b737c91cd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779mb.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779mb.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0 or MIT) +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Device Tree Source for the R-Car H3Ne-1.7G (R8A779MB) SoC * diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 27c35a657b15..8721f4c9fa0f 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -74,6 +74,76 @@ #size-cells = <2>; ranges; + mtu3: timer@10001200 { + compatible = "renesas,r9a07g043-mtu3", + "renesas,rz-mtu3"; + reg = <0 0x10001200 0 0xb00>; + interrupts = <SOC_PERIPHERAL_IRQ(170) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(171) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(172) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(173) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(174) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(175) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(176) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(177) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(178) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(179) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(180) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(181) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(182) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(183) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(184) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(185) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(186) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(187) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(188) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(189) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(190) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(191) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(192) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(193) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(194) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(195) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(196) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(197) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(198) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(199) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(200) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(201) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(202) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(203) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(204) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(205) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(206) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(207) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(208) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(209) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(210) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(211) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(212) IRQ_TYPE_EDGE_RISING>, + <SOC_PERIPHERAL_IRQ(213) IRQ_TYPE_EDGE_RISING>; + interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", + "tciv0", "tgie0", "tgif0", + "tgia1", "tgib1", "tciv1", "tciu1", + "tgia2", "tgib2", "tciv2", "tciu2", + "tgia3", "tgib3", "tgic3", "tgid3", + "tciv3", + "tgia4", "tgib4", "tgic4", "tgid4", + "tciv4", + "tgiu5", "tgiv5", "tgiw5", + "tgia6", "tgib6", "tgic6", "tgid6", + "tciv6", + "tgia7", "tgib7", "tgic7", "tgid7", + "tciv7", + "tgia8", "tgib8", "tgic8", "tgid8", + "tciv8", "tciu8"; + clocks = <&cpg CPG_MOD R9A07G043_MTU_X_MCK_MTU3>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_MTU_X_PRESET_MTU3>; + #pwm-cells = <2>; + status = "disabled"; + }; + ssi0: ssi@10049c00 { compatible = "renesas,r9a07g043-ssi", "renesas,rz-ssi"; diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 01483b4302c2..8e0107df2d46 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -17,6 +17,17 @@ #define SW_SW0_DEV_SEL 1 #define SW_ET0_EN_N 1 +/* + * To enable MTU3a PWM on PMOD0, + * - Set DIP-Switch SW1-3 to On position. + * - Set PMOD_MTU3 macro to 1. + */ +#define PMOD_MTU3 0 + +#if (PMOD_MTU3 && !SW_ET0_EN_N) +#error "Cannot set as both PMOD_MTU3 and !SW_ET0_EN_N are mutually exclusive" +#endif + #include "r9a07g043u.dtsi" #include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index f67a6f125d9c..0b90367b6d1e 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -35,6 +35,18 @@ /* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ #define PMOD1_SER0 1 +/* + * To enable MTU3a PWM on PMOD0, + * - Set DIP-Switch SW1-4 to Off position. + * - Set SW_RSPI_CAN macro to 0. + * - Set PMOD_MTU3 macro to 1. + */ +#define PMOD_MTU3 0 + +#if (PMOD_MTU3 && SW_RSPI_CAN) +#error "Cannot set as both PMOD_MTU3 and SW_RSPI_CAN are mutually exclusive" +#endif + #include "r9a07g044c2.dtsi" #include "rzg2lc-smarc-som.dtsi" #include "rzg2lc-smarc.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts index bc2af6c92ccd..568d49cfe44a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044l2-smarc.dts @@ -6,6 +6,27 @@ */ /dts-v1/; + +/* Enable SCIF2 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + +/* + * To enable MTU3a PWM on PMOD0, + * Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and + * enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below. + */ +#define PMOD_MTU3 0 + +#if (PMOD_MTU3 && PMOD1_SER0) +#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive " +#endif + +#define MTU3_COUNTER_Z_PHASE_SIGNAL 0 + +#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL) +#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0" +#endif + #include "r9a07g044l2.dtsi" #include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc-pinfunction.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts index 3d01a4cf0fbe..b3e6016880dd 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -6,6 +6,26 @@ */ /dts-v1/; + +/* Enable SCIF2 (SER0) on PMOD1 (CN7) */ +#define PMOD1_SER0 1 + +/* + * To enable MTU3a PWM on PMOD0, + * Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and + * enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below. + */ +#define PMOD_MTU3 0 + +#if (PMOD_MTU3 && PMOD1_SER0) +#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive " +#endif + +#define MTU3_COUNTER_Z_PHASE_SIGNAL 0 +#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL) +#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0" +#endif + #include "r9a07g054l2.dtsi" #include "rzg2l-smarc-som.dtsi" #include "rzg2l-smarc-pinfunction.dtsi" diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index 46d67b200a66..33f2ecf42441 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -236,6 +236,34 @@ reg = <0 0xa3f03000 0 0x400>; }; + csi0: spi@a4020000 { + compatible = "renesas,rzv2m-csi"; + reg = <0 0xa4020000 0 0x80>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_CSI0_CLK>, + <&cpg CPG_MOD R9A09G011_CPERI_GRPG_PCLK>; + clock-names = "csiclk", "pclk"; + resets = <&cpg R9A09G011_CSI_GPG_PRESETN>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + csi4: spi@a4020200 { + compatible = "renesas,rzv2m-csi"; + reg = <0 0xa4020200 0 0x80>; + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>, + <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>; + clock-names = "csiclk", "pclk"; + resets = <&cpg R9A09G011_CSI_GPH_PRESETN>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c0: i2c@a4030000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi index 3962d47b3e59..a7594ba3a998 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -78,11 +78,11 @@ }; }; -&audio_clk1{ +&audio_clk1 { clock-frequency = <11289600>; }; -&audio_clk2{ +&audio_clk2 { clock-frequency = <12288000>; }; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi index 9085d8c76ce1..18c526c7a4cf 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi @@ -53,6 +53,26 @@ <RZG2L_PORT_PINMUX(18, 1, 3)>; /* SCL */ }; + mtu3_pins: mtu3 { + mtu3-ext-clk-input-pin { + pinmux = <RZG2L_PORT_PINMUX(48, 0, 4)>, /* MTCLKA */ + <RZG2L_PORT_PINMUX(48, 1, 4)>; /* MTCLKB */ + }; + + mtu3-pwm { + pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */ + <RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */ + <RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */ + <RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */ + }; + +#if MTU3_COUNTER_Z_PHASE_SIGNAL + mtu3-zphase-clk { + pinmux = <RZG2L_PORT_PINMUX(19, 0, 3)>; /* MTIOC1A */ + }; +#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */ + }; + scif0_pins: scif0 { pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index fbbb4f03440b..547859c388ce 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -73,6 +73,13 @@ gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; regulator-always-on; }; + + /* 32.768kHz crystal */ + x2: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; &adc { @@ -100,7 +107,7 @@ rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; - txdv-skew-psec = <0>; + txen-skew-psec = <0>; rxd0-skew-psec = <0>; rxd1-skew-psec = <0>; rxd2-skew-psec = <0>; @@ -128,7 +135,7 @@ rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; - txdv-skew-psec = <0>; + txen-skew-psec = <0>; rxd0-skew-psec = <0>; rxd1-skew-psec = <0>; rxd2-skew-psec = <0>; @@ -148,6 +155,17 @@ mali-supply = <®_1p1v>; }; +&i2c3 { + raa215300: pmic@12 { + compatible = "renesas,raa215300"; + reg = <0x12>, <0x6f>; + reg-names = "main", "rtc"; + + clocks = <&x2>; + clock-names = "xin"; + }; +}; + &ostm1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 2a158a954b2f..68eab8e26bf2 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -8,9 +8,6 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> -/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */ -#define PMOD1_SER0 1 - / { aliases { serial1 = &scif2; @@ -115,6 +112,26 @@ }; }; +#if PMOD_MTU3 +&mtu3 { + pinctrl-0 = <&mtu3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +#if MTU3_COUNTER_Z_PHASE_SIGNAL +/* SDHI cd pin is muxed with counter Z phase signal */ +&sdhi1 { + status = "disabled"; +}; +#endif /* MTU3_COUNTER_Z_PHASE_SIGNAL */ + +&spi1 { + status = "disabled"; +}; +#endif /* PMOD_MTU3 */ + /* * To enable SCIF2 (SER0) on PMOD1 (CN7) * SW1 should be at position 2->3 so that SER0_CTS# line is activated diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index a78a8def363e..92c64d58349f 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -50,6 +50,15 @@ <RZG2L_PORT_PINMUX(42, 4, 1)>; /* SCL */ }; + mtu3_pins: mtu3 { + mtu3-pwm { + pinmux = <RZG2L_PORT_PINMUX(44, 0, 4)>, /* MTIOC3A */ + <RZG2L_PORT_PINMUX(44, 1, 4)>, /* MTIOC3B */ + <RZG2L_PORT_PINMUX(44, 2, 4)>, /* MTIOC3C */ + <RZG2L_PORT_PINMUX(44, 3, 4)>; /* MTIOC3D */ + }; + }; + scif0_pins: scif0 { pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 8a0d56872de7..56ff92453976 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -6,6 +6,7 @@ */ #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irqc-rzg2l.h> #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> / { @@ -61,6 +62,13 @@ gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; regulator-always-on; }; + + /* 32.768kHz crystal */ + x2: x2-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; }; ð0 { @@ -74,10 +82,12 @@ compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = <RZG2L_IRQ0 IRQ_TYPE_LEVEL_LOW>; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; - txdv-skew-psec = <0>; + txen-skew-psec = <0>; rxd0-skew-psec = <0>; rxd1-skew-psec = <0>; rxd2-skew-psec = <0>; @@ -97,6 +107,17 @@ mali-supply = <®_1p1v>; }; +&i2c2 { + raa215300: pmic@12 { + compatible = "renesas,raa215300"; + reg = <0x12>, <0x6f>; + reg-names = "main", "rtc"; + + clocks = <&x2>; + clock-names = "xin"; + }; +}; + &ostm1 { status = "okay"; }; @@ -121,7 +142,8 @@ <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */ <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */ <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */ - <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */ + <RZG2L_PORT_PINMUX(0, 0, 1)>; /* IRQ0 */ }; gpio-sd0-pwr-en-hog { diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 6818fd49b2be..83fce96a2575 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -11,7 +11,6 @@ #include "rzg2lc-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" - / { aliases { serial1 = &scif1; @@ -129,6 +128,19 @@ }; }; +#if PMOD_MTU3 +&mtu3 { + pinctrl-0 = <&mtu3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&spi1 { + status = "disabled"; +}; +#endif + /* * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board * SW1 should be at position 2->3 so that SER0_CTS# line is activated diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi index 58923dc83faa..355694fe4af6 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -50,6 +50,12 @@ input-enable; }; + mtu3_pins: mtu3 { + mtu2-pwm { + pinmux = <RZG2L_PORT_PINMUX(4, 0, 4)>; /* MTIOC2A */ + }; + }; + scif0_pins: scif0 { pinmux = <RZG2L_PORT_PINMUX(6, 4, 6)>, /* TxD */ <RZG2L_PORT_PINMUX(6, 3, 6)>; /* RxD */ diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 49ecd33aeeb8..97cdad2a12e2 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -83,7 +83,7 @@ rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; - txdv-skew-psec = <0>; + txen-skew-psec = <0>; rxd0-skew-psec = <0>; rxd1-skew-psec = <0>; rxd2-skew-psec = <0>; @@ -112,7 +112,7 @@ rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; - txdv-skew-psec = <0>; + txen-skew-psec = <0>; rxd0-skew-psec = <0>; rxd1-skew-psec = <0>; rxd2-skew-psec = <0>; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index 2a1331ed1a5c..8eb411aac80d 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -28,6 +28,19 @@ }; }; +#if PMOD_MTU3 +&mtu3 { + pinctrl-0 = <&mtu3_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&spi1 { + status = "disabled"; +}; +#endif + #if (SW_ET0_EN_N) &ssi1 { pinctrl-0 = <&ssi1_pins>; diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index b7fb908eb92d..e7728007fd1b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -58,6 +58,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-4c-plus.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-4se.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb @@ -94,10 +95,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi index bf10a3d29fca..80db778c9684 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-ctouch2.dtsi @@ -26,5 +26,5 @@ }; &vcc3v3_btreg { - enable-gpio = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts index d759478e1c84..165d09ccb942 100644 --- a/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts +++ b/arch/arm64/boot/dts/rockchip/px30-engicam-px30-core-edimm2.2.dts @@ -39,5 +39,5 @@ }; &vcc3v3_btreg { - enable-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 23bfba86daab..c9bf1d5c3a42 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -250,7 +250,7 @@ pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; enable-active-high; - enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; states = <1800000 0x1>, <3000000 0x0>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi index aa3e21bd6c8f..20e3f41efe97 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -27,7 +27,7 @@ extcon_usb3: extcon-usb3 { compatible = "linux,extcon-usb-gpio"; - id-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + id-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb3_id>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts new file mode 100644 index 000000000000..7cfc198bbae7 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4se.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Akash Gajjar <Akash_Gajjar@mentor.com> + * Copyright (c) 2019 Pragnesh Patel <Pragnesh_Patel@mentor.com> + */ + +/dts-v1/; +#include "rk3399-rock-pi-4.dtsi" +#include "rk3399-t-opp.dtsi" + +/ { + model = "Radxa ROCK 4SE"; + compatible = "radxa,rock-4se", "rockchip,rk3399"; + + aliases { + mmc2 = &sdio0; + }; +}; + +&pinctrl { + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio0 { + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&uart0 { + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&vcc5v0_host { + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi index 980c4534313a..7dccbe8a9393 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi @@ -9,7 +9,6 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/pwm/pwm.h> #include "rk3399.dtsi" -#include "rk3399-opp.dtsi" / { aliases { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts index 89f2af5e111d..d5df8939a658 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dts @@ -6,8 +6,19 @@ /dts-v1/; #include "rk3399-rock-pi-4.dtsi" +#include "rk3399-opp.dtsi" / { model = "Radxa ROCK Pi 4A"; compatible = "radxa,rockpi4a", "radxa,rockpi4", "rockchip,rk3399"; }; + +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts index 0806545922f5..bee6d7588302 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "rk3399-rock-pi-4.dtsi" +#include "rk3399-opp.dtsi" / { model = "Radxa ROCK Pi 4B"; @@ -30,6 +31,16 @@ }; }; +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + &uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts index 4053ba72618c..de2ebe4cb4f3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "rk3399-rock-pi-4.dtsi" +#include "rk3399-opp.dtsi" / { model = "Radxa ROCK Pi 4C"; @@ -42,6 +43,16 @@ hp-det-gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; }; +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + &uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 928948e7c7bb..9da0b6d77c8d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -265,6 +265,33 @@ }; }; + pcie0_ep: pcie-ep@f8000000 { + compatible = "rockchip,rk3399-pcie-ep"; + reg = <0x0 0xfd000000 0x0 0x1000000>, + <0x0 0xfa000000 0x0 0x2000000>; + reg-names = "apb-base", "mem-base"; + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; + clock-names = "aclk", "aclk-perf", + "hclk", "pm"; + max-functions = /bits/ 8 <8>; + num-lanes = <4>; + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, + <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, + <&cru SRST_A_PCIE>; + reset-names = "core", "mgmt", "mgmt-sticky", "pipe", + "pm", "pclk", "aclk"; + phys = <&pcie_phy 0>, <&pcie_phy 1>, + <&pcie_phy 2>, <&pcie_phy 3>; + phy-names = "pcie-phy-0", "pcie-phy-1", + "pcie-phy-2", "pcie-phy-3"; + rockchip,max-outbound-regions = <32>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqnb_cpm>; + status = "disabled"; + }; + gmac: ethernet@fe300000 { compatible = "rockchip,rk3399-gmac"; reg = <0x0 0xfe300000 0x0 0x10000>; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts index 63c4bd873188..72ad74c38a2b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts @@ -47,6 +47,9 @@ vin-supply = <&vcc5v0_sys>; }; + /* actually fed by vcc5v0_sys, dependent + * on pi6c clock generator + */ vcc3v3_minipcie: vcc3v3-minipcie-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -54,9 +57,9 @@ pinctrl-names = "default"; pinctrl-0 = <&minipcie_enable_h>; regulator-name = "vcc3v3_minipcie"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_pi6c_05>; }; vcc3v3_ngff: vcc3v3-ngff-regulator { @@ -71,9 +74,6 @@ vin-supply = <&vcc5v0_sys>; }; - /* actually fed by vcc5v0_sys, dependent - * on pi6c clock generator - */ vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -83,7 +83,7 @@ regulator-name = "vcc3v3_pcie30x1"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_pi6c_05>; + vin-supply = <&vcc5v0_sys>; }; vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { @@ -99,6 +99,10 @@ }; }; +&combphy1 { + phy-supply = <&vcc3v3_pcie30x1>; +}; + &pcie2x1 { pinctrl-names = "default"; pinctrl-0 = <&pcie20_reset_h>; @@ -117,7 +121,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie30x1m0_pins>; reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30x1>; + vpcie3v3-supply = <&vcc3v3_minipcie>; status = "okay"; }; @@ -178,6 +182,10 @@ status = "okay"; }; +&sata1 { + status = "okay"; +}; + &sdmmc0 { bus-width = <4>; cap-sd-highspeed; diff --git a/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts new file mode 100644 index 000000000000..e333449ead04 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts @@ -0,0 +1,643 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3568.dtsi" + +/ { + model = "Firefly Station P2"; + compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + dc_12v: dc-12v-regulator { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + gmac0_clkin: external-gmac0-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac0_clkin"; + #clock-cells = <0>; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + + led-user { + label = "user-led"; + default-state = "on"; + gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led_enable_h>; + retain-state-suspended; + }; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + pcie30_avdd0v9: pcie30-avdd0v9-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie_en_pin>; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-always-on; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&combphy0 { + /* used for USB3 */ + status = "okay"; +}; + +&combphy1 { + /* used for USB3 */ + status = "okay"; +}; + +&combphy2 { + /* used for SATA */ + status = "okay"; +}; + +&gmac0 { + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + &gmac0_clkinout>; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii"; + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x3c>; + rx_delay = <0x2f>; + status = "okay"; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1m1_clkinout>; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii"; + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x4f>; + rx_delay = <0x26>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_pin>; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + leds { + user_led_enable_h: user-led-enable-h { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_reset_pin: pcie-reset-pin { + rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi index 38e1a1e25f33..727580aaa105 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi @@ -25,7 +25,6 @@ no-sdio; no-sd; non-removable; - max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts index e9d5a8bab581..9933765e4097 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts @@ -21,7 +21,73 @@ }; }; +&combphy0_ps { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* FAN */ +&pwm2 { + pinctrl-0 = <&pwm2m1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; }; + +/* RS232 */ +&uart6 { + pinctrl-0 = <&uart6m0_xfer>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* RS485 */ +&uart7 { + pinctrl-0 = <&uart7m2_xfer>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi index 1c5bcf1280b4..017559bba37f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi @@ -18,6 +18,42 @@ regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; }; &sdhci { @@ -25,8 +61,329 @@ no-sdio; no-sd; non-removable; - max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; }; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts index 4b2d857ee219..229a9111f5eb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -38,6 +38,20 @@ regulator-max-microvolt = <12000000>; }; + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_usb>; + }; + vcc5v0_sys: vcc5v0-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -47,6 +61,30 @@ regulator-max-microvolt = <5000000>; vin-supply = <&vcc12v_dcin>; }; + + vcc5v0_usbdcin: vcc5v0-usbdcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; +}; + +&combphy0_ps { + status = "okay"; }; &cpu_b0 { @@ -138,6 +176,12 @@ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm2 { @@ -149,7 +193,6 @@ no-sdio; no-sd; non-removable; - max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; @@ -760,7 +803,45 @@ }; }; +&sata0 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts new file mode 100644 index 000000000000..0bd80e515754 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dts @@ -0,0 +1,888 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2023 Thomas McKahan + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/usb/pd.h> +#include "rk3588.dtsi" + +/ { + model = "FriendlyElec NanoPC-T6"; + compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + + sys_led: led-0 { + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + label = "system-led"; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>; + }; + + usr_led: led-1 { + gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + label = "user-led"; + pinctrl-names = "default"; + pinctrl-0 = <&usr_led_pin>; + }; + }; + + sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + + simple-audio-card,name = "realtek,rt5616-codec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; + simple-audio-card,hp-pin-name = "Headphones"; + + simple-audio-card,widgets = + "Headphone", "Headphones", + "Microphone", "Microphone Jack"; + simple-audio-card,routing = + "Headphones", "HPOL", + "Headphones", "HPOR", + "MIC1", "Microphone Jack", + "Microphone Jack", "micbias1"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rt5616>; + }; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* vcc5v0_sys powers peripherals */ + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + /* vcc4v0_sys powers the RK806, RK860's */ + vcc4v0_sys: vcc4v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc-1v1-nldo-s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc4v0_sys>; + }; + + vcc_3v3_pcie20: vcc3v3-pcie20-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_pcie20"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vbus5v0_typec: vbus5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_m2_0_pwren>; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0{ + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1{ + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2{ + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3{ + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&gpio0 { + gpio-line-names = /* GPIO0 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO0 C0-C7 */ + "", "", "", "", + "HEADER_10", "HEADER_08", "HEADER_32", "", + /* GPIO0 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio1 { + gpio-line-names = /* GPIO1 A0-A7 */ + "HEADER_27", "HEADER_28", "", "", + "", "", "", "HEADER_15", + /* GPIO1 B0-B7 */ + "HEADER_26", "HEADER_21", "HEADER_19", "HEADER_23", + "HEADER_24", "HEADER_22", "", "", + /* GPIO1 C0-C7 */ + "", "", "", "", + "", "", "", "", + /* GPIO1 D0-D7 */ + "", "", "", "", + "", "", "HEADER_05", "HEADER_03"; +}; + +&gpio2 { + gpio-line-names = /* GPIO2 A0-A7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO2 C0-C7 */ + "", "CSI1_11", "CSI1_12", "", + "", "", "", "", + /* GPIO2 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = /* GPIO3 A0-A7 */ + "HEADER_35", "HEADER_38", "HEADER_40", "HEADER_36", + "HEADER_37", "", "DSI0_12", "", + /* GPIO3 B0-B7 */ + "HEADER_33", "DSI0_10", "HEADER_07", "HEADER_16", + "HEADER_18", "HEADER_29", "HEADER_31", "HEADER_12", + /* GPIO3 C0-C7 */ + "DSI0_08", "DSI0_14", "HEADER_11", "HEADER_13", + "", "", "", "", + /* GPIO3 D0-D7 */ + "", "", "", "", + "", "DSI1_10", "", ""; +}; + +&gpio4 { + gpio-line-names = /* GPIO4 A0-A7 */ + "DSI1_08", "DSI1_14", "", "DSI1_12", + "", "", "", "", + /* GPIO4 B0-B7 */ + "", "", "", "", + "", "", "", "", + /* GPIO4 C0-C7 */ + "", "", "", "", + "CSI0_11", "CSI0_12", "", "", + /* GPIO4 D0-D7 */ + "", "", "", "", + "", "", "", ""; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + rockchip,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc4v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + clock-frequency = <200000>; + status = "okay"; + + fusb302: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&usbc0_int>; + pinctrl-names = "default"; + vbus-supply = <&vbus5v0_typec>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + power-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>; + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + op-sink-microwatt = <1000000>; + }; + }; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + }; +}; + +&i2c7 { + clock-frequency = <200000>; + status = "okay"; + + rt5616: codec@1b { + compatible = "realtek,rt5616"; + reg = <0x1b>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + + port { + rt5616_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; + + /* connected with MIPI-CSI1 */ +}; + +&i2c8 { + pinctrl-0 = <&i2c8m2_xfer>; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&rt5616_p0_0>; + }; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_0_rst>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc_3v3_pcie20>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie2_2_rst>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + gpio-leds { + sys_led_pin: sys-led-pin { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usr_led_pin: usr-led-pin { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_2_rst: pcie2-2-rst { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_m2_0_pwren: pcie-m20-pwren { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm1 { + pinctrl-0 = <&pwm1m1_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + pmic@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + vcc1-supply = <&vcc4v0_sys>; + vcc2-supply = <&vcc4v0_sys>; + vcc3-supply = <&vcc4v0_sys>; + vcc4-supply = <&vcc4v0_sys>; + vcc5-supply = <&vcc4v0_sys>; + vcc6-supply = <&vcc4v0_sys>; + vcc7-supply = <&vcc4v0_sys>; + vcc8-supply = <&vcc4v0_sys>; + vcc9-supply = <&vcc4v0_sys>; + vcc10-supply = <&vcc4v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc4v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc4v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 51537030f8e3..8ab60968f275 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -11,6 +11,7 @@ aliases { mmc0 = &sdhci; + mmc1 = &sdmmc; serial2 = &uart2; }; @@ -18,17 +19,9 @@ stdout-path = "serial2:1500000n8"; }; - fan: pwm-fan { - compatible = "pwm-fan"; - cooling-levels = <0 95 145 195 255>; - fan-supply = <&vcc5v0_sys>; - pwms = <&pwm1 0 50000 0>; - #cooling-cells = <2>; - }; - - sound { + analog-sound { compatible = "audio-graph-card"; - label = "Analog"; + label = "rk3588-es8316"; widgets = "Microphone", "Mic Jack", "Headphone", "Headphones"; @@ -43,6 +36,28 @@ pinctrl-0 = <&hp_detect>; }; + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 95 145 195 255>; + fan-supply = <&vcc5v0_sys>; + pwms = <&pwm1 0 50000 0>; + #cooling-cells = <2>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + vcc5v0_sys: vcc5v0-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys"; @@ -201,6 +216,12 @@ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm1 { @@ -217,7 +238,6 @@ no-sdio; no-sd; non-removable; - max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; @@ -230,6 +250,7 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; disable-wp; sd-uhs-sdr104; vmmc-supply = <&vcc_3v3_s3>; @@ -564,3 +585,38 @@ pinctrl-0 = <&uart2m0_xfer>; status = "okay"; }; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + /* connected to USB hub, which is powered by vcc5v0_sys */ + phy-supply = <&vcc5v0_sys>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 8be75556af8f..5519c1430cb7 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,16 @@ #include "rk3588-pinctrl.dtsi" / { + pcie30_phy_grf: syscon@fd5b8000 { + compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; + }; + + pipe_phy1_grf: syscon@fd5c0000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c0000 0x0 0x100>; + }; + i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>; @@ -75,6 +85,159 @@ status = "disabled"; }; + pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0x0f>; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, + <0 0 0 2 &pcie3x4_intc 1>, + <0 0 0 3 &pcie3x4_intc 2>, + <0 0 0 4 &pcie3x4_intc 3>; + linux,pci-domain = <0>; + max-link-speed = <3>; + msi-map = <0x0000 &its1 0x0000 0x1000>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>, + <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>; + reg = <0xa 0x40000000 0x0 0x00400000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x0 0xf0000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x4_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie3x2: pcie@fe160000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x10 0x1f>; + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <1>; + max-link-speed = <3>; + msi-map = <0x1000 &its1 0x1000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>, + <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>; + reg = <0xa 0x40400000 0x0 0x00400000>, + <0x0 0xfe160000 0x0 0x00010000>, + <0x0 0xf1000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names = "pwr", "pipe"; + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie2x1l0: pcie@fe170000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, + <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, + <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, + <0 0 0 2 &pcie2x1l0_intc 1>, + <0 0 0 3 &pcie2x1l0_intc 2>, + <0 0 0 4 &pcie2x1l0_intc 3>; + linux,pci-domain = <2>; + max-link-speed = <2>; + msi-map = <0x2000 &its0 0x2000 0x1000>; + num-lanes = <1>; + phys = <&combphy1_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>, + <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>; + reg = <0xa 0x40800000 0x0 0x00400000>, + <0x0 0xfe170000 0x0 0x00010000>, + <0x0 0xf2000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + gmac0: ethernet@fe1b0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1b0000 0x0 0x10000>; @@ -123,4 +286,56 @@ queue1 {}; }; }; + + sata1: sata@fe220000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe220000 0 0x1000>; + interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, + <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, + <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy1_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + combphy1_ps: phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee10000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy1_grf>; + status = "disabled"; + }; + + pcie30phy: phy@fee80000 { + compatible = "rockchip,rk3588-pcie3-phy"; + reg = <0x0 0xfee80000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; + clock-names = "pclk"; + resets = <&cru SRST_PCIE30_PHY>; + reset-names = "phy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts index 1a60a275ddf9..d1503a4b233a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts @@ -401,7 +401,6 @@ no-sd; no-sdio; non-removable; - max-frequency = <200000000>; vmmc-supply = <&vcc_3v3_s0>; vqmmc-supply = <&vcc_1v8_s3>; status = "okay"; @@ -429,7 +428,6 @@ cap-mmc-highspeed; cap-sd-highspeed; disable-wp; - max-frequency = <200000000>; no-sdio; no-mmc; sd-uhs-sdr104; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts index 93b4a0c4ed0f..82478a452533 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts @@ -25,7 +25,6 @@ no-sdio; no-sd; non-removable; - max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts index 901825514f9d..8347adcbd003 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts @@ -3,6 +3,7 @@ /dts-v1/; #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> #include <dt-bindings/pinctrl/rockchip.h> #include "rk3588s.dtsi" @@ -12,12 +13,252 @@ aliases { mmc0 = &sdhci; + mmc1 = &sdmmc; serial2 = &uart2; }; + analog-sound { + compatible = "audio-graph-card"; + label = "rk3588-es8316"; + + widgets = "Microphone", "Mic Jack", + "Headphone", "Headphones"; + + routing = "MIC2", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR"; + + dais = <&i2s0_8ch_p0>; + }; + chosen { stdout-path = "serial2:1500000n8"; }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&io_led>; + + io-led { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_STATUS; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 95 145 195 255>; + fan-supply = <&vcc_5v0>; + pwms = <&pwm3 0 50000 0>; + #cooling-cells = <2>; + }; + + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_5v0: vcc-5v0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_npu_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + eeprom: eeprom@50 { + compatible = "belling,bl24c16a", "atmel,24c16"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m2_xfer>; +}; + +&i2c7 { + status = "okay"; + + es8316: audio-codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_8ch_p0_0>; + }; + }; + }; +}; + +&i2s0_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status = "okay"; + + i2s0_8ch_p0: port { + i2s0_8ch_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; }; &gmac1 { @@ -49,11 +290,62 @@ }; &pinctrl { + leds { + io_led: io-led { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + power { + vcc_5v0_en: vcc-5v0-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + rtl8211f { rtl8211f_rst: rtl8211f-rst { rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifibt { + wl_reset: wl-reset { + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wl_dis: wl-dis { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_output_high>; + }; + + wl_wake_host: wl-wake-host { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + bt_dis: bt-dis { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m1_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; }; &sdhci { @@ -61,13 +353,384 @@ no-sdio; no-sd; non-removable; - max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; }; +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-name = "vdd_gpu_s0"; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-name = "vdd_cpu_lit_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-name = "vdd_log_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-name = "vdd_vdenc_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-name = "vdd_ddr_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-name = "vdd2_ddr_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-name = "vdd_2v0_pldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-name = "vddq_ddr_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-name = "vcc_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-name = "avcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-name = "avdd_1v2_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-name = "vcc_3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-name = "vccio_sd_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-name = "pldo6_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-name = "vdd_0v75_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-name = "vdd_ddr_pll_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-name = "avdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-name = "vdd_0v85_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-name = "vdd_0v75_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; }; + +&usb_host0_ehci { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wl_reset &wl_dis &wl_wake_host &bt_dis &bt_wake_host>; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 1576f9bfd6de..5544f66c6ff4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -8,6 +8,8 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/rk3588-power.h> #include <dt-bindings/reset/rockchip,rk3588-cru.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/ata/ahci.h> / { compatible = "rockchip,rk3588"; @@ -397,6 +399,50 @@ }; }; + usb_host0_ehci: usb@fc800000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; + interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; + phys = <&u2phy2_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host0_ohci: usb@fc840000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc840000 0x0 0x40000>; + interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>; + phys = <&u2phy2_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ehci: usb@fc880000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc880000 0x0 0x40000>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; + phys = <&u2phy3_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ohci: usb@fc8c0000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc8c0000 0x0 0x40000>; + interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>; + phys = <&u2phy3_host>; + phy-names = "usb"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + sys_grf: syscon@fd58c000 { compatible = "rockchip,rk3588-sys-grf", "syscon"; reg = <0x0 0xfd58c000 0x0 0x1000>; @@ -407,6 +453,66 @@ reg = <0x0 0xfd5b0000 0x0 0x1000>; }; + pipe_phy0_grf: syscon@fd5bc000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + }; + + pipe_phy2_grf: syscon@fd5c4000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c4000 0x0 0x100>; + }; + + usb2phy2_grf: syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy2: usb2-phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; + #clock-cells = <0>; + status = "disabled"; + + u2phy2_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy3_grf: syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy3: usb2-phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>; + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; + #clock-cells = <0>; + status = "disabled"; + + u2phy3_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + ioc: syscon@fd5f0000 { compatible = "rockchip,rk3588-ioc", "syscon"; reg = <0x0 0xfd5f0000 0x0 0x10000>; @@ -1121,6 +1227,108 @@ reg = <0x0 0xfdf82200 0x0 0x20>; }; + pcie2x1l1: pcie@fe180000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x30 0x3f>; + clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, + <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, + <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, + <0 0 0 2 &pcie2x1l1_intc 1>, + <0 0 0 3 &pcie2x1l1_intc 2>, + <0 0 0 4 &pcie2x1l1_intc 3>; + linux,pci-domain = <3>; + max-link-speed = <2>; + msi-map = <0x3000 &its0 0x3000 0x1000>; + num-lanes = <1>; + phys = <&combphy2_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>, + <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>; + reg = <0xa 0x40c00000 0x0 0x00400000>, + <0x0 0xfe180000 0x0 0x00010000>, + <0x0 0xf3000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + + pcie2x1l2: pcie@fe190000 { + compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; + bus-range = <0x40 0x4f>; + clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, + <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, + <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, + <0 0 0 2 &pcie2x1l2_intc 1>, + <0 0 0 3 &pcie2x1l2_intc 2>, + <0 0 0 4 &pcie2x1l2_intc 3>; + linux,pci-domain = <4>; + max-link-speed = <2>; + msi-map = <0x4000 &its0 0x4000 0x1000>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>, + <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>, + <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>; + reg = <0xa 0x41000000 0x0 0x00400000>, + <0x0 0xfe190000 0x0 0x00010000>, + <0x0 0xf4000000 0x0 0x00100000>; + reg-names = "dbi", "apb", "config"; + resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; + reset-names = "pwr", "pipe"; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + pcie2x1l2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>; + }; + }; + gmac1: ethernet@fe1c0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1c0000 0x0 0x10000>; @@ -1170,6 +1378,52 @@ }; }; + sata0: sata@fe210000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe210000 0 0x1000>; + interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, + <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, + <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy0_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + + sata2: sata@fe230000 { + compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfe230000 0 0x1000>; + interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, + <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, + <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + ports-implemented = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sata-port@0 { + reg = <0>; + hba-port-cap = <HBA_PORT_FBSCP>; + phys = <&combphy2_psu PHY_TYPE_SATA>; + phy-names = "sata-phy"; + snps,rx-ts-max = <32>; + snps,tx-ts-max = <32>; + }; + }; + sdmmc: mmc@fe2c0000 { compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe2c0000 0x0 0x4000>; @@ -1943,6 +2197,38 @@ #dma-cells = <1>; }; + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + status = "disabled"; + }; + + combphy2_psu: phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee20000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy2_grf>; + status = "disabled"; + }; + system_sram2: sram@ff001000 { compatible = "mmio-sram"; reg = <0x0 0xff001000 0x0 0xef000>; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 1c53c68efd53..bb50a9f7db4a 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -353,8 +353,8 @@ compatible = "arm,gic-v3"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */ - <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ + reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */ + <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 6dd7b6f1d6ab..e7b8e2e7f083 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -19,14 +19,27 @@ dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_K3) += k3-am625-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am62x-sk-hdmi-audio.dtbo # Boards with AM62Ax SoC dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb +# Boards with AM62Px SoC +dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb + # Boards with AM64x SoC dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-phyboard-electra-rdk.dtb dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl.dtb + +k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ + k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo +k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ + k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo + +dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb +dtb-$(CONFIG_ARCH_K3) += k3-am642-tqma64xxl-mbax4xxl-wlan.dtb # Boards with AM65x SoC k3-am654-gp-evm-dtbs := k3-am654-base-board.dtb k3-am654-base-board-rocktech-rk101-panel.dtbo @@ -46,15 +59,21 @@ dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm.dtb k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb # Boards with J721s2 SoC dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb # Enable support for device-tree overlays +DTC_FLAGS_k3-am625-sk += -@ +DTC_FLAGS_k3-am62-lp-sk += -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ +DTC_FLAGS_k3-j721e-common-proc-board += -@ +DTC_FLAGS_k3-j721s2-common-proc-board += -@ diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 2488e3a537fe..284b90c94da8 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -55,11 +55,29 @@ #phy-cells = <1>; }; - epwm_tbclk: clock@4130 { - compatible = "ti,am62-epwm-tbclk", "syscon"; + epwm_tbclk: clock-controller@4130 { + compatible = "ti,am62-epwm-tbclk"; reg = <0x4130 0x4>; #clock-cells = <1>; }; + + audio_refclk0: clock-controller@82e0 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e0 0x4>; + clocks = <&k3_clks 157 0>; + assigned-clocks = <&k3_clks 157 0>; + assigned-clock-parents = <&k3_clks 157 8>; + #clock-cells = <0>; + }; + + audio_refclk1: clock-controller@82e4 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e4 0x4>; + clocks = <&k3_clks 157 10>; + assigned-clocks = <&k3_clks 157 10>; + assigned-clock-parents = <&k3_clks 157 18>; + #clock-cells = <0>; + }; }; dmss: bus@48000000 { @@ -174,7 +192,6 @@ crypto: crypto@40900000 { compatible = "ti,am62-sa3ul"; reg = <0x00 0x40900000 0x00 0x1200>; - power-domains = <&k3_pds 70 TI_SCI_PD_SHARED>; #address-cells = <2>; #size-cells = <2>; ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; @@ -590,7 +607,7 @@ usb0: usb@31000000 { compatible = "snps,dwc3"; - reg =<0x00 0x31000000 0x00 0x50000>; + reg = <0x00 0x31000000 0x00 0x50000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ interrupt-names = "host", "peripheral"; @@ -613,7 +630,7 @@ usb1: usb@31100000 { compatible = "snps,dwc3"; - reg =<0x00 0x31100000 0x00 0x50000>; + reg = <0x00 0x31100000 0x00 0x50000>; interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ interrupt-names = "host", "peripheral"; @@ -718,6 +735,31 @@ }; }; + dss: dss@30200000 { + compatible = "ti,am625-dss"; + reg = <0x00 0x30200000 0x00 0x1000>, /* common */ + <0x00 0x30202000 0x00 0x1000>, /* vidl1 */ + <0x00 0x30206000 0x00 0x1000>, /* vid */ + <0x00 0x30207000 0x00 0x1000>, /* ovr1 */ + <0x00 0x30208000 0x00 0x1000>, /* ovr2 */ + <0x00 0x3020a000 0x00 0x1000>, /* vp1: Used for OLDI */ + <0x00 0x3020b000 0x00 0x1000>; /* vp2: Used as DPI Out */ + reg-names = "common", "vidl1", "vid", + "ovr1", "ovr2", "vp1", "vp2"; + power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 186 6>, + <&dss_vp1_clk>, + <&k3_clks 186 2>; + clock-names = "fck", "vp1", "vp2"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + dss_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + hwspinlock: spinlock@2a000000 { compatible = "ti,am64-hwspinlock"; reg = <0x00 0x2a000000 0x00 0x1000>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi index 19fc38157d94..80a3e1db26a9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -147,4 +147,28 @@ /* Tightly coupled to M4F */ status = "reserved"; }; + + mcu_mcan0: can@4e08000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e08000 0x00 0x200>, + <0x00 0x4e00000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcu_mcan1: can@4e18000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e18000 0x00 0x200>, + <0x00 0x4e10000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi index 3abd8d1d6761..013357d17d48 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dahlia.dtsi @@ -8,6 +8,43 @@ * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit */ +/ { + reg_1v8_sw: regulator-1v8-sw { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-carrier +V1.8_SW"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,name = "verdin-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Headphone Jack", "MICBIAS", + "IN1L", "Headphone Jack"; + simple-audio-card,widgets = + "Microphone", "Headphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + clocks = <&audio_refclk1>; + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + }; + }; +}; + /* Verdin ETHs */ &cpsw3g { status = "okay"; @@ -46,6 +83,22 @@ &main_i2c1 { status = "okay"; + /* Audio Codec */ + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s1_mclk>; + #sound-dai-cells = <0>; + clocks = <&audio_refclk1>; + clock-names = "mclk"; + AVDD-supply = <®_1v8_sw>; + CPVDD-supply = <®_1v8_sw>; + DBVDD-supply = <®_1v8_sw>; + DCVDD-supply = <®_1v8_sw>; + MICVDD-supply = <®_1v8_sw>; + }; + /* Current measurement into module VCC */ hwmon@40 { compatible = "ti,ina219"; @@ -115,6 +168,11 @@ status = "okay"; }; +/* Verdin CAN_2 */ +&mcu_mcan0 { + status = "okay"; +}; + /* Verdin UART_4 */ &mcu_uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi index 846caee7dfa4..6701cb8974bb 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi @@ -8,6 +8,42 @@ * https://www.toradex.com/products/carrier-board/verdin-development-board-kit */ +/ { + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,name = "verdin-nau8822"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "Line Out", "AUXOUT1", + "Line Out", "AUXOUT2", + "LAUX", "Line In", + "RAUX", "Line In", + "LMICP", "Mic In", + "RMICP", "Mic In"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Line Out", "Line Out", + "Speaker", "Speaker", + "Microphone", "Mic In", + "Line", "Line In"; + + codec_dai: simple-audio-card,codec { + clocks = <&audio_refclk1>; + sound-dai = <&nau8822_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + }; + }; +}; + /* Verdin ETHs */ &cpsw3g { pinctrl-names = "default"; @@ -65,6 +101,15 @@ &main_i2c1 { status = "okay"; + /* Audio Codec */ + nau8822_1a: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s1_mclk>; + #sound-dai-cells = <0>; + }; + /* IO Expander */ gpio_expander_21: gpio@21 { compatible = "nxp,pcal6416"; @@ -144,6 +189,11 @@ status = "okay"; }; +/* Verdin CAN_2 */ +&mcu_mcan0 { + status = "okay"; +}; + /* Verdin UART_4 */ &mcu_uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi index cb11d6e7f525..c685df7deaee 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-yavia.dtsi @@ -167,6 +167,11 @@ status = "okay"; }; +/* Verdin CAN_2 */ +&mcu_mcan0 { + status = "okay"; +}; + /* Verdin UART_4 */ &mcu_uart0 { status = "okay"; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index 57dd061911ab..40992e7e4c30 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -19,6 +19,8 @@ }; aliases { + can0 = &main_mcan0; + can1 = &mcu_mcan0; ethernet0 = &cpsw_port1; ethernet1 = &cpsw_port2; i2c0 = &main_i2c0; @@ -732,6 +734,14 @@ >; }; + /* Verdin CAN_2 */ + pinctrl_mcu_mcan0: mcu-mcan0-default-pins { + pinctrl-single,pins = < + AM62X_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (B3) MCU_MCAN0_RX */ /* SODIMM 26 */ + AM62X_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (D6) MCU_MCAN0_TX */ /* SODIMM 24 */ + >; + }; + /* Verdin UART_4 - Reserved to Cortex-M4 */ pinctrl_mcu_uart0: mcu-uart0-default-pins { pinctrl-single,pins = < @@ -758,6 +768,11 @@ }; }; +/* VERDIN I2S_1_MCLK */ +&audio_refclk1 { + assigned-clock-rates = <25000000>; +}; + &cpsw3g { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rgmii1>; @@ -800,6 +815,26 @@ }; }; +&dss { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_rgb>; + status = "disabled"; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* VP2: DPI Output */ + port@1 { + reg = <1>; + + dpi_out: endpoint { + remote-endpoint = <&rgb_in>; + }; + }; +}; + /* Verdin PWM_1, PWM_2 */ &epwm0 { pinctrl-names = "default"; @@ -1036,6 +1071,7 @@ rgb_in: endpoint { data-lines = <18>; + remote-endpoint = <&dpi_out>; }; }; @@ -1238,8 +1274,6 @@ status = "disabled"; }; -/* Verdin CAN_2 - Reserved to Cortex-M4 */ - /* Verdin SPI_1 */ &main_spi1 { pinctrl-names = "default"; @@ -1333,6 +1367,13 @@ ""; }; +/* Verdin CAN_2 */ +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_mcan0>; + status = "disabled"; +}; + /* Verdin UART_4 - Cortex-M4 UART */ &mcu_uart0 { pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi index 5e72c445f37a..11f14eef2d44 100644 --- a/arch/arm64/boot/dts/ti/k3-am62.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -102,6 +102,14 @@ }; }; + dss_vp1_clk: clock-divider-oldi { + compatible = "fixed-factor-clock"; + clocks = <&k3_clks 186 0>; + #clock-cells = <0>; + clock-div = <7>; + clock-mult = <1>; + }; + #include "k3-am62-thermal.dtsi" }; diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts index 589bf998bc52..7cfdf562b53b 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -14,7 +14,7 @@ #include "k3-am625.dtsi" / { - compatible = "beagle,am625-beagleplay", "ti,am625"; + compatible = "beagle,am625-beagleplay", "ti,am625"; model = "BeagleBoard.org BeaglePlay"; aliases { @@ -192,6 +192,34 @@ }; + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&it66121_out>; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "it66121 HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&hdmi_dailink_master>; + simple-audio-card,frame-master = <&hdmi_dailink_master>; + + hdmi_dailink_master: simple-audio-card,cpu { + sound-dai = <&mcasp1>; + system-clock-direction-out; + }; + + simple-audio-card,codec { + sound-dai = <&it66121>; + }; + }; + /* Workaround for errata i2329 - just use mdio bitbang */ mdio0: mdio { compatible = "virtual,mdio-gpio"; @@ -422,6 +450,57 @@ AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */ >; }; + + hdmi_gpio_pins_default: hdmi-gpio-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0094, PIN_INPUT_PULLUP | PIN_DEBOUNCE_CONF6, 7) /* (N20) GPMC0_BE1n.GPIO0_36 */ + AM62X_IOPAD(0x0054, PIN_OUTPUT_PULLUP, 7) /* (P21) GPMC0_AD6.GPIO0_21 */ + >; + }; + + mcasp_hdmi_pins_default: mcasp-hdmi-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0090, PIN_INPUT, 2) /* (M24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ + AM62X_IOPAD(0x0098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ + AM62X_IOPAD(0x008c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEn.MCASP1_AXR0 */ + AM62X_IOPAD(0x0088, PIN_INPUT, 2) /* (L24) GPMC0_OEn_REn.MCASP1_AXR1 */ + AM62X_IOPAD(0x0084, PIN_INPUT, 2) /* (L23) GPMC0_ADVn_ALE.MCASP1_AXR2 */ + AM62X_IOPAD(0x007c, PIN_INPUT, 2) /* (P25) GPMC0_CLK.MCASP1_AXR3 */ + >; + }; + + dss0_pins_default: dss0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x0100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ + AM62X_IOPAD(0x00f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ + AM62X_IOPAD(0x0104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ + AM62X_IOPAD(0x00fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ + AM62X_IOPAD(0x00b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62X_IOPAD(0x00bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ + AM62X_IOPAD(0x00c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ + AM62X_IOPAD(0x00c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ + AM62X_IOPAD(0x00c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ + AM62X_IOPAD(0x00cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ + AM62X_IOPAD(0x00d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ + AM62X_IOPAD(0x00d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ + AM62X_IOPAD(0x00d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ + AM62X_IOPAD(0x00dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ + AM62X_IOPAD(0x00e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ + AM62X_IOPAD(0x00e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ + AM62X_IOPAD(0x00e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ + AM62X_IOPAD(0x00ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ + AM62X_IOPAD(0x00f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ + AM62X_IOPAD(0x00f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ + AM62X_IOPAD(0x005c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ + AM62X_IOPAD(0x0060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ + AM62X_IOPAD(0x0064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */ + AM62X_IOPAD(0x0068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */ + AM62X_IOPAD(0x006c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ + AM62X_IOPAD(0x0070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */ + AM62X_IOPAD(0x0074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */ + AM62X_IOPAD(0x0078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */ + >; + }; }; &mcu_pmx0 { @@ -432,7 +511,7 @@ >; }; - gbe_pmx_obsclk: gbe-pmx-clk-default { + gbe_pmx_obsclk: gbe-pmx-obsclk-default-pins { pinctrl-single,pins = < AM62X_MCU_IOPAD(0x0004, PIN_OUTPUT, 1) /* (B8) MCU_SPI0_CS1.MCU_OBSCLK0 */ >; @@ -670,6 +749,42 @@ pinctrl-0 = <&i2c2_1v8_pins_default>; clock-frequency = <100000>; status = "okay"; + + it66121: bridge-hdmi@4c { + compatible = "ite,it66121"; + reg = <0x4c>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_gpio_pins_default>; + vcn33-supply = <&vdd_3v3>; + vcn18-supply = <&buck2_reg>; + vrf12-supply = <&buck3_reg>; + reset-gpios = <&main_gpio0 21 GPIO_ACTIVE_LOW>; + interrupt-parent = <&main_gpio0>; + interrupts = <36 IRQ_TYPE_EDGE_FALLING>; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + it66121_in: endpoint { + bus-width = <24>; + remote-endpoint = <&dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + it66121_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; }; &main_i2c3 { @@ -756,3 +871,38 @@ pinctrl-0 = <&wifi_debug_uart_pins_default>; status = "okay"; }; + +&dss { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dss0_pins_default>; +}; + +&dss_ports { + /* VP2: DPI Output */ + port@1 { + reg = <1>; + + dpi1_out: endpoint { + remote-endpoint = <&it66121_in>; + }; + }; +}; + +&mcasp1 { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp_hdmi_pins_default>; + auxclk-fs-ratio = <2177>; + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 3f9ef4053aa6..7c98c1b855d1 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -212,7 +212,7 @@ pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi index 8b315cc61550..3198af08fb9f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -56,7 +56,7 @@ }; epwm_tbclk: clock-controller@4130 { - compatible = "ti,am62-epwm-tbclk", "syscon"; + compatible = "ti,am62-epwm-tbclk"; reg = <0x4130 0x4>; #clock-cells = <1>; }; @@ -150,8 +150,8 @@ reg-names = "debug_messages"; ti,host-id = <12>; mbox-names = "rx", "tx"; - mboxes= <&secure_proxy_main 12>, - <&secure_proxy_main 13>; + mboxes = <&secure_proxy_main 12>, + <&secure_proxy_main 13>; k3_pds: power-controller { compatible = "ti,sci-pm-domain"; @@ -527,7 +527,7 @@ usb0: usb@31000000 { compatible = "snps,dwc3"; - reg =<0x00 0x31000000 0x00 0x50000>; + reg = <0x00 0x31000000 0x00 0x50000>; interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ interrupt-names = "host", "peripheral"; @@ -550,7 +550,7 @@ usb1: usb@31100000 { compatible = "snps,dwc3"; - reg =<0x00 0x31100000 0x00 0x50000>; + reg = <0x00 0x31100000 0x00 0x50000>; interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ interrupt-names = "host", "peripheral"; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi index 04599762c2b7..a6d16a94088c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -143,4 +143,28 @@ /* Tightly coupled to M4F */ status = "reserved"; }; + + mcu_mcan0: can@4e08000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e08000 0x00 0x200>, + <0x00 0x4e00000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 188 6>, <&k3_clks 188 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; + + mcu_mcan1: can@4e18000 { + compatible = "bosch,m_can"; + reg = <0x00 0x4e18000 0x00 0x200>, + <0x00 0x4e10000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 189 6>, <&k3_clks 189 1>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index ecc0e13331c4..cff283c75f8e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -13,7 +13,7 @@ #include "k3-am62a7.dtsi" / { - compatible = "ti,am62a7-sk", "ti,am62a7"; + compatible = "ti,am62a7-sk", "ti,am62a7"; model = "Texas Instruments AM62A7 SK"; aliases { @@ -226,6 +226,24 @@ pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + + typec_pd0: usb-power-controller@3f { + compatible = "ti,tps6598x"; + reg = <0x3f>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + self-powered; + data-role = "dual"; + power-role = "sink"; + port { + usb_con_hs: endpoint { + remote-endpoint = <&usb0_hs_ep>; + }; + }; + }; + }; }; &main_i2c1 { @@ -290,6 +308,21 @@ status = "reserved"; }; +&usbss0 { + status = "okay"; + ti,vbus-divider; +}; + +&usb0 { + usb-role-switch; + + port { + usb0_hs_ep: endpoint { + remote-endpoint = <&usb_con_hs>; + }; + }; +}; + &usbss1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi new file mode 100644 index 000000000000..c24ff905437f --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P main domain peripherals + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_main { + oc_sram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x00 0x70000000 0x00 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x70000000 0x10000>; + }; + + gic500: interrupt-controller@1800000 { + compatible = "arm,gic-v3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ + <0x00 0x01880000 0x00 0xc0000>, /* GICR */ + <0x01 0x00000000 0x00 0x2000>, /* GICC */ + <0x01 0x00010000 0x00 0x1000>, /* GICH */ + <0x01 0x00020000 0x00 0x2000>; /* GICV */ + /* + * vcpumntirq: + * virtual CPU interface maintenance interrupt + */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gic_its: msi-controller@1820000 { + compatible = "arm,gic-v3-its"; + reg = <0x00 0x01820000 0x00 0x10000>; + socionext,synquacer-pre-its = <0x1000000 0x400000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + dmss: bus@48000000 { + bootph-all; + compatible = "simple-mfd"; + #address-cells = <2>; + #size-cells = <2>; + dma-ranges; + ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; + + ti,sci-dev-id = <25>; + + secure_proxy_main: mailbox@4d000000 { + bootph-all; + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg-names = "target_data", "rt", "scfg"; + reg = <0x00 0x4d000000 0x00 0x80000>, + <0x00 0x4a600000 0x00 0x80000>, + <0x00 0x4a400000 0x00 0x80000>; + interrupt-names = "rx_012"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + dmsc: system-controller@44043000 { + bootph-all; + compatible = "ti,k2g-sci"; + ti,host-id = <12>; + mbox-names = "rx", "tx"; + mboxes = <&secure_proxy_main 12>, + <&secure_proxy_main 13>; + reg-names = "debug_messages"; + reg = <0x00 0x44043000 0x00 0xfe0>; + + k3_pds: power-controller { + bootph-all; + compatible = "ti,sci-pm-domain"; + #power-domain-cells = <2>; + }; + + k3_clks: clock-controller { + bootph-all; + compatible = "ti,k2g-sci-clk"; + #clock-cells = <2>; + }; + + k3_reset: reset-controller { + bootph-all; + compatible = "ti,sci-reset"; + #reset-cells = <2>; + }; + }; + + main_pmx0: pinctrl@f4000 { + bootph-all; + compatible = "pinctrl-single"; + reg = <0x00 0xf4000 0x00 0x2ac>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + main_timer0: timer@2400000 { + bootph-all; + compatible = "ti,am654-timer"; + reg = <0x00 0x2400000 0x00 0x400>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&k3_clks 36 2>; + clock-names = "fck"; + assigned-clocks = <&k3_clks 36 2>; + assigned-clock-parents = <&k3_clks 36 3>; + power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; + ti,timer-pwm; + }; + + main_uart0: serial@2800000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02800000 0x00 0x100>; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 146 0>; + clock-names = "fclk"; + status = "disabled"; + }; + + main_uart1: serial@2810000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x02810000 0x00 0x100>; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 152 0>; + clock-names = "fclk"; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi new file mode 100644 index 000000000000..27ca1c9c6d13 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P MCU domain peripherals + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_mcu { + mcu_pmx0: pinctrl@4084000 { + compatible = "pinctrl-single"; + reg = <0x00 0x04084000 0x00 0x88>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi new file mode 100644 index 000000000000..aaf4b793b58e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P wakeup domain peripherals + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +&cbass_wakeup { + wkup_conf: bus@43000000 { + bootph-all; + compatible = "simple-bus"; + reg = <0x00 0x43000000 0x00 0x20000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00 0x00 0x43000000 0x20000>; + + chipid: chipid@14 { + bootph-all; + compatible = "ti,am654-chipid"; + reg = <0x14 0x4>; + }; + }; + + wkup_uart0: serial@2b300000 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0x00 0x2b300000 0x00 0x100>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 114 0>; + clock-names = "fclk"; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p.dtsi new file mode 100644 index 000000000000..294ab73ec98b --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p.dtsi @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for AM62P SoC Family + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/ti,sci_pm_domain.h> + +#include "k3-pinctrl.h" + +/ { + model = "Texas Instruments K3 AM62P5 SoC"; + compatible = "ti,am62p5"; + interrupt-parent = <&gic500>; + #address-cells = <2>; + #size-cells = <2>; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + a53_timer0: timer-cl0-cpu0 { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ + }; + + pmu: pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + cbass_main: bus@f0000 { + bootph-all; + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ + <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ + <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ + <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ + <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ + <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ + <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ + <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ + <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ + <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ + <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ + <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ + <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ + <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ + <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */ + <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ + <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ + <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ + <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ + <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ + <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ + <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ + <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ + <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ + <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ + + /* MCU Domain Range */ + <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, + + /* Wakeup Domain Range */ + <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; + + cbass_mcu: bus@4000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, /* Peripheral window */ + <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */ + <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */ + <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU IRAM0 */ + <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>; /* MCU IRAM1 */ + }; + + cbass_wakeup: bus@b00000 { + bootph-all; + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ + <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* WKUP CTRL MMR */ + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ + }; + }; +}; + +/* Now include peripherals for each bus segment */ +#include "k3-am62p-main.dtsi" +#include "k3-am62p-mcu.dtsi" +#include "k3-am62p-wakeup.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts new file mode 100644 index 000000000000..6fb17b17c95e --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P5-SK + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * Schematics: https://www.ti.com/lit/zip/sprr487 + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" + +/ { + compatible = "ti,am62p5-sk", "ti,am62p5"; + model = "Texas Instruments AM62P5 SK"; + + aliases { + serial0 = &wkup_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + }; + + chosen { + stdout-path = &main_uart0; + }; + + memory@80000000 { + /* 8G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0x01e00000>; + no-map; + }; + }; +}; + +&main_pmx0 { + main_uart0_pins_default: main-uart0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ + AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ + AM62PX_IOPAD(0x1d0, PIN_INPUT, 0) /* (A23) UART0_CTSn */ + AM62PX_IOPAD(0x1d4, PIN_OUTPUT, 0) /* (C22) UART0_RTSn */ + >; + }; + + main_uart1_pins_default: main-uart1-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62PX_IOPAD(0x194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3 */ + AM62PX_IOPAD(0x198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2 */ + AM62PX_IOPAD(0x1ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR */ + AM62PX_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR */ + >; + }; +}; + +&main_uart0 { + bootph-all; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; + status = "okay"; +}; + +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; + /* Main UART1 is used by TIFS firmware */ + status = "reserved"; +}; + +&cbass_mcu { + bootph-all; +}; + +&mcu_pmx0 { + bootph-all; + wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-all; + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x02c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ + AM62PX_MCU_IOPAD(0x030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ + AM62PX_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ + AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ + >; + }; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + bootph-all; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; + status = "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi new file mode 100644 index 000000000000..50147bb63e03 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree file for the AM62P5 SoC family (quad core) + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + * + * TRM: https://www.ti.com/lit/pdf/spruj83 + */ + +/dts-v1/; + +#include "k3-am62p.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x000>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 135 0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x001>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 136 0>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x002>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 137 0>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x003>; + device_type = "cpu"; + enable-method = "psci"; + i-cache-size = <0x8000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_0>; + clocks = <&k3_clks 138 0>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <512>; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi index 34c8ffc553ec..677ff8de4b6e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -114,6 +114,17 @@ clocks = <&tlv320_mclk>; }; }; + + hdmi0: connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&sii9022_out>; + }; + }; + }; }; &main_pmx0 { @@ -226,6 +237,39 @@ AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23/K20) GPMC0_ADVN_ALE.MCASP1_AXR2 */ >; }; + + main_dss0_pins_default: main-dss0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x100, PIN_OUTPUT, 0) /* (AC25) VOUT0_VSYNC */ + AM62X_IOPAD(0x0f8, PIN_OUTPUT, 0) /* (AB24) VOUT0_HSYNC */ + AM62X_IOPAD(0x104, PIN_OUTPUT, 0) /* (AC24) VOUT0_PCLK */ + AM62X_IOPAD(0x0fc, PIN_OUTPUT, 0) /* (Y20) VOUT0_DE */ + AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ + AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V24) VOUT0_DATA1 */ + AM62X_IOPAD(0x0c0, PIN_OUTPUT, 0) /* (W25) VOUT0_DATA2 */ + AM62X_IOPAD(0x0c4, PIN_OUTPUT, 0) /* (W24) VOUT0_DATA3 */ + AM62X_IOPAD(0x0c8, PIN_OUTPUT, 0) /* (Y25) VOUT0_DATA4 */ + AM62X_IOPAD(0x0cc, PIN_OUTPUT, 0) /* (Y24) VOUT0_DATA5 */ + AM62X_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (Y23) VOUT0_DATA6 */ + AM62X_IOPAD(0x0d4, PIN_OUTPUT, 0) /* (AA25) VOUT0_DATA7 */ + AM62X_IOPAD(0x0d8, PIN_OUTPUT, 0) /* (V21) VOUT0_DATA8 */ + AM62X_IOPAD(0x0dc, PIN_OUTPUT, 0) /* (W21) VOUT0_DATA9 */ + AM62X_IOPAD(0x0e0, PIN_OUTPUT, 0) /* (V20) VOUT0_DATA10 */ + AM62X_IOPAD(0x0e4, PIN_OUTPUT, 0) /* (AA23) VOUT0_DATA11 */ + AM62X_IOPAD(0x0e8, PIN_OUTPUT, 0) /* (AB25) VOUT0_DATA12 */ + AM62X_IOPAD(0x0ec, PIN_OUTPUT, 0) /* (AA24) VOUT0_DATA13 */ + AM62X_IOPAD(0x0f0, PIN_OUTPUT, 0) /* (Y22) VOUT0_DATA14 */ + AM62X_IOPAD(0x0f4, PIN_OUTPUT, 0) /* (AA21) VOUT0_DATA15 */ + AM62X_IOPAD(0x05c, PIN_OUTPUT, 1) /* (R24) GPMC0_AD8.VOUT0_DATA16 */ + AM62X_IOPAD(0x060, PIN_OUTPUT, 1) /* (R25) GPMC0_AD9.VOUT0_DATA17 */ + AM62X_IOPAD(0x064, PIN_OUTPUT, 1) /* (T25) GPMC0_AD10.VOUT0_DATA18 */ + AM62X_IOPAD(0x068, PIN_OUTPUT, 1) /* (R21) GPMC0_AD11.VOUT0_DATA19 */ + AM62X_IOPAD(0x06c, PIN_OUTPUT, 1) /* (T22) GPMC0_AD12.VOUT0_DATA20 */ + AM62X_IOPAD(0x070, PIN_OUTPUT, 1) /* (T24) GPMC0_AD13.VOUT0_DATA21 */ + AM62X_IOPAD(0x074, PIN_OUTPUT, 1) /* (U25) GPMC0_AD14.VOUT0_DATA22 */ + AM62X_IOPAD(0x078, PIN_OUTPUT, 1) /* (U24) GPMC0_AD15.VOUT0_DATA23 */ + >; + }; }; &mcu_pmx0 { @@ -300,7 +344,7 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; - clock-frequency = <400000>; + clock-frequency = <100000>; tlv320aic3106: audio-codec@1b { #sound-dai-cells = <0>; @@ -313,6 +357,36 @@ IOVDD-supply = <&vcc_3v3_sys>; DRVDD-supply = <&vcc_3v3_sys>; }; + + sii9022: bridge-hdmi@3b { + compatible = "sil,sii9022"; + reg = <0x3b>; + interrupt-parent = <&exp1>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; + #sound-dai-cells = <0>; + sil,i2s-data-lanes = < 0 >; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in: endpoint { + remote-endpoint = <&dpi1_out>; + }; + }; + + port@1 { + reg = <1>; + + sii9022_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; }; &sdhci0 { @@ -410,3 +484,20 @@ tx-num-evt = <32>; rx-num-evt = <32>; }; + +&dss { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_dss0_pins_default>; +}; + +&dss_ports { + /* VP2: DPI Output */ + port@1 { + reg = <1>; + + dpi1_out: endpoint { + remote-endpoint = <&sii9022_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-audio.dtso b/arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-audio.dtso new file mode 100644 index 000000000000..43a0ddc123e5 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-hdmi-audio.dtso @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * Audio playback via HDMI for AM625-SK and AM62-LP SK. + * + * Links: + * AM625 SK: https://www.ti.com/tool/SK-AM62 + * AM62-LP SK: https://www.ti.com/tool/SK-AM62-LP + * + * Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +&{/} { + hdmi_audio: sound-sii9022 { + compatible = "simple-audio-card"; + simple-audio-card,name = "AM62x-Sil9022-HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&hdmi_dailink_master>; + simple-audio-card,frame-master = <&hdmi_dailink_master>; + + hdmi_dailink_master: simple-audio-card,cpu { + sound-dai = <&mcasp1>; + system-clock-direction-out; + }; + + simple-audio-card,codec { + sound-dai = <&sii9022>; + }; + }; +}; + +&mcasp1 { + auxclk-fs-ratio = <2177>; +}; + +&codec_audio { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 1664d9f0241c..0df54a741824 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -44,11 +44,28 @@ #size-cells = <1>; ranges = <0x0 0x0 0x43000000 0x20000>; + chipid@14 { + compatible = "ti,am654-chipid"; + reg = <0x00000014 0x4>; + }; + serdes_ln_ctrl: mux-controller { compatible = "mmio-mux"; #mux-control-cells = <1>; mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ }; + + phy_gmii_sel: phy@4044 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4044 0x8>; + #phy-cells = <1>; + }; + + epwm_tbclk: clock-controller@4140 { + compatible = "ti,am64-epwm-tbclk"; + reg = <0x4130 0x4>; + #clock-cells = <1>; + }; }; gic500: interrupt-controller@1800000 { @@ -203,31 +220,6 @@ pinctrl-single,function-mask = <0xffffffff>; }; - main_conf: syscon@43000000 { - compatible = "syscon", "simple-mfd"; - reg = <0x00 0x43000000 0x00 0x20000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x00 0x00 0x43000000 0x20000>; - - chipid@14 { - compatible = "ti,am654-chipid"; - reg = <0x00000014 0x4>; - }; - - phy_gmii_sel: phy@4044 { - compatible = "ti,am654-phy-gmii-sel"; - reg = <0x4044 0x8>; - #phy-cells = <1>; - }; - - epwm_tbclk: clock@4140 { - compatible = "ti,am64-epwm-tbclk", "syscon"; - reg = <0x4130 0x4>; - #clock-cells = <1>; - }; - }; - main_timer0: timer@2400000 { compatible = "ti,am654-timer"; reg = <0x00 0x2400000 0x00 0x400>; @@ -733,7 +725,7 @@ pinctrl-single,function-mask = <0x000107ff>; }; - usbss0: cdns-usb@f900000{ + usbss0: cdns-usb@f900000 { compatible = "ti,am64-usb"; reg = <0x00 0xf900000 0x00 0x100>; power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; @@ -744,7 +736,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; - usb0: usb@f400000{ + usb0: usb@f400000 { compatible = "cdns,usb3"; reg = <0x00 0xf400000 0x00 0x10000>, <0x00 0xf410000 0x00 0x10000>, @@ -773,6 +765,7 @@ assigned-clock-parents = <&k3_clks 0 3>; assigned-clock-rates = <60000000>; clock-names = "fck"; + status = "disabled"; adc { #io-channel-cells = <1>; @@ -802,6 +795,7 @@ assigned-clock-parents = <&k3_clks 75 7>; assigned-clock-rates = <166666666>; power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi index 5606d775153d..1c2c8f0daca9 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -181,6 +181,7 @@ }; &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso b/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso new file mode 100644 index 000000000000..79ed19c6c0e9 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-sdcard.dtso @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany. + */ + +/dts-v1/; +/plugin/; + +&sdhci1 { + vmmc-supply = <®_sd>; + no-sdio; + status = "okay"; +}; + +&main_gpio0 { + line43-hog { + gpio-hog; + gpios = <43 0>; + line-name = "MMC1_CTRL"; + output-low; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso b/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso new file mode 100644 index 000000000000..32596a84b7ba --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am64-tqma64xxl-mbax4xxl-wlan.dtso @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany. + */ + +/dts-v1/; +/plugin/; + +&sdhci1 { + mmc-pwrseq = <&wifi_pwrseq>; + no-sd; + status = "okay"; +}; + +&main_gpio0 { + line43-hog { + gpio-hog; + gpios = <43 0>; + line-name = "MMC1_CTRL"; + output-high; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 15c282c93467..b4a1f73d4fb1 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -6,12 +6,13 @@ /dts-v1/; #include <dt-bindings/phy/phy.h> -#include <dt-bindings/mux/ti-serdes.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/net/ti-dp83867.h> #include "k3-am642.dtsi" +#include "k3-serdes.h" + / { compatible = "ti,am642-evm", "ti,am642"; model = "Texas Instruments AM642 EVM"; @@ -519,6 +520,7 @@ }; &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts index 9c418abd29d8..9175e96842d8 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-phyboard-electra-rdk.dts @@ -16,11 +16,12 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/leds/leds-pca9532.h> -#include <dt-bindings/mux/ti-serdes.h> #include <dt-bindings/phy/phy.h> #include "k3-am642.dtsi" #include "k3-am64-phycore-som.dtsi" +#include "k3-serdes.h" + / { compatible = "phytec,am642-phyboard-electra-rdk", "phytec,am64-phycore-som", "ti,am642"; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index cbce43dbe3f9..722fd285a34e 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -5,13 +5,14 @@ /dts-v1/; -#include <dt-bindings/mux/ti-serdes.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/net/ti-dp83867.h> #include <dt-bindings/leds/common.h> #include "k3-am642.dtsi" +#include "k3-serdes.h" + / { compatible = "ti,am642-sk", "ti,am642"; model = "Texas Instruments AM642 SK"; @@ -512,11 +513,8 @@ }; }; -&tscadc0 { - status = "disabled"; -}; - &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts new file mode 100644 index 000000000000..04c15b64f0b7 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts @@ -0,0 +1,872 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/pwm/pwm.h> +#include "k3-serdes.h" + +#include "k3-am642-tqma64xxl.dtsi" + +/ { + compatible = "tq,am642-tqma6442l-mbax4xxl", "tq,am642-tqma6442l", + "ti,am642"; + model = "TQ-Systems TQMa64xxL SoM on MBax4xxL carrier board"; + + aliases { + ethernet0 = &cpsw_port1; + i2c1 = &mcu_i2c0; + mmc1 = &sdhci1; + serial0 = &mcu_uart0; + serial1 = &mcu_uart1; + serial2 = &main_uart0; + serial3 = &main_uart1; + serial4 = &main_uart2; + serial5 = &main_uart4; + serial6 = &main_uart5; + serial7 = &main_uart3; + spi1 = &main_spi0; + spi2 = &mcu_spi0; + }; + + chosen { + stdout-path = &main_uart0; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_gpio_keys_pins>; + + user-button { + label = "USER_BUTTON"; + linux,code = <BTN_0>; + gpios = <&mcu_gpio0 5 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_gpio_leds_pins>; + + led-0 { + label = "led0"; + gpios = <&mcu_gpio0 8 GPIO_ACTIVE_HIGH>; + }; + led-1 { + label = "led1"; + gpios = <&mcu_gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_fan_pins>; + fan-supply = <®_pwm_fan>; + #cooling-cells = <2>; + /* typical 25 kHz -> 40.000 nsec */ + pwms = <&epwm5 0 40000 PWM_POLARITY_INVERTED>; + cooling-levels = <0 32 64 128 196 240>; + pulses-per-revolution = <2>; + interrupt-parent = <&main_gpio1>; + interrupts = <49 IRQ_TYPE_EDGE_FALLING>; + status = "disabled"; + }; + + wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_wifi_pwrseq_pins>; + reset-gpios = <&main_gpio0 23 GPIO_ACTIVE_LOW>; + }; + + reg_pwm_fan: regulator-pwm-fan { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm_fan_reg_pins>; + regulator-name = "FAN_PWR"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&main_gpio1 48 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd: regulator-sd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_reg_pins>; + regulator-name = "V_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&main_gpio1 43 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_pins>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + status = "disabled"; +}; + +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&cpsw_mdio_pins>; + status = "okay"; + + cpsw3g_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + reset-gpios = <&main_gpio0 44 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + ti,rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; +}; + +&epwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&epwm5_pins>; + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio0_digital_pins>, + <&main_gpio0_hog_pins>; + gpio-line-names = + "", "", "", "", /* 0-3 */ + "", "", "", "", /* 4-7 */ + "", "", "", "", /* 8-11 */ + "", "", "", "", /* 12-15 */ + "", "", "", "", /* 16-19 */ + "", "", "", "", /* 20-23 */ + "", "", "EN_DIG_OUT_1", "STATUS_OUT_1", /* 24-27 */ + "EN_DIG_OUT_2", "STATUS_OUT_2", "EN_SIG_OUT_3", "", /* 28-31 */ + "", "", "STATUS_OUT_3", "EN_DIG_OUT_4", /* 32-35 */ + "", "", "STATUS_OUT_4", "DIG_IN_1", /* 36-39 */ + "DIG_IN_2", "DIG_IN_3", "DIG_IN_4"; /* 40- */ +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_hog_pins>; + gpio-line-names = + "", "", "", "", /* 0-3 */ + "", "", "", "", /* 4-7 */ + "", "", "", "", /* 8-11 */ + "", "", "", "", /* 12-15 */ + "", "", "", "", /* 16-19 */ + "", "", "", "", /* 20-23 */ + "", "", "", "", /* 24-27 */ + "", "", "", "", /* 28-31 */ + "", "", "", "", /* 32-35 */ + "", "", "", "", /* 36-39 */ + "", "", "", "", /* 40-43 */ + "", "", "", "", /* 44-47 */ + "", "", "", "", /* 48-51 */ + "", "", "", "ADC_SYNC", /* 52-55 */ + "", "", "ADC_RST#", "ADC_DATA_RDY", /* 56-59 */ + "", "", "", "", /* 60-63 */ + "", "", "", "ADC_INT#", /* 64-67 */ + "BG95_PWRKEY", "BG95_RESET"; /* 68- */ + + line50-hog { + /* See also usb0 */ + gpio-hog; + gpios = <50 0>; + line-name = "USB0_VBUS_OC#"; + input; + }; + + line54-hog { + gpio-hog; + gpios = <54 0>; + line-name = "PRG0_MDIO_SWITCH"; + output-low; + }; + + line70-hog { + gpio-hog; + gpios = <70 0>; + line-name = "PHY_INT#"; + input; + }; +}; + +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan0_pins>; + status = "okay"; +}; + +&main_mcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan1_pins>; + status = "okay"; +}; + +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi0_pins>; + ti,pindir-d0-out-d1-in; + status = "okay"; + + /* adc@0: NXP NAFE13388 */ +}; + +/* UART/USB adapter port 1 */ +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins>; + status = "okay"; +}; + +/* + * IOT Module - GNSS UART + * + * Note: We expect usage of a SYSFW that does not reserve UART1 for debug traces + */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins>; + status = "okay"; +}; + +/* RS485 port */ +&main_uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart2_pins>; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + status = "okay"; +}; + +/* Bluetooth module */ +&main_uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart3_pins>; + /* + * Left disabled for now, until a way to deal with drivers and firmware + * for the combined WLAN/BT module has been figured out + */ +}; + +/* IOT module - Main UART */ +&main_uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart4_pins>; + status = "okay"; +}; + +/* IOT module - DBG UART */ +&main_uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart5_pins>; + status = "okay"; +}; + +&main0_thermal { + trips { + main0_active0: trip-active0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + + main0_active1: trip-active1 { + temperature = <48000>; + hysteresis = <3000>; + type = "active"; + }; + + main0_active2: trip-active2 { + temperature = <60000>; + hysteresis = <10000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&main0_active0>; + cooling-device = <&fan0 1 1>; + }; + + map2 { + trip = <&main0_active1>; + cooling-device = <&fan0 2 2>; + }; + + map3 { + trip = <&main0_active2>; + cooling-device = <&fan0 3 3>; + }; + }; +}; + +&main1_thermal { + trips { + main1_active0: trip-active0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + + main1_active1: trip-active1 { + temperature = <48000>; + hysteresis = <3000>; + type = "active"; + }; + + main1_active2: trip-active2 { + temperature = <60000>; + hysteresis = <10000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&main1_active0>; + cooling-device = <&fan0 1 1>; + }; + + map2 { + trip = <&main1_active1>; + cooling-device = <&fan0 2 2>; + }; + + map3 { + trip = <&main1_active2>; + cooling-device = <&fan0 3 3>; + }; + }; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_gpio0_pins>; +}; + +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins>; + /* Left disabled: not functional without external pullup */ +}; + +&mcu_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_spi0_pins>; + ti,pindir-d0-out-d1-in; + status = "okay"; +}; + +/* UART/USB adapter port 2 */ +&mcu_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins>; + status = "okay"; +}; + +/* Pin header */ +&mcu_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart1_pins>; + status = "okay"; +}; + +&serdes_ln_ctrl { + idle-states = <AM64_SERDES0_LANE0_USB>; +}; + +&serdes0 { + serdes0_usb_link: phy@0 { + reg = <0>; + #phy-cells = <0>; + resets = <&serdes_wiz0 1>; + cdns,num-lanes = <1>; + cdns,phy-type = <PHY_TYPE_USB3>; + }; +}; + +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins>; + bus-width = <4>; + cd-gpios = <&main_gpio1 77 GPIO_ACTIVE_LOW>; + disable-wp; + no-mmc; + ti,driver-strength-ohm = <50>; + ti,fails-without-test-cd; + /* Enabled by overlay */ + status = "disabled"; +}; + +&tscadc0 { + status = "okay"; + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + +&usb0 { + /* + * The CDNS USB driver currently doesn't support overcurrent GPIOs, + * so there is no overcurrent detection. The OC pin is configured + * as a GPIO hog instead. + */ + pinctrl-names = "default"; + pinctrl-0 = <&main_usb0_pins>; + dr_mode = "otg"; + maximum-speed = "super-speed"; + phys = <&serdes0_usb_link>; + phy-names = "cdns3,usb3-phy"; +}; + +&usbss0 { + ti,vbus-divider; +}; + +&main_pmx0 { + cpsw_pins: cpsw-pins { + pinctrl-single,pins = < + /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ + AM64X_IOPAD(0x01cc, PIN_INPUT, 4) + /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ + AM64X_IOPAD(0x01d4, PIN_INPUT, 4) + /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ + AM64X_IOPAD(0x01d8, PIN_INPUT, 4) + /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ + AM64X_IOPAD(0x01f4, PIN_INPUT, 4) + /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ + AM64X_IOPAD(0x0188, PIN_INPUT, 4) + /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ + AM64X_IOPAD(0x0184, PIN_INPUT, 4) + /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ + AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) + /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ + AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) + /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ + AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) + /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ + AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) + /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ + AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) + /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ + AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) + >; + }; + + cpsw_mdio_pins: cpsw-mdio-pins { + pinctrl-single,pins = < + /* (R21) GPMC0_CSn3.GPIO0_44 - RESET_RGMII1# */ + AM64X_IOPAD(0x00b4, PIN_OUTPUT, 7) + + /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ + AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) + /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ + AM64X_IOPAD(0x01f8, PIN_INPUT, 4) + >; + }; + + epwm5_pins: epwm5-pins { + pinctrl-single,pins = < + /* (W19) GPMC0_WAIT0.EHRPWM5_B */ + AM64X_IOPAD(0x0098, PIN_OUTPUT, 3) + >; + }; + + /* Digital IOs */ + main_gpio0_digital_pins: main-gpio0-digital-pins { + pinctrl-single,pins = < + /* (W20) GPMC0_AD11.GPIO0_26 - EN_DIG_OUT_1 */ + AM64X_IOPAD(0x0068, PIN_OUTPUT, 7) + /* (W21) GPMC0_AD12.GPIO0_27 - STATUS_OUT_1 */ + AM64X_IOPAD(0x006c, PIN_INPUT, 7) + /* (V18) GPMC0_AD13.GPIO0_28 - EN_DIG_OUT_2 */ + AM64X_IOPAD(0x0070, PIN_OUTPUT, 7) + /* (Y21) GPMC0_AD14.GPIO0_29 - STATUS_OUT_2 */ + AM64X_IOPAD(0x0074, PIN_INPUT, 7) + /* (Y20) GPMC0_AD15.GPIO0_30 - EN_DIG_OUT_3 */ + AM64X_IOPAD(0x0078, PIN_OUTPUT, 7) + /* (T21) GPMC0_WEn.GPIO0_34 - STATUS_OUT_3 */ + AM64X_IOPAD(0x008c, PIN_INPUT, 7) + /* (P17) GPMC0_BE0n_CLE.GPIO0_35 - EN_DIG_OUT_4 */ + AM64X_IOPAD(0x0090, PIN_OUTPUT, 7) + /* (Y18) GPMC0_WAIT1.GPIO0_38 - STATUS_OUT_4 */ + AM64X_IOPAD(0x009c, PIN_INPUT, 7) + /* (N16) GPMC0_WPn.GPIO0_39 - DIG_IN_1 */ + AM64X_IOPAD(0x00a0, PIN_INPUT, 7) + /* (N17) GPMC0_DIR.GPIO0_40 - DIG_IN_2 */ + AM64X_IOPAD(0x00a4, PIN_INPUT, 7) + /* (R19) GPMC0_CSn0.GPIO0_41 - DIG_IN_3 */ + AM64X_IOPAD(0x00a8, PIN_INPUT, 7) + /* (R20) GPMC0_CSn1.GPIO0_42 - DIG_IN_4 */ + AM64X_IOPAD(0x00ac, PIN_INPUT, 7) + >; + }; + + main_gpio0_hog_pins: main-gpio0-hog-pins { + pinctrl-single,pins = < + /* (P19) GPMC0_CSn2.GPIO0_43 - MMC1_CTRL */ + AM64X_IOPAD(0x00b0, PIN_OUTPUT, 7) + >; + }; + + main_gpio1_hog_pins: main-gpio1-hog-pins { + pinctrl-single,pins = < + /* (B15) SPI1_D0.GPIO1_50 - USB0_VBUS_OC# */ + AM64X_IOPAD(0x0228, PIN_INPUT, 7) + /* (B16) UART0_CTSn.GPIO1_54 - PRG0_MDIO_SWITCH */ + AM64X_IOPAD(0x0238, PIN_OUTPUT, 7) + /* (C19) EXTINTn.GPIO1_70 - PHY_INT# */ + AM64X_IOPAD(0x0278, PIN_INPUT, 7) + >; + }; + + main_mcan0_pins: main-mcan0-pins { + pinctrl-single,pins = < + /* (B17) MCAN0_RX */ + AM64X_IOPAD(0x0254, PIN_INPUT, 0) + /* (A17) MCAN0_TX */ + AM64X_IOPAD(0x0250, PIN_OUTPUT, 0) + >; + }; + + main_mcan1_pins: main-mcan1-pins { + pinctrl-single,pins = < + /* (D17) MCAN1_RX */ + AM64X_IOPAD(0x025c, PIN_INPUT, 0) + /* (C17) MCAN1_TX */ + AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) + >; + }; + + main_mmc1_pins: main-mmc1-pins { + pinctrl-single,pins = < + /* (J19) MMC1_CMD */ + AM64X_IOPAD(0x0294, PIN_INPUT, 0) + /* (L20) MMC1_CLK */ + AM64X_IOPAD(0x028c, PIN_INPUT, 0) + /* (K21) MMC1_DAT0 */ + AM64X_IOPAD(0x0288, PIN_INPUT, 0) + /* (L21) MMC1_DAT1 */ + AM64X_IOPAD(0x0284, PIN_INPUT, 0) + /* (K19) MMC1_DAT2 */ + AM64X_IOPAD(0x0280, PIN_INPUT, 0) + /* (K18) MMC1_DAT3 */ + AM64X_IOPAD(0x027c, PIN_INPUT, 0) + /* (D19) MMC1_SDCD.GPIO1_77 */ + AM64X_IOPAD(0x0298, PIN_INPUT, 7) + /* (#N/A) MMC1_CLKLB */ + AM64X_IOPAD(0x0290, PIN_INPUT, 0) + >; + }; + + main_mmc1_reg_pins: main-mmc1-reg-pins { + pinctrl-single,pins = < + /* (C13) SPI0_CS1.GPIO1_43 - MMC1_SD_EN */ + AM64X_IOPAD(0x020c, PIN_OUTPUT, 7) + >; + }; + + main_mmc1_wifi_pwrseq_pins: main-mmc1-wifi-pwrseq-pins { + pinctrl-single,pins = < + /* (V19) GPMC0_AD8.GPIO0_23 - WIFI-BT_EN */ + AM64X_IOPAD(0x005c, PIN_OUTPUT, 7) + >; + }; + + main_spi0_pins: main-spi0-pins { + pinctrl-single,pins = < + /* (D13) SPI0_CLK */ + AM64X_IOPAD(0x0210, PIN_OUTPUT, 0) + /* (D12) SPI0_CS0 */ + AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) + /* (A13) SPI0_D0 */ + AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) + /* (A14) SPI0_D1 */ + AM64X_IOPAD(0x0218, PIN_INPUT, 0) + >; + }; + + main_spi0_adc_pins: main-spi0-adc-pins { + pinctrl-single,pins = < + /* (A16) UART0_RTSn.GPIO1_55 - ADC_SYNC */ + AM64X_IOPAD(0x023c, PIN_INPUT, 7) + /* (D16) UART1_CTSn.GPIO1_58 - ADC_RST# */ + AM64X_IOPAD(0x0248, PIN_OUTPUT, 7) + /* (E16) UART1_RTSn.GPIO1_59 - ADC_DATA_RDY */ + AM64X_IOPAD(0x024c, PIN_INPUT, 7) + /* (B19) I2C1_SDA.GPIO1_67 - ADC_INT# */ + AM64X_IOPAD(0x026c, PIN_INPUT, 7) + >; + }; + + main_uart0_pins: main-uart0-pins { + pinctrl-single,pins = < + /* (D15) UART0_RXD */ + AM64X_IOPAD(0x0230, PIN_INPUT, 0) + /* (C16) UART0_TXD */ + AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) + >; + }; + + main_uart1_pins: main-uart1-pins { + pinctrl-single,pins = < + /* (E15) UART1_RXD */ + AM64X_IOPAD(0x0240, PIN_INPUT, 0) + /* (E14) UART1_TXD */ + AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) + >; + }; + + main_uart2_pins: main-uart2-pins { + pinctrl-single,pins = < + /* (T18) GPMC0_AD2.UART2_RTSn */ + AM64X_IOPAD(0x0044, PIN_OUTPUT, 2) + /* (T20) GPMC0_AD0.UART2_RXD */ + AM64X_IOPAD(0x003c, PIN_INPUT, 2) + /* (U21) GPMC0_AD1.UART2_TXD */ + AM64X_IOPAD(0x0040, PIN_OUTPUT, 2) + >; + }; + + main_uart3_pins: main-uart3-pins { + pinctrl-single,pins = < + /* (T17) GPMC0_AD9.UART3_CTSn */ + AM64X_IOPAD(0x0060, PIN_INPUT, 2) + /* (U19) GPMC0_AD5.UART3_RTSn */ + AM64X_IOPAD(0x0050, PIN_OUTPUT, 2) + /* (U20) GPMC0_AD3.UART3_RXD */ + AM64X_IOPAD(0x0048, PIN_INPUT, 2) + /* (U18) GPMC0_AD4.UART3_TXD */ + AM64X_IOPAD(0x004c, PIN_OUTPUT, 2) + >; + }; + + main_uart4_pins: main-uart4-pins { + pinctrl-single,pins = < + /* (R16) GPMC0_AD10.UART4_CTSn */ + AM64X_IOPAD(0x0064, PIN_INPUT, 2) + /* (R17) GPMC0_CLK.UART4_RTSn */ + AM64X_IOPAD(0x007c, PIN_OUTPUT, 2) + /* (V20) GPMC0_AD6.UART4_RXD */ + AM64X_IOPAD(0x0054, PIN_INPUT, 2) + /* (V21) GPMC0_AD7.UART4_TXD */ + AM64X_IOPAD(0x0058, PIN_OUTPUT, 2) + + /* Control GPIOs for IOT Module connected to UART4 */ + /* (D18) ECAP0_IN_APWM_OUT.GPIO1_68 - BG95_PWRKEY */ + AM64X_IOPAD(0x0270, PIN_OUTPUT, 7) + /* (A19) EXT_REFCLK1.GPIO1_69 - BG95_RESET */ + AM64X_IOPAD(0x0274, PIN_OUTPUT, 7) + >; + }; + + main_uart5_pins: main-uart5-pins { + pinctrl-single,pins = < + /* (P16) GPMC0_ADVn_ALE.UART5_RXD */ + AM64X_IOPAD(0x0084, PIN_INPUT, 2) + /* (R18) GPMC0_OEn_REn.UART5_TXD */ + AM64X_IOPAD(0x0088, PIN_OUTPUT, 2) + >; + }; + + main_usb0_pins: main-usb0-pins { + pinctrl-single,pins = < + /* (E19) USB0_DRVVBUS */ + AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) + >; + }; + + pru_icssg1_mdio_pins: pru-icssg1-mdio-pins { + pinctrl-single,pins = < + /* (A15) SPI1_D1.GPIO1_51 - RESET_PRG1_RGMII1# */ + AM64X_IOPAD(0x022c, PIN_OUTPUT, 7) + /* (B14) SPI1_CS0.GPIO1_47 - RESET_PRG1_RGMII2# */ + AM64X_IOPAD(0x021c, PIN_OUTPUT, 7) + + /* (Y6) PRG1_MDIO0_MDC */ + AM64X_IOPAD(0x015c, PIN_OUTPUT, 0) + /* (AA6) PRG1_MDIO0_MDIO */ + AM64X_IOPAD(0x0158, PIN_INPUT, 0) + >; + }; + + pru_icssg1_rgmii1_pins: pru-icssg1-rgmii1-pins { + pinctrl-single,pins = < + /* (Y7) PRG1_PRU0_GPO0.PRG1_RGMII1_RD0 */ + AM64X_IOPAD(0x00b8, PIN_INPUT, 2) + /* (U8) PRG1_PRU0_GPO1.PRG1_RGMII1_RD1 */ + AM64X_IOPAD(0x00bc, PIN_INPUT, 2) + /* (W8) PRG1_PRU0_GPO2.PRG1_RGMII1_RD2 */ + AM64X_IOPAD(0x00c0, PIN_INPUT, 2) + /* (V8) PRG1_PRU0_GPO3.PRG1_RGMII1_RD3 */ + AM64X_IOPAD(0x00c4, PIN_INPUT, 2) + /* (AA7) PRG1_PRU0_GPO6.PRG1_RGMII1_RXC */ + AM64X_IOPAD(0x00d0, PIN_INPUT, 2) + /* (Y8) PRG1_PRU0_GPO4.PRG1_RGMII1_RX_CTL */ + AM64X_IOPAD(0x00c8, PIN_INPUT, 2) + /* (AA8) PRG1_PRU0_GPO11.PRG1_RGMII1_TD0 */ + AM64X_IOPAD(0x00e4, PIN_OUTPUT, 2) + /* (U9) PRG1_PRU0_GPO12.PRG1_RGMII1_TD1 */ + AM64X_IOPAD(0x00e8, PIN_OUTPUT, 2) + /* (W9) PRG1_PRU0_GPO13.PRG1_RGMII1_TD2 */ + AM64X_IOPAD(0x00ec, PIN_OUTPUT, 2) + /* (AA9) PRG1_PRU0_GPO14.PRG1_RGMII1_TD3 */ + AM64X_IOPAD(0x00f0, PIN_OUTPUT, 2) + /* (V9) PRG1_PRU0_GPO16.PRG1_RGMII1_TXC */ + AM64X_IOPAD(0x00f8, PIN_OUTPUT, 2) + /* (Y9) PRG1_PRU0_GPO15.PRG1_RGMII1_TX_CTL */ + AM64X_IOPAD(0x00f4, PIN_OUTPUT, 2) + >; + }; + + pru_icssg1_rgmii2_pins: pru-icssg1-rgmii2-pins { + pinctrl-single,pins = < + /* (W11) PRG1_PRU1_GPO0.PRG1_RGMII2_RD0 */ + AM64X_IOPAD(0x0108, PIN_INPUT, 2) + /* (V11) PRG1_PRU1_GPO1.PRG1_RGMII2_RD1 */ + AM64X_IOPAD(0x010c, PIN_INPUT, 2) + /* (AA12) PRG1_PRU1_GPO2.PRG1_RGMII2_RD2 */ + AM64X_IOPAD(0x0110, PIN_INPUT, 2) + /* (Y12) PRG1_PRU1_GPO3.PRG1_RGMII2_RD3 */ + AM64X_IOPAD(0x0114, PIN_INPUT, 2) + /* (U11) PRG1_PRU1_GPO6.PRG1_RGMII2_RXC */ + AM64X_IOPAD(0x0120, PIN_INPUT, 2) + /* (W12) PRG1_PRU1_GPO4.PRG1_RGMII2_RX_CTL */ + AM64X_IOPAD(0x0118, PIN_INPUT, 2) + /* (AA10) PRG1_PRU1_GPO11.PRG1_RGMII2_TD0 */ + AM64X_IOPAD(0x0134, PIN_OUTPUT, 2) + /* (V10) PRG1_PRU1_GPO12.PRG1_RGMII2_TD1 */ + AM64X_IOPAD(0x0138, PIN_OUTPUT, 2) + /* (U10) PRG1_PRU1_GPO13.PRG1_RGMII2_TD2 */ + AM64X_IOPAD(0x013c, PIN_OUTPUT, 2) + /* (AA11) PRG1_PRU1_GPO14.PRG1_RGMII2_TD3 */ + AM64X_IOPAD(0x0140, PIN_OUTPUT, 2) + /* (Y10) PRG1_PRU1_GPO16.PRG1_RGMII2_TXC */ + AM64X_IOPAD(0x0148, PIN_OUTPUT, 2) + /* (Y11) PRG1_PRU1_GPO15.PRG1_RGMII2_TX_CTL */ + AM64X_IOPAD(0x0144, PIN_OUTPUT, 2) + >; + }; + + pwm_fan_pins: pwm-fan-pins { + pinctrl-single,pins = < + /* (T19) GPMC0_BE1n.EHRPWM5_A */ + AM64X_IOPAD(0x0094, PIN_OUTPUT, 3) + /* (C14) SPI1_CLK.GPIO1_49 - FAN_RPM */ + AM64X_IOPAD(0x0224, PIN_INPUT, 7) + >; + }; + + pwm_fan_reg_pins: pwm-fan-reg-pins { + pinctrl-single,pins = < + /* (D14) SPI1_CS1.GPIO1_48 - FAN_PWR */ + AM64X_IOPAD(0x0220, PIN_OUTPUT, 7) + >; + }; +}; + +&mcu_pmx0 { + mcu_gpio_keys_pins: mcu-gpio-keys-pins { + pinctrl-single,pins = < + /* (A7) MCU_SPI1_CS0.MCU_GPIO0_5 */ + AM64X_MCU_IOPAD(0x0014, PIN_INPUT, 7) + >; + }; + + mcu_gpio_leds_pins: mcu-gpio-leds-pins { + pinctrl-single,pins = < + /* (C7) MCU_SPI1_D0.MCU_GPIO0_8 */ + AM64X_MCU_IOPAD(0x0020, PIN_OUTPUT, 7) + /* (C8) MCU_SPI1_D1.MCU_GPIO0_9 */ + AM64X_MCU_IOPAD(0x0024, PIN_OUTPUT, 7) + >; + }; + + mcu_gpio0_pins: mcu-gpio0-pins { + pinctrl-single,pins = < + /* (E8) MCU_UART0_RTSn.MCU_GPIO0_0 */ + AM64X_MCU_IOPAD(0x0034, PIN_INPUT, 7) + /* (D8) MCU_UART0_CTSn.MCU_GPIO0_1 */ + AM64X_MCU_IOPAD(0x0030, PIN_INPUT, 7) + /* (B7) MCU_SPI1_CS1.MCU_GPIO0_6 */ + AM64X_MCU_IOPAD(0x0018, PIN_INPUT, 7) + /* (D7) MCU_SPI1_CLK.MCU_GPIO0_7 */ + AM64X_MCU_IOPAD(0x001c, PIN_INPUT, 7) + /* (A11) MCU_I2C1_SCL.MCU_GPIO0_20 */ + AM64X_MCU_IOPAD(0x0050, PIN_INPUT, 7) + /* (B10) MCU_I2C1_SDA.MCU_GPIO0_21 */ + AM64X_MCU_IOPAD(0x0054, PIN_INPUT, 7) + >; + }; + + mcu_i2c0_pins: mcu-i2c0-pins { + pinctrl-single,pins = < + /* (E9) MCU_I2C0_SCL */ + AM64X_MCU_IOPAD(0x0048, PIN_INPUT, 0) + /* (A10) MCU_I2C0_SDA */ + AM64X_MCU_IOPAD(0x004c, PIN_INPUT, 0) + >; + }; + + mcu_spi0_pins: mcu-spi0-pins { + pinctrl-single,pins = < + /* (E6) MCU_SPI0_CLK */ + AM64X_MCU_IOPAD(0x0008, PIN_OUTPUT, 0) + /* (D6) MCU_SPI0_CS0 */ + AM64X_MCU_IOPAD(0x0000, PIN_OUTPUT, 0) + /* (C6) MCU_SPI0_CS1 */ + AM64X_MCU_IOPAD(0x0004, PIN_OUTPUT, 0) + /* (E7) MCU_SPI0_D0 */ + AM64X_MCU_IOPAD(0x000c, PIN_OUTPUT, 0) + /* (B6) MCU_SPI0_D1 */ + AM64X_MCU_IOPAD(0x0010, PIN_INPUT, 0) + >; + }; + + mcu_uart0_pins: mcu-uart0-pins { + pinctrl-single,pins = < + /* (A9) MCU_UART0_RXD */ + AM64X_MCU_IOPAD(0x0028, PIN_INPUT, 0) + /* (A8) MCU_UART0_TXD */ + AM64X_MCU_IOPAD(0x002c, PIN_OUTPUT, 0) + >; + }; + + mcu_uart1_pins: mcu-uart1-pins { + pinctrl-single,pins = < + /* (B8) MCU_UART1_CTSn */ + AM64X_MCU_IOPAD(0x0040, PIN_INPUT, 0) + /* (B9) MCU_UART1_RTSn */ + AM64X_MCU_IOPAD(0x0044, PIN_OUTPUT, 0) + /* (C9) MCU_UART1_RXD */ + AM64X_MCU_IOPAD(0x0038, PIN_INPUT, 0) + /* (D9) MCU_UART1_TXD */ + AM64X_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) + >; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi new file mode 100644 index 000000000000..6229849b5d96 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, D-82229 Seefeld, Germany. + */ + +#include "k3-am642.dtsi" + +/ { + aliases { + i2c0 = &main_i2c0; + mmc0 = &sdhci0; + spi0 = &ospi0; + }; + + memory@80000000 { + device_type = "memory"; + /* 1G RAM - default variant */ + reg = <0x00000000 0x80000000 0x00000000 0x40000000>; + + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; + alignment = <0x1000>; + no-map; + }; + + main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; + }; +}; + +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c0_pins>; + clock-frequency = <400000>; + status = "okay"; + + tmp1075: temperature-sensor@4a { + compatible = "ti,tmp1075"; + reg = <0x4a>; + }; + + eeprom0: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + read-only; + }; + + pcf85063: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <12500>; + }; + + eeprom1: eeprom@54 { + compatible = "st,24c64", "atmel,24c64"; + reg = <0x54>; + pagesize = <32>; + }; +}; + +&mailbox0_cluster2 { + status = "okay"; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster4 { + status = "okay"; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 2>; + ti,mbox-tx = <3 0 2>; + }; +}; + +&mailbox0_cluster6 { + status = "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; +}; + +&main_r5fss0_core0 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + memory-region = <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; +}; + +&main_r5fss0_core1 { + mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + memory-region = <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; +}; + +&main_r5fss1_core0 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + memory-region = <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; +}; + +&main_r5fss1_core1 { + mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + memory-region = <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; +}; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <84000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Filled by bootloader */ + }; + }; +}; + +&sdhci0 { + non-removable; + disable-wp; + no-sdio; + no-sd; + ti,driver-strength-ohm = <50>; +}; + +&main_pmx0 { + main_i2c0_pins: main-i2c0-pins { + pinctrl-single,pins = < + /* (A18) I2C0_SCL */ + AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) + /* (B18) I2C0_SDA */ + AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) + >; + }; + + ospi0_pins: ospi0-pins { + pinctrl-single,pins = < + /* (N20) OSPI0_CLK */ + AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) + /* (L19) OSPI0_CSn0 */ + AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) + /* (M19) OSPI0_D0 */ + AM64X_IOPAD(0x000c, PIN_INPUT, 0) + /* (M18) OSPI0_D1 */ + AM64X_IOPAD(0x0010, PIN_INPUT, 0) + /* (M20) OSPI0_D2 */ + AM64X_IOPAD(0x0014, PIN_INPUT, 0) + /* (M21) OSPI0_D3 */ + AM64X_IOPAD(0x0018, PIN_INPUT, 0) + /* (P21) OSPI0_D4 */ + AM64X_IOPAD(0x001c, PIN_INPUT, 0) + /* (P20) OSPI0_D5 */ + AM64X_IOPAD(0x0020, PIN_INPUT, 0) + /* (N18) OSPI0_D6 */ + AM64X_IOPAD(0x0024, PIN_INPUT, 0) + /* (M17) OSPI0_D7 */ + AM64X_IOPAD(0x0028, PIN_INPUT, 0) + /* (N19) OSPI0_DQS */ + AM64X_IOPAD(0x0008, PIN_INPUT, 0) + >; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi index e73458ca6900..e9419c4fe605 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi @@ -10,7 +10,7 @@ */ &main_pmx0 { - cp2102n_reset_pin_default: cp2102n-reset-pin-default { + cp2102n_reset_pin_default: cp2102n-reset-default-pins { pinctrl-single,pins = < /* (AF12) GPIO1_24, used as cp2102 reset */ AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi index e26bd988e522..ba1c14a54acf 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -582,17 +582,15 @@ ti,pindir-d0-out-d1-in; }; -&tscadc0 { - status = "disabled"; -}; - &tscadc1 { + status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5>; }; }; &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 3f8ff2589842..bc460033a37a 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -502,8 +502,8 @@ reg = <0x000041e0 0x14>; }; - ehrpwm_tbclk: clock@4140 { - compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + ehrpwm_tbclk: clock-controller@4140 { + compatible = "ti,am654-ehrpwm-tbclk"; reg = <0x4140 0x18>; #clock-cells = <1>; }; @@ -773,11 +773,12 @@ ringacc: ringacc@3c000000 { compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x3c000000 0x0 0x400000>, - <0x0 0x38000000 0x0 0x400000>, - <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>, + <0x0 0x31080000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <818>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; @@ -787,9 +788,9 @@ main_udmap: dma-controller@31150000 { compatible = "ti,am654-navss-main-udmap"; - reg = <0x0 0x31150000 0x0 0x100>, - <0x0 0x34000000 0x0 0x100000>, - <0x0 0x35000000 0x0 0x100000>; + reg = <0x0 0x31150000 0x0 0x100>, + <0x0 0x34000000 0x0 0x100000>, + <0x0 0x35000000 0x0 0x100000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&inta_main_udmass>; #dma-cells = <1>; @@ -1006,13 +1007,13 @@ dss: dss@4a00000 { compatible = "ti,am65x-dss"; - reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ - <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ - <0x0 0x04a06000 0x0 0x1000>, /* vid */ - <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ - <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ - <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ - <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ + reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ + <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ + <0x0 0x04a06000 0x0 0x1000>, /* vid */ + <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ + <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ + <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ + <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ reg-names = "common", "vidl1", "vid", "ovr1", "ovr2", "vp1", "vp2"; diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi index b7a4b5a89aaf..1e536dc41f61 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -112,6 +112,7 @@ dmas = <&mcu_udmap 0x7100>, <&mcu_udmap 0x7101 >; dma-names = "fifo0", "fifo1"; + status = "disabled"; adc { #io-channel-cells = <1>; @@ -130,6 +131,7 @@ dmas = <&mcu_udmap 0x7102>, <&mcu_udmap 0x7103>; dma-names = "fifo0", "fifo1"; + status = "disabled"; adc { #io-channel-cells = <1>; @@ -194,11 +196,13 @@ mcu_ringacc: ringacc@2b800000 { compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", + "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; @@ -208,9 +212,9 @@ mcu_udmap: dma-controller@285c0000 { compatible = "ti,am654-navss-mcu-udmap"; - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x2aa00000 0x0 0x40000>; + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x2aa00000 0x0 0x40000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&inta_main_udmass>; #dma-cells = <1>; @@ -274,7 +278,7 @@ status = "disabled"; }; - fss: fss@47000000 { + fss: bus@47000000 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -295,6 +299,7 @@ power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; ospi1: spi@47050000 { @@ -309,6 +314,7 @@ power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts index 973a89b04a22..f5c26e9fba98 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -192,7 +192,7 @@ >; }; - wkup_pca554_default: wkup-pca554-default { + wkup_pca554_default: wkup-pca554-default-pins { pinctrl-single,pins = < AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ >; @@ -478,12 +478,14 @@ }; &tscadc0 { + status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; &tscadc1 { + status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; @@ -530,6 +532,7 @@ }; &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts index cbe44634914f..774eb14ac907 100644 --- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts +++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts @@ -33,7 +33,7 @@ >; }; - main_bkey_pcie_reset: main-bkey-pcie-reset { + main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */ >; @@ -46,7 +46,7 @@ >; }; - main_m2_pcie_mux_control: main-m2-pcie-mux-control { + main_m2_pcie_mux_control: main-m2-pcie-mux-control-default-pins { pinctrl-single,pins = < AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */ AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */ diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index d5889ba3fa46..5df5946687b3 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -11,7 +11,8 @@ #include <dt-bindings/net/ti-dp83867.h> #include <dt-bindings/phy/phy-cadence.h> #include <dt-bindings/phy/phy.h> -#include <dt-bindings/mux/ti-serdes.h> + +#include "k3-serdes.h" / { compatible = "ti,am68-sk", "ti,j721s2"; @@ -121,6 +122,52 @@ #phy-cells = <0>; max-bitrate = <5000000>; }; + + connector-hdmi { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_pins_default>; + ddc-i2c-bus = <&mcu_i2c1>; + /* HDMI_HPD */ + hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + bridge-dvi { + compatible = "ti,tfp410"; + /* HDMI_PDn */ + powerdown-gpios = <&exp2 0 GPIO_ACTIVE_LOW>; + ti,deskew = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi_out0>; + pclk-sample = <1>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; }; &main_pmx0 { @@ -201,6 +248,45 @@ J721S2_IOPAD(0x08c, PIN_INPUT, 7) /* (T25) MCASP0_AXR7.GPIO0_35 */ >; }; + + dss_vout0_pins_default: dss-vout0-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x074, PIN_OUTPUT, 2) /* (R28) MCAN2_TX.VOUT0_DATA0 */ + J721S2_IOPAD(0x070, PIN_OUTPUT, 2) /* (R27) MCAN1_RX.VOUT0_DATA1 */ + J721S2_IOPAD(0x04c, PIN_OUTPUT, 2) /* (V27) MCASP1_AXR1.VOUT0_DATA10 */ + J721S2_IOPAD(0x048, PIN_OUTPUT, 2) /* (AB27) MCASP0_AXR2.VOUT0_DATA11 */ + J721S2_IOPAD(0x044, PIN_OUTPUT, 2) /* (Y26) MCASP0_AXR1.VOUT0_DATA12 */ + J721S2_IOPAD(0x040, PIN_OUTPUT, 2) /* (AC28) MCASP0_AXR0.VOUT0_DATA13 */ + J721S2_IOPAD(0x03c, PIN_OUTPUT, 2) /* (U27) MCASP0_AFSX.VOUT0_DATA14 */ + J721S2_IOPAD(0x038, PIN_OUTPUT, 2) /* (AB28) MCASP0_ACLKX.VOUT0_DATA15 */ + J721S2_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AD28) EXT_REFCLK1.VOUT0_DATA16 */ + J721S2_IOPAD(0x030, PIN_OUTPUT, 2) /* (T26) GPIO0_12.VOUT0_DATA17 */ + J721S2_IOPAD(0x02c, PIN_OUTPUT, 2) /* (V23) GPIO0_11.VOUT0_DATA18 */ + J721S2_IOPAD(0x028, PIN_OUTPUT, 2) /* (AB24) MCAN16_RX.VOUT0_DATA19 */ + J721S2_IOPAD(0x07c, PIN_OUTPUT, 2) /* (T27) MCASP0_AXR3.VOUT0_DATA2 */ + J721S2_IOPAD(0x024, PIN_OUTPUT, 2) /* (Y28) MCAN16_TX.VOUT0_DATA20 */ + J721S2_IOPAD(0x020, PIN_OUTPUT, 2) /* (AA23) MCAN15_RX.VOUT0_DATA21 */ + J721S2_IOPAD(0x01c, PIN_OUTPUT, 2) /* (Y24) MCAN15_TX.VOUT0_DATA22 */ + J721S2_IOPAD(0x018, PIN_OUTPUT, 2) /* (W23) MCAN14_RX.VOUT0_DATA23 */ + J721S2_IOPAD(0x068, PIN_OUTPUT, 2) /* (U28) MCAN0_RX.VOUT0_DATA3 */ + J721S2_IOPAD(0x064, PIN_OUTPUT, 2) /* (W28) MCAN0_TX.VOUT0_DATA4 */ + J721S2_IOPAD(0x060, PIN_OUTPUT, 2) /* (AC27) MCASP2_AXR1.VOUT0_DATA5 */ + J721S2_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AA26) MCASP2_AXR0.VOUT0_DATA6 */ + J721S2_IOPAD(0x058, PIN_OUTPUT, 2) /* (AA27) MCASP2_AFSX.VOUT0_DATA7 */ + J721S2_IOPAD(0x054, PIN_OUTPUT, 2) /* (Y27) MCASP2_ACLKX.VOUT0_DATA8 */ + J721S2_IOPAD(0x050, PIN_OUTPUT, 2) /* (W27) MCASP1_AXR2.VOUT0_DATA9 */ + J721S2_IOPAD(0x084, PIN_OUTPUT, 2) /* (AA28) MCASP0_AXR5.VOUT0_DE */ + J721S2_IOPAD(0x080, PIN_OUTPUT, 2) /* (U26) MCASP0_AXR4.VOUT0_HSYNC */ + J721S2_IOPAD(0x078, PIN_OUTPUT, 2) /* (Y25) MCAN2_RX.VOUT0_PCLK */ + J721S2_IOPAD(0x088, PIN_OUTPUT, 2) /* (AD27) MCASP0_AXR6.VOUT0_VP0_VSYNC */ + >; + }; + + hdmi_hpd_pins_default: hdmi-hpd-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x000, PIN_INPUT, 7) /* (AG24) EXTINTN.GPIO0_0 */ + >; + }; }; &wkup_pmx2 { @@ -272,7 +358,7 @@ >; }; - mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-pins0-default { + mcu_rpi_header_gpio0_pins0_default: mcu-rpi-header-gpio0-default-pins-0 { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (G25) WKUP_GPIO0_66 */ J721S2_WKUP_IOPAD(0x05C, PIN_INPUT, 7) /* (E24) MCU_SPI1_D0.WKUP_GPIO0_1 */ @@ -288,7 +374,7 @@ }; &wkup_pmx3 { - mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-pins1-default { + mcu_rpi_header_gpio0_pins1_default: mcu-rpi-header-gpio0-default-pins-1 { pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_GPIO0_49 */ >; @@ -296,31 +382,17 @@ }; &main_gpio0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&rpi_header_gpio0_pins_default>; }; -&main_gpio2 { - status = "disabled"; -}; - -&main_gpio4 { - status = "disabled"; -}; - -&main_gpio6 { - status = "disabled"; -}; - &wkup_gpio0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_rpi_header_gpio0_pins0_default>, <&mcu_rpi_header_gpio0_pins1_default>; }; -&wkup_gpio1 { - status = "disabled"; -}; - &wkup_uart0 { status = "reserved"; pinctrl-names = "default"; @@ -372,13 +444,26 @@ clock-frequency = <400000>; }; -&main_sdhci0 { - /* Unused */ - status = "disabled"; +&mcu_i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c1_pins_default>; + /* i2c1 is used for DVI DDC, so we need to use 100kHz */ + clock-frequency = <100000>; + + exp2: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "HDMI_PDn","HDMI_LS_OE", + "DP0_3V3_EN","eDP_ENABLE"; + }; }; &main_sdhci1 { /* SD card */ + status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>; pinctrl-names = "default"; disable-wp; @@ -432,3 +517,39 @@ pinctrl-0 = <&main_mcan7_pins_default>; phys = <&transceiver4>; }; + +&dss { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dss_vout0_pins_default>; + /* + * These clock assignments are chosen to enable the following outputs: + * + * VP0 - DisplayPort SST + * VP1 - DPI0 + * VP2 - DSI + * VP3 - DPI1 + */ + assigned-clocks = <&k3_clks 158 2>, + <&k3_clks 158 5>, + <&k3_clks 158 14>, + <&k3_clks 158 18>; + assigned-clock-parents = <&k3_clks 158 3>, + <&k3_clks 158 7>, + <&k3_clks 158 16>, + <&k3_clks 158 22>; +}; + +&dss_ports { + #address-cells = <1>; + #size-cells = <0>; + + /* HDMI */ + port@1 { + reg = <1>; + + dpi_out0: endpoint { + remote-endpoint = <&tfp410_in>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index d282c2c633c1..06993709111e 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -110,7 +110,9 @@ }; &main_pmx0 { + bootph-all; main_uart8_pins_default: main-uart8-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ @@ -125,6 +127,7 @@ }; main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -164,7 +167,9 @@ }; &wkup_pmx2 { + bootph-all; wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-all; pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ @@ -174,6 +179,7 @@ }; wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-all; pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ @@ -181,6 +187,7 @@ }; mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ @@ -249,6 +256,7 @@ }; &wkup_i2c0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; @@ -268,6 +276,7 @@ }; &mcu_uart0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; @@ -281,6 +290,7 @@ }; &main_uart8 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart8_pins_default>; @@ -307,6 +317,7 @@ }; &main_sdhci0 { + bootph-all; /* eMMC */ status = "okay"; non-removable; @@ -315,6 +326,7 @@ }; &main_sdhci1 { + bootph-all; /* SD card */ status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts index 3cf288128c3f..cee2b4b0eb87 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -8,9 +8,10 @@ #include "k3-j7200-som-p0.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/net/ti-dp83867.h> -#include <dt-bindings/mux/ti-serdes.h> #include <dt-bindings/phy/phy.h> +#include "k3-serdes.h" + / { compatible = "ti,j7200-evm", "ti,j7200"; model = "Texas Instruments J7200 EVM"; @@ -239,27 +240,16 @@ pinctrl-0 = <&main_uart3_pins_default>; }; -&main_gpio2 { - status = "disabled"; -}; - -&main_gpio4 { - status = "disabled"; -}; - -&main_gpio6 { - status = "disabled"; +&main_gpio0 { + status = "okay"; }; &wkup_gpio0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_gpio_pins_default>; }; -&wkup_gpio1 { - status = "disabled"; -}; - &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; @@ -325,6 +315,7 @@ &main_sdhci0 { /* eMMC */ + status = "okay"; non-removable; ti,driver-strength-ohm = <50>; disable-wp; @@ -332,6 +323,7 @@ &main_sdhci1 { /* SD card */ + status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>; pinctrl-names = "default"; vmmc-supply = <&vdd_mmc1>; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso index 34a0747cbe69..32d905235ed7 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso +++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso @@ -10,9 +10,9 @@ /plugin/; #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/mux/ti-serdes.h> #include "k3-pinctrl.h" +#include "k3-serdes.h" &{/} { aliases { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi index ac62bbc1660d..cdb1d6b2a982 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi @@ -264,11 +264,12 @@ main_ringacc: ringacc@3c000000 { compatible = "ti,am654-navss-ringacc"; - reg = <0x00 0x3c000000 0x00 0x400000>, - <0x00 0x38000000 0x00 0x400000>, - <0x00 0x31120000 0x00 0x100>, - <0x00 0x33000000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + reg = <0x00 0x3c000000 0x00 0x400000>, + <0x00 0x38000000 0x00 0x400000>, + <0x00 0x31120000 0x00 0x100>, + <0x00 0x33000000 0x00 0x40000>, + <0x00 0x31080000 0x00 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <1024>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; @@ -278,9 +279,9 @@ main_udmap: dma-controller@31150000 { compatible = "ti,j721e-navss-main-udmap"; - reg = <0x00 0x31150000 0x00 0x100>, - <0x00 0x34000000 0x00 0x100000>, - <0x00 0x35000000 0x00 0x100000>; + reg = <0x00 0x31150000 0x00 0x100>, + <0x00 0x34000000 0x00 0x100000>, + <0x00 0x35000000 0x00 0x100000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; @@ -654,6 +655,7 @@ mmc-hs200-1_8v; mmc-hs400-1_8v; dma-coherent; + status = "disabled"; }; main_sdhci1: mmc@4fb0000 { @@ -677,6 +679,7 @@ ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; + status = "disabled"; }; serdes_wiz0: wiz@5060000 { @@ -830,6 +833,7 @@ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio2: gpio@610000 { @@ -847,6 +851,7 @@ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 107 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio4: gpio@620000 { @@ -864,6 +869,7 @@ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 109 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio6: gpio@630000 { @@ -881,6 +887,7 @@ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 111 0>; clock-names = "gpio"; + status = "disabled"; }; main_spi0: spi@2100000 { diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi index c5e4c41effd1..6ffaf85fa63f 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -297,6 +297,7 @@ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 113 0>; clock-names = "gpio"; + status = "disabled"; }; wkup_gpio1: gpio@42100000 { @@ -313,6 +314,7 @@ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; clock-names = "gpio"; + status = "disabled"; }; mcu_navss: bus@28380000 { @@ -326,11 +328,13 @@ mcu_ringacc: ringacc@2b800000 { compatible = "ti,am654-navss-ringacc"; - reg = <0x00 0x2b800000 0x00 0x400000>, - <0x00 0x2b000000 0x00 0x400000>, - <0x00 0x28590000 0x00 0x100>, - <0x00 0x2a500000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + reg = <0x00 0x2b800000 0x00 0x400000>, + <0x00 0x2b000000 0x00 0x400000>, + <0x00 0x28590000 0x00 0x100>, + <0x00 0x2a500000 0x00 0x40000>, + <0x00 0x28440000 0x00 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", + "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; @@ -340,9 +344,9 @@ mcu_udmap: dma-controller@285c0000 { compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x00 0x285c0000 0x00 0x100>, - <0x00 0x2a800000 0x00 0x40000>, - <0x00 0x2aa00000 0x00 0x40000>; + reg = <0x00 0x285c0000 0x00 0x100>, + <0x00 0x2a800000 0x00 0x40000>, + <0x00 0x2aa00000 0x00 0x40000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; @@ -544,6 +548,7 @@ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi index b37f4f88ece4..5a300d4c8ba0 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi @@ -267,6 +267,7 @@ }; &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index 66aac145e753..2f954729f353 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -563,6 +563,7 @@ &main_sdhci0 { /* eMMC */ + status = "okay"; non-removable; ti,driver-strength-ohm = <50>; disable-wp; @@ -570,6 +571,7 @@ &main_sdhci1 { /* SD Card */ + status = "okay"; vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv_alt>; pinctrl-names = "default"; @@ -578,21 +580,6 @@ disable-wp; }; -&main_sdhci2 { - /* Unused */ - status = "disabled"; -}; - -&ospi0 { - /* Unused */ - status = "disabled"; -}; - -&ospi1 { - /* Unused */ - status = "disabled"; -}; - &main_i2c0 { status = "okay"; pinctrl-names = "default"; @@ -660,52 +647,23 @@ }; }; -&main_gpio2 { - /* Unused */ - status = "disabled"; -}; - -&main_gpio3 { - /* Unused */ - status = "disabled"; -}; - -&main_gpio4 { - /* Unused */ - status = "disabled"; -}; - -&main_gpio5 { - /* Unused */ - status = "disabled"; -}; - -&main_gpio6 { - /* Unused */ - status = "disabled"; -}; - -&main_gpio7 { - /* Unused */ - status = "disabled"; -}; - &wkup_gpio0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_adc0_pins_default>, <&mcu_adc1_pins_default>, <&mikro_bus_pins_default>; }; -&wkup_gpio1 { - /* Unused */ - status = "disabled"; -}; - &main_gpio0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&csi1_gpio_pins_default>, <&csi0_gpio_pins_default>; }; +&main_gpio1 { + status = "okay"; +}; + &usb_serdes_mux { idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ }; @@ -789,6 +747,7 @@ }; &tscadc0 { + status = "okay"; /* BBB Header: P9.39, P9.40, P9.37, P9.38, P9.33, P9.36, P9.35 */ adc { ti,adc-channels = <0 1 2 3 4 5 6>; @@ -796,6 +755,7 @@ }; &tscadc1 { + status = "okay"; /* MCU mikroBUS Header J10.1 - MCU_ADC1_AIN0 */ adc { ti,adc-channels = <0>; @@ -1012,18 +972,21 @@ }; &c66_0 { + status = "okay"; mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { + status = "okay"; mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { + status = "okay"; mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index c1cbbae76182..fe5207ac7d85 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -469,41 +469,23 @@ pinctrl-0 = <&main_uart4_pins_default>; }; -&main_gpio2 { - status = "disabled"; -}; - -&main_gpio3 { - status = "disabled"; -}; - -&main_gpio4 { - status = "disabled"; -}; - -&main_gpio5 { - status = "disabled"; -}; - -&main_gpio6 { - status = "disabled"; -}; - -&main_gpio7 { - status = "disabled"; -}; - &wkup_gpio0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_gpio_pins_default>; }; -&wkup_gpio1 { - status = "disabled"; +&main_gpio0 { + status = "okay"; +}; + +&main_gpio1 { + status = "okay"; }; &main_sdhci0 { /* eMMC */ + status = "okay"; non-removable; ti,driver-strength-ohm = <50>; disable-wp; @@ -511,6 +493,7 @@ &main_sdhci1 { /* SD/MMC */ + status = "okay"; vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv_alt>; pinctrl-names = "default"; @@ -519,11 +502,6 @@ disable-wp; }; -&main_sdhci2 { - /* Unused */ - status = "disabled"; -}; - &usb_serdes_mux { idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ }; @@ -641,12 +619,14 @@ }; &tscadc0 { + status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; &tscadc1 { + status = "okay"; adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso new file mode 100644 index 000000000000..6a7d37575da1 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with + * J721E board. + * + * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/net/ti-dp83867.h> + +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; + ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; + ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; + ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; + }; +}; + +&cpsw0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_default_pins + &rgmii2_default_pins + &rgmii3_default_pins + &rgmii4_default_pins>; +}; + +&cpsw0_port1 { + status = "okay"; + phy-handle = <&cpsw9g_phy12>; + phy-mode = "rgmii-rxid"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 1>; +}; + +&cpsw0_port2 { + status = "okay"; + phy-handle = <&cpsw9g_phy15>; + phy-mode = "rgmii-rxid"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 2>; +}; + +&cpsw0_port3 { + status = "okay"; + phy-handle = <&cpsw9g_phy0>; + phy-mode = "rgmii-rxid"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 3>; +}; + +&cpsw0_port4 { + status = "okay"; + phy-handle = <&cpsw9g_phy3>; + phy-mode = "rgmii-rxid"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 4>; +}; + +&cpsw9g_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_default_pins>; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + + cpsw9g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + }; + cpsw9g_phy3: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + }; + cpsw9g_phy12: ethernet-phy@12 { + reg = <12>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + }; + cpsw9g_phy15: ethernet-phy@15 { + reg = <15>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + }; +}; + +&exp1 { + p15-hog { + /* P15 - EXP_MUX2 */ + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_MUX2"; + }; + + p16-hog { + /* P16 - EXP_MUX3 */ + gpio-hog; + gpios = <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_MUX3"; + }; +}; + +&main_pmx0 { + mdio0_default_pins: mdio0-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */ + J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */ + >; + }; + + rgmii1_default_pins: rgmii1-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x4, PIN_INPUT, 4) /* (AC23) PRG1_PRU0_GPO0.RGMII1_RD0 */ + J721E_IOPAD(0x8, PIN_INPUT, 4) /* (AG22) PRG1_PRU0_GPO1.RGMII1_RD1 */ + J721E_IOPAD(0xc, PIN_INPUT, 4) /* (AF22) PRG1_PRU0_GPO2.RGMII1_RD2 */ + J721E_IOPAD(0x10, PIN_INPUT, 4) /* (AJ23) PRG1_PRU0_GPO3.RGMII1_RD3 */ + J721E_IOPAD(0x1c, PIN_INPUT, 4) /* (AD22) PRG1_PRU0_GPO6.RGMII1_RXC */ + J721E_IOPAD(0x14, PIN_INPUT, 4) /* (AH23) PRG1_PRU0_GPO4.RGMII1_RX_CTL */ + J721E_IOPAD(0x30, PIN_OUTPUT, 4) /* (AF24) PRG1_PRU0_GPO11.RGMII1_TD0 */ + J721E_IOPAD(0x34, PIN_OUTPUT, 4) /* (AJ24) PRG1_PRU0_GPO12.RGMII1_TD1 */ + J721E_IOPAD(0x38, PIN_OUTPUT, 4) /* (AG24) PRG1_PRU0_GPO13.RGMII1_TD2 */ + J721E_IOPAD(0x3c, PIN_OUTPUT, 4) /* (AD24) PRG1_PRU0_GPO14.RGMII1_TD3 */ + J721E_IOPAD(0x44, PIN_OUTPUT, 4) /* (AE24) PRG1_PRU0_GPO16.RGMII1_TXC */ + J721E_IOPAD(0x40, PIN_OUTPUT, 4) /* (AC24) PRG1_PRU0_GPO15.RGMII1_TX_CTL */ + >; + }; + + rgmii2_default_pins: rgmii2-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x58, PIN_INPUT, 4) /* (AE22) PRG1_PRU1_GPO0.RGMII2_RD0 */ + J721E_IOPAD(0x5c, PIN_INPUT, 4) /* (AG23) PRG1_PRU1_GPO1.RGMII2_RD1 */ + J721E_IOPAD(0x60, PIN_INPUT, 4) /* (AF23) PRG1_PRU1_GPO2.RGMII2_RD2 */ + J721E_IOPAD(0x64, PIN_INPUT, 4) /* (AD23) PRG1_PRU1_GPO3.RGMII2_RD3 */ + J721E_IOPAD(0x70, PIN_INPUT, 4) /* (AE23) PRG1_PRU1_GPO6.RGMII2_RXC */ + J721E_IOPAD(0x68, PIN_INPUT, 4) /* (AH24) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ + J721E_IOPAD(0x84, PIN_OUTPUT, 4) /* (AJ25) PRG1_PRU1_GPO11.RGMII2_TD0 */ + J721E_IOPAD(0x88, PIN_OUTPUT, 4) /* (AH25) PRG1_PRU1_GPO12.RGMII2_TD1 */ + J721E_IOPAD(0x8c, PIN_OUTPUT, 4) /* (AG25) PRG1_PRU1_GPO13.RGMII2_TD2 */ + J721E_IOPAD(0x90, PIN_OUTPUT, 4) /* (AH26) PRG1_PRU1_GPO14.RGMII2_TD3 */ + J721E_IOPAD(0x98, PIN_OUTPUT, 4) /* (AJ26) PRG1_PRU1_GPO16.RGMII2_TXC */ + J721E_IOPAD(0x94, PIN_OUTPUT, 4) /* (AJ27) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ + >; + }; + + rgmii3_default_pins: rgmii3-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0xb0, PIN_INPUT, 4) /* (AF28) PRG0_PRU0_GPO0.RGMII3_RD0 */ + J721E_IOPAD(0xb4, PIN_INPUT, 4) /* (AE28) PRG0_PRU0_GPO1.RGMII3_RD1 */ + J721E_IOPAD(0xb8, PIN_INPUT, 4) /* (AE27) PRG0_PRU0_GPO2.RGMII3_RD2 */ + J721E_IOPAD(0xbc, PIN_INPUT, 4) /* (AD26) PRG0_PRU0_GPO3.RGMII3_RD3 */ + J721E_IOPAD(0xc8, PIN_INPUT, 4) /* (AE26) PRG0_PRU0_GPO6.RGMII3_RXC */ + J721E_IOPAD(0xc0, PIN_INPUT, 4) /* (AD25) PRG0_PRU0_GPO4.RGMII3_RX_CTL */ + J721E_IOPAD(0xdc, PIN_OUTPUT, 4) /* (AJ28) PRG0_PRU0_GPO11.RGMII3_TD0 */ + J721E_IOPAD(0xe0, PIN_OUTPUT, 4) /* (AH27) PRG0_PRU0_GPO12.RGMII3_TD1 */ + J721E_IOPAD(0xe4, PIN_OUTPUT, 4) /* (AH29) PRG0_PRU0_GPO13.RGMII3_TD2 */ + J721E_IOPAD(0xe8, PIN_OUTPUT, 4) /* (AG28) PRG0_PRU0_GPO14.RGMII3_TD3 */ + J721E_IOPAD(0xf0, PIN_OUTPUT, 4) /* (AH28) PRG0_PRU0_GPO16.RGMII3_TXC */ + J721E_IOPAD(0xec, PIN_OUTPUT, 4) /* (AG27) PRG0_PRU0_GPO15.RGMII3_TX_CTL */ + >; + }; + + rgmii4_default_pins: rgmii4-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x100, PIN_INPUT, 4) /* (AE29) PRG0_PRU1_GPO0.RGMII4_RD0 */ + J721E_IOPAD(0x104, PIN_INPUT, 4) /* (AD28) PRG0_PRU1_GPO1.RGMII4_RD1 */ + J721E_IOPAD(0x108, PIN_INPUT, 4) /* (AD27) PRG0_PRU1_GPO2.RGMII4_RD2 */ + J721E_IOPAD(0x10c, PIN_INPUT, 4) /* (AC25) PRG0_PRU1_GPO3.RGMII4_RD3 */ + J721E_IOPAD(0x118, PIN_INPUT, 4) /* (AC26) PRG0_PRU1_GPO6.RGMII4_RXC */ + J721E_IOPAD(0x110, PIN_INPUT, 4) /* (AD29) PRG0_PRU1_GPO4.RGMII4_RX_CTL */ + J721E_IOPAD(0x12c, PIN_OUTPUT, 4) /* (AG26) PRG0_PRU1_GPO11.RGMII4_TD0 */ + J721E_IOPAD(0x130, PIN_OUTPUT, 4) /* (AF27) PRG0_PRU1_GPO12.RGMII4_TD1 */ + J721E_IOPAD(0x134, PIN_OUTPUT, 4) /* (AF26) PRG0_PRU1_GPO13.RGMII4_TD2 */ + J721E_IOPAD(0x138, PIN_OUTPUT, 4) /* (AE25) PRG0_PRU1_GPO14.RGMII4_TD3 */ + J721E_IOPAD(0x140, PIN_OUTPUT, 4) /* (AG29) PRG0_PRU1_GPO16.RGMII4_TXC */ + J721E_IOPAD(0x13c, PIN_OUTPUT, 4) /* (AF29) PRG0_PRU1_GPO15.RGMII4_TX_CTL */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso index 6f0adf591b98..d4c51ffc3d6b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso @@ -10,11 +10,11 @@ /plugin/; #include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/mux/ti-serdes.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/phy/phy-cadence.h> #include "k3-pinctrl.h" +#include "k3-serdes.h" &{/} { aliases { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 2ded1ee1a854..f6c7e1614521 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -7,7 +7,8 @@ #include <dt-bindings/phy/phy.h> #include <dt-bindings/phy/phy-ti.h> #include <dt-bindings/mux/mux.h> -#include <dt-bindings/mux/ti-serdes.h> + +#include "k3-serdes.h" / { cmn_refclk: clock-cmnrefclk { @@ -76,7 +77,7 @@ }; ehrpwm_tbclk: clock-controller@4140 { - compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + compatible = "ti,am654-ehrpwm-tbclk"; reg = <0x4140 0x18>; #clock-cells = <1>; }; @@ -364,11 +365,12 @@ main_ringacc: ringacc@3c000000 { compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x3c000000 0x0 0x400000>, - <0x0 0x38000000 0x0 0x400000>, - <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + reg = <0x0 0x3c000000 0x0 0x400000>, + <0x0 0x38000000 0x0 0x400000>, + <0x0 0x31120000 0x0 0x100>, + <0x0 0x33000000 0x0 0x40000>, + <0x0 0x31080000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <1024>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; @@ -378,9 +380,9 @@ main_udmap: dma-controller@31150000 { compatible = "ti,j721e-navss-main-udmap"; - reg = <0x0 0x31150000 0x0 0x100>, - <0x0 0x34000000 0x0 0x100000>, - <0x0 0x35000000 0x0 0x100000>; + reg = <0x0 0x31150000 0x0 0x100>, + <0x0 0x34000000 0x0 0x100000>, + <0x0 0x35000000 0x0 0x100000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; @@ -660,7 +662,7 @@ assigned-clock-parents = <&k3_clks 293 13>; }; - wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{ + wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div { clocks = <&wiz1_refclk_dig>; #clock-cells = <0>; }; @@ -1338,6 +1340,7 @@ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio1: gpio@601000 { @@ -1354,6 +1357,7 @@ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 106 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio2: gpio@610000 { @@ -1371,6 +1375,7 @@ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 107 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio3: gpio@611000 { @@ -1387,6 +1392,7 @@ power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 108 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio4: gpio@620000 { @@ -1404,6 +1410,7 @@ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 109 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio5: gpio@621000 { @@ -1420,6 +1427,7 @@ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 110 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio6: gpio@630000 { @@ -1437,6 +1445,7 @@ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 111 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio7: gpio@631000 { @@ -1453,6 +1462,7 @@ power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 112 0>; clock-names = "gpio"; + status = "disabled"; }; main_sdhci0: mmc@4f80000 { @@ -1477,6 +1487,7 @@ ti,itap-del-sel-ddr52 = <0x3>; ti,trm-icp = <0x8>; dma-coherent; + status = "disabled"; }; main_sdhci1: mmc@4fb0000 { @@ -1504,6 +1515,7 @@ ti,clkbuf-sel = <0x7>; dma-coherent; sdhci-caps-mask = <0x2 0x0>; + status = "disabled"; }; main_sdhci2: mmc@4f98000 { @@ -1531,6 +1543,7 @@ ti,clkbuf-sel = <0x7>; dma-coherent; sdhci-caps-mask = <0x2 0x0>; + status = "disabled"; }; usbss0: cdns-usb@4104000 { @@ -1761,11 +1774,11 @@ "vp1", "vp2", "vp3", "vp4", "wb"; - clocks = <&k3_clks 152 0>, - <&k3_clks 152 1>, - <&k3_clks 152 4>, - <&k3_clks 152 9>, - <&k3_clks 152 13>; + clocks = <&k3_clks 152 0>, + <&k3_clks 152 1>, + <&k3_clks 152 4>, + <&k3_clks 152 9>, + <&k3_clks 152 13>; clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; @@ -2108,6 +2121,7 @@ ti,sci-proc-ids = <0x03 0xff>; resets = <&k3_reset 142 1>; firmware-name = "j7-c66_0-fw"; + status = "disabled"; }; c66_1: dsp@4d81800000 { @@ -2121,6 +2135,7 @@ ti,sci-proc-ids = <0x04 0xff>; resets = <&k3_reset 143 1>; firmware-name = "j7-c66_1-fw"; + status = "disabled"; }; c71_0: dsp@64800000 { @@ -2133,6 +2148,7 @@ ti,sci-proc-ids = <0x30 0xff>; resets = <&k3_reset 15 1>; firmware-name = "j7-c71_0-fw"; + status = "disabled"; }; icssg0: icssg@b000000 { diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi index ea5b9e104491..05d6ef127ba7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -281,6 +281,7 @@ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 113 0>; clock-names = "gpio"; + status = "disabled"; }; wkup_gpio1: gpio@42100000 { @@ -297,6 +298,7 @@ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; clock-names = "gpio"; + status = "disabled"; }; mcu_i2c0: i2c@40b00000 { @@ -335,7 +337,7 @@ status = "disabled"; }; - fss: fss@47000000 { + fss: bus@47000000 { compatible = "simple-bus"; reg = <0x0 0x47000000 0x0 0x100>; #address-cells = <2>; @@ -378,6 +380,7 @@ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; ospi1: spi@47050000 { @@ -392,6 +395,7 @@ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; }; }; @@ -407,6 +411,7 @@ dmas = <&main_udmap 0x7400>, <&main_udmap 0x7401>; dma-names = "fifo0", "fifo1"; + status = "disabled"; adc { #io-channel-cells = <1>; @@ -426,6 +431,7 @@ dmas = <&main_udmap 0x7402>, <&main_udmap 0x7403>; dma-names = "fifo0", "fifo1"; + status = "disabled"; adc { #io-channel-cells = <1>; @@ -445,11 +451,12 @@ mcu_ringacc: ringacc@2b800000 { compatible = "ti,am654-navss-ringacc"; - reg = <0x0 0x2b800000 0x0 0x400000>, - <0x0 0x2b000000 0x0 0x400000>, - <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ ti,sci = <&dmsc>; @@ -459,9 +466,9 @@ mcu_udmap: dma-controller@285c0000 { compatible = "ti,j721e-navss-mcu-udmap"; - reg = <0x0 0x285c0000 0x0 0x100>, - <0x0 0x2a800000 0x0 0x40000>, - <0x0 0x2aa00000 0x0 0x40000>; + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x2aa00000 0x0 0x40000>; reg-names = "gcfg", "rchanrt", "tchanrt"; msi-parent = <&main_udmass_inta>; #dma-cells = <1>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 0ee4f38ec8f0..42fe8eee9ec8 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -582,13 +582,9 @@ pinctrl-0 = <&main_uart1_pins_default>; }; -&main_sdhci0 { - /* Unused */ - status = "disabled"; -}; - &main_sdhci1 { /* SD Card */ + status = "okay"; vmmc-supply = <&vdd_mmc1>; vqmmc-supply = <&vdd_sd_dv_alt>; pinctrl-names = "default"; @@ -597,12 +593,8 @@ disable-wp; }; -&main_sdhci2 { - /* Unused */ - status = "disabled"; -}; - &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; @@ -666,11 +658,6 @@ }; }; -&ospi1 { - /* Unused */ - status = "disabled"; -}; - &main_i2c0 { status = "okay"; pinctrl-names = "default"; @@ -744,41 +731,19 @@ }; &main_gpio0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&rpi_header_gpio0_pins_default>; }; &main_gpio1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&rpi_header_gpio1_pins_default>; }; -&main_gpio2 { - status = "disabled"; -}; - -&main_gpio3 { - status = "disabled"; -}; - -&main_gpio4 { - status = "disabled"; -}; - -&main_gpio5 { - status = "disabled"; -}; - -&main_gpio6 { - status = "disabled"; -}; - -&main_gpio7 { - status = "disabled"; -}; - -&wkup_gpio1 { - status = "disabled"; +&wkup_gpio0 { + status = "okay"; }; &usb_serdes_mux { @@ -863,16 +828,6 @@ phy-names = "cdns3,usb3-phy"; }; -&tscadc0 { - /* Unused */ - status = "disabled"; -}; - -&tscadc1 { - /* Unused */ - status = "disabled"; -}; - &mcu_cpsw { pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; @@ -1098,18 +1053,21 @@ }; &c66_0 { + status = "okay"; mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { + status = "okay"; mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { + status = "okay"; mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index 38ae13cc3aa3..7f0686c2ce37 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -201,20 +201,8 @@ }; }; -&wkup_i2c0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&wkup_i2c0_pins_default>; - clock-frequency = <400000>; - - eeprom@50 { - /* CAV24C256WE-GT3 */ - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - &ospi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; @@ -437,18 +425,21 @@ }; &c66_0 { + status = "okay"; mboxes = <&mailbox0_cluster3>, <&mbox_c66_0>; memory-region = <&c66_0_dma_memory_region>, <&c66_0_memory_region>; }; &c66_1 { + status = "okay"; mboxes = <&mailbox0_cluster3>, <&mbox_c66_1>; memory-region = <&c66_1_dma_memory_region>, <&c66_1_memory_region>; }; &c71_0 { + status = "okay"; mboxes = <&mailbox0_cluster4>, <&mbox_c71_0>; memory-region = <&c71_0_dma_memory_region>, <&c71_0_memory_region>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 04d4739d7245..c6b85bbf9a17 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -11,7 +11,8 @@ #include <dt-bindings/net/ti-dp83867.h> #include <dt-bindings/phy/phy-cadence.h> #include <dt-bindings/phy/phy.h> -#include <dt-bindings/mux/ti-serdes.h> + +#include "k3-serdes.h" / { compatible = "ti,j721s2-evm", "ti,j721s2"; @@ -29,6 +30,8 @@ can0 = &main_mcan16; can1 = &mcu_mcan0; can2 = &mcu_mcan1; + can3 = &main_mcan3; + can4 = &main_mcan5; }; evm_12v0: fixedregulator-evm12v0 { @@ -109,6 +112,22 @@ standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; }; + transceiver3: can-phy3 { + compatible = "ti,tcan1043"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>; + enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; + mux-states = <&mux0 1>; + }; + + transceiver4: can-phy4 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>; + mux-states = <&mux1 1>; + }; }; &main_pmx0 { @@ -152,6 +171,20 @@ J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ >; }; + + main_mcan3_pins_default: main-mcan3-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x080, PIN_INPUT, 0) /* (U26) MCASP0_AXR4.MCAN3_RX */ + J721S2_IOPAD(0x07c, PIN_OUTPUT, 0) /* (T27) MCASP0_AXR3.MCAN3_TX */ + >; + }; + + main_mcan5_pins_default: main-mcan5-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x03c, PIN_INPUT, 0) /* (U27) MCASP0_AFSX.MCAN5_RX */ + J721S2_IOPAD(0x038, PIN_OUTPUT, 0) /* (AB28) MCASP0_ACLKX.MCAN5_TX */ + >; + }; }; &wkup_pmx2 { @@ -249,36 +282,29 @@ J721S2_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ >; }; +}; +&wkup_pmx1 { mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { pinctrl-single,pins = < - J721S2_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ - J721S2_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ - J721S2_WKUP_IOPAD(0x060, PIN_OUTPUT, 0) /* (C21) MCU_OSPI1_CSn1 */ - J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ - J721S2_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ - J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ - J721S2_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ - J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ - J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ + J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ + J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ + J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ + J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ + J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ + J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ + J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B19) MCU_OSPI1_DQS */ + J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B20) MCU_OSPI1_LBCLKO */ >; }; }; -&main_gpio2 { - status = "disabled"; -}; - -&main_gpio4 { - status = "disabled"; -}; - -&main_gpio6 { - status = "disabled"; +&main_gpio0 { + status = "okay"; }; -&wkup_gpio1 { - status = "disabled"; +&wkup_gpio0 { + status = "okay"; }; &wkup_uart0 { @@ -332,6 +358,7 @@ &main_sdhci0 { /* eMMC */ + status = "okay"; non-removable; ti,driver-strength-ohm = <50>; disable-wp; @@ -339,6 +366,7 @@ &main_sdhci1 { /* SD card */ + status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>; pinctrl-names = "default"; disable-wp; @@ -407,7 +435,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - flash@0{ + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; @@ -460,3 +488,17 @@ ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; + +&main_mcan3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan3_pins_default>; + phys = <&transceiver3>; +}; + +&main_mcan5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan5_pins_default>; + phys = <&transceiver4>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso new file mode 100644 index 000000000000..b78feea31b54 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board. + * + * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/net/ti-dp83867.h> + +#include "k3-pinctrl.h" + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1"; + }; +}; + +&main_pmx0 { + main_cpsw_mdio_default_pins: main-cpsw-mdio-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */ + J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; + + rgmii1_default_pins: rgmii1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */ + J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */ + J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */ + J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */ + J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */ + J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */ + J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */ + J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */ + J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */ + J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */ + J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */ + >; + }; +}; + +&exp1 { + p15 { + /* P15 - EXP_MUX2 */ + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "EXP_MUX2"; + }; +}; + +&main_cpsw { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_default_pins>; +}; + +&main_cpsw_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw_mdio_default_pins>; + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,min-output-impedance; + }; +}; + +&main_cpsw_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&main_cpsw_phy0>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index ed79ab3a3271..084f8f5b6699 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -51,6 +51,12 @@ mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */ }; + phy_gmii_sel_cpsw: phy@34 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x34 0x4>; + #phy-cells = <1>; + }; + serdes_ln_ctrl: mux-controller@80 { compatible = "mmio-mux"; reg = <0x80 0x10>; @@ -58,6 +64,72 @@ mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */ <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */ }; + + ehrpwm_tbclk: clock-controller@140 { + compatible = "ti,am654-ehrpwm-tbclk"; + reg = <0x140 0x18>; + #clock-cells = <1>; + }; + }; + + main_ehrpwm0: pwm@3000000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3000000 0x00 0x100>; + power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm1: pwm@3010000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3010000 0x00 0x100>; + power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm2: pwm@3020000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3020000 0x00 0x100>; + power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm3: pwm@3030000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3030000 0x00 0x100>; + power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm4: pwm@3040000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3040000 0x00 0x100>; + power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm5: pwm@3050000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3050000 0x00 0x100>; + power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; }; gic500: interrupt-controller@1800000 { @@ -507,6 +579,7 @@ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 111 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio2: gpio@610000 { @@ -523,6 +596,7 @@ power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 112 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio4: gpio@620000 { @@ -539,6 +613,7 @@ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 113 0>; clock-names = "gpio"; + status = "disabled"; }; main_gpio6: gpio@630000 { @@ -555,6 +630,7 @@ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; clock-names = "gpio"; + status = "disabled"; }; main_i2c0: i2c@2000000 { @@ -665,6 +741,7 @@ mmc-hs200-1_8v; mmc-hs400-1_8v; dma-coherent; + status = "disabled"; }; main_sdhci1: mmc@4fb0000 { @@ -694,6 +771,7 @@ dma-coherent; /* Masking support for SDR104 capability */ sdhci-caps-mask = <0x00000003 0x00000000>; + status = "disabled"; }; main_navss: bus@30000000 { @@ -993,8 +1071,9 @@ reg = <0x0 0x3c000000 0x0 0x400000>, <0x0 0x38000000 0x0 0x400000>, <0x0 0x31120000 0x0 0x100>, - <0x0 0x33000000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x33000000 0x0 0x40000>, + <0x0 0x31080000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <1024>; ti,sci-rm-range-gp-rings = <0x1>; ti,sci = <&sms>; @@ -1039,6 +1118,69 @@ }; }; + main_cpsw: ethernet@c200000 { + compatible = "ti,j721e-cpsw-nuss"; + reg = <0x00 0xc200000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>; + #address-cells = <2>; + #size-cells = <2>; + dma-coherent; + clocks = <&k3_clks 28 28>; + clock-names = "fck"; + power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xc640>, + <&main_udmap 0xc641>, + <&main_udmap 0xc642>, + <&main_udmap 0xc643>, + <&main_udmap 0xc644>, + <&main_udmap 0xc645>, + <&main_udmap 0xc646>, + <&main_udmap 0xc647>, + <&main_udmap 0x4640>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + phys = <&phy_gmii_sel_cpsw 1>; + status = "disabled"; + }; + }; + + main_cpsw_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 28 28>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 28 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + usbss0: cdns-usb@4104000 { compatible = "ti,j721e-usb"; reg = <0x00 0x04104000 0x00 0x100>; @@ -1507,4 +1649,50 @@ clocks = <&k3_clks 346 1>; status = "disabled"; }; + + dss: dss@4a00000 { + compatible = "ti,j721e-dss"; + reg = <0x00 0x04a00000 0x00 0x10000>, /* common_m */ + <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/ + <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/ + <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/ + <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */ + <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */ + <0x00 0x04a50000 0x00 0x10000>, /* vid1 */ + <0x00 0x04a60000 0x00 0x10000>, /* vid2 */ + <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */ + <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */ + <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */ + <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */ + <0x00 0x04a80000 0x00 0x10000>, /* vp1 */ + <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */ + <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */ + <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */ + <0x00 0x04af0000 0x00 0x10000>; /* wb */ + reg-names = "common_m", "common_s0", + "common_s1", "common_s2", + "vidl1", "vidl2","vid1","vid2", + "ovr1", "ovr2", "ovr3", "ovr4", + "vp1", "vp2", "vp3", "vp4", + "wb"; + clocks = <&k3_clks 158 0>, + <&k3_clks 158 2>, + <&k3_clks 158 5>, + <&k3_clks 158 14>, + <&k3_clks 158 18>; + clock-names = "fck", "vp1", "vp2", "vp3", "vp4"; + power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "common_m", + "common_s0", + "common_s1", + "common_s2"; + status = "disabled"; + + dss_ports: ports { + }; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index e7dd947a1814..2ddad9318554 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -323,6 +323,7 @@ power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 115 0>; clock-names = "gpio"; + status = "disabled"; }; wkup_gpio1: gpio@42100000 { @@ -339,6 +340,7 @@ power-domains = <&k3_pds 116 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 116 0>; clock-names = "gpio"; + status = "disabled"; }; wkup_i2c0: i2c@42120000 { @@ -440,7 +442,7 @@ status = "disabled"; }; - mcu_navss: bus@28380000{ + mcu_navss: bus@28380000 { compatible = "simple-mfd"; #address-cells = <2>; #size-cells = <2>; @@ -455,8 +457,9 @@ reg = <0x0 0x2b800000 0x0 0x400000>, <0x0 0x2b000000 0x0 0x400000>, <0x0 0x28590000 0x0 0x100>, - <0x0 0x2a500000 0x0 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; ti,sci = <&sms>; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi index d57dd43da0ef..a4006f328027 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -31,6 +31,18 @@ }; }; + mux0: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 1 GPIO_ACTIVE_HIGH>; + }; + + mux1: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp_som 2 GPIO_ACTIVE_HIGH>; + }; + transceiver0: can-phy0 { /* standby pin has been grounded by default */ compatible = "ti,tcan1042"; @@ -44,9 +56,6 @@ pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (D19) MCU_OSPI0_CLK */ J721S2_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F15) MCU_OSPI0_CSn0 */ - J721S2_WKUP_IOPAD(0x030, PIN_OUTPUT, 0) /* (G17) MCU_OSPI0_CSn1 */ - J721S2_WKUP_IOPAD(0x038, PIN_OUTPUT, 0) /* (F14) MCU_OSPI0_CSn2 */ - J721S2_WKUP_IOPAD(0x03c, PIN_OUTPUT, 0) /* (F17) MCU_OSPI0_CSn3 */ J721S2_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (C19) MCU_OSPI0_D0 */ J721S2_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F16) MCU_OSPI0_D1 */ J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (G15) MCU_OSPI0_D2 */ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 430b8a2c5df5..5991c2e1d994 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -252,7 +252,9 @@ }; &main_pmx0 { + bootph-all; main_uart8_pins_default: main-uart8-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ @@ -269,6 +271,7 @@ }; main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ @@ -289,7 +292,9 @@ }; &wkup_pmx2 { + bootph-all; wkup_uart0_pins_default: wkup-uart0-default-pins { + bootph-all; pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ @@ -299,6 +304,7 @@ }; wkup_i2c0_pins_default: wkup-i2c0-default-pins { + bootph-all; pinctrl-single,pins = < J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ @@ -306,6 +312,7 @@ }; mcu_uart0_pins_default: mcu-uart0-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ @@ -340,33 +347,35 @@ mcu_adc0_pins_default: mcu-adc0-default-pins { pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ - J784S4_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ - J784S4_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ - J784S4_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ - J784S4_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ - J784S4_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ - J784S4_WKUP_IOPAD(0x14c, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ - J784S4_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ + J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ + J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ + J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ + J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ + J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ + J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ + J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ + J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ >; }; mcu_adc1_pins_default: mcu-adc1-default-pins { pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ - J784S4_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ - J784S4_WKUP_IOPAD(0x15c, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ - J784S4_WKUP_IOPAD(0x160, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ - J784S4_WKUP_IOPAD(0x164, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ - J784S4_WKUP_IOPAD(0x168, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ - J784S4_WKUP_IOPAD(0x16c, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ - J784S4_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ + J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ + J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ + J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ + J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ + J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ + J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ + J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ + J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ >; }; }; &wkup_pmx0 { + bootph-all; mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + bootph-all; pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ @@ -379,21 +388,31 @@ J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ - J784S4_WKUP_IOPAD(0x03c, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_CSn3.MCU_OSPI0_ECC_FAIL */ - J784S4_WKUP_IOPAD(0x038, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_CSn2.MCU_OSPI0_RESET_OUT0 */ + >; + }; +}; + +&wkup_pmx1 { + bootph-all; + mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { + bootph-all; + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ >; }; mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { + bootph-all; pinctrl-single,pins = < - J784S4_WKUP_IOPAD(0x040, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ - J784S4_WKUP_IOPAD(0x05c, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ - J784S4_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ - J784S4_WKUP_IOPAD(0x050, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ - J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ - J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ - J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ - J784S4_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ + J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ + J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ + J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ >; }; }; @@ -406,6 +425,7 @@ }; &wkup_i2c0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&wkup_i2c0_pins_default>; @@ -419,27 +439,36 @@ }; &mcu_uart0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart8 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart8_pins_default>; }; +&ufs_wrapper { + status = "okay"; +}; + &fss { + bootph-all; status = "okay"; }; &ospi0 { + bootph-all; status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; flash@0 { + bootph-all; compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <8>; @@ -487,6 +516,7 @@ }; partition@3fc0000 { + bootph-all; label = "ospi.phypattern"; reg = <0x3fc0000 0x40000>; }; @@ -495,11 +525,13 @@ }; &ospi1 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; - flash@0{ + flash@0 { + bootph-all; compatible = "jedec,spi-nor"; reg = <0x0>; spi-tx-bus-width = <1>; @@ -547,6 +579,7 @@ }; partition@3fc0000 { + bootph-all; label = "qspi.phypattern"; reg = <0x3fc0000 0x40000>; }; @@ -591,6 +624,7 @@ }; &main_sdhci0 { + bootph-all; /* eMMC */ status = "okay"; non-removable; @@ -599,6 +633,7 @@ }; &main_sdhci1 { + bootph-all; /* SD card */ status = "okay"; pinctrl-0 = <&main_mmc1_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 2ea0adae6832..efed2d683f63 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -60,7 +60,7 @@ #interrupt-cells = <1>; ti,sci = <&sms>; ti,sci-dev-id = <10>; - ti,interrupt-ranges = <8 360 56>; + ti,interrupt-ranges = <8 392 56>; }; main_pmx0: pinctrl@11c000 { @@ -618,7 +618,7 @@ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 140 1>, <&k3_clks 140 2>; - clock-names = "clk_ahb", "clk_xin"; + clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 140 2>; assigned-clock-parents = <&k3_clks 140 3>; bus-width = <8>; @@ -646,7 +646,7 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 141 3>, <&k3_clks 141 4>; - clock-names = "clk_ahb", "clk_xin"; + clock-names = "clk_ahb", "clk_xin"; assigned-clocks = <&k3_clks 141 4>; assigned-clock-parents = <&k3_clks 141 5>; bus-width = <4>; @@ -670,6 +670,7 @@ }; main_navss: bus@30000000 { + bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -705,6 +706,7 @@ }; secure_proxy_main: mailbox@32c00000 { + bootph-all; compatible = "ti,am654-secure-proxy"; #mbox-cells = <1>; reg-names = "target_data", "rt", "scfg"; @@ -966,8 +968,9 @@ reg = <0x00 0x3c000000 0x00 0x400000>, <0x00 0x38000000 0x00 0x400000>, <0x00 0x31120000 0x00 0x100>, - <0x00 0x33000000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x00 0x33000000 0x00 0x40000>, + <0x00 0x31080000 0x00 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <1024>; ti,sci-rm-range-gp-rings = <0x1>; ti,sci = <&sms>; @@ -1370,6 +1373,30 @@ status = "disabled"; }; + ufs_wrapper: ufs-wrapper@4e80000 { + compatible = "ti,j721e-ufs"; + reg = <0x00 0x4e80000 0x00 0x100>; + power-domains = <&k3_pds 387 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 387 3>; + assigned-clocks = <&k3_clks 387 3>; + assigned-clock-parents = <&k3_clks 387 6>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + ufs@4e84000 { + compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0"; + reg = <0x00 0x4e84000 0x00 0x10000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + freq-table-hz = <250000000 250000000>, <19200000 19200000>, + <19200000 19200000>; + clocks = <&k3_clks 387 1>, <&k3_clks 387 3>, <&k3_clks 387 3>; + clock-names = "core_clk", "phy_clk", "ref_clk"; + dma-coherent; + }; + }; + main_r5fss0: r5fss@5c00000 { compatible = "ti,j721s2-r5fss"; ti,cluster-mode = <1>; @@ -1500,6 +1527,7 @@ ti,sci-proc-ids = <0x30 0xff>; resets = <&k3_reset 30 1>; firmware-name = "j784s4-c71_0-fw"; + status = "disabled"; }; c71_1: dsp@65800000 { @@ -1512,6 +1540,7 @@ ti,sci-proc-ids = <0x31 0xff>; resets = <&k3_reset 33 1>; firmware-name = "j784s4-c71_1-fw"; + status = "disabled"; }; c71_2: dsp@66800000 { @@ -1524,6 +1553,7 @@ ti,sci-proc-ids = <0x32 0xff>; resets = <&k3_reset 37 1>; firmware-name = "j784s4-c71_2-fw"; + status = "disabled"; }; c71_3: dsp@67800000 { @@ -1536,5 +1566,6 @@ ti,sci-proc-ids = <0x33 0xff>; resets = <&k3_reset 40 1>; firmware-name = "j784s4-c71_3-fw"; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi index 657fb1d72512..4ab4018d3695 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi @@ -7,6 +7,7 @@ &cbass_mcu_wakeup { sms: system-controller@44083000 { + bootph-all; compatible = "ti,k2g-sci"; ti,host-id = <12>; @@ -19,22 +20,26 @@ reg = <0x00 0x44083000 0x00 0x1000>; k3_pds: power-controller { + bootph-all; compatible = "ti,sci-pm-domain"; #power-domain-cells = <2>; }; k3_clks: clock-controller { + bootph-all; compatible = "ti,k2g-sci-clk"; #clock-cells = <2>; }; k3_reset: reset-controller { + bootph-all; compatible = "ti,sci-reset"; #reset-cells = <2>; }; }; chipid@43000014 { + bootph-all; compatible = "ti,am654-chipid"; reg = <0x00 0x43000014 0x00 0x4>; }; @@ -107,7 +112,7 @@ #interrupt-cells = <1>; ti,sci = <&sms>; ti,sci-dev-id = <177>; - ti,interrupt-ranges = <16 928 16>; + ti,interrupt-ranges = <16 960 16>; }; /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ @@ -161,6 +166,7 @@ }; mcu_timer1: timer@40410000 { + bootph-all; compatible = "ti,am654-timer"; reg = <0x00 0x40410000 0x00 0x400>; interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; @@ -441,7 +447,8 @@ status = "disabled"; }; - mcu_navss: bus@28380000{ + mcu_navss: bus@28380000 { + bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -451,12 +458,14 @@ dma-ranges; mcu_ringacc: ringacc@2b800000 { + bootph-all; compatible = "ti,am654-navss-ringacc"; reg = <0x00 0x2b800000 0x00 0x400000>, <0x00 0x2b000000 0x00 0x400000>, <0x00 0x28590000 0x00 0x100>, - <0x00 0x2a500000 0x00 0x40000>; - reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; + <0x00 0x2a500000 0x00 0x40000>, + <0x00 0x28440000 0x00 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; ti,num-rings = <286>; ti,sci-rm-range-gp-rings = <0x1>; ti,sci = <&sms>; @@ -465,6 +474,7 @@ }; mcu_udmap: dma-controller@285c0000 { + bootph-all; compatible = "ti,j721e-navss-mcu-udmap"; reg = <0x00 0x285c0000 0x00 0x100>, <0x00 0x2a800000 0x00 0x40000>, diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi index 8b5974d92e33..4398c3a463e1 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi @@ -228,6 +228,7 @@ }; cbass_main: bus@100000 { + bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -263,6 +264,7 @@ <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; cbass_mcu_wakeup: bus@28380000 { + bootph-all; compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/ti/k3-pinctrl.h b/arch/arm64/boot/dts/ti/k3-pinctrl.h index c97548a3f42d..2a4e0e084d69 100644 --- a/arch/arm64/boot/dts/ti/k3-pinctrl.h +++ b/arch/arm64/boot/dts/ti/k3-pinctrl.h @@ -11,6 +11,7 @@ #define PULLUDEN_SHIFT (16) #define PULLTYPESEL_SHIFT (17) #define RXACTIVE_SHIFT (18) +#define DEBOUNCE_SHIFT (11) #define PULL_DISABLE (1 << PULLUDEN_SHIFT) #define PULL_ENABLE (0 << PULLUDEN_SHIFT) @@ -29,9 +30,20 @@ #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) #define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) +#define PIN_DEBOUNCE_DISABLE (0 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF1 (1 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF2 (2 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF3 (3 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF4 (4 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF5 (5 << DEBOUNCE_SHIFT) +#define PIN_DEBOUNCE_CONF6 (6 << DEBOUNCE_SHIFT) + #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62PX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define AM62PX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) + #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h new file mode 100644 index 000000000000..29167f85c1f6 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-serdes.h @@ -0,0 +1,204 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for SERDES MUX for TI SoCs + * + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef DTS_ARM64_TI_K3_SERDES_H +#define DTS_ARM64_TI_K3_SERDES_H + +/* J721E */ + +#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 +#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 +#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 +#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 + +#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 +#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 +#define J721E_SERDES0_LANE1_USB3_0 0x2 +#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 + +#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 +#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 +#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 +#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 + +#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 +#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 +#define J721E_SERDES1_LANE1_USB3_1 0x2 +#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 + +#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 +#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 +#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 +#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 + +#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 +#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 +#define J721E_SERDES2_LANE1_USB3_1 0x2 +#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 + +#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 +#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 +#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 +#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 + +#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 +#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 +#define J721E_SERDES3_LANE1_USB3_0 0x2 +#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 + +#define J721E_SERDES4_LANE0_EDP_LANE0 0x0 +#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 +#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 +#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 + +#define J721E_SERDES4_LANE1_EDP_LANE1 0x0 +#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 +#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 +#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 + +#define J721E_SERDES4_LANE2_EDP_LANE2 0x0 +#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 +#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 +#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 + +#define J721E_SERDES4_LANE3_EDP_LANE3 0x0 +#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 +#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 +#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 + +/* J7200 */ + +#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 +#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 +#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 +#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 +#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 +#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 +#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 +#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 + +#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 +#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 +#define J7200_SERDES0_LANE3_USB 0x2 +#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 + +/* AM64 */ + +#define AM64_SERDES0_LANE0_PCIE0 0x0 +#define AM64_SERDES0_LANE0_USB 0x1 + +/* J721S2 */ + +#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0 +#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1 +#define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2 +#define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3 + +#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0 +#define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1 +#define J721S2_SERDES0_LANE1_USB 0x2 +#define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3 + +#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 +#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 +#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 +#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 + +#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 +#define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1 +#define J721S2_SERDES0_LANE3_USB 0x2 +#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3 + +/* J784S4 */ + +#define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0 +#define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1 +#define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2 +#define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3 + +#define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0 +#define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1 +#define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2 +#define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3 + +#define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0 +#define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1 +#define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2 +#define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3 + +#define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0 +#define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1 +#define J784S4_SERDES0_LANE3_USB 0x2 +#define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3 + +#define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0 +#define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1 +#define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2 +#define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3 + +#define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0 +#define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1 +#define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2 +#define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3 + +#define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0 +#define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1 +#define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2 +#define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3 + +#define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0 +#define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1 +#define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2 +#define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3 + +#define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0 +#define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1 +#define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2 +#define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3 + +#define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0 +#define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1 +#define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2 +#define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3 + +#define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0 +#define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1 +#define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2 +#define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3 + +#define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0 +#define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1 +#define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2 +#define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3 + +#define J784S4_SERDES4_LANE0_EDP_LANE0 0x0 +#define J784S4_SERDES4_LANE0_QSGMII_LANE5 0x1 +#define J784S4_SERDES4_LANE0_IP3_UNUSED 0x2 +#define J784S4_SERDES4_LANE0_IP4_UNUSED 0x3 + +#define J784S4_SERDES4_LANE1_EDP_LANE1 0x0 +#define J784S4_SERDES4_LANE1_QSGMII_LANE6 0x1 +#define J784S4_SERDES4_LANE1_IP3_UNUSED 0x2 +#define J784S4_SERDES4_LANE1_IP4_UNUSED 0x3 + +#define J784S4_SERDES4_LANE2_EDP_LANE2 0x0 +#define J784S4_SERDES4_LANE2_QSGMII_LANE7 0x1 +#define J784S4_SERDES4_LANE2_IP3_UNUSED 0x2 +#define J784S4_SERDES4_LANE2_IP4_UNUSED 0x3 + +#define J784S4_SERDES4_LANE3_EDP_LANE3 0x0 +#define J784S4_SERDES4_LANE3_QSGMII_LANE8 0x1 +#define J784S4_SERDES4_LANE3_USB 0x2 +#define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3 + +#endif /* DTS_ARM64_TI_K3_SERDES_H */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index f04716841a0c..ccaca29200bb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -146,24 +146,28 @@ clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>, <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem1 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem2 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>, <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gem3 { clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>, <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>, <&zynqmp_clk GEM_TSU>; + assigned-clocks = <&zynqmp_clk GEM_TSU>; }; &gpio { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 603839c82599..ae1b9b2bdbee 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -27,8 +27,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* u14 - 0x40 - ina260 */ /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */ @@ -145,6 +145,7 @@ pinctrl-0 = <&pinctrl_gem3_default>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; mdio: mdio { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index a91d09e7da4b..b59e48be6465 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -22,8 +22,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* u14 - 0x40 - ina260 */ /* u43 - 0x2d - usb5744 */ @@ -128,6 +128,7 @@ pinctrl-0 = <&pinctrl_gem3_default>; phy-handle = <&phy0>; phy-mode = "rgmii-id"; + assigned-clock-rates = <250000000>; mdio: mdio { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index dfd1a18f5a10..c4774a42d5fc 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -50,6 +50,17 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pmu_region: pmu@7ff00000 { + reg = <0x0 0x7ff00000 0x0 0x100000>; + no-map; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -245,8 +256,8 @@ status = "okay"; bootph-all; clock-frequency = <400000>; - scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; eeprom: eeprom@50 { /* u46 - also at address 0x58 */ bootph-all; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index d9d1de5f313c..e821d55d8d5a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -119,8 +119,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; eeprom: eeprom@55 { compatible = "atmel,24c64"; /* 24AA64 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index 6503f4985f8d..b59e11316b4b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -110,8 +110,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u26: gpio@20 { compatible = "ti,tca6416"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts index b1e933b8a2cd..0d2ea9c09a0a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts @@ -91,8 +91,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 74 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 75 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; &i2c1 { @@ -100,8 +100,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 76 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 77 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 44d1f351bb75..d0091d3cb764 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -180,8 +180,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; i2c-mux@75 { /* u11 */ compatible = "nxp,pca9548"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 8767f147cbe3..84952c14f021 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -233,8 +233,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; @@ -497,8 +497,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index e185709c0d84..5084ddcee00f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -140,8 +140,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* Another connection to this bus via PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 7fceebd1815c..b273bd1d920a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -145,8 +145,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 27b2416cb6d8..50c384aa253e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -245,8 +245,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u97: gpio@20 { compatible = "ti,tca6416"; @@ -508,8 +508,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PL i2c via PCA9306 - u45 */ i2c-mux@74 { /* u34 */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index 6224365826d8..617cb0405a7d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -205,8 +205,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0_default>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; tca6416_u22: gpio@20 { compatible = "ti,tca6416"; @@ -385,8 +385,8 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; pinctrl-1 = <&pinctrl_i2c1_gpio>; - scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; i2c-mux@74 { /* u26 */ compatible = "nxp,pca9548"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 02cfcc716936..b61fc99cd911 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -14,6 +14,8 @@ #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h> @@ -33,6 +35,7 @@ operating-points-v2 = <&cpu_opp_table>; reg = <0x0>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -42,6 +45,7 @@ reg = <0x1>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu2: cpu@2 { @@ -51,6 +55,7 @@ reg = <0x2>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; }; cpu3: cpu@3 { @@ -60,6 +65,13 @@ reg = <0x3>; operating-points-v2 = <&cpu_opp_table>; cpu-idle-states = <&CPU_SLEEP_0>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; }; idle-states { @@ -121,7 +133,7 @@ bootph-all; compatible = "xlnx,zynqmp-ipi-mailbox"; interrupt-parent = <&gic>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; xlnx,ipi-id = <0>; #address-cells = <2>; #size-cells = <2>; @@ -151,10 +163,10 @@ pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; - interrupts = <0 143 4>, - <0 144 4>, - <0 145 4>, - <0 146 4>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, @@ -177,7 +189,7 @@ bootph-all; compatible = "xlnx,zynqmp-power"; interrupt-parent = <&gic>; - interrupts = <0 35 4>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; mbox-names = "tx", "rx"; }; @@ -221,10 +233,10 @@ timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; - interrupts = <1 13 0xf08>, - <1 14 0xf08>, - <1 11 0xf08>, - <1 10 0xf08>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; fpga_full: fpga-full { @@ -264,7 +276,7 @@ status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff060000 0x0 0x1000>; - interrupts = <0 23 4>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; @@ -276,7 +288,7 @@ status = "disabled"; clock-names = "can_clk", "pclk"; reg = <0x0 0xff070000 0x0 0x1000>; - interrupts = <0 24 4>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; @@ -295,11 +307,11 @@ compatible = "arm,cci-400-pmu,r1"; reg = <0x9000 0x5000>; interrupt-parent = <&gic>; - interrupts = <0 123 4>, - <0 123 4>, - <0 123 4>, - <0 123 4>, - <0 123 4>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; }; }; @@ -309,7 +321,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd500000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 124 4>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -322,7 +334,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd510000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 125 4>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -335,7 +347,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd520000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 126 4>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -348,7 +360,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd530000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 127 4>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -361,7 +373,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd540000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 128 4>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -374,7 +386,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd550000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 129 4>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -387,7 +399,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd560000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 130 4>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -400,7 +412,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xfd570000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 131 4>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <128>; @@ -417,7 +429,7 @@ <0x0 0xf9060000 0x0 0x20000>; interrupt-controller; interrupt-parent = <&gic>; - interrupts = <1 9 0xf04>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; gpu: gpu@fd4b0000 { @@ -425,8 +437,12 @@ compatible = "xlnx,zynqmp-mali", "arm,mali-400"; reg = <0x0 0xfd4b0000 0x0 0x10000>; interrupt-parent = <&gic>; - interrupts = <0 132 4>, <0 132 4>, <0 132 4>, - <0 132 4>, <0 132 4>, <0 132 4>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; clock-names = "bus", "core"; power-domains = <&zynqmp_firmware PD_GPU>; @@ -441,7 +457,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 77 4>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -454,7 +470,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 78 4>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -467,7 +483,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 79 4>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -480,7 +496,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 80 4>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -493,7 +509,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 81 4>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -506,7 +522,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 82 4>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -519,7 +535,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 83 4>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -532,7 +548,7 @@ compatible = "xlnx,zynqmp-dma-1.0"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; - interrupts = <0 84 4>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; clock-names = "clk_main", "clk_apb"; #dma-cells = <1>; xlnx,bus-width = <64>; @@ -544,7 +560,7 @@ compatible = "xlnx,zynqmp-ddrc-2.40a"; reg = <0x0 0xfd070000 0x0 0x30000>; interrupt-parent = <&gic>; - interrupts = <0 112 4>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; }; nand0: nand-controller@ff100000 { @@ -553,7 +569,7 @@ reg = <0x0 0xff100000 0x0 0x1000>; clock-names = "controller", "bus"; interrupt-parent = <&gic>; - interrupts = <0 14 4>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; iommus = <&smmu 0x872>; @@ -564,7 +580,8 @@ compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 57 4>, <0 57 4>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0b0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; @@ -579,7 +596,8 @@ compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 59 4>, <0 59 4>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0c0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; @@ -594,7 +612,8 @@ compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 61 4>, <0 61 4>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0d0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; @@ -609,7 +628,8 @@ compatible = "xlnx,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 63 4>, <0 63 4>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff0e0000 0x0 0x1000>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; @@ -626,7 +646,7 @@ #gpio-cells = <0x2>; gpio-controller; interrupt-parent = <&gic>; - interrupts = <0 16 4>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; @@ -637,7 +657,8 @@ compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 17 4>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -648,7 +669,8 @@ compatible = "cdns,i2c-r1p14"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 18 4>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; @@ -664,11 +686,11 @@ msi-controller; device_type = "pci"; interrupt-parent = <&gic>; - interrupts = <0 118 4>, - <0 117 4>, - <0 116 4>, - <0 115 4>, /* MSI_1 [63...32] */ - <0 114 4>; /* MSI_0 [31...0] */ + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, /* MSI_1 [63...32] */ + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */ interrupt-names = "misc", "dummy", "intx", "msi1", "msi0"; msi-parent = <&pcie>; @@ -698,7 +720,7 @@ compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; - interrupts = <0 15 4>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, @@ -723,7 +745,8 @@ status = "disabled"; reg = <0x0 0xffa60000 0x0 0x100>; interrupt-parent = <&gic>; - interrupts = <0 26 4>, <0 27 4>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "alarm", "sec"; calibration = <0x7FFF>; }; @@ -733,7 +756,7 @@ status = "disabled"; reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; - interrupts = <0 133 4>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&zynqmp_firmware PD_SATA>; resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, @@ -745,7 +768,7 @@ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 48 4>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff160000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x870>; @@ -760,7 +783,7 @@ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 49 4>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff170000 0x0 0x1000>; clock-names = "clk_xin", "clk_ahb"; iommus = <&smmu 0x871>; @@ -777,18 +800,30 @@ status = "disabled"; #global-interrupts = <1>; interrupt-parent = <&gic>; - interrupts = <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, - <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; }; spi0: spi@ff040000 { compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 19 4>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; @@ -800,7 +835,7 @@ compatible = "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 20 4>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff050000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; #address-cells = <1>; @@ -812,7 +847,9 @@ compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 36 4>, <0 37 4>, <0 38 4>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_0>; @@ -822,7 +859,9 @@ compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 39 4>, <0 40 4>, <0 41 4>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_1>; @@ -832,7 +871,9 @@ compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 42 4>, <0 43 4>, <0 44 4>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_2>; @@ -842,7 +883,9 @@ compatible = "cdns,ttc"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 45 4>, <0 46 4>, <0 47 4>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; power-domains = <&zynqmp_firmware PD_TTC_3>; @@ -853,7 +896,7 @@ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 21 4>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_0>; @@ -864,7 +907,7 @@ compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 22 4>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; power-domains = <&zynqmp_firmware PD_UART_1>; @@ -888,8 +931,10 @@ compatible = "snps,dwc3"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupt-names = "dwc_usb3", "otg"; - interrupts = <0 65 4>, <0 69 4>; + interrupt-names = "host", "peripheral", "otg"; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clock-names = "bus_early", "ref"; iommus = <&smmu 0x860>; snps,quirk-frame-length-adjustment = <0x20>; @@ -915,8 +960,10 @@ compatible = "snps,dwc3"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; - interrupt-names = "dwc_usb3", "otg"; - interrupts = <0 70 4>, <0 74 4>; + interrupt-names = "host", "peripheral", "otg"; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clock-names = "bus_early", "ref"; iommus = <&smmu 0x861>; snps,quirk-frame-length-adjustment = <0x20>; @@ -929,7 +976,7 @@ compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 113 1>; + interrupts = <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>; reg = <0x0 0xfd4d0000 0x0 0x1000>; timeout-sec = <60>; reset-on-timeout; @@ -939,7 +986,7 @@ compatible = "cdns,wdt-r1p2"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 52 1>; + interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; @@ -948,7 +995,7 @@ compatible = "xlnx,zynqmp-ams"; status = "disabled"; interrupt-parent = <&gic>; - interrupts = <0 56 4>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; reg = <0x0 0xffa50000 0x0 0x800>; #address-cells = <1>; #size-cells = <1>; @@ -974,7 +1021,7 @@ compatible = "xlnx,zynqmp-dpdma"; status = "disabled"; reg = <0x0 0xfd4c0000 0x0 0x1000>; - interrupts = <0 122 4>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clock-names = "axi_clk"; power-domains = <&zynqmp_firmware PD_DP>; @@ -990,7 +1037,7 @@ <0x0 0xfd4ab000 0x0 0x1000>, <0x0 0xfd4ac000 0x0 0x1000>; reg-names = "dp", "blend", "av_buf", "aud"; - interrupts = <0 119 4>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in"; diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 1bb1e5cae602..822f022eec2d 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -53,6 +53,18 @@ #interrupt-cells = <3>; /omit-if-no-ref/ + can0_pins: can0-pins { + pins = "PB2", "PB3"; + function = "can0"; + }; + + /omit-if-no-ref/ + can1_pins: can1-pins { + pins = "PB4", "PB5"; + function = "can1"; + }; + + /omit-if-no-ref/ clk_pg11_pin: clk-pg11-pin { pins = "PG11"; function = "clk"; @@ -144,6 +156,16 @@ #reset-cells = <1>; }; + gpadc: adc@2009000 { + compatible = "allwinner,sun20i-d1-gpadc"; + reg = <0x2009000 0x400>; + clocks = <&ccu CLK_BUS_GPADC>; + resets = <&ccu RST_BUS_GPADC>; + interrupts = <SOC_PERIPHERAL_IRQ(57) IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + #io-channel-cells = <1>; + }; + dmic: dmic@2031000 { compatible = "allwinner,sun20i-d1-dmic", "allwinner,sun50i-h6-dmic"; @@ -346,6 +368,28 @@ #size-cells = <0>; }; + can0: can@2504000 { + compatible = "allwinner,sun20i-d1-can"; + reg = <0x02504000 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(21) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CAN0>; + resets = <&ccu RST_BUS_CAN0>; + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins>; + status = "disabled"; + }; + + can1: can@2504400 { + compatible = "allwinner,sun20i-d1-can"; + reg = <0x02504400 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CAN1>; + resets = <&ccu RST_BUS_CAN1>; + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins>; + status = "disabled"; + }; + syscon: syscon@3000000 { compatible = "allwinner,sun20i-d1-system-control"; reg = <0x3000000 0x1000>; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi index d6f18754eb5d..c62debc7ca7e 100644 --- a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi @@ -22,6 +22,7 @@ status = "disabled"; }; +#if (!SW_ET0_EN_N) ð0 { status = "disabled"; @@ -30,6 +31,7 @@ /delete-property/ interrupts; }; }; +#endif ð1 { status = "disabled"; diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile index 170956846d49..0141504c0f5c 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -1,4 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 +# Enables support for device-tree overlays +DTC_FLAGS_jh7100-beaglev-starlight := -@ +DTC_FLAGS_jh7100-starfive-visionfive-v1 := -@ +DTC_FLAGS_jh7110-starfive-visionfive-2-v1.2a := -@ +DTC_FLAGS_jh7110-starfive-visionfive-2-v1.3b := -@ + dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 4218621ea3b9..35ab54fb235f 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -80,6 +80,31 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <15000>; + + thermal-sensors = <&sfctemp>; + + trips { + cpu_alert0 { + /* milliCelsius */ + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit { + /* milliCelsius */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + osc_sys: osc_sys { compatible = "fixed-clock"; #clock-cells = <0>; @@ -248,5 +273,17 @@ resets = <&rstgen JH7100_RSTN_WDTIMER_APB>, <&rstgen JH7100_RSTN_WDT>; }; + + sfctemp: temperature-sensor@124a0000 { + compatible = "starfive,jh7100-temp"; + reg = <0x0 0x124a0000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_TEMP_SENSE>, + <&clkgen JH7100_CLK_TEMP_APB>; + clock-names = "sense", "bus"; + resets = <&rstgen JH7100_RSTN_TEMP_SENSE>, + <&rstgen JH7100_RSTN_TEMP_APB>; + reset-names = "sense", "bus"; + #thermal-sensor-cells = <0>; + }; }; }; diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts index 4af3300f3cf3..205a13d8c8b1 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts @@ -11,3 +11,16 @@ model = "StarFive VisionFive 2 v1.2A"; compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110"; }; + +&gmac1 { + phy-mode = "rmii"; + assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>, + <&syscrg JH7110_SYSCLK_GMAC1_RX>; + assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>, + <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; +}; + +&phy0 { + rx-internal-delay-ps = <1900>; + tx-internal-delay-ps = <1350>; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts index 9230cc3d8946..d4ea4a2c0b9b 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts @@ -11,3 +11,34 @@ model = "StarFive VisionFive 2 v1.3B"; compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110"; }; + +&gmac0 { + starfive,tx-use-rgmii-clk; + assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; + assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>; +}; + +&gmac1 { + starfive,tx-use-rgmii-clk; + assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>; + assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>; +}; + +&phy0 { + motorcomm,tx-clk-adj-enabled; + motorcomm,tx-clk-100-inverted; + motorcomm,tx-clk-1000-inverted; + motorcomm,rx-clk-drv-microamp = <3970>; + motorcomm,rx-data-drv-microamp = <2910>; + rx-internal-delay-ps = <1500>; + tx-internal-delay-ps = <1500>; +}; + +&phy1 { + motorcomm,tx-clk-adj-enabled; + motorcomm,tx-clk-100-inverted; + motorcomm,rx-clk-drv-microamp = <3970>; + motorcomm,rx-data-drv-microamp = <2910>; + rx-internal-delay-ps = <300>; + tx-internal-delay-ps = <0>; +}; diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index fa0061eb33a7..d79f94432b27 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -11,10 +11,14 @@ / { aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; i2c0 = &i2c0; i2c2 = &i2c2; i2c5 = &i2c5; i2c6 = &i2c6; + mmc0 = &mmc0; + mmc1 = &mmc1; serial0 = &uart0; }; @@ -38,6 +42,10 @@ }; }; +&dvp_clk { + clock-frequency = <74250000>; +}; + &gmac0_rgmii_rxin { clock-frequency = <125000000>; }; @@ -54,6 +62,10 @@ clock-frequency = <50000000>; }; +&hdmitx0_pixelclk { + clock-frequency = <297000000>; +}; + &i2srx_bclk_ext { clock-frequency = <12288000>; }; @@ -86,6 +98,38 @@ clock-frequency = <49152000>; }; +&gmac0 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; + }; +}; + +&gmac1 { + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy1: ethernet-phy@1 { + reg = <0>; + }; + }; +}; + &i2c0 { clock-frequency = <100000>; i2c-sda-hold-time-ns = <300>; @@ -123,12 +167,28 @@ #interrupt-cells = <1>; regulators { + vcc_3v3: dcdc1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3"; + }; + vdd_cpu: dcdc2 { regulator-always-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1540000>; regulator-name = "vdd-cpu"; }; + + emmc_vdd: aldo4 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "emmc_vdd"; + }; }; }; }; @@ -143,6 +203,83 @@ status = "okay"; }; +&mmc0 { + max-frequency = <100000000>; + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + cap-mmc-hw-reset; + post-power-on-delay-ms = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&emmc_vdd>; + status = "okay"; +}; + +&mmc1 { + max-frequency = <100000000>; + bus-width = <4>; + no-sdio; + no-mmc; + broken-cd; + cap-sd-highspeed; + post-power-on-delay-ms = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + status = "okay"; +}; + +&qspi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nor_flash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + cdns,read-delay = <5>; + spi-max-frequency = <12000000>; + cdns,tshsl-ns = <1>; + cdns,tsd2d-ns = <1>; + cdns,tchsh-ns = <1>; + cdns,tslch-ns = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + spl@0 { + reg = <0x0 0x80000>; + }; + uboot-env@f0000 { + reg = <0xf0000 0x10000>; + }; + uboot@100000 { + reg = <0x100000 0x400000>; + }; + reserved-data@600000 { + reg = <0x600000 0x1000000>; + }; + }; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + spi_dev0: spi@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + &sysgpio { i2c0_pins: i2c0-0 { i2c-pins { @@ -200,6 +337,109 @@ }; }; + mmc0_pins: mmc0-0 { + rst-pins { + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST, + GPOEN_ENABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + mmc-pins { + pinmux = <PINMUX(64, 0)>, + <PINMUX(65, 0)>, + <PINMUX(66, 0)>, + <PINMUX(67, 0)>, + <PINMUX(68, 0)>, + <PINMUX(69, 0)>, + <PINMUX(70, 0)>, + <PINMUX(71, 0)>, + <PINMUX(72, 0)>, + <PINMUX(73, 0)>; + bias-pull-up; + drive-strength = <12>; + input-enable; + }; + }; + + mmc1_pins: mmc1-0 { + clk-pins { + pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK, + GPOEN_ENABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + mmc-pins { + pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD, + GPOEN_SYS_SDIO1_CMD, + GPI_SYS_SDIO1_CMD)>, + <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0, + GPOEN_SYS_SDIO1_DATA0, + GPI_SYS_SDIO1_DATA0)>, + <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1, + GPOEN_SYS_SDIO1_DATA1, + GPI_SYS_SDIO1_DATA1)>, + <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2, + GPOEN_SYS_SDIO1_DATA2, + GPI_SYS_SDIO1_DATA2)>, + <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3, + GPOEN_SYS_SDIO1_DATA3, + GPI_SYS_SDIO1_DATA3)>; + bias-pull-up; + drive-strength = <12>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + + spi0_pins: spi0-0 { + mosi-pins { + pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD, + GPOEN_ENABLE, + GPI_NONE)>; + bias-disable; + input-disable; + input-schmitt-disable; + }; + + miso-pins { + pinmux = <GPIOMUX(53, GPOUT_LOW, + GPOEN_DISABLE, + GPI_SYS_SPI0_RXD)>; + bias-pull-up; + input-enable; + input-schmitt-enable; + }; + + sck-pins { + pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK, + GPOEN_ENABLE, + GPI_SYS_SPI0_CLK)>; + bias-disable; + input-disable; + input-schmitt-disable; + }; + + ss-pins { + pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS, + GPOEN_ENABLE, + GPI_SYS_SPI0_FSS)>; + bias-disable; + input-disable; + input-schmitt-disable; + }; + }; + uart0_pins: uart0-0 { tx-pins { pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX, @@ -223,6 +463,46 @@ slew-rate = <0>; }; }; + + tdm_pins: tdm-0 { + tx-pins { + pinmux = <GPIOMUX(44, GPOUT_SYS_TDM_TXD, + GPOEN_ENABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <2>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pinmux = <GPIOMUX(61, GPOUT_HIGH, + GPOEN_DISABLE, + GPI_SYS_TDM_RXD)>; + input-enable; + }; + + sync-pins { + pinmux = <GPIOMUX(63, GPOUT_HIGH, + GPOEN_DISABLE, + GPI_SYS_TDM_SYNC)>; + input-enable; + }; + + pcmclk-pins { + pinmux = <GPIOMUX(38, GPOUT_HIGH, + GPOEN_DISABLE, + GPI_SYS_TDM_CLK)>; + input-enable; + }; + }; +}; + +&tdm { + pinctrl-names = "default"; + pinctrl-0 = <&tdm_pins>; + status = "okay"; }; &uart0 { @@ -231,6 +511,10 @@ status = "okay"; }; +&usb0 { + dr_mode = "peripheral"; +}; + &U74_1 { cpu-supply = <&vdd_cpu>; }; diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index ec2e70011a73..e85464c328d0 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -6,7 +6,9 @@ /dts-v1/; #include <dt-bindings/clock/starfive,jh7110-crg.h> +#include <dt-bindings/power/starfive,jh7110-pmu.h> #include <dt-bindings/reset/starfive,jh7110-crg.h> +#include <dt-bindings/thermal/thermal.h> / { compatible = "starfive,jh7110"; @@ -56,6 +58,7 @@ operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; clock-names = "cpu"; + #cooling-cells = <2>; cpu1_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -85,6 +88,7 @@ operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; clock-names = "cpu"; + #cooling-cells = <2>; cpu2_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -114,6 +118,7 @@ operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; clock-names = "cpu"; + #cooling-cells = <2>; cpu3_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -143,6 +148,7 @@ operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; clock-names = "cpu"; + #cooling-cells = <2>; cpu4_intc: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -197,6 +203,47 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <15000>; + + thermal-sensors = <&sfctemp>; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&U74_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&U74_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&U74_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&U74_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert0: cpu_alert0 { + /* milliCelsius */ + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit { + /* milliCelsius */ + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + dvp_clk: dvp-clock { + compatible = "fixed-clock"; + clock-output-names = "dvp_clk"; + #clock-cells = <0>; + }; gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { compatible = "fixed-clock"; clock-output-names = "gmac0_rgmii_rxin"; @@ -221,6 +268,12 @@ #clock-cells = <0>; }; + hdmitx0_pixelclk: hdmitx0-pixel-clock { + compatible = "fixed-clock"; + clock-output-names = "hdmitx0_pixelclk"; + #clock-cells = <0>; + }; + i2srx_bclk_ext: i2srx-bclk-ext-clock { compatible = "fixed-clock"; clock-output-names = "i2srx_bclk_ext"; @@ -263,6 +316,13 @@ #clock-cells = <0>; }; + stmmac_axi_setup: stmmac-axi-config { + snps,lpi_en; + snps,wr_osr_lmt = <15>; + snps,rd_osr_lmt = <15>; + snps,blen = <256 128 64 32 0 0 0>; + }; + tdm_ext: tdm-ext-clock { compatible = "fixed-clock"; clock-output-names = "tdm_ext"; @@ -386,6 +446,149 @@ status = "disabled"; }; + spi0: spi@10060000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x10060000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI0_APB>, + <&syscrg JH7110_SYSCLK_SPI0_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI0_APB>; + interrupts = <38>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@10070000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x10070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI1_APB>, + <&syscrg JH7110_SYSCLK_SPI1_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI1_APB>; + interrupts = <39>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@10080000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x10080000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI2_APB>, + <&syscrg JH7110_SYSCLK_SPI2_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI2_APB>; + interrupts = <40>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + tdm: tdm@10090000 { + compatible = "starfive,jh7110-tdm"; + reg = <0x0 0x10090000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>, + <&syscrg JH7110_SYSCLK_TDM_APB>, + <&syscrg JH7110_SYSCLK_TDM_INTERNAL>, + <&syscrg JH7110_SYSCLK_TDM_TDM>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&tdm_ext>; + clock-names = "tdm_ahb", "tdm_apb", + "tdm_internal", "tdm", + "mclk_inner", "tdm_ext"; + resets = <&syscrg JH7110_SYSRST_TDM_AHB>, + <&syscrg JH7110_SYSRST_TDM_APB>, + <&syscrg JH7110_SYSRST_TDM_CORE>; + dmas = <&dma 20>, <&dma 21>; + dma-names = "rx","tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + usb0: usb@10100000 { + compatible = "starfive,jh7110-usb"; + ranges = <0x0 0x0 0x10100000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + starfive,stg-syscon = <&stg_syscon 0x4>; + clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>, + <&stgcrg JH7110_STGCLK_USB0_STB>, + <&stgcrg JH7110_STGCLK_USB0_APB>, + <&stgcrg JH7110_STGCLK_USB0_AXI>, + <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>; + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb"; + resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>, + <&stgcrg JH7110_STGRST_USB0_APB>, + <&stgcrg JH7110_STGRST_USB0_AXI>, + <&stgcrg JH7110_STGRST_USB0_UTMI_APB>; + reset-names = "pwrup", "apb", "axi", "utmi_apb"; + status = "disabled"; + + usb_cdns3: usb@0 { + compatible = "cdns,usb3"; + reg = <0x0 0x10000>, + <0x10000 0x10000>, + <0x20000 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <100>, <108>, <110>; + interrupt-names = "host", "peripheral", "otg"; + phys = <&usbphy0>; + phy-names = "cdns3,usb2-phy"; + }; + }; + + usbphy0: phy@10200000 { + compatible = "starfive,jh7110-usb-phy"; + reg = <0x0 0x10200000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_USB_125M>, + <&stgcrg JH7110_STGCLK_USB0_APP_125>; + clock-names = "125m", "app_125m"; + #phy-cells = <0>; + }; + + pciephy0: phy@10210000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10210000 0x0 0x10000>; + #phy-cells = <0>; + }; + + pciephy1: phy@10220000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10220000 0x0 0x10000>; + #phy-cells = <0>; + }; + + stgcrg: clock-controller@10230000 { + compatible = "starfive,jh7110-stgcrg"; + reg = <0x0 0x10230000 0x0 0x10000>; + clocks = <&osc>, + <&syscrg JH7110_SYSCLK_HIFI4_CORE>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_USB_125M>, + <&syscrg JH7110_SYSCLK_CPU_BUS>, + <&syscrg JH7110_SYSCLK_HIFI4_AXI>, + <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, + <&syscrg JH7110_SYSCLK_APB_BUS>; + clock-names = "osc", "hifi4_core", + "stg_axiahb", "usb_125m", + "cpu_bus", "hifi4_axi", + "nocstg_bus", "apb_bus"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + stg_syscon: syscon@10240000 { + compatible = "starfive,jh7110-stg-syscon", "syscon"; + reg = <0x0 0x10240000 0x0 0x1000>; + }; + uart3: serial@12000000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x12000000 0x0 0x10000>; @@ -473,6 +676,97 @@ status = "disabled"; }; + spi3: spi@12070000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x12070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>, + <&syscrg JH7110_SYSCLK_SPI3_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI3_APB>; + interrupts = <52>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@12080000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x12080000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI4_APB>, + <&syscrg JH7110_SYSCLK_SPI4_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI4_APB>; + interrupts = <53>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@12090000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x12090000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI5_APB>, + <&syscrg JH7110_SYSCLK_SPI5_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI5_APB>; + interrupts = <54>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@120a0000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x120A0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI6_APB>, + <&syscrg JH7110_SYSCLK_SPI6_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI6_APB>; + interrupts = <55>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sfctemp: temperature-sensor@120e0000 { + compatible = "starfive,jh7110-temp"; + reg = <0x0 0x120e0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>, + <&syscrg JH7110_SYSCLK_TEMP_APB>; + clock-names = "sense", "bus"; + resets = <&syscrg JH7110_SYSRST_TEMP_CORE>, + <&syscrg JH7110_SYSRST_TEMP_APB>; + reset-names = "sense", "bus"; + #thermal-sensor-cells = <0>; + }; + + qspi: spi@13010000 { + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; + reg = <0x0 0x13010000 0x0 0x10000>, + <0x0 0x21000000 0x0 0x400000>; + interrupts = <25>; + clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>, + <&syscrg JH7110_SYSCLK_QSPI_AHB>, + <&syscrg JH7110_SYSCLK_QSPI_APB>; + clock-names = "ref", "ahb", "apb"; + resets = <&syscrg JH7110_SYSRST_QSPI_APB>, + <&syscrg JH7110_SYSRST_QSPI_AHB>, + <&syscrg JH7110_SYSRST_QSPI_REF>; + reset-names = "qspi", "qspi-ocp", "rstc_ref"; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + status = "disabled"; + }; + syscrg: clock-controller@13020000 { compatible = "starfive,jh7110-syscrg"; reg = <0x0 0x13020000 0x0 0x10000>; @@ -480,16 +774,31 @@ <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, - <&tdm_ext>, <&mclk_ext>; + <&tdm_ext>, <&mclk_ext>, + <&pllclk JH7110_PLLCLK_PLL0_OUT>, + <&pllclk JH7110_PLLCLK_PLL1_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>; clock-names = "osc", "gmac1_rmii_refin", "gmac1_rgmii_rxin", "i2stx_bclk_ext", "i2stx_lrck_ext", "i2srx_bclk_ext", "i2srx_lrck_ext", - "tdm_ext", "mclk_ext"; + "tdm_ext", "mclk_ext", + "pll0_out", "pll1_out", "pll2_out"; #clock-cells = <1>; #reset-cells = <1>; }; + sys_syscon: syscon@13030000 { + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; + reg = <0x0 0x13030000 0x0 0x1000>; + + pllclk: clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; + }; + sysgpio: pinctrl@13040000 { compatible = "starfive,jh7110-sys-pinctrl"; reg = <0x0 0x13040000 0x0 0x10000>; @@ -512,6 +821,155 @@ <&syscrg JH7110_SYSRST_WDT_CORE>; }; + crypto: crypto@16000000 { + compatible = "starfive,jh7110-crypto"; + reg = <0x0 0x16000000 0x0 0x4000>; + clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, + <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; + clock-names = "hclk", "ahb"; + interrupts = <28>; + resets = <&stgcrg JH7110_STGRST_SEC_AHB>; + dmas = <&sdma 1 2>, <&sdma 0 2>; + dma-names = "tx", "rx"; + }; + + sdma: dma-controller@16008000 { + compatible = "arm,pl080", "arm,primecell"; + arm,primecell-periphid = <0x00041080>; + reg = <0x0 0x16008000 0x0 0x4000>; + interrupts = <29>; + clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>; + clock-names = "apb_pclk"; + resets = <&stgcrg JH7110_STGRST_SEC_AHB>; + lli-bus-interface-ahb1; + mem-bus-interface-ahb1; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <2>; + }; + + rng: rng@1600c000 { + compatible = "starfive,jh7110-trng"; + reg = <0x0 0x1600C000 0x0 0x4000>; + clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, + <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; + clock-names = "hclk", "ahb"; + resets = <&stgcrg JH7110_STGRST_SEC_AHB>; + interrupts = <30>; + }; + + mmc0: mmc@16010000 { + compatible = "starfive,jh7110-mmc"; + reg = <0x0 0x16010000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>, + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; + clock-names = "biu","ciu"; + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>; + reset-names = "reset"; + interrupts = <74>; + fifo-depth = <32>; + fifo-watermark-aligned; + data-addr = <0>; + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>; + status = "disabled"; + }; + + mmc1: mmc@16020000 { + compatible = "starfive,jh7110-mmc"; + reg = <0x0 0x16020000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>, + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; + clock-names = "biu","ciu"; + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>; + reset-names = "reset"; + interrupts = <75>; + fifo-depth = <32>; + fifo-watermark-aligned; + data-addr = <0>; + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>; + status = "disabled"; + }; + + gmac0: ethernet@16030000 { + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; + reg = <0x0 0x16030000 0x0 0x10000>; + clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, + <&aoncrg JH7110_AONCLK_GMAC0_AHB>, + <&syscrg JH7110_SYSCLK_GMAC0_PTP>, + <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXC>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "gtx"; + resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, + <&aoncrg JH7110_AONRST_GMAC0_AHB>; + reset-names = "stmmaceth", "ahb"; + interrupts = <7>, <6>, <5>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <256>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,tso; + snps,en-tx-lpi-clockgating; + snps,txpbl = <16>; + snps,rxpbl = <16>; + starfive,syscon = <&aon_syscon 0xc 0x12>; + status = "disabled"; + }; + + gmac1: ethernet@16040000 { + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; + reg = <0x0 0x16040000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, + <&syscrg JH7110_SYSCLK_GMAC1_AHB>, + <&syscrg JH7110_SYSCLK_GMAC1_PTP>, + <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>, + <&syscrg JH7110_SYSCLK_GMAC1_GTXC>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "gtx"; + resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, + <&syscrg JH7110_SYSRST_GMAC1_AHB>; + reset-names = "stmmaceth", "ahb"; + interrupts = <78>, <77>, <76>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <256>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,tso; + snps,en-tx-lpi-clockgating; + snps,txpbl = <16>; + snps,rxpbl = <16>; + starfive,syscon = <&sys_syscon 0x90 0x2>; + status = "disabled"; + }; + + dma: dma-controller@16050000 { + compatible = "starfive,jh7110-axi-dma"; + reg = <0x0 0x16050000 0x0 0x10000>; + clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>, + <&stgcrg JH7110_STGCLK_DMA1P_AHB>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>, + <&stgcrg JH7110_STGRST_DMA1P_AHB>; + interrupts = <73>; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <3>; + snps,block-size = <65536 65536 65536 65536>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <16>; + }; + aoncrg: clock-controller@17000000 { compatible = "starfive,jh7110-aoncrg"; reg = <0x0 0x17000000 0x0 0x10000>; @@ -529,6 +987,12 @@ #reset-cells = <1>; }; + aon_syscon: syscon@17010000 { + compatible = "starfive,jh7110-aon-syscon", "syscon"; + reg = <0x0 0x17010000 0x0 0x1000>; + #power-domain-cells = <1>; + }; + aongpio: pinctrl@17020000 { compatible = "starfive,jh7110-aon-pinctrl"; reg = <0x0 0x17020000 0x0 0x10000>; @@ -546,5 +1010,40 @@ interrupts = <111>; #power-domain-cells = <1>; }; + + ispcrg: clock-controller@19810000 { + compatible = "starfive,jh7110-ispcrg"; + reg = <0x0 0x19810000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, + <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, + <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, + <&dvp_clk>; + clock-names = "isp_top_core", "isp_top_axi", + "noc_bus_isp_axi", "dvp_clk"; + resets = <&syscrg JH7110_SYSRST_ISP_TOP>, + <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, + <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_ISP>; + }; + + voutcrg: clock-controller@295c0000 { + compatible = "starfive,jh7110-voutcrg"; + reg = <0x0 0x295c0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, + <&hdmitx0_pixelclk>; + clock-names = "vout_src", "vout_top_ahb", + "vout_top_axi", "vout_top_hdmitx0_mclk", + "i2stx0_bclk", "hdmitx0_pixelclk"; + resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_VOUT>; + }; }; }; diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile index e311fc9a5939..b55a17127c2b 100644 --- a/arch/riscv/boot/dts/thead/Makefile +++ b/arch/riscv/boot/dts/thead/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb +dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb th1520-beaglev-ahead.dtb diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts new file mode 100644 index 000000000000..70e8042c8304 --- /dev/null +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> + * Copyright (C) 2023 Drew Fustini <dfustini@baylibre.com> + */ + +/dts-v1/; + +#include "th1520.dtsi" + +/ { + model = "BeagleV Ahead"; + compatible = "beagle,beaglev-ahead", "thead,th1520"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x00000000 0x1 0x00000000>; + + }; +}; + +&osc { + clock-frequency = <24000000>; +}; + +&osc_32k { + clock-frequency = <32768>; +}; + +&apb_clk { + clock-frequency = <62500000>; +}; + +&uart_sclk { + clock-frequency = <100000000>; +}; + +&dmac0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 4b0249ac710f..a802ab110429 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> */ diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts index a1248b2ee3a3..9a3884a73e13 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> */ diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index 56a73134b49e..ce708183b6f6 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2021 Alibaba Group Holding Limited. * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> diff --git a/include/dt-bindings/clock/intel,agilex5-clkmgr.h b/include/dt-bindings/clock/intel,agilex5-clkmgr.h new file mode 100644 index 000000000000..2f3a23b31c5c --- /dev/null +++ b/include/dt-bindings/clock/intel,agilex5-clkmgr.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2023, Intel Corporation + */ + +#ifndef __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H +#define __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H + +/* fixed rate clocks */ +#define AGILEX5_OSC1 0 +#define AGILEX5_CB_INTOSC_HS_DIV2_CLK 1 +#define AGILEX5_CB_INTOSC_LS_CLK 2 +#define AGILEX5_F2S_FREE_CLK 3 + +/* PLL clocks */ +#define AGILEX5_MAIN_PLL_CLK 4 +#define AGILEX5_MAIN_PLL_C0_CLK 5 +#define AGILEX5_MAIN_PLL_C1_CLK 6 +#define AGILEX5_MAIN_PLL_C2_CLK 7 +#define AGILEX5_MAIN_PLL_C3_CLK 8 +#define AGILEX5_PERIPH_PLL_CLK 9 +#define AGILEX5_PERIPH_PLL_C0_CLK 10 +#define AGILEX5_PERIPH_PLL_C1_CLK 11 +#define AGILEX5_PERIPH_PLL_C2_CLK 12 +#define AGILEX5_PERIPH_PLL_C3_CLK 13 +#define AGILEX5_CORE0_FREE_CLK 14 +#define AGILEX5_CORE1_FREE_CLK 15 +#define AGILEX5_CORE2_FREE_CLK 16 +#define AGILEX5_CORE3_FREE_CLK 17 +#define AGILEX5_DSU_FREE_CLK 18 +#define AGILEX5_BOOT_CLK 19 + +/* fixed factor clocks */ +#define AGILEX5_L3_MAIN_FREE_CLK 20 +#define AGILEX5_NOC_FREE_CLK 21 +#define AGILEX5_S2F_USR0_CLK 22 +#define AGILEX5_NOC_CLK 23 +#define AGILEX5_EMAC_A_FREE_CLK 24 +#define AGILEX5_EMAC_B_FREE_CLK 25 +#define AGILEX5_EMAC_PTP_FREE_CLK 26 +#define AGILEX5_GPIO_DB_FREE_CLK 27 +#define AGILEX5_S2F_USER0_FREE_CLK 28 +#define AGILEX5_S2F_USER1_FREE_CLK 29 +#define AGILEX5_PSI_REF_FREE_CLK 30 +#define AGILEX5_USB31_FREE_CLK 31 + +/* Gate clocks */ +#define AGILEX5_CORE0_CLK 32 +#define AGILEX5_CORE1_CLK 33 +#define AGILEX5_CORE2_CLK 34 +#define AGILEX5_CORE3_CLK 35 +#define AGILEX5_MPU_CLK 36 +#define AGILEX5_MPU_PERIPH_CLK 37 +#define AGILEX5_MPU_CCU_CLK 38 +#define AGILEX5_L4_MAIN_CLK 39 +#define AGILEX5_L4_MP_CLK 40 +#define AGILEX5_L4_SYS_FREE_CLK 41 +#define AGILEX5_L4_SP_CLK 42 +#define AGILEX5_CS_AT_CLK 43 +#define AGILEX5_CS_TRACE_CLK 44 +#define AGILEX5_CS_PDBG_CLK 45 +#define AGILEX5_EMAC1_CLK 47 +#define AGILEX5_EMAC2_CLK 48 +#define AGILEX5_EMAC_PTP_CLK 49 +#define AGILEX5_GPIO_DB_CLK 50 +#define AGILEX5_S2F_USER0_CLK 51 +#define AGILEX5_S2F_USER1_CLK 52 +#define AGILEX5_PSI_REF_CLK 53 +#define AGILEX5_USB31_SUSPEND_CLK 54 +#define AGILEX5_EMAC0_CLK 46 +#define AGILEX5_USB31_BUS_CLK_EARLY 55 +#define AGILEX5_USB2OTG_HCLK 56 +#define AGILEX5_SPIM_0_CLK 57 +#define AGILEX5_SPIM_1_CLK 58 +#define AGILEX5_SPIS_0_CLK 59 +#define AGILEX5_SPIS_1_CLK 60 +#define AGILEX5_DMA_CORE_CLK 61 +#define AGILEX5_DMA_HS_CLK 62 +#define AGILEX5_I3C_0_CORE_CLK 63 +#define AGILEX5_I3C_1_CORE_CLK 64 +#define AGILEX5_I2C_0_PCLK 65 +#define AGILEX5_I2C_1_PCLK 66 +#define AGILEX5_I2C_EMAC0_PCLK 67 +#define AGILEX5_I2C_EMAC1_PCLK 68 +#define AGILEX5_I2C_EMAC2_PCLK 69 +#define AGILEX5_UART_0_PCLK 70 +#define AGILEX5_UART_1_PCLK 71 +#define AGILEX5_SPTIMER_0_PCLK 72 +#define AGILEX5_SPTIMER_1_PCLK 73 +#define AGILEX5_DFI_CLK 74 +#define AGILEX5_NAND_NF_CLK 75 +#define AGILEX5_NAND_BCH_CLK 76 +#define AGILEX5_SDMMC_SDPHY_REG_CLK 77 +#define AGILEX5_SDMCLK 78 +#define AGILEX5_SOFTPHY_REG_PCLK 79 +#define AGILEX5_SOFTPHY_PHY_CLK 80 +#define AGILEX5_SOFTPHY_CTRL_CLK 81 +#define AGILEX5_NUM_CLKS 82 + +#endif /* __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H */ diff --git a/include/dt-bindings/clock/qcom,gcc-ipq5018.h b/include/dt-bindings/clock/qcom,gcc-ipq5018.h new file mode 100644 index 000000000000..f3de2fdfeea1 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-ipq5018.h @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H +#define _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H + +#define GPLL0_MAIN 0 +#define GPLL0 1 +#define GPLL2_MAIN 2 +#define GPLL2 3 +#define GPLL4_MAIN 4 +#define GPLL4 5 +#define UBI32_PLL_MAIN 6 +#define UBI32_PLL 7 +#define ADSS_PWM_CLK_SRC 8 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 9 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 10 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 11 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 12 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC 13 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC 14 +#define BLSP1_UART1_APPS_CLK_SRC 15 +#define BLSP1_UART2_APPS_CLK_SRC 16 +#define CRYPTO_CLK_SRC 17 +#define GCC_ADSS_PWM_CLK 18 +#define GCC_BLSP1_AHB_CLK 19 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 20 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 21 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 22 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 23 +#define GCC_BLSP1_QUP3_I2C_APPS_CLK 24 +#define GCC_BLSP1_QUP3_SPI_APPS_CLK 25 +#define GCC_BLSP1_UART1_APPS_CLK 26 +#define GCC_BLSP1_UART2_APPS_CLK 27 +#define GCC_BTSS_LPO_CLK 28 +#define GCC_CMN_BLK_AHB_CLK 29 +#define GCC_CMN_BLK_SYS_CLK 30 +#define GCC_CRYPTO_AHB_CLK 31 +#define GCC_CRYPTO_AXI_CLK 32 +#define GCC_CRYPTO_CLK 33 +#define GCC_CRYPTO_PPE_CLK 34 +#define GCC_DCC_CLK 35 +#define GCC_GEPHY_RX_CLK 36 +#define GCC_GEPHY_TX_CLK 37 +#define GCC_GMAC0_CFG_CLK 38 +#define GCC_GMAC0_PTP_CLK 39 +#define GCC_GMAC0_RX_CLK 40 +#define GCC_GMAC0_SYS_CLK 41 +#define GCC_GMAC0_TX_CLK 42 +#define GCC_GMAC1_CFG_CLK 43 +#define GCC_GMAC1_PTP_CLK 44 +#define GCC_GMAC1_RX_CLK 45 +#define GCC_GMAC1_SYS_CLK 46 +#define GCC_GMAC1_TX_CLK 47 +#define GCC_GP1_CLK 48 +#define GCC_GP2_CLK 49 +#define GCC_GP3_CLK 50 +#define GCC_LPASS_CORE_AXIM_CLK 51 +#define GCC_LPASS_SWAY_CLK 52 +#define GCC_MDIO0_AHB_CLK 53 +#define GCC_MDIO1_AHB_CLK 54 +#define GCC_PCIE0_AHB_CLK 55 +#define GCC_PCIE0_AUX_CLK 56 +#define GCC_PCIE0_AXI_M_CLK 57 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 58 +#define GCC_PCIE0_AXI_S_CLK 59 +#define GCC_PCIE0_PIPE_CLK 60 +#define GCC_PCIE1_AHB_CLK 61 +#define GCC_PCIE1_AUX_CLK 62 +#define GCC_PCIE1_AXI_M_CLK 63 +#define GCC_PCIE1_AXI_S_BRIDGE_CLK 64 +#define GCC_PCIE1_AXI_S_CLK 65 +#define GCC_PCIE1_PIPE_CLK 66 +#define GCC_PRNG_AHB_CLK 67 +#define GCC_Q6_AXIM_CLK 68 +#define GCC_Q6_AXIM2_CLK 69 +#define GCC_Q6_AXIS_CLK 70 +#define GCC_Q6_AHB_CLK 71 +#define GCC_Q6_AHB_S_CLK 72 +#define GCC_Q6_TSCTR_1TO2_CLK 73 +#define GCC_Q6SS_ATBM_CLK 74 +#define GCC_Q6SS_PCLKDBG_CLK 75 +#define GCC_Q6SS_TRIG_CLK 76 +#define GCC_QDSS_AT_CLK 77 +#define GCC_QDSS_CFG_AHB_CLK 78 +#define GCC_QDSS_DAP_AHB_CLK 79 +#define GCC_QDSS_DAP_CLK 80 +#define GCC_QDSS_ETR_USB_CLK 81 +#define GCC_QDSS_EUD_AT_CLK 82 +#define GCC_QDSS_STM_CLK 83 +#define GCC_QDSS_TRACECLKIN_CLK 84 +#define GCC_QDSS_TSCTR_DIV8_CLK 85 +#define GCC_QPIC_AHB_CLK 86 +#define GCC_QPIC_CLK 87 +#define GCC_QPIC_IO_MACRO_CLK 88 +#define GCC_SDCC1_AHB_CLK 89 +#define GCC_SDCC1_APPS_CLK 90 +#define GCC_SLEEP_CLK_SRC 91 +#define GCC_SNOC_GMAC0_AHB_CLK 92 +#define GCC_SNOC_GMAC0_AXI_CLK 93 +#define GCC_SNOC_GMAC1_AHB_CLK 94 +#define GCC_SNOC_GMAC1_AXI_CLK 95 +#define GCC_SNOC_LPASS_AXIM_CLK 96 +#define GCC_SNOC_LPASS_SWAY_CLK 97 +#define GCC_SNOC_UBI0_AXI_CLK 98 +#define GCC_SYS_NOC_PCIE0_AXI_CLK 99 +#define GCC_SYS_NOC_PCIE1_AXI_CLK 100 +#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 101 +#define GCC_SYS_NOC_USB0_AXI_CLK 102 +#define GCC_SYS_NOC_WCSS_AHB_CLK 103 +#define GCC_UBI0_AXI_CLK 104 +#define GCC_UBI0_CFG_CLK 105 +#define GCC_UBI0_CORE_CLK 106 +#define GCC_UBI0_DBG_CLK 107 +#define GCC_UBI0_NC_AXI_CLK 108 +#define GCC_UBI0_UTCM_CLK 109 +#define GCC_UNIPHY_AHB_CLK 110 +#define GCC_UNIPHY_RX_CLK 111 +#define GCC_UNIPHY_SYS_CLK 112 +#define GCC_UNIPHY_TX_CLK 113 +#define GCC_USB0_AUX_CLK 114 +#define GCC_USB0_EUD_AT_CLK 115 +#define GCC_USB0_LFPS_CLK 116 +#define GCC_USB0_MASTER_CLK 117 +#define GCC_USB0_MOCK_UTMI_CLK 118 +#define GCC_USB0_PHY_CFG_AHB_CLK 119 +#define GCC_USB0_SLEEP_CLK 120 +#define GCC_WCSS_ACMT_CLK 121 +#define GCC_WCSS_AHB_S_CLK 122 +#define GCC_WCSS_AXI_M_CLK 123 +#define GCC_WCSS_AXI_S_CLK 124 +#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 125 +#define GCC_WCSS_DBG_IFC_APB_CLK 126 +#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 127 +#define GCC_WCSS_DBG_IFC_ATB_CLK 128 +#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 129 +#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 130 +#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 131 +#define GCC_WCSS_DBG_IFC_NTS_CLK 132 +#define GCC_WCSS_ECAHB_CLK 133 +#define GCC_XO_CLK 134 +#define GCC_XO_CLK_SRC 135 +#define GMAC0_RX_CLK_SRC 136 +#define GMAC0_TX_CLK_SRC 137 +#define GMAC1_RX_CLK_SRC 138 +#define GMAC1_TX_CLK_SRC 139 +#define GMAC_CLK_SRC 140 +#define GP1_CLK_SRC 141 +#define GP2_CLK_SRC 142 +#define GP3_CLK_SRC 143 +#define LPASS_AXIM_CLK_SRC 144 +#define LPASS_SWAY_CLK_SRC 145 +#define PCIE0_AUX_CLK_SRC 146 +#define PCIE0_AXI_CLK_SRC 147 +#define PCIE1_AUX_CLK_SRC 148 +#define PCIE1_AXI_CLK_SRC 149 +#define PCNOC_BFDCD_CLK_SRC 150 +#define Q6_AXI_CLK_SRC 151 +#define QDSS_AT_CLK_SRC 152 +#define QDSS_STM_CLK_SRC 153 +#define QDSS_TSCTR_CLK_SRC 154 +#define QDSS_TRACECLKIN_CLK_SRC 155 +#define QPIC_IO_MACRO_CLK_SRC 156 +#define SDCC1_APPS_CLK_SRC 157 +#define SYSTEM_NOC_BFDCD_CLK_SRC 158 +#define UBI0_AXI_CLK_SRC 159 +#define UBI0_CORE_CLK_SRC 160 +#define USB0_AUX_CLK_SRC 161 +#define USB0_LFPS_CLK_SRC 162 +#define USB0_MASTER_CLK_SRC 163 +#define USB0_MOCK_UTMI_CLK_SRC 164 +#define WCSS_AHB_CLK_SRC 165 +#define PCIE0_PIPE_CLK_SRC 166 +#define PCIE1_PIPE_CLK_SRC 167 +#define USB0_PIPE_CLK_SRC 168 +#define GCC_USB0_PIPE_CLK 169 +#define GMAC0_RX_DIV_CLK_SRC 170 +#define GMAC0_TX_DIV_CLK_SRC 171 +#define GMAC1_RX_DIV_CLK_SRC 172 +#define GMAC1_TX_DIV_CLK_SRC 173 +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h index 1badb4f9c58f..b5456a64d421 100644 --- a/include/dt-bindings/clock/qcom,gcc-msm8998.h +++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h @@ -190,6 +190,9 @@ #define AGGRE2_SNOC_NORTH_AXI 181 #define SSC_XO 182 #define SSC_CNOC_AHBS_CLK 183 +#define GCC_MMSS_GPLL0_DIV_CLK 184 +#define GCC_GPU_GPLL0_DIV_CLK 185 +#define GCC_GPU_GPLL0_CLK 186 #define PCIE_0_GDSC 0 #define UFS_GDSC 1 diff --git a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h b/include/dt-bindings/clock/qcom,gcc-sc8280xp.h index 721105ea4fad..845491591784 100644 --- a/include/dt-bindings/clock/qcom,gcc-sc8280xp.h +++ b/include/dt-bindings/clock/qcom,gcc-sc8280xp.h @@ -494,5 +494,15 @@ #define USB30_SEC_GDSC 11 #define EMAC_0_GDSC 12 #define EMAC_1_GDSC 13 +#define USB4_1_GDSC 14 +#define USB4_GDSC 15 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 16 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 17 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 18 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 19 +#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 20 +#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 21 +#define HLOS1_VOTE_TURING_MMU_TBU2_GDSC 22 +#define HLOS1_VOTE_TURING_MMU_TBU3_GDSC 23 #endif diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index b32a7aa65349..08fd3a37acaa 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -214,4 +214,6 @@ #define GCC_CRYPTO_CLK 205 #define GCC_CRYPTO_AXI_CLK 206 #define GCC_CRYPTO_AHB_CLK 207 +#define GCC_USB0_PIPE_CLK 208 +#define GCC_USB0_SLEEP_CLK 209 #endif diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h index 06257bfd9ac1..467ccab3bfaa 100644 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h @@ -1,11 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* * Copyright 2022 Emil Renner Berthing <kernel@esmil.dk> + * Copyright 2022 StarFive Technology Co., Ltd. */ #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ +/* PLL clocks */ +#define JH7110_PLLCLK_PLL0_OUT 0 +#define JH7110_PLLCLK_PLL1_OUT 1 +#define JH7110_PLLCLK_PLL2_OUT 2 +#define JH7110_PLLCLK_END 3 + /* SYSCRG clocks */ #define JH7110_SYSCLK_CPU_ROOT 0 #define JH7110_SYSCLK_CPU_CORE 1 @@ -218,4 +225,77 @@ #define JH7110_AONCLK_END 14 +/* STGCRG clocks */ +#define JH7110_STGCLK_HIFI4_CLK_CORE 0 +#define JH7110_STGCLK_USB0_APB 1 +#define JH7110_STGCLK_USB0_UTMI_APB 2 +#define JH7110_STGCLK_USB0_AXI 3 +#define JH7110_STGCLK_USB0_LPM 4 +#define JH7110_STGCLK_USB0_STB 5 +#define JH7110_STGCLK_USB0_APP_125 6 +#define JH7110_STGCLK_USB0_REFCLK 7 +#define JH7110_STGCLK_PCIE0_AXI_MST0 8 +#define JH7110_STGCLK_PCIE0_APB 9 +#define JH7110_STGCLK_PCIE0_TL 10 +#define JH7110_STGCLK_PCIE1_AXI_MST0 11 +#define JH7110_STGCLK_PCIE1_APB 12 +#define JH7110_STGCLK_PCIE1_TL 13 +#define JH7110_STGCLK_PCIE_SLV_MAIN 14 +#define JH7110_STGCLK_SEC_AHB 15 +#define JH7110_STGCLK_SEC_MISC_AHB 16 +#define JH7110_STGCLK_GRP0_MAIN 17 +#define JH7110_STGCLK_GRP0_BUS 18 +#define JH7110_STGCLK_GRP0_STG 19 +#define JH7110_STGCLK_GRP1_MAIN 20 +#define JH7110_STGCLK_GRP1_BUS 21 +#define JH7110_STGCLK_GRP1_STG 22 +#define JH7110_STGCLK_GRP1_HIFI 23 +#define JH7110_STGCLK_E2_RTC 24 +#define JH7110_STGCLK_E2_CORE 25 +#define JH7110_STGCLK_E2_DBG 26 +#define JH7110_STGCLK_DMA1P_AXI 27 +#define JH7110_STGCLK_DMA1P_AHB 28 + +#define JH7110_STGCLK_END 29 + +/* ISPCRG clocks */ +#define JH7110_ISPCLK_DOM4_APB_FUNC 0 +#define JH7110_ISPCLK_MIPI_RX0_PXL 1 +#define JH7110_ISPCLK_DVP_INV 2 +#define JH7110_ISPCLK_M31DPHY_CFG_IN 3 +#define JH7110_ISPCLK_M31DPHY_REF_IN 4 +#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5 +#define JH7110_ISPCLK_VIN_APB 6 +#define JH7110_ISPCLK_VIN_SYS 7 +#define JH7110_ISPCLK_VIN_PIXEL_IF0 8 +#define JH7110_ISPCLK_VIN_PIXEL_IF1 9 +#define JH7110_ISPCLK_VIN_PIXEL_IF2 10 +#define JH7110_ISPCLK_VIN_PIXEL_IF3 11 +#define JH7110_ISPCLK_VIN_P_AXI_WR 12 +#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13 + +#define JH7110_ISPCLK_END 14 + +/* VOUTCRG clocks */ +#define JH7110_VOUTCLK_APB 0 +#define JH7110_VOUTCLK_DC8200_PIX 1 +#define JH7110_VOUTCLK_DSI_SYS 2 +#define JH7110_VOUTCLK_TX_ESC 3 +#define JH7110_VOUTCLK_DC8200_AXI 4 +#define JH7110_VOUTCLK_DC8200_CORE 5 +#define JH7110_VOUTCLK_DC8200_AHB 6 +#define JH7110_VOUTCLK_DC8200_PIX0 7 +#define JH7110_VOUTCLK_DC8200_PIX1 8 +#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9 +#define JH7110_VOUTCLK_DSITX_APB 10 +#define JH7110_VOUTCLK_DSITX_SYS 11 +#define JH7110_VOUTCLK_DSITX_DPI 12 +#define JH7110_VOUTCLK_DSITX_TXESC 13 +#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14 +#define JH7110_VOUTCLK_HDMI_TX_MCLK 15 +#define JH7110_VOUTCLK_HDMI_TX_BCLK 16 +#define JH7110_VOUTCLK_HDMI_TX_SYS 17 + +#define JH7110_VOUTCLK_END 18 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */ diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h index 669ca2d6abce..b0b1091aad6d 100644 --- a/include/dt-bindings/mux/ti-serdes.h +++ b/include/dt-bindings/mux/ti-serdes.h @@ -6,6 +6,14 @@ #ifndef _DT_BINDINGS_MUX_TI_SERDES #define _DT_BINDINGS_MUX_TI_SERDES +/* + * These bindings are deprecated, because they do not match the actual + * concept of bindings but rather contain pure constants values used only + * in DTS board files. + * Instead include the header in the DTS source directory. + */ +#warning "These bindings are deprecated. Instead, use the header in the DTS source directory." + /* J721E */ #define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 diff --git a/include/dt-bindings/regulator/st,stm32mp13-regulator.h b/include/dt-bindings/regulator/st,stm32mp13-regulator.h new file mode 100644 index 000000000000..b3a974dfc585 --- /dev/null +++ b/include/dt-bindings/regulator/st,stm32mp13-regulator.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H +#define __DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H + +/* SCMI voltage domains identifiers */ + +/* SOC Internal regulators */ +#define VOLTD_SCMI_REG11 0 +#define VOLTD_SCMI_REG18 1 +#define VOLTD_SCMI_USB33 2 +#define VOLTD_SCMI_SDMMC1_IO 3 +#define VOLTD_SCMI_SDMMC2_IO 4 +#define VOLTD_SCMI_VREFBUF 5 + +/* STPMIC1 regulators */ +#define VOLTD_SCMI_STPMIC1_BUCK1 6 +#define VOLTD_SCMI_STPMIC1_BUCK2 7 +#define VOLTD_SCMI_STPMIC1_BUCK3 8 +#define VOLTD_SCMI_STPMIC1_BUCK4 9 +#define VOLTD_SCMI_STPMIC1_LDO1 10 +#define VOLTD_SCMI_STPMIC1_LDO2 11 +#define VOLTD_SCMI_STPMIC1_LDO3 12 +#define VOLTD_SCMI_STPMIC1_LDO4 13 +#define VOLTD_SCMI_STPMIC1_LDO5 14 +#define VOLTD_SCMI_STPMIC1_LDO6 15 +#define VOLTD_SCMI_STPMIC1_VREFDDR 16 +#define VOLTD_SCMI_STPMIC1_BOOST 17 +#define VOLTD_SCMI_STPMIC1_PWR_SW1 18 +#define VOLTD_SCMI_STPMIC1_PWR_SW2 19 + +/* External regulators */ +#define VOLTD_SCMI_REGU0 20 +#define VOLTD_SCMI_REGU1 21 +#define VOLTD_SCMI_REGU2 22 +#define VOLTD_SCMI_REGU3 23 +#define VOLTD_SCMI_REGU4 24 + +#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP13_REGULATOR_H */ diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bindings/reset/altr,rst-mgr-s10.h index 70ea3a09dbe1..04c4d0c6fd34 100644 --- a/include/dt-bindings/reset/altr,rst-mgr-s10.h +++ b/include/dt-bindings/reset/altr,rst-mgr-s10.h @@ -63,12 +63,15 @@ #define I2C2_RESET 74 #define I2C3_RESET 75 #define I2C4_RESET 76 -/* 77-79 is empty */ +#define I3C0_RESET 77 +#define I3C1_RESET 78 +/* 79 is empty */ #define UART0_RESET 80 #define UART1_RESET 81 /* 82-87 is empty */ #define GPIO0_RESET 88 #define GPIO1_RESET 89 +#define WATCHDOG4_RESET 90 /* BRGMODRST */ #define SOC2FPGA_RESET 96 diff --git a/include/dt-bindings/reset/qcom,gcc-ipq5018.h b/include/dt-bindings/reset/qcom,gcc-ipq5018.h new file mode 100644 index 000000000000..8f03c92fc23b --- /dev/null +++ b/include/dt-bindings/reset/qcom,gcc-ipq5018.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_GCC_5018_H +#define _DT_BINDINGS_RESET_IPQ_GCC_5018_H + +#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 0 +#define GCC_BLSP1_BCR 1 +#define GCC_BLSP1_QUP1_BCR 2 +#define GCC_BLSP1_QUP2_BCR 3 +#define GCC_BLSP1_QUP3_BCR 4 +#define GCC_BLSP1_UART1_BCR 5 +#define GCC_BLSP1_UART2_BCR 6 +#define GCC_BOOT_ROM_BCR 7 +#define GCC_BTSS_BCR 8 +#define GCC_CMN_BLK_BCR 9 +#define GCC_CMN_LDO_BCR 10 +#define GCC_CE_BCR 11 +#define GCC_CRYPTO_BCR 12 +#define GCC_DCC_BCR 13 +#define GCC_DCD_BCR 14 +#define GCC_DDRSS_BCR 15 +#define GCC_EDPD_BCR 16 +#define GCC_GEPHY_BCR 17 +#define GCC_GEPHY_MDC_SW_ARES 18 +#define GCC_GEPHY_DSP_HW_ARES 19 +#define GCC_GEPHY_RX_ARES 20 +#define GCC_GEPHY_TX_ARES 21 +#define GCC_GMAC0_BCR 22 +#define GCC_GMAC0_CFG_ARES 23 +#define GCC_GMAC0_SYS_ARES 24 +#define GCC_GMAC1_BCR 25 +#define GCC_GMAC1_CFG_ARES 26 +#define GCC_GMAC1_SYS_ARES 27 +#define GCC_IMEM_BCR 28 +#define GCC_LPASS_BCR 29 +#define GCC_MDIO0_BCR 30 +#define GCC_MDIO1_BCR 31 +#define GCC_MPM_BCR 32 +#define GCC_PCIE0_BCR 33 +#define GCC_PCIE0_LINK_DOWN_BCR 34 +#define GCC_PCIE0_PHY_BCR 35 +#define GCC_PCIE0PHY_PHY_BCR 36 +#define GCC_PCIE0_PIPE_ARES 37 +#define GCC_PCIE0_SLEEP_ARES 38 +#define GCC_PCIE0_CORE_STICKY_ARES 39 +#define GCC_PCIE0_AXI_MASTER_ARES 40 +#define GCC_PCIE0_AXI_SLAVE_ARES 41 +#define GCC_PCIE0_AHB_ARES 42 +#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 43 +#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 44 +#define GCC_PCIE1_BCR 45 +#define GCC_PCIE1_LINK_DOWN_BCR 46 +#define GCC_PCIE1_PHY_BCR 47 +#define GCC_PCIE1PHY_PHY_BCR 48 +#define GCC_PCIE1_PIPE_ARES 49 +#define GCC_PCIE1_SLEEP_ARES 50 +#define GCC_PCIE1_CORE_STICKY_ARES 51 +#define GCC_PCIE1_AXI_MASTER_ARES 52 +#define GCC_PCIE1_AXI_SLAVE_ARES 53 +#define GCC_PCIE1_AHB_ARES 54 +#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 55 +#define GCC_PCIE1_AXI_SLAVE_STICKY_ARES 56 +#define GCC_PCNOC_BCR 57 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 +#define GCC_PCNOC_BUS_TIMEOUT10_BCR 68 +#define GCC_PCNOC_BUS_TIMEOUT11_BCR 69 +#define GCC_PRNG_BCR 70 +#define GCC_Q6SS_DBG_ARES 71 +#define GCC_Q6_AHB_S_ARES 72 +#define GCC_Q6_AHB_ARES 73 +#define GCC_Q6_AXIM2_ARES 74 +#define GCC_Q6_AXIM_ARES 75 +#define GCC_Q6_AXIS_ARES 76 +#define GCC_QDSS_BCR 77 +#define GCC_QPIC_BCR 78 +#define GCC_QUSB2_0_PHY_BCR 79 +#define GCC_SDCC1_BCR 80 +#define GCC_SEC_CTRL_BCR 81 +#define GCC_SPDM_BCR 82 +#define GCC_SYSTEM_NOC_BCR 83 +#define GCC_TCSR_BCR 84 +#define GCC_TLMM_BCR 85 +#define GCC_UBI0_AXI_ARES 86 +#define GCC_UBI0_AHB_ARES 87 +#define GCC_UBI0_NC_AXI_ARES 88 +#define GCC_UBI0_DBG_ARES 89 +#define GCC_UBI0_UTCM_ARES 90 +#define GCC_UBI0_CORE_ARES 91 +#define GCC_UBI32_BCR 92 +#define GCC_UNIPHY_BCR 93 +#define GCC_UNIPHY_AHB_ARES 94 +#define GCC_UNIPHY_SYS_ARES 95 +#define GCC_UNIPHY_RX_ARES 96 +#define GCC_UNIPHY_TX_ARES 97 +#define GCC_USB0_BCR 98 +#define GCC_USB0_PHY_BCR 99 +#define GCC_WCSS_BCR 100 +#define GCC_WCSS_DBG_ARES 101 +#define GCC_WCSS_ECAHB_ARES 102 +#define GCC_WCSS_ACMT_ARES 103 +#define GCC_WCSS_DBG_BDG_ARES 104 +#define GCC_WCSS_AHB_S_ARES 105 +#define GCC_WCSS_AXI_M_ARES 106 +#define GCC_WCSS_AXI_S_ARES 107 +#define GCC_WCSS_Q6_BCR 108 +#define GCC_WCSSAON_RESET 109 +#define GCC_UNIPHY_SOFT_RESET 110 +#define GCC_GEPHY_MISC_ARES 111 + +#endif diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h index d78e38690ceb..eaf4a0d84f6a 100644 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> + * Copyright (C) 2022 StarFive Technology Co., Ltd. */ #ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ @@ -151,4 +152,63 @@ #define JH7110_AONRST_END 8 +/* STGCRG resets */ +#define JH7110_STGRST_SYSCON 0 +#define JH7110_STGRST_HIFI4_CORE 1 +#define JH7110_STGRST_HIFI4_AXI 2 +#define JH7110_STGRST_SEC_AHB 3 +#define JH7110_STGRST_E24_CORE 4 +#define JH7110_STGRST_DMA1P_AXI 5 +#define JH7110_STGRST_DMA1P_AHB 6 +#define JH7110_STGRST_USB0_AXI 7 +#define JH7110_STGRST_USB0_APB 8 +#define JH7110_STGRST_USB0_UTMI_APB 9 +#define JH7110_STGRST_USB0_PWRUP 10 +#define JH7110_STGRST_PCIE0_AXI_MST0 11 +#define JH7110_STGRST_PCIE0_AXI_SLV0 12 +#define JH7110_STGRST_PCIE0_AXI_SLV 13 +#define JH7110_STGRST_PCIE0_BRG 14 +#define JH7110_STGRST_PCIE0_CORE 15 +#define JH7110_STGRST_PCIE0_APB 16 +#define JH7110_STGRST_PCIE1_AXI_MST0 17 +#define JH7110_STGRST_PCIE1_AXI_SLV0 18 +#define JH7110_STGRST_PCIE1_AXI_SLV 19 +#define JH7110_STGRST_PCIE1_BRG 20 +#define JH7110_STGRST_PCIE1_CORE 21 +#define JH7110_STGRST_PCIE1_APB 22 + +#define JH7110_STGRST_END 23 + +/* ISPCRG resets */ +#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P 0 +#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C 1 +#define JH7110_ISPRST_M31DPHY_HW 2 +#define JH7110_ISPRST_M31DPHY_B09_AON 3 +#define JH7110_ISPRST_VIN_APB 4 +#define JH7110_ISPRST_VIN_PIXEL_IF0 5 +#define JH7110_ISPRST_VIN_PIXEL_IF1 6 +#define JH7110_ISPRST_VIN_PIXEL_IF2 7 +#define JH7110_ISPRST_VIN_PIXEL_IF3 8 +#define JH7110_ISPRST_VIN_SYS 9 +#define JH7110_ISPRST_VIN_P_AXI_RD 10 +#define JH7110_ISPRST_VIN_P_AXI_WR 11 + +#define JH7110_ISPRST_END 12 + +/* VOUTCRG resets */ +#define JH7110_VOUTRST_DC8200_AXI 0 +#define JH7110_VOUTRST_DC8200_AHB 1 +#define JH7110_VOUTRST_DC8200_CORE 2 +#define JH7110_VOUTRST_DSITX_DPI 3 +#define JH7110_VOUTRST_DSITX_APB 4 +#define JH7110_VOUTRST_DSITX_RXESC 5 +#define JH7110_VOUTRST_DSITX_SYS 6 +#define JH7110_VOUTRST_DSITX_TXBYTEHS 7 +#define JH7110_VOUTRST_DSITX_TXESC 8 +#define JH7110_VOUTRST_HDMI_TX_HDMI 9 +#define JH7110_VOUTRST_MIPITX_DPHY_SYS 10 +#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS 11 + +#define JH7110_VOUTRST_END 12 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */ |