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authorConor Dooley <conor.dooley@microchip.com>2022-09-09 13:31:16 +0100
committerConor Dooley <conor.dooley@microchip.com>2023-03-07 15:09:28 +0000
commit0e9b70c1e3623fa110fb6be553e644524228ef60 (patch)
tree66c756b45c3c9a113e25671f91194c29bc3d1333
parentfe15c26ee26efa11741a7b632e9f23b01aca4cc6 (diff)
riscv: dts: microchip: add mpfs specific macb reset support
The macb on PolarFire SoC has reset support which the generic compatible does not use. Add the newly introduced MPFS specific compatible as the primary compatible to avail of this support & wire up the reset to the clock controllers devicetree entry. Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
-rw-r--r--arch/riscv/boot/dts/microchip/mpfs.dtsi7
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index 0a9bb84af438..23b7b05ee291 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -234,6 +234,7 @@
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
clocks = <&refclk>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
ccc_se: clock-controller@38010000 {
@@ -415,7 +416,7 @@
};
mac0: ethernet@20110000 {
- compatible = "cdns,macb";
+ compatible = "microchip,mpfs-macb", "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
@@ -424,11 +425,12 @@
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
+ resets = <&clkcfg CLK_MAC0>;
status = "disabled";
};
mac1: ethernet@20112000 {
- compatible = "cdns,macb";
+ compatible = "microchip,mpfs-macb", "cdns,macb";
reg = <0x0 0x20112000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
@@ -437,6 +439,7 @@
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
+ resets = <&clkcfg CLK_MAC1>;
status = "disabled";
};