diff options
| author | Tao Zhou <tao.zhou1@amd.com> | 2022-09-21 16:43:47 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-09-29 09:42:21 -0400 |
| commit | 1014bd1cb32552b732fd0f6ff4e68f32188d59e7 (patch) | |
| tree | 3876720a8c47c7ad08bf5c5343b12100b05a8c28 | |
| parent | c19a5f325a7fb5b353976d66d6a92b35c0322138 (diff) | |
drm/amdgpu: support to convert dedicated umc mca address
Update umc error address query interface, the mca address can be read
from register or input from parameter.
TODO: define a common address conversion function to simplify the code.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 45 |
1 files changed, 27 insertions, 18 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c index 7d92984ad8d0..2cc961534542 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c @@ -460,32 +460,39 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev, uint64_t mc_umc_status, mc_umc_addrt0; uint64_t err_addr, soc_pa, retired_page, column; - mc_umc_status_addr = - SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); - mc_umc_addrt0 = - SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); + if (mca_addr == UMC_INVALID_ADDR) { + mc_umc_status_addr = + SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0); + mc_umc_addrt0 = + SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_ADDRT0); - mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); + mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); - if (mc_umc_status == 0) - return; + if (mc_umc_status == 0) + return; - if (!err_data->err_addr) { - /* clear umc status */ - WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); - return; + if (!err_data->err_addr) { + /* clear umc status */ + WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); + return; + } } channel_index = adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst]; /* calculate error address if ue/ce error is detected */ - if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && + if ((REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 && (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 || - REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) { - - err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4); - err_addr = REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); + REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)) || + mca_addr != UMC_INVALID_ADDR) { + if (mca_addr == UMC_INVALID_ADDR) { + err_addr = RREG64_PCIE((mc_umc_addrt0 + umc_reg_offset) * 4); + err_addr = + REG_GET_FIELD(err_addr, MCA_UMC_UMC0_MCUMC_ADDRT0, ErrorAddr); + } else { + err_addr = mca_addr; + } /* translate umc channel address to soc pa, 3 parts are included */ soc_pa = ADDR_OF_8KB_BLOCK(err_addr) | @@ -500,7 +507,8 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev, /* we only save ue error information currently, ce is skipped */ if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) - == 1) { + == 1 || + mca_addr != UMC_INVALID_ADDR) { /* loop for all possibilities of [C4 C3 C2] */ for (column = 0; column < UMC_V6_7_NA_MAP_PA_NUM; column++) { retired_page = soc_pa | (column << UMC_V6_7_PA_C2_BIT); @@ -518,7 +526,8 @@ static void umc_v6_7_query_error_address(struct amdgpu_device *adev, } /* clear umc status */ - WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); + if (mca_addr == UMC_INVALID_ADDR) + WREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4, 0x0ULL); } static void umc_v6_7_query_ras_error_address(struct amdgpu_device *adev, |