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authorJacopo Mondi <jacopo+renesas@jmondi.org>2017-10-09 10:48:35 +0200
committerSimon Horman <horms+renesas@verge.net.au>2017-10-12 13:51:25 +0200
commit1126e108a3ad8ae92a0532259e3da4b14072355f (patch)
tree62f8c8c0ae08d8ebc57129becb0e168747b576cc
parent349adfbf27269bad4fa6915e77c97a06487266a5 (diff)
ARM: dts: gr-peach: Enable ostm0 and ostm1 timers
Enable ostm0 and ostm1 timers to be used as clock source and clockevent source. The timers provides greater accuracy than the already enabled mtu2 one. With these enabled: clocksource: ostm: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 57352151442 ns sched_clock: 32 bits at 33MHz, resolution 30ns, wraps every 64440619504ns ostm: used for clocksource ostm: used for clock events Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Suggested-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm/boot/dts/r7s72100-gr-peach.dts8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts
index eca14e3801ec..779f724b4531 100644
--- a/arch/arm/boot/dts/r7s72100-gr-peach.dts
+++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts
@@ -104,6 +104,14 @@
status = "okay";
};
+&ostm0 {
+ status = "okay";
+};
+
+&ostm1 {
+ status = "okay";
+};
+
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;