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| author | Amelie Delaunay <amelie.delaunay@foss.st.com> | 2021-02-08 12:46:58 +0100 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2021-03-15 15:25:29 +0530 |
| commit | 12810cb9c2be12b0da64d295711fa932e9836ec9 (patch) | |
| tree | f49036cc790172f467c0d08cc9c111eb1f5538a6 | |
| parent | eb445a15fa6910dd25b2fc1217ac39f47104b7d6 (diff) | |
dt-bindings: phy: phy-stm32-usbphyc: add #clock-cells property
usbphyc provides a unique clock called ck_usbo_48m.
STM32 USB OTG needs a 48Mhz clock (utmifs_clk48) for Full-Speed operation.
ck_usbo_48m is a possible parent clock for USB OTG 48Mhz clock.
ck_usbo_48m is available as soon as the PLL is enabled.
Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210208114659.15269-2-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml index 46df6786727a..018cc1246ee1 100644 --- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml @@ -51,6 +51,10 @@ properties: vdda1v8-supply: description: regulator providing 1V8 power supply to the PLL block + '#clock-cells': + description: number of clock cells for ck_usbo_48m consumer + const: 0 + #Required child nodes: patternProperties: @@ -120,6 +124,7 @@ examples: vdda1v8-supply = <®18>; #address-cells = <1>; #size-cells = <0>; + #clock-cells = <0>; usbphyc_port0: usb-phy@0 { reg = <0>; |