diff options
| author | Conor Dooley <conor.dooley@microchip.com> | 2023-09-16 10:14:00 +0100 |
|---|---|---|
| committer | Jernej Skrabec <jernej.skrabec@gmail.com> | 2023-09-24 21:53:55 +0200 |
| commit | 267860b10c67dd396c73a9e6e8103670d78a4c01 (patch) | |
| tree | f34293d63cc27ba6e673bda18c42c25282406c45 | |
| parent | 062b9b661f42e76eb6e4b8328f1121cba61a447e (diff) | |
riscv: dts: allwinner: remove address-cells from intc node
A recent submission [1] from Rob has added additionalProperties: false
to the interrupt-controller child node of RISC-V cpus, highlighting that
the D1 DT has been incorrectly using #address-cells since its
introduction. It has no child nodes, so #address-cells is not needed.
Remove it.
Fixes: 077e5f4f5528 ("riscv: dts: allwinner: Add the D1/D1s SoC devicetree")
Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/ [1]
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230916-saddling-dastardly-8cf6d1263c24@spud
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
| -rw-r--r-- | arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 450387265469..0917b18656a2 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -30,7 +30,6 @@ cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; interrupt-controller; - #address-cells = <0>; #interrupt-cells = <1>; }; }; |