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authorShawn Lin <shawn.lin@rock-chips.com>2016-11-14 15:20:57 -0600
committerBjorn Helgaas <bhelgaas@google.com>2016-11-14 15:20:57 -0600
commit2fa39159b6a9931d6fd82ecbe65357e0ad77e1a4 (patch)
treea98db41563f1d3689eef856dced74fee8ed72571
parent1001354ca34179f3db924eb66672442a173147dc (diff)
Documentation/devicetree: Add PCIe max-link-speed property
Some of the host drivers have the requirement of knowing whether the EP would never train at some link speed at all. For instance, on some boards, the link won't train at 5 GT/s but the host driver still sacrifice some cycles to wait for the result of training at 5 GT/s as the host could actually support 5 GT/s. So we could parse this new property and make the host drivers be aware of these cases. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/pci/pci.txt6
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
index 08dcfad09f8d..50f9e2ca5b13 100644
--- a/Documentation/devicetree/bindings/pci/pci.txt
+++ b/Documentation/devicetree/bindings/pci/pci.txt
@@ -18,3 +18,9 @@ driver implementation may support the following properties:
host bridges in the system, otherwise potentially conflicting domain numbers
may be assigned to root buses behind different host bridges. The domain
number for each host bridge in the system must be unique.
+- max-link-speed:
+ If present this property specifies PCI gen for link capability. Host
+ drivers could add this as a strategy to avoid unnecessary operation for
+ unsupported link speed, for instance, trying to do training for
+ unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'
+ for gen2, and '1' for gen1. Any other values are invalid.