diff options
| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2022-12-28 20:52:24 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-01-10 22:43:43 -0600 |
| commit | 3727ce670b298003375c9a00d388ef02cd08ba08 (patch) | |
| tree | 126ce7a788ba58e41cf8242f8fd2f898c8b8d96b | |
| parent | 5fe4abe32e328be785768b916fb50a42c85a1947 (diff) | |
dt-bindings: clock: qcom,gcc-sdx65: drop core_bi_pll_test_se
The test clock apparently it's not used by anyone upstream. Remove it.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228185237.3111988-4-dmitry.baryshkov@linaro.org
| -rw-r--r-- | Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml index ba62baab916c..523e18d7f150 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx65.yaml @@ -26,8 +26,6 @@ properties: - description: Sleep clock source - description: PCIE Pipe clock source - description: USB3 phy wrapper pipe clock source - - description: PLL test clock source (Optional clock) - minItems: 5 clock-names: items: @@ -36,8 +34,6 @@ properties: - const: sleep_clk - const: pcie_pipe_clk - const: usb3_phy_wrapper_gcc_usb30_pipe_clk - - const: core_bi_pll_test_se # Optional clock - minItems: 5 required: - compatible @@ -56,9 +52,9 @@ examples: compatible = "qcom,gcc-sdx65"; reg = <0x100000 0x1f7400>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&pll_test_clk>; + <&pcie_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", - "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk", "core_bi_pll_test_se"; + "pcie_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; |