diff options
| author | Tao Zhou <tao.zhou1@amd.com> | 2019-07-29 14:28:35 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-02 10:30:38 -0500 |
| commit | 3aacf4ea1102f24c8dc63eb6f3d734cbc8bad86e (patch) | |
| tree | b1538af25df750fa0c574339da69ba40f5a8f978 | |
| parent | 33b97cf896d4ec6c05e8febdf73ee30c508a0481 (diff) | |
drm/amdgpu: initialize new parameters and functions for amdgpu_umc structure
add initialization for new members of amdgpu_umc structure
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/umc_v6_1.c | 10 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/umc_v6_1.h | 3 |
3 files changed, 17 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 7c4d9d99c6d1..24387026fdee 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -635,8 +635,11 @@ static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev) { switch (adev->asic_type) { case CHIP_VEGA20: - adev->umc.max_ras_err_cnt_per_query = - UMC_V6_1_UMC_INSTANCE_NUM * UMC_V6_1_CHANNEL_INSTANCE_NUM; + adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM; + adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM; + adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM; + adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET; + adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0]; adev->umc.funcs = &umc_v6_1_funcs; break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c index 035e4fea472c..9ba015d7eb57 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.c @@ -41,7 +41,7 @@ /* offset in 256B block */ #define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL) -static uint32_t +const uint32_t umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM] = { {2, 18, 11, 27}, {4, 20, 13, 29}, {1, 17, 8, 24}, {7, 23, 14, 30}, @@ -235,7 +235,15 @@ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev, umc_v6_1_disable_umc_index_mode(adev); } +static void umc_v6_1_ras_init(struct amdgpu_device *adev) +{ + +} + const struct amdgpu_umc_funcs umc_v6_1_funcs = { + .ras_init = umc_v6_1_ras_init, .query_ras_error_count = umc_v6_1_query_ras_error_count, .query_ras_error_address = umc_v6_1_query_ras_error_address, + .enable_umc_index_mode = umc_v6_1_enable_umc_index_mode, + .disable_umc_index_mode = umc_v6_1_disable_umc_index_mode, }; diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h index bddaf14a77f9..ad4598c0e495 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_1.h @@ -24,6 +24,7 @@ #define __UMC_V6_1_H__ #include "soc15_common.h" +#include "amdgpu.h" /* HBM Memory Channel Width */ #define UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH 128 @@ -37,5 +38,7 @@ #define UMC_V6_1_PER_CHANNEL_OFFSET 0x800 extern const struct amdgpu_umc_funcs umc_v6_1_funcs; +extern const uint32_t + umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM]; #endif |