diff options
| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2023-03-01 10:55:14 +0100 |
|---|---|---|
| committer | Matthias Brugger <matthias.bgg@gmail.com> | 2023-03-30 09:47:08 +0200 |
| commit | 3daabcb2392678c1d5997404b29c13bc27dac306 (patch) | |
| tree | 8a7d620238b4593dc1c2fbdd68644089d4b0be5f | |
| parent | 6fe90cc51988f929d96a2b69417b442413145732 (diff) | |
arm64: dts: mediatek: mt8192-asurada: Assign sram supply to MFG1 pd
Add a phandle to the MT8192_POWER_DOMAIN_MFG1 power domain and
assign the GPU VSRAM supply to this in mt8192-asurada: this allows to
keep the sram powered up while the GPU is used.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230301095523.428461-11-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 4 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index ec013d5ef157..df477eb89f21 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -384,6 +384,10 @@ domain-supply = <&mt6315_7_vbuck1>; }; +&mfg1 { + domain-supply = <&mt6359_vsram_others_ldo_reg>; +}; + &mipi_tx0 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index f19d4a8ef3f6..5c30caf74026 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -506,7 +506,7 @@ #size-cells = <0>; #power-domain-cells = <1>; - power-domain@MT8192_POWER_DOMAIN_MFG1 { + mfg1: power-domain@MT8192_POWER_DOMAIN_MFG1 { reg = <MT8192_POWER_DOMAIN_MFG1>; mediatek,infracfg = <&infracfg>; #address-cells = <1>; |