diff options
| author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-07-30 10:21:14 +0200 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2018-07-30 10:21:14 +0200 |
| commit | 45dd7af410b71da511085b806c22caf8ecca87e4 (patch) | |
| tree | c04c335512353c6aa0f35d6420a6de22ae0f6c39 | |
| parent | 8a7b5d0f75f757fa88b0d17c19523161b27b8e80 (diff) | |
| parent | 4ea438da76f4277627347147f6f7004affae07b9 (diff) | |
Merge tag 'usb-for-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next
Felipe writes:
usb: changes for v4.19
Not a big pull request with only 37 non-merge commits, most of which
are touching dwc2 (74% of the changes).
The most important changes are dwc2's support for uframe scheduling
and its endian-agnostic readl/writel wrappers.
From dwc3 side we have a special new glue layer for Synopsys HAPS
which will help Synopsys running FPGA validation using our upstream
driver. We also have the beginnings of dual-role support for Intel
Merrifield platform.
Apart from these, just a series of non-critical changes.
41 files changed, 1506 insertions, 1041 deletions
diff --git a/Documentation/ABI/testing/configfs-usb-gadget-uvc b/Documentation/ABI/testing/configfs-usb-gadget-uvc index 1ba0d0fda9c0..9281e2aa38df 100644 --- a/Documentation/ABI/testing/configfs-usb-gadget-uvc +++ b/Documentation/ABI/testing/configfs-usb-gadget-uvc @@ -263,3 +263,8 @@ Description: Specific streaming header descriptors is connected bmInfo - capabilities of this video streaming interface + +What: /sys/class/udc/udc.name/device/gadget/video4linux/video.name/function_name +Date: May 2018 +KernelVersion: 4.19 +Description: UVC configfs function instance name diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index 7f13ebef06cb..3e4c38b806ac 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -96,6 +96,11 @@ Optional properties: enable periodic ESS TX threshold. - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated. + - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0 + register, undefined length INCR burst type enable and INCRx type. + When just one value, which means INCRX burst mode enabled. When + more than one value, which means undefined length INCR burst type + enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256. - in addition all properties from usb-xhci.txt from the current directory are supported as well @@ -108,4 +113,5 @@ dwc3@4a030000 { reg = <0x4a030000 0xcfff>; interrupts = <0 92 4> usb-phy = <&usb2_phy>, <&usb3,phy>; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; }; diff --git a/MAINTAINERS b/MAINTAINERS index b6f6c22c03f1..a16450acf347 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15007,6 +15007,7 @@ L: linux-usb@vger.kernel.org S: Maintained F: drivers/usb/gadget/function/*uvc* F: drivers/usb/gadget/legacy/webcam.c +F: include/uapi/linux/usb/g_uvc.h USB WIRELESS RNDIS DRIVER (rndis_wlan) M: Jussi Kivilinna <jussi.kivilinna@iki.fi> diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c index 1c36a6a9dd63..55d5ae2a7ec7 100644 --- a/drivers/usb/dwc2/core.c +++ b/drivers/usb/dwc2/core.c @@ -73,17 +73,17 @@ int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg) /* Backup global regs */ gr = &hsotg->gr_backup; - gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); - gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK); - gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); - gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); - gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); - gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); - gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); - gr->pcgcctl1 = dwc2_readl(hsotg->regs + PCGCCTL1); - gr->glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG); - gr->gi2cctl = dwc2_readl(hsotg->regs + GI2CCTL); - gr->pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); + gr->gotgctl = dwc2_readl(hsotg, GOTGCTL); + gr->gintmsk = dwc2_readl(hsotg, GINTMSK); + gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG); + gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG); + gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ); + gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); + gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG); + gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1); + gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG); + gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL); + gr->pcgcctl = dwc2_readl(hsotg, PCGCTL); gr->valid = true; return 0; @@ -111,18 +111,18 @@ int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg) } gr->valid = false; - dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); - dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL); - dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK); - dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); - dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG); - dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ); - dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ); - dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG); - dwc2_writel(gr->pcgcctl1, hsotg->regs + PCGCCTL1); - dwc2_writel(gr->glpmcfg, hsotg->regs + GLPMCFG); - dwc2_writel(gr->pcgcctl, hsotg->regs + PCGCTL); - dwc2_writel(gr->gi2cctl, hsotg->regs + GI2CCTL); + dwc2_writel(hsotg, 0xffffffff, GINTSTS); + dwc2_writel(hsotg, gr->gotgctl, GOTGCTL); + dwc2_writel(hsotg, gr->gintmsk, GINTMSK); + dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); + dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG); + dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ); + dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ); + dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG); + dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1); + dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG); + dwc2_writel(hsotg, gr->pcgcctl, PCGCTL); + dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL); return 0; } @@ -141,17 +141,17 @@ int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, bool restore) if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) return -ENOTSUPP; - pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgcctl = dwc2_readl(hsotg, PCGCTL); pcgcctl &= ~PCGCTL_STOPPCLK; - dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgcctl, PCGCTL); - pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgcctl = dwc2_readl(hsotg, PCGCTL); pcgcctl &= ~PCGCTL_PWRCLMP; - dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgcctl, PCGCTL); - pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgcctl = dwc2_readl(hsotg, PCGCTL); pcgcctl &= ~PCGCTL_RSTPDWNMODULE; - dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgcctl, PCGCTL); udelay(100); if (restore) { @@ -222,21 +222,21 @@ int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg) * Clear any pending interrupts since dwc2 will not be able to * clear them after entering partial_power_down. */ - dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, 0xffffffff, GINTSTS); /* Put the controller in low power state */ - pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgcctl = dwc2_readl(hsotg, PCGCTL); pcgcctl |= PCGCTL_PWRCLMP; - dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgcctl, PCGCTL); ndelay(20); pcgcctl |= PCGCTL_RSTPDWNMODULE; - dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgcctl, PCGCTL); ndelay(20); pcgcctl |= PCGCTL_STOPPCLK; - dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgcctl, PCGCTL); return ret; } @@ -272,39 +272,39 @@ static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode, if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK)) pcgcctl |= BIT(17); } - dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgcctl, PCGCTL); /* Umnask global Interrupt in GAHBCFG and restore it */ - dwc2_writel(gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); + dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG); /* Clear all pending interupts */ - dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, 0xffffffff, GINTSTS); /* Unmask restore done interrupt */ - dwc2_writel(GINTSTS_RESTOREDONE, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK); /* Restore GUSBCFG and HCFG/DCFG */ - dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); + dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); if (is_host) { - dwc2_writel(hr->hcfg, hsotg->regs + HCFG); + dwc2_writel(hsotg, hr->hcfg, HCFG); if (rmode) pcgcctl |= PCGCTL_RESTOREMODE; - dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgcctl, PCGCTL); udelay(10); pcgcctl |= PCGCTL_ESS_REG_RESTORED; - dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgcctl, PCGCTL); udelay(10); } else { - dwc2_writel(dr->dcfg, hsotg->regs + DCFG); + dwc2_writel(hsotg, dr->dcfg, DCFG); if (!rmode) pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE; - dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgcctl, PCGCTL); udelay(10); pcgcctl |= PCGCTL_ESS_REG_RESTORED; - dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgcctl, PCGCTL); udelay(10); } } @@ -322,42 +322,42 @@ void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup, u32 gpwrdn; /* Switch-on voltage to the core */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn &= ~GPWRDN_PWRDNSWTCH; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); /* Reset core */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn &= ~GPWRDN_PWRDNRSTN; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); /* Enable restore from PMU */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn |= GPWRDN_RESTORE; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); /* Disable Power Down Clamp */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn &= ~GPWRDN_PWRDNCLMP; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(50); if (!is_host && rem_wakeup) udelay(70); /* Deassert reset core */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn |= GPWRDN_PWRDNRSTN; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); /* Disable PMU interrupt */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn &= ~GPWRDN_PMUINTSEL; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); /* Set Restore Essential Regs bit in PCGCCTL register */ @@ -431,7 +431,7 @@ static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg) return false; /* Check if core configuration includes the IDDIG filter. */ - ghwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); + ghwcfg4 = dwc2_readl(hsotg, GHWCFG4); if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN)) return false; @@ -439,9 +439,9 @@ static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg) * Check if the IDDIG debounce filter is bypassed. Available * in core version >= 3.10a. */ - gsnpsid = dwc2_readl(hsotg->regs + GSNPSID); + gsnpsid = dwc2_readl(hsotg, GSNPSID); if (gsnpsid >= DWC2_CORE_REV_3_10a) { - u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + u32 gotgctl = dwc2_readl(hsotg, GOTGCTL); if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS) return false; @@ -510,8 +510,8 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait) * reset and account for this delay after the reset. */ if (dwc2_iddig_filter_enabled(hsotg)) { - u32 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); - u32 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + u32 gotgctl = dwc2_readl(hsotg, GOTGCTL); + u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG); if (!(gotgctl & GOTGCTL_CONID_B) || (gusbcfg & GUSBCFG_FORCEHOSTMODE)) { @@ -520,9 +520,9 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait) } /* Core Soft Reset */ - greset = dwc2_readl(hsotg->regs + GRSTCTL); + greset = dwc2_readl(hsotg, GRSTCTL); greset |= GRSTCTL_CSFTRST; - dwc2_writel(greset, hsotg->regs + GRSTCTL); + dwc2_writel(hsotg, greset, GRSTCTL); if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_CSFTRST, 50)) { dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL GRSTCTL_CSFTRST\n", @@ -594,14 +594,14 @@ void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host) if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST)) return; - gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg = dwc2_readl(hsotg, GUSBCFG); set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE; clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE; gusbcfg &= ~clear; gusbcfg |= set; - dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + dwc2_writel(hsotg, gusbcfg, GUSBCFG); dwc2_wait_for_mode(hsotg, host); return; @@ -627,10 +627,10 @@ static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg) dev_dbg(hsotg->dev, "Clearing force mode bits\n"); - gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg = dwc2_readl(hsotg, GUSBCFG); gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; gusbcfg &= ~GUSBCFG_FORCEDEVMODE; - dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + dwc2_writel(hsotg, gusbcfg, GUSBCFG); if (dwc2_iddig_filter_enabled(hsotg)) msleep(100); @@ -670,11 +670,11 @@ void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg) void dwc2_enable_acg(struct dwc2_hsotg *hsotg) { if (hsotg->params.acg_enable) { - u32 pcgcctl1 = dwc2_readl(hsotg->regs + PCGCCTL1); + u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1); dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n"); pcgcctl1 |= PCGCCTL1_GATEEN; - dwc2_writel(pcgcctl1, hsotg->regs + PCGCCTL1); + dwc2_writel(hsotg, pcgcctl1, PCGCCTL1); } } @@ -695,56 +695,57 @@ void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg) dev_dbg(hsotg->dev, "Host Global Registers\n"); addr = hsotg->regs + HCFG; dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, HCFG)); addr = hsotg->regs + HFIR; dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, HFIR)); addr = hsotg->regs + HFNUM; dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, HFNUM)); addr = hsotg->regs + HPTXSTS; dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, HPTXSTS)); addr = hsotg->regs + HAINT; dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, HAINT)); addr = hsotg->regs + HAINTMSK; dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, HAINTMSK)); if (hsotg->params.dma_desc_enable) { addr = hsotg->regs + HFLBADDR; dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, HFLBADDR)); } addr = hsotg->regs + HPRT0; dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, HPRT0)); for (i = 0; i < hsotg->params.host_channels; i++) { dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); addr = hsotg->regs + HCCHAR(i); dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i))); addr = hsotg->regs + HCSPLT(i); dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i))); addr = hsotg->regs + HCINT(i); dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, HCINT(i))); addr = hsotg->regs + HCINTMSK(i); dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i))); addr = hsotg->regs + HCTSIZ(i); dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i))); addr = hsotg->regs + HCDMA(i); dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, HCDMA(i))); if (hsotg->params.dma_desc_enable) { addr = hsotg->regs + HCDMAB(i); dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, + HCDMAB(i))); } } #endif @@ -766,80 +767,80 @@ void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg) dev_dbg(hsotg->dev, "Core Global Registers\n"); addr = hsotg->regs + GOTGCTL; dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GOTGCTL)); addr = hsotg->regs + GOTGINT; dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GOTGINT)); addr = hsotg->regs + GAHBCFG; dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GAHBCFG)); addr = hsotg->regs + GUSBCFG; dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GUSBCFG)); addr = hsotg->regs + GRSTCTL; dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GRSTCTL)); addr = hsotg->regs + GINTSTS; dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GINTSTS)); addr = hsotg->regs + GINTMSK; dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GINTMSK)); addr = hsotg->regs + GRXSTSR; dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GRXSTSR)); addr = hsotg->regs + GRXFSIZ; dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ)); addr = hsotg->regs + GNPTXFSIZ; dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ)); addr = hsotg->regs + GNPTXSTS; dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS)); addr = hsotg->regs + GI2CCTL; dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GI2CCTL)); addr = hsotg->regs + GPVNDCTL; dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL)); addr = hsotg->regs + GGPIO; dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GGPIO)); addr = hsotg->regs + GUID; dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GUID)); addr = hsotg->regs + GSNPSID; dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GSNPSID)); addr = hsotg->regs + GHWCFG1; dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GHWCFG1)); addr = hsotg->regs + GHWCFG2; dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GHWCFG2)); addr = hsotg->regs + GHWCFG3; dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GHWCFG3)); addr = hsotg->regs + GHWCFG4; dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GHWCFG4)); addr = hsotg->regs + GLPMCFG; dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GLPMCFG)); addr = hsotg->regs + GPWRDN; dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GPWRDN)); addr = hsotg->regs + GDFIFOCFG; dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG)); addr = hsotg->regs + HPTXFSIZ; dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ)); addr = hsotg->regs + PCGCTL; dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", - (unsigned long)addr, dwc2_readl(addr)); + (unsigned long)addr, dwc2_readl(hsotg, PCGCTL)); #endif } @@ -862,7 +863,7 @@ void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) greset = GRSTCTL_TXFFLSH; greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; - dwc2_writel(greset, hsotg->regs + GRSTCTL); + dwc2_writel(hsotg, greset, GRSTCTL); if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000)) dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n", @@ -889,7 +890,7 @@ void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) __func__); greset = GRSTCTL_RXFFLSH; - dwc2_writel(greset, hsotg->regs + GRSTCTL); + dwc2_writel(hsotg, greset, GRSTCTL); /* Wait for RxFIFO flush done */ if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000)) @@ -902,7 +903,7 @@ void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg) bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) { - if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff) + if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff) return false; else return true; @@ -916,10 +917,10 @@ bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) */ void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) { - u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG); ahbcfg |= GAHBCFG_GLBL_INTR_EN; - dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); + dwc2_writel(hsotg, ahbcfg, GAHBCFG); } /** @@ -930,16 +931,16 @@ void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) */ void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) { - u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG); ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; - dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); + dwc2_writel(hsotg, ahbcfg, GAHBCFG); } /* Returns the controller's GHWCFG2.OTG_MODE. */ unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg) { - u32 ghwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); + u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2); return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >> GHWCFG2_OP_MODE_SHIFT; @@ -988,7 +989,7 @@ int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, u32 i; for (i = 0; i < timeout; i++) { - if (dwc2_readl(hsotg->regs + offset) & mask) + if (dwc2_readl(hsotg, offset) & mask) return 0; udelay(1); } @@ -1011,7 +1012,7 @@ int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, u32 i; for (i = 0; i < timeout; i++) { - if (!(dwc2_readl(hsotg->regs + offset) & mask)) + if (!(dwc2_readl(hsotg, offset) & mask)) return 0; udelay(1); } diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h index 71b3b08ad516..cc9c93affa14 100644 --- a/drivers/usb/dwc2/core.h +++ b/drivers/usb/dwc2/core.h @@ -65,60 +65,6 @@ DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \ dev_name(hsotg->dev), ##__VA_ARGS__) -#ifdef CONFIG_MIPS -/* - * There are some MIPS machines that can run in either big-endian - * or little-endian mode and that use the dwc2 register without - * a byteswap in both ways. - * Unlike other architectures, MIPS apparently does not require a - * barrier before the __raw_writel() to synchronize with DMA but does - * require the barrier after the __raw_writel() to serialize a set of - * writes. This set of operations was added specifically for MIPS and - * should only be used there. - */ -static inline u32 dwc2_readl(const void __iomem *addr) -{ - u32 value = __raw_readl(addr); - - /* In order to preserve endianness __raw_* operation is used. Therefore - * a barrier is needed to ensure IO access is not re-ordered across - * reads or writes - */ - mb(); - return value; -} - -static inline void dwc2_writel(u32 value, void __iomem *addr) -{ - __raw_writel(value, addr); - - /* - * In order to preserve endianness __raw_* operation is used. Therefore - * a barrier is needed to ensure IO access is not re-ordered across - * reads or writes - */ - mb(); -#ifdef DWC2_LOG_WRITES - pr_info("INFO:: wrote %08x to %p\n", value, addr); -#endif -} -#else -/* Normal architectures just use readl/write */ -static inline u32 dwc2_readl(const void __iomem *addr) -{ - return readl(addr); -} - -static inline void dwc2_writel(u32 value, void __iomem *addr) -{ - writel(value, addr); - -#ifdef DWC2_LOG_WRITES - pr_info("info:: wrote %08x to %p\n", value, addr); -#endif -} -#endif - /* Maximum number of Endpoints/HostChannels */ #define MAX_EPS_CHANNELS 16 @@ -911,6 +857,7 @@ struct dwc2_hregs_backup { * @gr_backup: Backup of global registers during suspend * @dr_backup: Backup of device registers during suspend * @hr_backup: Backup of host registers during suspend + * @needs_byte_swap: Specifies whether the opposite endianness. * * These are for host mode: * @@ -1100,6 +1047,7 @@ struct dwc2_hsotg { struct dentry *debug_root; struct debugfs_regset32 *regset; + bool needs_byte_swap; /* DWC OTG HW Release versions */ #define DWC2_CORE_REV_2_71a 0x4f54271a @@ -1215,6 +1163,55 @@ struct dwc2_hsotg { #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ }; +/* Normal architectures just use readl/write */ +static inline u32 dwc2_readl(struct dwc2_hsotg *hsotg, u32 offset) +{ + u32 val; + + val = readl(hsotg->regs + offset); + if (hsotg->needs_byte_swap) + return swab32(val); + else + return val; +} + +static inline void dwc2_writel(struct dwc2_hsotg *hsotg, u32 value, u32 offset) +{ + if (hsotg->needs_byte_swap) + writel(swab32(value), hsotg->regs + offset); + else + writel(value, hsotg->regs + offset); + +#ifdef DWC2_LOG_WRITES + pr_info("info:: wrote %08x to %p\n", value, hsotg->regs + offset); +#endif +} + +static inline void dwc2_readl_rep(struct dwc2_hsotg *hsotg, u32 offset, + void *buffer, unsigned int count) +{ + if (count) { + u32 *buf = buffer; + + do { + u32 x = dwc2_readl(hsotg, offset); + *buf++ = x; + } while (--count); + } +} + +static inline void dwc2_writel_rep(struct dwc2_hsotg *hsotg, u32 offset, + const void *buffer, unsigned int count) +{ + if (count) { + const u32 *buf = buffer; + + do { + dwc2_writel(hsotg, *buf++, offset); + } while (--count); + } +} + /* Reasons for halting a host channel */ enum dwc2_halt_status { DWC2_HC_XFER_NO_HALT_STATUS, @@ -1320,12 +1317,12 @@ bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg); */ static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) { - return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; + return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) != 0; } static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) { - return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; + return (dwc2_readl(hsotg, GINTSTS) & GINTSTS_CURMODE_HOST) == 0; } /* diff --git a/drivers/usb/dwc2/core_intr.c b/drivers/usb/dwc2/core_intr.c index cc90b58b6b3c..19ae2595f1c3 100644 --- a/drivers/usb/dwc2/core_intr.c +++ b/drivers/usb/dwc2/core_intr.c @@ -81,11 +81,11 @@ static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg) */ static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg) { - u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); + u32 hprt0 = dwc2_readl(hsotg, HPRT0); if (hprt0 & HPRT0_ENACHG) { hprt0 &= ~HPRT0_ENA; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); } } @@ -97,7 +97,7 @@ static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg) static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg) { /* Clear interrupt */ - dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, GINTSTS_MODEMIS, GINTSTS); dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n", dwc2_is_host_mode(hsotg) ? "Host" : "Device"); @@ -115,8 +115,8 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) u32 gotgctl; u32 gintmsk; - gotgint = dwc2_readl(hsotg->regs + GOTGINT); - gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgint = dwc2_readl(hsotg, GOTGINT); + gotgctl = dwc2_readl(hsotg, GOTGCTL); dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint, dwc2_op_state_str(hsotg)); @@ -124,7 +124,7 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) dev_dbg(hsotg->dev, " ++OTG Interrupt: Session End Detected++ (%s)\n", dwc2_op_state_str(hsotg)); - gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl = dwc2_readl(hsotg, GOTGCTL); if (dwc2_is_device_mode(hsotg)) dwc2_hsotg_disconnect(hsotg); @@ -150,24 +150,24 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) hsotg->lx_state = DWC2_L0; } - gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl = dwc2_readl(hsotg, GOTGCTL); gotgctl &= ~GOTGCTL_DEVHNPEN; - dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + dwc2_writel(hsotg, gotgctl, GOTGCTL); } if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) { dev_dbg(hsotg->dev, " ++OTG Interrupt: Session Request Success Status Change++\n"); - gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl = dwc2_readl(hsotg, GOTGCTL); if (gotgctl & GOTGCTL_SESREQSCS) { if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS && hsotg->params.i2c_enable) { hsotg->srp_success = 1; } else { /* Clear Session Request */ - gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl = dwc2_readl(hsotg, GOTGCTL); gotgctl &= ~GOTGCTL_SESREQ; - dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + dwc2_writel(hsotg, gotgctl, GOTGCTL); } } } @@ -177,7 +177,7 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) * Print statements during the HNP interrupt handling * can cause it to fail */ - gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl = dwc2_readl(hsotg, GOTGCTL); /* * WA for 3.00a- HW is not setting cur_mode, even sometimes * this does not help @@ -197,9 +197,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) * interrupt does not get handled and Linux * complains loudly. */ - gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk = dwc2_readl(hsotg, GINTMSK); gintmsk &= ~GINTSTS_SOF; - dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, gintmsk, GINTMSK); /* * Call callback function with spin lock @@ -213,9 +213,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) hsotg->op_state = OTG_STATE_B_HOST; } } else { - gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl = dwc2_readl(hsotg, GOTGCTL); gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN); - dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + dwc2_writel(hsotg, gotgctl, GOTGCTL); dev_dbg(hsotg->dev, "HNP Failed\n"); dev_err(hsotg->dev, "Device Not Connected/Responding\n"); @@ -241,9 +241,9 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) hsotg->op_state = OTG_STATE_A_PERIPHERAL; } else { /* Need to disable SOF interrupt immediately */ - gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk = dwc2_readl(hsotg, GINTMSK); gintmsk &= ~GINTSTS_SOF; - dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, gintmsk, GINTMSK); spin_unlock(&hsotg->lock); dwc2_hcd_start(hsotg); spin_lock(&hsotg->lock); @@ -258,7 +258,7 @@ static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg) dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n"); /* Clear GOTGINT */ - dwc2_writel(gotgint, hsotg->regs + GOTGINT); + dwc2_writel(hsotg, gotgint, GOTGINT); } /** @@ -276,12 +276,12 @@ static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg) u32 gintmsk; /* Clear interrupt */ - dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, GINTSTS_CONIDSTSCHNG, GINTSTS); /* Need to disable SOF interrupt immediately */ - gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk = dwc2_readl(hsotg, GINTMSK); gintmsk &= ~GINTSTS_SOF; - dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, gintmsk, GINTMSK); dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n", dwc2_is_host_mode(hsotg) ? "Host" : "Device"); @@ -314,7 +314,7 @@ static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg) int ret; /* Clear interrupt */ - dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, GINTSTS_SESSREQINT, GINTSTS); dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n", hsotg->lx_state); @@ -351,15 +351,15 @@ static void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg) return; } - glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG); + glpmcfg = dwc2_readl(hsotg, GLPMCFG); if (dwc2_is_device_mode(hsotg)) { dev_dbg(hsotg->dev, "Exit from L1 state\n"); glpmcfg &= ~GLPMCFG_ENBLSLPM; glpmcfg &= ~GLPMCFG_HIRD_THRES_EN; - dwc2_writel(glpmcfg, hsotg->regs + GLPMCFG); + dwc2_writel(hsotg, glpmcfg, GLPMCFG); do { - glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG); + glpmcfg = dwc2_readl(hsotg, GLPMCFG); if (!(glpmcfg & (GLPMCFG_COREL1RES_MASK | GLPMCFG_L1RESUMEOK | GLPMCFG_SLPSTS))) @@ -398,7 +398,7 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) int ret; /* Clear interrupt */ - dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS); dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n"); dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state); @@ -410,13 +410,13 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) if (dwc2_is_device_mode(hsotg)) { dev_dbg(hsotg->dev, "DSTS=0x%0x\n", - dwc2_readl(hsotg->regs + DSTS)); + dwc2_readl(hsotg, DSTS)); if (hsotg->lx_state == DWC2_L2) { - u32 dctl = dwc2_readl(hsotg->regs + DCTL); + u32 dctl = dwc2_readl(hsotg, DCTL); /* Clear Remote Wakeup Signaling */ dctl &= ~DCTL_RMTWKUPSIG; - dwc2_writel(dctl, hsotg->regs + DCTL); + dwc2_writel(hsotg, dctl, DCTL); ret = dwc2_exit_partial_power_down(hsotg, true); if (ret && (ret != -ENOTSUPP)) dev_err(hsotg->dev, "exit power_down failed\n"); @@ -430,11 +430,11 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) return; if (hsotg->lx_state != DWC2_L1) { - u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); + u32 pcgcctl = dwc2_readl(hsotg, PCGCTL); /* Restart the Phy Clock */ pcgcctl &= ~PCGCTL_STOPPCLK; - dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgcctl, PCGCTL); mod_timer(&hsotg->wkp_timer, jiffies + msecs_to_jiffies(71)); } else { @@ -450,7 +450,7 @@ static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) */ static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg) { - dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, GINTSTS_DISCONNINT, GINTSTS); dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n", dwc2_is_host_mode(hsotg) ? "Host" : "Device", @@ -474,7 +474,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) int ret; /* Clear interrupt */ - dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, GINTSTS_USBSUSP, GINTSTS); dev_dbg(hsotg->dev, "USB SUSPEND\n"); @@ -483,7 +483,7 @@ static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg) * Check the Device status register to determine if the Suspend * state is active */ - dsts = dwc2_readl(hsotg->regs + DSTS); + dsts = dwc2_readl(hsotg, DSTS); dev_dbg(hsotg->dev, "%s: DSTS=0x%0x\n", __func__, dsts); dev_dbg(hsotg->dev, "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d HWCFG4.Hibernation=%d\n", @@ -563,9 +563,9 @@ static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg) u32 enslpm; /* Clear interrupt */ - dwc2_writel(GINTSTS_LPMTRANRCVD, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, GINTSTS_LPMTRANRCVD, GINTSTS); - glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG); + glpmcfg = dwc2_readl(hsotg, GLPMCFG); if (!(glpmcfg & GLPMCFG_LPMCAP)) { dev_err(hsotg->dev, "Unexpected LPM interrupt\n"); @@ -588,16 +588,16 @@ static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg) } else { dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n"); - pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgcctl = dwc2_readl(hsotg, PCGCTL); pcgcctl |= PCGCTL_ENBL_SLEEP_GATING; - dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgcctl, PCGCTL); } /** * Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */ udelay(10); - glpmcfg = dwc2_readl(hsotg->regs + GLPMCFG); + glpmcfg = dwc2_readl(hsotg, GLPMCFG); if (glpmcfg & GLPMCFG_SLPSTS) { /* Save the current state */ @@ -627,9 +627,9 @@ static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg) u32 gahbcfg; u32 gintmsk_common = GINTMSK_COMMON; - gintsts = dwc2_readl(hsotg->regs + GINTSTS); - gintmsk = dwc2_readl(hsotg->regs + GINTMSK); - gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + gintsts = dwc2_readl(hsotg, GINTSTS); + gintmsk = dwc2_readl(hsotg, GINTMSK); + gahbcfg = dwc2_readl(hsotg, GAHBCFG); /* If any common interrupts set */ if (gintsts & gintmsk_common) @@ -653,9 +653,9 @@ static void dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg) u32 gpwrdn; int linestate; - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); /* clear all interrupt */ - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT; dev_dbg(hsotg->dev, "%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__, @@ -668,38 +668,38 @@ static void dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg) dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__); /* Switch-on voltage to the core */ - gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH; - dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); udelay(10); /* Reset core */ - gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN; - dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); udelay(10); /* Disable Power Down Clamp */ - gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP; - dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); udelay(10); /* Deassert reset core */ - gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); gpwrdn_tmp |= GPWRDN_PWRDNRSTN; - dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); udelay(10); /* Disable PMU interrupt */ - gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); gpwrdn_tmp &= ~GPWRDN_PMUINTSEL; - dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); /* De-assert Wakeup Logic */ - gpwrdn_tmp = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN); gpwrdn_tmp &= ~GPWRDN_PMUACTV; - dwc2_writel(gpwrdn_tmp, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN); hsotg->hibernated = 0; @@ -780,10 +780,10 @@ irqreturn_t dwc2_handle_common_intr(int irq, void *dev) /* Reading current frame number value in device or host modes. */ if (dwc2_is_device_mode(hsotg)) - hsotg->frame_number = (dwc2_readl(hsotg->regs + DSTS) + hsotg->frame_number = (dwc2_readl(hsotg, DSTS) & DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT; else - hsotg->frame_number = (dwc2_readl(hsotg->regs + HFNUM) + hsotg->frame_number = (dwc2_readl(hsotg, HFNUM) & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT; gintsts = dwc2_read_common_intr(hsotg); diff --git a/drivers/usb/dwc2/debugfs.c b/drivers/usb/dwc2/debugfs.c index d0bdb7997557..22d015b0424f 100644 --- a/drivers/usb/dwc2/debugfs.c +++ b/drivers/usb/dwc2/debugfs.c @@ -69,7 +69,7 @@ static int testmode_show(struct seq_file *s, void *unused) int dctl; spin_lock_irqsave(&hsotg->lock, flags); - dctl = dwc2_readl(hsotg->regs + DCTL); + dctl = dwc2_readl(hsotg, DCTL); dctl &= DCTL_TSTCTL_MASK; dctl >>= DCTL_TSTCTL_SHIFT; spin_unlock_irqrestore(&hsotg->lock, flags); @@ -126,42 +126,41 @@ static const struct file_operations testmode_fops = { static int state_show(struct seq_file *seq, void *v) { struct dwc2_hsotg *hsotg = seq->private; - void __iomem *regs = hsotg->regs; int idx; seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", - dwc2_readl(regs + DCFG), - dwc2_readl(regs + DCTL), - dwc2_readl(regs + DSTS)); + dwc2_readl(hsotg, DCFG), + dwc2_readl(hsotg, DCTL), + dwc2_readl(hsotg, DSTS)); seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", - dwc2_readl(regs + DIEPMSK), dwc2_readl(regs + DOEPMSK)); + dwc2_readl(hsotg, DIEPMSK), dwc2_readl(hsotg, DOEPMSK)); seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", - dwc2_readl(regs + GINTMSK), - dwc2_readl(regs + GINTSTS)); + dwc2_readl(hsotg, GINTMSK), + dwc2_readl(hsotg, GINTSTS)); seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", - dwc2_readl(regs + DAINTMSK), - dwc2_readl(regs + DAINT)); + dwc2_readl(hsotg, DAINTMSK), + dwc2_readl(hsotg, DAINT)); seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", - dwc2_readl(regs + GNPTXSTS), - dwc2_readl(regs + GRXSTSR)); + dwc2_readl(hsotg, GNPTXSTS), + dwc2_readl(hsotg, GRXSTSR)); seq_puts(seq, "\nEndpoint status:\n"); for (idx = 0; idx < hsotg->num_of_eps; idx++) { u32 in, out; - in = dwc2_readl(regs + DIEPCTL(idx)); - out = dwc2_readl(regs + DOEPCTL(idx)); + in = dwc2_readl(hsotg, DIEPCTL(idx)); + out = dwc2_readl(hsotg, DOEPCTL(idx)); seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", idx, in, out); - in = dwc2_readl(regs + DIEPTSIZ(idx)); - out = dwc2_readl(regs + DOEPTSIZ(idx)); + in = dwc2_readl(hsotg, DIEPTSIZ(idx)); + out = dwc2_readl(hsotg, DOEPTSIZ(idx)); seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", in, out); @@ -184,14 +183,13 @@ DEFINE_SHOW_ATTRIBUTE(state); static int fifo_show(struct seq_file *seq, void *v) { struct dwc2_hsotg *hsotg = seq->private; - void __iomem *regs = hsotg->regs; u32 val; int idx; seq_puts(seq, "Non-periodic FIFOs:\n"); - seq_printf(seq, "RXFIFO: Size %d\n", dwc2_readl(regs + GRXFSIZ)); + seq_printf(seq, "RXFIFO: Size %d\n", dwc2_readl(hsotg, GRXFSIZ)); - val = dwc2_readl(regs + GNPTXFSIZ); + val = dwc2_readl(hsotg, GNPTXFSIZ); seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", val >> FIFOSIZE_DEPTH_SHIFT, val & FIFOSIZE_STARTADDR_MASK); @@ -199,7 +197,7 @@ static int fifo_show(struct seq_file *seq, void *v) seq_puts(seq, "\nPeriodic TXFIFOs:\n"); for (idx = 1; idx < hsotg->num_of_eps; idx++) { - val = dwc2_readl(regs + DPTXFSIZN(idx)); + val = dwc2_readl(hsotg, DPTXFSIZN(idx)); seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, val >> FIFOSIZE_DEPTH_SHIFT, @@ -228,7 +226,6 @@ static int ep_show(struct seq_file *seq, void *v) struct dwc2_hsotg_ep *ep = seq->private; struct dwc2_hsotg *hsotg = ep->parent; struct dwc2_hsotg_req *req; - void __iomem *regs = hsotg->regs; int index = ep->index; int show_limit = 15; unsigned long flags; @@ -239,20 +236,20 @@ static int ep_show(struct seq_file *seq, void *v) /* first show the register state */ seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", - dwc2_readl(regs + DIEPCTL(index)), - dwc2_readl(regs + DOEPCTL(index))); + dwc2_readl(hsotg, DIEPCTL(index)), + dwc2_readl(hsotg, DOEPCTL(index))); seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", - dwc2_readl(regs + DIEPDMA(index)), - dwc2_readl(regs + DOEPDMA(index))); + dwc2_readl(hsotg, DIEPDMA(index)), + dwc2_readl(hsotg, DOEPDMA(index))); seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", - dwc2_readl(regs + DIEPINT(index)), - dwc2_readl(regs + DOEPINT(index))); + dwc2_readl(hsotg, DIEPINT(index)), + dwc2_readl(hsotg, DOEPINT(index))); seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", - dwc2_readl(regs + DIEPTSIZ(index)), - dwc2_readl(regs + DOEPTSIZ(index))); + dwc2_readl(hsotg, DIEPTSIZ(index)), + dwc2_readl(hsotg, DOEPTSIZ(index))); seq_puts(seq, "\n"); seq_printf(seq, "mps %d\n", ep->ep.maxpacket); diff --git a/drivers/usb/dwc2/gadget.c b/drivers/usb/dwc2/gadget.c index cefc99ae69b2..220c0f9b89b0 100644 --- a/drivers/usb/dwc2/gadget.c +++ b/drivers/usb/dwc2/gadget.c @@ -47,14 +47,14 @@ static inline struct dwc2_hsotg *to_hsotg(struct usb_gadget *gadget) return container_of(gadget, struct dwc2_hsotg, gadget); } -static inline void dwc2_set_bit(void __iomem *ptr, u32 val) +static inline void dwc2_set_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) { - dwc2_writel(dwc2_readl(ptr) | val, ptr); + dwc2_writel(hsotg, dwc2_readl(hsotg, offset) | val, offset); } -static inline void dwc2_clear_bit(void __iomem *ptr, u32 val) +static inline void dwc2_clear_bit(struct dwc2_hsotg *hsotg, u32 offset, u32 val) { - dwc2_writel(dwc2_readl(ptr) & ~val, ptr); + dwc2_writel(hsotg, dwc2_readl(hsotg, offset) & ~val, offset); } static inline struct dwc2_hsotg_ep *index_to_ep(struct dwc2_hsotg *hsotg, @@ -129,14 +129,14 @@ static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep *hs_ep) */ static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) { - u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); + u32 gsintmsk = dwc2_readl(hsotg, GINTMSK); u32 new_gsintmsk; new_gsintmsk = gsintmsk | ints; if (new_gsintmsk != gsintmsk) { dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); - dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, new_gsintmsk, GINTMSK); } } @@ -147,13 +147,13 @@ static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) */ static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg *hsotg, u32 ints) { - u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); + u32 gsintmsk = dwc2_readl(hsotg, GINTMSK); u32 new_gsintmsk; new_gsintmsk = gsintmsk & ~ints; if (new_gsintmsk != gsintmsk) - dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, new_gsintmsk, GINTMSK); } /** @@ -178,12 +178,12 @@ static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg *hsotg, bit <<= 16; local_irq_save(flags); - daint = dwc2_readl(hsotg->regs + DAINTMSK); + daint = dwc2_readl(hsotg, DAINTMSK); if (en) daint |= bit; else daint &= ~bit; - dwc2_writel(daint, hsotg->regs + DAINTMSK); + dwc2_writel(hsotg, daint, DAINTMSK); local_irq_restore(flags); } @@ -266,10 +266,11 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) hsotg->fifo_map = 0; /* set RX/NPTX FIFO sizes */ - dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ); - dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) | + dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ); + dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size << + FIFOSIZE_STARTADDR_SHIFT) | (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), - hsotg->regs + GNPTXFSIZ); + GNPTXFSIZ); /* * arange all the rest of the TX FIFOs, as some versions of this @@ -295,25 +296,25 @@ static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) "insufficient fifo memory"); addr += txfsz[ep]; - dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); - val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep)); + dwc2_writel(hsotg, val, DPTXFSIZN(ep)); + val = dwc2_readl(hsotg, DPTXFSIZN(ep)); } - dwc2_writel(hsotg->hw_params.total_fifo_size | + dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size | addr << GDFIFOCFG_EPINFOBASE_SHIFT, - hsotg->regs + GDFIFOCFG); + GDFIFOCFG); /* * according to p428 of the design guide, we need to ensure that * all fifos are flushed before continuing */ - dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | - GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); + dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | + GRSTCTL_RXFFLSH, GRSTCTL); /* wait until the fifos are both flushed */ timeout = 100; while (1) { - val = dwc2_readl(hsotg->regs + GRSTCTL); + val = dwc2_readl(hsotg, GRSTCTL); if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) break; @@ -451,7 +452,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, struct dwc2_hsotg_req *hs_req) { bool periodic = is_ep_periodic(hs_ep); - u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); + u32 gnptxsts = dwc2_readl(hsotg, GNPTXSTS); int buf_pos = hs_req->req.actual; int to_write = hs_ep->size_loaded; void *data; @@ -466,7 +467,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, return 0; if (periodic && !hsotg->dedicated_fifos) { - u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); + u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index)); int size_left; int size_done; @@ -507,8 +508,8 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, return -ENOSPC; } } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { - can_write = dwc2_readl(hsotg->regs + - DTXFSTS(hs_ep->fifo_index)); + can_write = dwc2_readl(hsotg, + DTXFSTS(hs_ep->fifo_index)); can_write &= 0xffff; can_write *= 4; @@ -598,7 +599,7 @@ static int dwc2_hsotg_write_fifo(struct dwc2_hsotg *hsotg, to_write = DIV_ROUND_UP(to_write, 4); data = hs_req->req.buf + buf_pos; - iowrite32_rep(hsotg->regs + EPFIFO(hs_ep->index), data, to_write); + dwc2_writel_rep(hsotg, EPFIFO(hs_ep->index), data, to_write); return (to_write >= can_write) ? -ENOSPC : 0; } @@ -652,7 +653,7 @@ static u32 dwc2_hsotg_read_frameno(struct dwc2_hsotg *hsotg) { u32 dsts; - dsts = dwc2_readl(hsotg->regs + DSTS); + dsts = dwc2_readl(hsotg, DSTS); dsts &= DSTS_SOFFN_MASK; dsts >>= DSTS_SOFFN_SHIFT; @@ -915,11 +916,11 @@ static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep *hs_ep) dma_reg = hs_ep->dir_in ? DIEPDMA(index) : DOEPDMA(index); /* write descriptor chain address to control register */ - dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); + dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg); - ctrl = dwc2_readl(hsotg->regs + depctl); + ctrl = dwc2_readl(hsotg, depctl); ctrl |= DXEPCTL_EPENA | DXEPCTL_CNAK; - dwc2_writel(ctrl, hsotg->regs + depctl); + dwc2_writel(hsotg, ctrl, depctl); } /** @@ -967,11 +968,11 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", - __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, + __func__, dwc2_readl(hsotg, epctrl_reg), index, hs_ep->dir_in ? "in" : "out"); /* If endpoint is stalled, we will restart request later */ - ctrl = dwc2_readl(hsotg->regs + epctrl_reg); + ctrl = dwc2_readl(hsotg, epctrl_reg); if (index && ctrl & DXEPCTL_STALL) { dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); @@ -1064,13 +1065,13 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, length); /* write descriptor chain address to control register */ - dwc2_writel(hs_ep->desc_list_dma, hsotg->regs + dma_reg); + dwc2_writel(hsotg, hs_ep->desc_list_dma, dma_reg); dev_dbg(hsotg->dev, "%s: %08x pad => 0x%08x\n", __func__, (u32)hs_ep->desc_list_dma, dma_reg); } else { /* write size / packets */ - dwc2_writel(epsize, hsotg->regs + epsize_reg); + dwc2_writel(hsotg, epsize, epsize_reg); if (using_dma(hsotg) && !continuing && (length != 0)) { /* @@ -1078,7 +1079,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, * already synced by dwc2_hsotg_ep_queue(). */ - dwc2_writel(ureq->dma, hsotg->regs + dma_reg); + dwc2_writel(hsotg, ureq->dma, dma_reg); dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", __func__, &ureq->dma, dma_reg); @@ -1104,7 +1105,7 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); - dwc2_writel(ctrl, hsotg->regs + epctrl_reg); + dwc2_writel(hsotg, ctrl, epctrl_reg); /* * set these, it seems that DMA support increments past the end @@ -1127,13 +1128,13 @@ static void dwc2_hsotg_start_req(struct dwc2_hsotg *hsotg, */ /* check ep is enabled */ - if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) + if (!(dwc2_readl(hsotg, epctrl_reg) & DXEPCTL_EPENA)) dev_dbg(hsotg->dev, "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", - index, dwc2_readl(hsotg->regs + epctrl_reg)); + index, dwc2_readl(hsotg, epctrl_reg)); dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", - __func__, dwc2_readl(hsotg->regs + epctrl_reg)); + __func__, dwc2_readl(hsotg, epctrl_reg)); /* enable ep interrupts */ dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); @@ -1466,7 +1467,7 @@ static struct dwc2_hsotg_ep *ep_from_windex(struct dwc2_hsotg *hsotg, */ int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) { - int dctl = dwc2_readl(hsotg->regs + DCTL); + int dctl = dwc2_readl(hsotg, DCTL); dctl &= ~DCTL_TSTCTL_MASK; switch (testmode) { @@ -1480,7 +1481,7 @@ int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode) default: return -EINVAL; } - dwc2_writel(dctl, hsotg->regs + DCTL); + dwc2_writel(hsotg, dctl, DCTL); return 0; } @@ -1634,9 +1635,9 @@ static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep *hs_ep) } else { dev_dbg(hsotg->dev, "%s: No more ISOC-OUT requests\n", __func__); - mask = dwc2_readl(hsotg->regs + epmsk_reg); + mask = dwc2_readl(hsotg, epmsk_reg); mask |= DOEPMSK_OUTTKNEPDISMSK; - dwc2_writel(mask, hsotg->regs + epmsk_reg); + dwc2_writel(hsotg, mask, epmsk_reg); } } @@ -1773,14 +1774,14 @@ static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg *hsotg) * taken effect, so no need to clear later. */ - ctrl = dwc2_readl(hsotg->regs + reg); + ctrl = dwc2_readl(hsotg, reg); ctrl |= DXEPCTL_STALL; ctrl |= DXEPCTL_CNAK; - dwc2_writel(ctrl, hsotg->regs + reg); + dwc2_writel(hsotg, ctrl, reg); dev_dbg(hsotg->dev, "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", - ctrl, reg, dwc2_readl(hsotg->regs + reg)); + ctrl, reg, dwc2_readl(hsotg, reg)); /* * complete won't be called, so we enqueue @@ -1825,11 +1826,11 @@ static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, switch (ctrl->bRequest) { case USB_REQ_SET_ADDRESS: hsotg->connected = 1; - dcfg = dwc2_readl(hsotg->regs + DCFG); + dcfg = dwc2_readl(hsotg, DCFG); dcfg &= ~DCFG_DEVADDR_MASK; dcfg |= (le16_to_cpu(ctrl->wValue) << DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; - dwc2_writel(dcfg, hsotg->regs + DCFG); + dwc2_writel(hsotg, dcfg, DCFG); dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); @@ -1955,16 +1956,16 @@ static void dwc2_hsotg_program_zlp(struct dwc2_hsotg *hsotg, dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep, dma, 0); } else { - dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | - DXEPTSIZ_XFERSIZE(0), hsotg->regs + + dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | + DXEPTSIZ_XFERSIZE(0), epsiz_reg); } - ctrl = dwc2_readl(hsotg->regs + epctl_reg); + ctrl = dwc2_readl(hsotg, epctl_reg); ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ ctrl |= DXEPCTL_USBACTEP; - dwc2_writel(ctrl, hsotg->regs + epctl_reg); + dwc2_writel(hsotg, ctrl, epctl_reg); } /** @@ -2124,13 +2125,12 @@ static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) { struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[ep_idx]; struct dwc2_hsotg_req *hs_req = hs_ep->req; - void __iomem *fifo = hsotg->regs + EPFIFO(ep_idx); int to_read; int max_req; int read_ptr; if (!hs_req) { - u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); + u32 epctl = dwc2_readl(hsotg, DOEPCTL(ep_idx)); int ptr; dev_dbg(hsotg->dev, @@ -2139,7 +2139,7 @@ static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) /* dump the data from the FIFO, we've nothing we can do */ for (ptr = 0; ptr < size; ptr += 4) - (void)dwc2_readl(fifo); + (void)dwc2_readl(hsotg, EPFIFO(ep_idx)); return; } @@ -2169,7 +2169,8 @@ static void dwc2_hsotg_rx_data(struct dwc2_hsotg *hsotg, int ep_idx, int size) * note, we might over-write the buffer end by 3 bytes depending on * alignment of the data. */ - ioread32_rep(fifo, hs_req->req.buf + read_ptr, to_read); + dwc2_readl_rep(hsotg, EPFIFO(ep_idx), + hs_req->req.buf + read_ptr, to_read); } /** @@ -2198,12 +2199,12 @@ static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg *hsotg, { u32 ctrl; - ctrl = dwc2_readl(hsotg->regs + epctl_reg); + ctrl = dwc2_readl(hsotg, epctl_reg); if (ctrl & DXEPCTL_EOFRNUM) ctrl |= DXEPCTL_SETEVENFR; else ctrl |= DXEPCTL_SETODDFR; - dwc2_writel(ctrl, hsotg->regs + epctl_reg); + dwc2_writel(hsotg, ctrl, epctl_reg); } /* @@ -2247,7 +2248,7 @@ static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep *hs_ep) */ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) { - u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); + u32 epsize = dwc2_readl(hsotg, DOEPTSIZ(epnum)); struct dwc2_hsotg_ep *hs_ep = hsotg->eps_out[epnum]; struct dwc2_hsotg_req *hs_req = hs_ep->req; struct usb_request *req = &hs_req->req; @@ -2343,7 +2344,7 @@ static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg *hsotg, int epnum) */ static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) { - u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); + u32 grxstsr = dwc2_readl(hsotg, GRXSTSP); u32 epnum, status, size; WARN_ON(using_dma(hsotg)); @@ -2374,7 +2375,7 @@ static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) dev_dbg(hsotg->dev, "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", dwc2_hsotg_read_frameno(hsotg), - dwc2_readl(hsotg->regs + DOEPCTL(0))); + dwc2_readl(hsotg, DOEPCTL(0))); /* * Call dwc2_hsotg_handle_outdone here if it was not called from * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't @@ -2392,7 +2393,7 @@ static void dwc2_hsotg_handle_rx(struct dwc2_hsotg *hsotg) dev_dbg(hsotg->dev, "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", dwc2_hsotg_read_frameno(hsotg), - dwc2_readl(hsotg->regs + DOEPCTL(0))); + dwc2_readl(hsotg, DOEPCTL(0))); WARN_ON(hsotg->ep0_state != DWC2_EP0_SETUP); @@ -2446,7 +2447,6 @@ static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, unsigned int mc, unsigned int dir_in) { struct dwc2_hsotg_ep *hs_ep; - void __iomem *regs = hsotg->regs; u32 reg; hs_ep = index_to_ep(hsotg, ep, dir_in); @@ -2472,15 +2472,15 @@ static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg *hsotg, } if (dir_in) { - reg = dwc2_readl(regs + DIEPCTL(ep)); + reg = dwc2_readl(hsotg, DIEPCTL(ep)); reg &= ~DXEPCTL_MPS_MASK; reg |= mps; - dwc2_writel(reg, regs + DIEPCTL(ep)); + dwc2_writel(hsotg, reg, DIEPCTL(ep)); } else { - reg = dwc2_readl(regs + DOEPCTL(ep)); + reg = dwc2_readl(hsotg, DOEPCTL(ep)); reg &= ~DXEPCTL_MPS_MASK; reg |= mps; - dwc2_writel(reg, regs + DOEPCTL(ep)); + dwc2_writel(hsotg, reg, DOEPCTL(ep)); } return; @@ -2496,8 +2496,8 @@ bad_mps: */ static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg *hsotg, unsigned int idx) { - dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, - hsotg->regs + GRSTCTL); + dwc2_writel(hsotg, GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, + GRSTCTL); /* wait until the fifo is flushed */ if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 100)) @@ -2550,7 +2550,7 @@ static void dwc2_hsotg_complete_in(struct dwc2_hsotg *hsotg, struct dwc2_hsotg_ep *hs_ep) { struct dwc2_hsotg_req *hs_req = hs_ep->req; - u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); + u32 epsize = dwc2_readl(hsotg, DIEPTSIZ(hs_ep->index)); int size_left, size_done; if (!hs_req) { @@ -2654,12 +2654,12 @@ static u32 dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg *hsotg, u32 mask; u32 diepempmsk; - mask = dwc2_readl(hsotg->regs + epmsk_reg); - diepempmsk = dwc2_readl(hsotg->regs + DIEPEMPMSK); + mask = dwc2_readl(hsotg, epmsk_reg); + diepempmsk = dwc2_readl(hsotg, DIEPEMPMSK); mask |= ((diepempmsk >> idx) & 0x1) ? DIEPMSK_TXFIFOEMPTY : 0; mask |= DXEPINT_SETUP_RCVD; - ints = dwc2_readl(hsotg->regs + epint_reg); + ints = dwc2_readl(hsotg, epint_reg); ints &= mask; return ints; } @@ -2684,12 +2684,12 @@ static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) unsigned char idx = hs_ep->index; int dir_in = hs_ep->dir_in; u32 epctl_reg = dir_in ? DIEPCTL(idx) : DOEPCTL(idx); - int dctl = dwc2_readl(hsotg->regs + DCTL); + int dctl = dwc2_readl(hsotg, DCTL); dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); if (dir_in) { - int epctl = dwc2_readl(hsotg->regs + epctl_reg); + int epctl = dwc2_readl(hsotg, epctl_reg); dwc2_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); @@ -2699,17 +2699,17 @@ static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep *hs_ep) } if ((epctl & DXEPCTL_STALL) && (epctl & DXEPCTL_EPTYPE_BULK)) { - int dctl = dwc2_readl(hsotg->regs + DCTL); + int dctl = dwc2_readl(hsotg, DCTL); dctl |= DCTL_CGNPINNAK; - dwc2_writel(dctl, hsotg->regs + DCTL); + dwc2_writel(hsotg, dctl, DCTL); } return; } if (dctl & DCTL_GOUTNAKSTS) { dctl |= DCTL_CGOUTNAK; - dwc2_writel(dctl, hsotg->regs + DCTL); + dwc2_writel(hsotg, dctl, DCTL); } if (!hs_ep->isochronous) @@ -2750,21 +2750,14 @@ static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) struct dwc2_hsotg *hsotg = ep->parent; int dir_in = ep->dir_in; u32 doepmsk; - u32 tmp; if (dir_in || !ep->isochronous) return; - /* - * Store frame in which irq was asserted here, as - * it can change while completing request below. - */ - tmp = dwc2_hsotg_read_frameno(hsotg); - if (using_desc_dma(hsotg)) { if (ep->target_frame == TARGET_FRAME_INITIAL) { /* Start first ISO Out */ - ep->target_frame = tmp; + ep->target_frame = hsotg->frame_number; dwc2_gadget_start_isoc_ddma(ep); } return; @@ -2772,26 +2765,24 @@ static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep *ep) if (ep->interval > 1 && ep->target_frame == TARGET_FRAME_INITIAL) { - u32 dsts; u32 ctrl; - dsts = dwc2_readl(hsotg->regs + DSTS); - ep->target_frame = dwc2_hsotg_read_frameno(hsotg); + ep->target_frame = hsotg->frame_number; dwc2_gadget_incr_frame_num(ep); - ctrl = dwc2_readl(hsotg->regs + DOEPCTL(ep->index)); + ctrl = dwc2_readl(hsotg, DOEPCTL(ep->index)); if (ep->target_frame & 0x1) ctrl |= DXEPCTL_SETODDFR; else ctrl |= DXEPCTL_SETEVENFR; - dwc2_writel(ctrl, hsotg->regs + DOEPCTL(ep->index)); + dwc2_writel(hsotg, ctrl, DOEPCTL(ep->index)); } dwc2_gadget_start_next_request(ep); - doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); + doepmsk = dwc2_readl(hsotg, DOEPMSK); doepmsk &= ~DOEPMSK_OUTTKNEPDISMSK; - dwc2_writel(doepmsk, hsotg->regs + DOEPMSK); + dwc2_writel(hsotg, doepmsk, DOEPMSK); } /** @@ -2812,31 +2803,29 @@ static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep *hs_ep) { struct dwc2_hsotg *hsotg = hs_ep->parent; int dir_in = hs_ep->dir_in; - u32 tmp; if (!dir_in || !hs_ep->isochronous) return; if (hs_ep->target_frame == TARGET_FRAME_INITIAL) { - tmp = dwc2_hsotg_read_frameno(hsotg); if (using_desc_dma(hsotg)) { - hs_ep->target_frame = tmp; + hs_ep->target_frame = hsotg->frame_number; dwc2_gadget_incr_frame_num(hs_ep); dwc2_gadget_start_isoc_ddma(hs_ep); return; } - hs_ep->target_frame = tmp; + hs_ep->target_frame = hsotg->frame_number; if (hs_ep->interval > 1) { - u32 ctrl = dwc2_readl(hsotg->regs + + u32 ctrl = dwc2_readl(hsotg, DIEPCTL(hs_ep->index)); if (hs_ep->target_frame & 0x1) ctrl |= DXEPCTL_SETODDFR; else ctrl |= DXEPCTL_SETEVENFR; - dwc2_writel(ctrl, hsotg->regs + DIEPCTL(hs_ep->index)); + dwc2_writel(hsotg, ctrl, DIEPCTL(hs_ep->index)); } dwc2_hsotg_complete_request(hsotg, hs_ep, @@ -2866,10 +2855,10 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, u32 ctrl; ints = dwc2_gadget_read_ep_interrupts(hsotg, idx, dir_in); - ctrl = dwc2_readl(hsotg->regs + epctl_reg); + ctrl = dwc2_readl(hsotg, epctl_reg); /* Clear endpoint interrupts */ - dwc2_writel(ints, hsotg->regs + epint_reg); + dwc2_writel(hsotg, ints, epint_reg); if (!hs_ep) { dev_err(hsotg->dev, "%s:Interrupt for unconfigured ep%d(%s)\n", @@ -2897,8 +2886,8 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, if (ints & DXEPINT_XFERCOMPL) { dev_dbg(hsotg->dev, "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", - __func__, dwc2_readl(hsotg->regs + epctl_reg), - dwc2_readl(hsotg->regs + epsiz_reg)); + __func__, dwc2_readl(hsotg, epctl_reg), + dwc2_readl(hsotg, epsiz_reg)); /* In DDMA handle isochronous requests separately */ if (using_desc_dma(hsotg) && hs_ep->isochronous) { @@ -3016,7 +3005,7 @@ static void dwc2_hsotg_epint(struct dwc2_hsotg *hsotg, unsigned int idx, */ static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) { - u32 dsts = dwc2_readl(hsotg->regs + DSTS); + u32 dsts = dwc2_readl(hsotg, DSTS); int ep0_mps = 0, ep_mps = 8; /* @@ -3087,8 +3076,8 @@ static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg *hsotg) dwc2_hsotg_enqueue_setup(hsotg); dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", - dwc2_readl(hsotg->regs + DIEPCTL0), - dwc2_readl(hsotg->regs + DOEPCTL0)); + dwc2_readl(hsotg, DIEPCTL0), + dwc2_readl(hsotg, DOEPCTL0)); } /** @@ -3115,7 +3104,7 @@ static void kill_all_requests(struct dwc2_hsotg *hsotg, if (!hsotg->dedicated_fifos) return; - size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->fifo_index)) & 0xffff) * 4; + size = (dwc2_readl(hsotg, DTXFSTS(ep->fifo_index)) & 0xffff) * 4; if (size < ep->fifo_size) dwc2_hsotg_txfifo_flush(hsotg, ep->fifo_index); } @@ -3216,7 +3205,7 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, */ /* keep other bits untouched (so e.g. forced modes are not lost) */ - usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg = dwc2_readl(hsotg, GUSBCFG); usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); @@ -3231,12 +3220,12 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | (val << GUSBCFG_USBTRDTIM_SHIFT); } - dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + dwc2_writel(hsotg, usbcfg, GUSBCFG); dwc2_hsotg_init_fifo(hsotg); if (!is_usb_reset) - dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); + dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); dcfg |= DCFG_EPMISCNT(1); @@ -3257,13 +3246,13 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, if (hsotg->params.ipg_isoc_en) dcfg |= DCFG_IPG_ISOC_SUPPORDED; - dwc2_writel(dcfg, hsotg->regs + DCFG); + dwc2_writel(hsotg, dcfg, DCFG); /* Clear any pending OTG interrupts */ - dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); + dwc2_writel(hsotg, 0xffffffff, GOTGINT); /* Clear any pending interrupts */ - dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, 0xffffffff, GINTSTS); intmsk = GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | GINTSTS_USBRST | GINTSTS_RESETDET | @@ -3277,22 +3266,22 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, if (!hsotg->params.external_id_pin_ctl) intmsk |= GINTSTS_CONIDSTSCHNG; - dwc2_writel(intmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, intmsk, GINTMSK); if (using_dma(hsotg)) { - dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | + dwc2_writel(hsotg, GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | hsotg->params.ahbcfg, - hsotg->regs + GAHBCFG); + GAHBCFG); /* Set DDMA mode support in the core if needed */ if (using_desc_dma(hsotg)) - dwc2_set_bit(hsotg->regs + DCFG, DCFG_DESCDMA_EN); + dwc2_set_bit(hsotg, DCFG, DCFG_DESCDMA_EN); } else { - dwc2_writel(((hsotg->dedicated_fifos) ? + dwc2_writel(hsotg, ((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL | GAHBCFG_P_TXF_EMP_LVL) : 0) | - GAHBCFG_GLBL_INTR_EN, hsotg->regs + GAHBCFG); + GAHBCFG_GLBL_INTR_EN, GAHBCFG); } /* @@ -3301,33 +3290,33 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, * interrupts. */ - dwc2_writel(((hsotg->dedicated_fifos && !using_dma(hsotg)) ? + dwc2_writel(hsotg, ((hsotg->dedicated_fifos && !using_dma(hsotg)) ? DIEPMSK_TXFIFOEMPTY | DIEPMSK_INTKNTXFEMPMSK : 0) | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK, - hsotg->regs + DIEPMSK); + DIEPMSK); /* * don't need XferCompl, we get that from RXFIFO in slave mode. In * DMA mode we may need this and StsPhseRcvd. */ - dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | + dwc2_writel(hsotg, (using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | DOEPMSK_STSPHSERCVDMSK) : 0) | DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | DOEPMSK_SETUPMSK, - hsotg->regs + DOEPMSK); + DOEPMSK); /* Enable BNA interrupt for DDMA */ if (using_desc_dma(hsotg)) { - dwc2_set_bit(hsotg->regs + DOEPMSK, DOEPMSK_BNAMSK); - dwc2_set_bit(hsotg->regs + DIEPMSK, DIEPMSK_BNAININTRMSK); + dwc2_set_bit(hsotg, DOEPMSK, DOEPMSK_BNAMSK); + dwc2_set_bit(hsotg, DIEPMSK, DIEPMSK_BNAININTRMSK); } - dwc2_writel(0, hsotg->regs + DAINTMSK); + dwc2_writel(hsotg, 0, DAINTMSK); dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", - dwc2_readl(hsotg->regs + DIEPCTL0), - dwc2_readl(hsotg->regs + DOEPCTL0)); + dwc2_readl(hsotg, DIEPCTL0), + dwc2_readl(hsotg, DOEPCTL0)); /* enable in and out endpoint interrupts */ dwc2_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); @@ -3345,12 +3334,12 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, dwc2_hsotg_ctrl_epint(hsotg, 0, 1, 1); if (!is_usb_reset) { - dwc2_set_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); + dwc2_set_bit(hsotg, DCTL, DCTL_PWRONPRGDONE); udelay(10); /* see openiboot */ - dwc2_clear_bit(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); + dwc2_clear_bit(hsotg, DCTL, DCTL_PWRONPRGDONE); } - dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); + dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg, DCTL)); /* * DxEPCTL_USBActEp says RO in manual, but seems to be set by @@ -3358,23 +3347,23 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, */ /* set to read 1 8byte packet */ - dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | - DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); + dwc2_writel(hsotg, DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | + DXEPTSIZ_XFERSIZE(8), DOEPTSIZ0); - dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | + dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | DXEPCTL_CNAK | DXEPCTL_EPENA | DXEPCTL_USBACTEP, - hsotg->regs + DOEPCTL0); + DOEPCTL0); /* enable, but don't activate EP0in */ - dwc2_writel(dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | - DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); + dwc2_writel(hsotg, dwc2_hsotg_ep0_mps(hsotg->eps_out[0]->ep.maxpacket) | + DXEPCTL_USBACTEP, DIEPCTL0); /* clear global NAKs */ val = DCTL_CGOUTNAK | DCTL_CGNPINNAK; if (!is_usb_reset) val |= DCTL_SFTDISCON; - dwc2_set_bit(hsotg->regs + DCTL, val); + dwc2_set_bit(hsotg, DCTL, val); /* configure the core to support LPM */ dwc2_gadget_init_lpm(hsotg); @@ -3387,20 +3376,20 @@ void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *hsotg, dwc2_hsotg_enqueue_setup(hsotg); dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", - dwc2_readl(hsotg->regs + DIEPCTL0), - dwc2_readl(hsotg->regs + DOEPCTL0)); + dwc2_readl(hsotg, DIEPCTL0), + dwc2_readl(hsotg, DOEPCTL0)); } static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg *hsotg) { /* set the soft-disconnect bit */ - dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); + dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); } void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) { /* remove the soft-disconnect and let's go */ - dwc2_clear_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); + dwc2_clear_bit(hsotg, DCTL, DCTL_SFTDISCON); } /** @@ -3425,7 +3414,7 @@ static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) dev_dbg(hsotg->dev, "Incomplete isoc in interrupt received:\n"); - daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); + daintmsk = dwc2_readl(hsotg, DAINTMSK); for (idx = 1; idx < hsotg->num_of_eps; idx++) { hs_ep = hsotg->eps_in[idx]; @@ -3433,17 +3422,17 @@ static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg *hsotg) if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) continue; - epctrl = dwc2_readl(hsotg->regs + DIEPCTL(idx)); + epctrl = dwc2_readl(hsotg, DIEPCTL(idx)); if ((epctrl & DXEPCTL_EPENA) && dwc2_gadget_target_frame_elapsed(hs_ep)) { epctrl |= DXEPCTL_SNAK; epctrl |= DXEPCTL_EPDIS; - dwc2_writel(epctrl, hsotg->regs + DIEPCTL(idx)); + dwc2_writel(hsotg, epctrl, DIEPCTL(idx)); } } /* Clear interrupt */ - dwc2_writel(GINTSTS_INCOMPL_SOIN, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, GINTSTS_INCOMPL_SOIN, GINTSTS); } /** @@ -3470,7 +3459,7 @@ static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) dev_dbg(hsotg->dev, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__); - daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); + daintmsk = dwc2_readl(hsotg, DAINTMSK); daintmsk >>= DAINT_OUTEP_SHIFT; for (idx = 1; idx < hsotg->num_of_eps; idx++) { @@ -3479,24 +3468,24 @@ static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg *hsotg) if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) continue; - epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); + epctrl = dwc2_readl(hsotg, DOEPCTL(idx)); if ((epctrl & DXEPCTL_EPENA) && dwc2_gadget_target_frame_elapsed(hs_ep)) { /* Unmask GOUTNAKEFF interrupt */ - gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk = dwc2_readl(hsotg, GINTMSK); gintmsk |= GINTSTS_GOUTNAKEFF; - dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, gintmsk, GINTMSK); - gintsts = dwc2_readl(hsotg->regs + GINTSTS); + gintsts = dwc2_readl(hsotg, GINTSTS); if (!(gintsts & GINTSTS_GOUTNAKEFF)) { - dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK); + dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK); break; } } } /* Clear interrupt */ - dwc2_writel(GINTSTS_INCOMPL_SOOUT, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, GINTSTS_INCOMPL_SOOUT, GINTSTS); } /** @@ -3516,8 +3505,8 @@ static irqreturn_t dwc2_hsotg_irq(int irq, void *pw) spin_lock(&hsotg->lock); irq_retry: - gintsts = dwc2_readl(hsotg->regs + GINTSTS); - gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintsts = dwc2_readl(hsotg, GINTSTS); + gintmsk = dwc2_readl(hsotg, GINTMSK); dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); @@ -3527,7 +3516,7 @@ irq_retry: if (gintsts & GINTSTS_RESETDET) { dev_dbg(hsotg->dev, "%s: USBRstDet\n", __func__); - dwc2_writel(GINTSTS_RESETDET, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, GINTSTS_RESETDET, GINTSTS); /* This event must be used only if controller is suspended */ if (hsotg->lx_state == DWC2_L2) { @@ -3537,34 +3526,34 @@ irq_retry: } if (gintsts & (GINTSTS_USBRST | GINTSTS_RESETDET)) { - u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); + u32 usb_status = dwc2_readl(hsotg, GOTGCTL); u32 connected = hsotg->connected; dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", - dwc2_readl(hsotg->regs + GNPTXSTS)); + dwc2_readl(hsotg, GNPTXSTS)); - dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, GINTSTS_USBRST, GINTSTS); /* Report disconnection if it is not already done. */ dwc2_hsotg_disconnect(hsotg); /* Reset device address to zero */ - dwc2_clear_bit(hsotg->regs + DCFG, DCFG_DEVADDR_MASK); + dwc2_clear_bit(hsotg, DCFG, DCFG_DEVADDR_MASK); if (usb_status & GOTGCTL_BSESVLD && connected) dwc2_hsotg_core_init_disconnected(hsotg, true); } if (gintsts & GINTSTS_ENUMDONE) { - dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, GINTSTS_ENUMDONE, GINTSTS); dwc2_hsotg_irq_enumdone(hsotg); } if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { - u32 daint = dwc2_readl(hsotg->regs + DAINT); - u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); + u32 daint = dwc2_readl(hsotg, DAINT); + u32 daintmsk = dwc2_readl(hsotg, DAINTMSK); u32 daint_out, daint_in; int ep; @@ -3623,7 +3612,7 @@ irq_retry: if (gintsts & GINTSTS_ERLYSUSP) { dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); - dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, GINTSTS_ERLYSUSP, GINTSTS); } /* @@ -3639,12 +3628,12 @@ irq_retry: u32 daintmsk; struct dwc2_hsotg_ep *hs_ep; - daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); + daintmsk = dwc2_readl(hsotg, DAINTMSK); daintmsk >>= DAINT_OUTEP_SHIFT; /* Mask this interrupt */ - gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk = dwc2_readl(hsotg, GINTMSK); gintmsk &= ~GINTSTS_GOUTNAKEFF; - dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, gintmsk, GINTMSK); dev_dbg(hsotg->dev, "GOUTNakEff triggered\n"); for (idx = 1; idx < hsotg->num_of_eps; idx++) { @@ -3653,12 +3642,12 @@ irq_retry: if ((BIT(idx) & ~daintmsk) || !hs_ep->isochronous) continue; - epctrl = dwc2_readl(hsotg->regs + DOEPCTL(idx)); + epctrl = dwc2_readl(hsotg, DOEPCTL(idx)); if (epctrl & DXEPCTL_EPENA) { epctrl |= DXEPCTL_SNAK; epctrl |= DXEPCTL_EPDIS; - dwc2_writel(epctrl, hsotg->regs + DOEPCTL(idx)); + dwc2_writel(hsotg, epctrl, DOEPCTL(idx)); } } @@ -3668,7 +3657,7 @@ irq_retry: if (gintsts & GINTSTS_GINNAKEFF) { dev_info(hsotg->dev, "GINNakEff triggered\n"); - dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK); + dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK); dwc2_hsotg_dump(hsotg); } @@ -3708,7 +3697,7 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, if (hs_ep->dir_in) { if (hsotg->dedicated_fifos || hs_ep->periodic) { - dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_SNAK); + dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_SNAK); /* Wait for Nak effect */ if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_INEPNAKEFF, 100)) @@ -3716,7 +3705,7 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, "%s: timeout DIEPINT.NAKEFF\n", __func__); } else { - dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGNPINNAK); + dwc2_set_bit(hsotg, DCTL, DCTL_SGNPINNAK); /* Wait for Nak effect */ if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_GINNAKEFF, 100)) @@ -3725,8 +3714,8 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, __func__); } } else { - if (!(dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_GOUTNAKEFF)) - dwc2_set_bit(hsotg->regs + DCTL, DCTL_SGOUTNAK); + if (!(dwc2_readl(hsotg, GINTSTS) & GINTSTS_GOUTNAKEFF)) + dwc2_set_bit(hsotg, DCTL, DCTL_SGOUTNAK); /* Wait for global nak to take effect */ if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, @@ -3736,7 +3725,7 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, } /* Disable ep */ - dwc2_set_bit(hsotg->regs + epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); + dwc2_set_bit(hsotg, epctrl_reg, DXEPCTL_EPDIS | DXEPCTL_SNAK); /* Wait for ep to be disabled */ if (dwc2_hsotg_wait_bit_set(hsotg, epint_reg, DXEPINT_EPDISBLD, 100)) @@ -3744,7 +3733,7 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, "%s: timeout DOEPCTL.EPDisable\n", __func__); /* Clear EPDISBLD interrupt */ - dwc2_set_bit(hsotg->regs + epint_reg, DXEPINT_EPDISBLD); + dwc2_set_bit(hsotg, epint_reg, DXEPINT_EPDISBLD); if (hs_ep->dir_in) { unsigned short fifo_index; @@ -3759,11 +3748,11 @@ static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg *hsotg, /* Clear Global In NP NAK in Shared FIFO for non periodic ep */ if (!hsotg->dedicated_fifos && !hs_ep->periodic) - dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGNPINNAK); + dwc2_set_bit(hsotg, DCTL, DCTL_CGNPINNAK); } else { /* Remove global NAKs */ - dwc2_set_bit(hsotg->regs + DCTL, DCTL_CGOUTNAK); + dwc2_set_bit(hsotg, DCTL, DCTL_CGOUTNAK); } } @@ -3831,7 +3820,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep, /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */ epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); - epctrl = dwc2_readl(hsotg->regs + epctrl_reg); + epctrl = dwc2_readl(hsotg, epctrl_reg); dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", __func__, epctrl, epctrl_reg); @@ -3879,13 +3868,13 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep, hs_ep->compl_desc = 0; if (dir_in) { hs_ep->periodic = 1; - mask = dwc2_readl(hsotg->regs + DIEPMSK); + mask = dwc2_readl(hsotg, DIEPMSK); mask |= DIEPMSK_NAKMSK; - dwc2_writel(mask, hsotg->regs + DIEPMSK); + dwc2_writel(hsotg, mask, DIEPMSK); } else { - mask = dwc2_readl(hsotg->regs + DOEPMSK); + mask = dwc2_readl(hsotg, DOEPMSK); mask |= DOEPMSK_OUTTKNEPDISMSK; - dwc2_writel(mask, hsotg->regs + DOEPMSK); + dwc2_writel(hsotg, mask, DOEPMSK); } break; @@ -3920,7 +3909,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep, for (i = 1; i < hsotg->num_of_eps; ++i) { if (hsotg->fifo_map & (1 << i)) continue; - val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); + val = dwc2_readl(hsotg, DPTXFSIZN(i)); val = (val >> FIFOSIZE_DEPTH_SHIFT) * 4; if (val < size) continue; @@ -3958,7 +3947,7 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep, * to 4.00a (including both). Also for FS_IOT_1.00a * and HS_IOT_1.00a. */ - u32 gsnpsid = dwc2_readl(hsotg->regs + GSNPSID); + u32 gsnpsid = dwc2_readl(hsotg, GSNPSID); if ((gsnpsid >= DWC2_CORE_REV_2_72a && gsnpsid <= DWC2_CORE_REV_4_00a) || @@ -3970,9 +3959,9 @@ static int dwc2_hsotg_ep_enable(struct usb_ep *ep, dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", __func__, epctrl); - dwc2_writel(epctrl, hsotg->regs + epctrl_reg); + dwc2_writel(hsotg, epctrl, epctrl_reg); dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", - __func__, dwc2_readl(hsotg->regs + epctrl_reg)); + __func__, dwc2_readl(hsotg, epctrl_reg)); /* enable the endpoint interrupt */ dwc2_hsotg_ctrl_epint(hsotg, index, dir_in, 1); @@ -4021,7 +4010,7 @@ static int dwc2_hsotg_ep_disable(struct usb_ep *ep) spin_lock_irqsave(&hsotg->lock, flags); - ctrl = dwc2_readl(hsotg->regs + epctrl_reg); + ctrl = dwc2_readl(hsotg, epctrl_reg); if (ctrl & DXEPCTL_EPENA) dwc2_hsotg_ep_stop_xfr(hsotg, hs_ep); @@ -4031,7 +4020,7 @@ static int dwc2_hsotg_ep_disable(struct usb_ep *ep) ctrl |= DXEPCTL_SNAK; dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); - dwc2_writel(ctrl, hsotg->regs + epctrl_reg); + dwc2_writel(hsotg, ctrl, epctrl_reg); /* disable endpoint interrupts */ dwc2_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); @@ -4138,7 +4127,7 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) if (hs_ep->dir_in) { epreg = DIEPCTL(index); - epctl = dwc2_readl(hs->regs + epreg); + epctl = dwc2_readl(hs, epreg); if (value) { epctl |= DXEPCTL_STALL | DXEPCTL_SNAK; @@ -4151,10 +4140,10 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) xfertype == DXEPCTL_EPTYPE_INTERRUPT) epctl |= DXEPCTL_SETD0PID; } - dwc2_writel(epctl, hs->regs + epreg); + dwc2_writel(hs, epctl, epreg); } else { epreg = DOEPCTL(index); - epctl = dwc2_readl(hs->regs + epreg); + epctl = dwc2_readl(hs, epreg); if (value) { epctl |= DXEPCTL_STALL; @@ -4165,7 +4154,7 @@ static int dwc2_hsotg_ep_sethalt(struct usb_ep *ep, int value, bool now) xfertype == DXEPCTL_EPTYPE_INTERRUPT) epctl |= DXEPCTL_SETD0PID; } - dwc2_writel(epctl, hs->regs + epreg); + dwc2_writel(hs, epctl, epreg); } hs_ep->halted = value; @@ -4213,29 +4202,29 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) u32 usbcfg; /* unmask subset of endpoint interrupts */ - dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | + dwc2_writel(hsotg, DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, - hsotg->regs + DIEPMSK); + DIEPMSK); - dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | + dwc2_writel(hsotg, DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, - hsotg->regs + DOEPMSK); + DOEPMSK); - dwc2_writel(0, hsotg->regs + DAINTMSK); + dwc2_writel(hsotg, 0, DAINTMSK); /* Be in disconnected state until gadget is registered */ - dwc2_set_bit(hsotg->regs + DCTL, DCTL_SFTDISCON); + dwc2_set_bit(hsotg, DCTL, DCTL_SFTDISCON); /* setup fifos */ dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", - dwc2_readl(hsotg->regs + GRXFSIZ), - dwc2_readl(hsotg->regs + GNPTXFSIZ)); + dwc2_readl(hsotg, GRXFSIZ), + dwc2_readl(hsotg, GNPTXFSIZ)); dwc2_hsotg_init_fifo(hsotg); /* keep other bits untouched (so e.g. forced modes are not lost) */ - usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg = dwc2_readl(hsotg, GUSBCFG); usbcfg &= ~(GUSBCFG_TOUTCAL_MASK | GUSBCFG_PHYIF16 | GUSBCFG_SRPCAP | GUSBCFG_HNPCAP | GUSBCFG_USBTRDTIM_MASK); @@ -4243,10 +4232,10 @@ static void dwc2_hsotg_init(struct dwc2_hsotg *hsotg) trdtim = (hsotg->phyif == GUSBCFG_PHYIF8) ? 9 : 5; usbcfg |= hsotg->phyif | GUSBCFG_TOUTCAL(7) | (trdtim << GUSBCFG_USBTRDTIM_SHIFT); - dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + dwc2_writel(hsotg, usbcfg, GUSBCFG); if (using_dma(hsotg)) - dwc2_set_bit(hsotg->regs + GAHBCFG, GAHBCFG_DMA_EN); + dwc2_set_bit(hsotg, GAHBCFG, GAHBCFG_DMA_EN); } /** @@ -4536,9 +4525,9 @@ static void dwc2_hsotg_initep(struct dwc2_hsotg *hsotg, u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); if (dir_in) - dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); + dwc2_writel(hsotg, next, DIEPCTL(epnum)); else - dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); + dwc2_writel(hsotg, next, DOEPCTL(epnum)); } } @@ -4607,24 +4596,23 @@ static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) { #ifdef DEBUG struct device *dev = hsotg->dev; - void __iomem *regs = hsotg->regs; u32 val; int idx; dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", - dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), - dwc2_readl(regs + DIEPMSK)); + dwc2_readl(hsotg, DCFG), dwc2_readl(hsotg, DCTL), + dwc2_readl(hsotg, DIEPMSK)); dev_info(dev, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n", - dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + GHWCFG1)); + dwc2_readl(hsotg, GAHBCFG), dwc2_readl(hsotg, GHWCFG1)); dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", - dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); + dwc2_readl(hsotg, GRXFSIZ), dwc2_readl(hsotg, GNPTXFSIZ)); /* show periodic fifo settings */ for (idx = 1; idx < hsotg->num_of_eps; idx++) { - val = dwc2_readl(regs + DPTXFSIZN(idx)); + val = dwc2_readl(hsotg, DPTXFSIZN(idx)); dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, val >> FIFOSIZE_DEPTH_SHIFT, val & FIFOSIZE_STARTADDR_MASK); @@ -4633,20 +4621,20 @@ static void dwc2_hsotg_dump(struct dwc2_hsotg *hsotg) for (idx = 0; idx < hsotg->num_of_eps; idx++) { dev_info(dev, "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, - dwc2_readl(regs + DIEPCTL(idx)), - dwc2_readl(regs + DIEPTSIZ(idx)), - dwc2_readl(regs + DIEPDMA(idx))); + dwc2_readl(hsotg, DIEPCTL(idx)), + dwc2_readl(hsotg, DIEPTSIZ(idx)), + dwc2_readl(hsotg, DIEPDMA(idx))); - val = dwc2_readl(regs + DOEPCTL(idx)); + val = dwc2_readl(hsotg, DOEPCTL(idx)); dev_info(dev, "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", - idx, dwc2_readl(regs + DOEPCTL(idx)), - dwc2_readl(regs + DOEPTSIZ(idx)), - dwc2_readl(regs + DOEPDMA(idx))); + idx, dwc2_readl(hsotg, DOEPCTL(idx)), + dwc2_readl(hsotg, DOEPTSIZ(idx)), + dwc2_readl(hsotg, DOEPDMA(idx))); } dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", - dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); + dwc2_readl(hsotg, DVBUSDIS), dwc2_readl(hsotg, DVBUSPULSE)); #endif } @@ -4835,15 +4823,15 @@ int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) /* Backup dev regs */ dr = &hsotg->dr_backup; - dr->dcfg = dwc2_readl(hsotg->regs + DCFG); - dr->dctl = dwc2_readl(hsotg->regs + DCTL); - dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); - dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK); - dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK); + dr->dcfg = dwc2_readl(hsotg, DCFG); + dr->dctl = dwc2_readl(hsotg, DCTL); + dr->daintmsk = dwc2_readl(hsotg, DAINTMSK); + dr->diepmsk = dwc2_readl(hsotg, DIEPMSK); + dr->doepmsk = dwc2_readl(hsotg, DOEPMSK); for (i = 0; i < hsotg->num_of_eps; i++) { /* Backup IN EPs */ - dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i)); + dr->diepctl[i] = dwc2_readl(hsotg, DIEPCTL(i)); /* Ensure DATA PID is correctly configured */ if (dr->diepctl[i] & DXEPCTL_DPID) @@ -4851,11 +4839,11 @@ int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) else dr->diepctl[i] |= DXEPCTL_SETD0PID; - dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i)); - dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i)); + dr->dieptsiz[i] = dwc2_readl(hsotg, DIEPTSIZ(i)); + dr->diepdma[i] = dwc2_readl(hsotg, DIEPDMA(i)); /* Backup OUT EPs */ - dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i)); + dr->doepctl[i] = dwc2_readl(hsotg, DOEPCTL(i)); /* Ensure DATA PID is correctly configured */ if (dr->doepctl[i] & DXEPCTL_DPID) @@ -4863,9 +4851,9 @@ int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg) else dr->doepctl[i] |= DXEPCTL_SETD0PID; - dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i)); - dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i)); - dr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); + dr->doeptsiz[i] = dwc2_readl(hsotg, DOEPTSIZ(i)); + dr->doepdma[i] = dwc2_readl(hsotg, DOEPDMA(i)); + dr->dtxfsiz[i] = dwc2_readl(hsotg, DPTXFSIZN(i)); } dr->valid = true; return 0; @@ -4898,17 +4886,17 @@ int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup) dr->valid = false; if (!remote_wakeup) - dwc2_writel(dr->dctl, hsotg->regs + DCTL); + dwc2_writel(hsotg, dr->dctl, DCTL); - dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK); - dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK); - dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK); + dwc2_writel(hsotg, dr->daintmsk, DAINTMSK); + dwc2_writel(hsotg, dr->diepmsk, DIEPMSK); + dwc2_writel(hsotg, dr->doepmsk, DOEPMSK); for (i = 0; i < hsotg->num_of_eps; i++) { /* Restore IN EPs */ - dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i)); - dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i)); - dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); + dwc2_writel(hsotg, dr->dieptsiz[i], DIEPTSIZ(i)); + dwc2_writel(hsotg, dr->diepdma[i], DIEPDMA(i)); + dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i)); /** WA for enabled EPx's IN in DDMA mode. On entering to * hibernation wrong value read and saved from DIEPDMAx, * as result BNA interrupt asserted on hibernation exit @@ -4917,10 +4905,10 @@ int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup) if (hsotg->params.g_dma_desc && (dr->diepctl[i] & DXEPCTL_EPENA)) dr->diepdma[i] = hsotg->eps_in[i]->desc_list_dma; - dwc2_writel(dr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i)); - dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i)); + dwc2_writel(hsotg, dr->dtxfsiz[i], DPTXFSIZN(i)); + dwc2_writel(hsotg, dr->diepctl[i], DIEPCTL(i)); /* Restore OUT EPs */ - dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i)); + dwc2_writel(hsotg, dr->doeptsiz[i], DOEPTSIZ(i)); /* WA for enabled EPx's OUT in DDMA mode. On entering to * hibernation wrong value read and saved from DOEPDMAx, * as result BNA interrupt asserted on hibernation exit @@ -4929,8 +4917,8 @@ int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg, int remote_wakeup) if (hsotg->params.g_dma_desc && (dr->doepctl[i] & DXEPCTL_EPENA)) dr->doepdma[i] = hsotg->eps_out[i]->desc_list_dma; - dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i)); - dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i)); + dwc2_writel(hsotg, dr->doepdma[i], DOEPDMA(i)); + dwc2_writel(hsotg, dr->doepctl[i], DOEPCTL(i)); } return 0; @@ -4954,9 +4942,8 @@ void dwc2_gadget_init_lpm(struct dwc2_hsotg *hsotg) val |= hsotg->params.lpm_clock_gating ? GLPMCFG_ENBLSLPM : 0; val |= hsotg->params.hird_threshold << GLPMCFG_HIRD_THRES_SHIFT; val |= hsotg->params.besl ? GLPMCFG_ENBESL : 0; - dwc2_writel(val, hsotg->regs + GLPMCFG); - dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg->regs - + GLPMCFG)); + dwc2_writel(hsotg, val, GLPMCFG); + dev_dbg(hsotg->dev, "GLPMCFG=0x%08x\n", dwc2_readl(hsotg, GLPMCFG)); } /** @@ -4989,40 +4976,40 @@ int dwc2_gadget_enter_hibernation(struct dwc2_hsotg *hsotg) gpwrdn = GPWRDN_PWRDNRSTN; gpwrdn |= GPWRDN_PMUACTV; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); /* Set flag to indicate that we are in hibernation */ hsotg->hibernated = 1; /* Enable interrupts from wake up logic */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn |= GPWRDN_PMUINTSEL; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); /* Unmask device mode interrupts in GPWRDN */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn |= GPWRDN_RST_DET_MSK; gpwrdn |= GPWRDN_LNSTSCHG_MSK; gpwrdn |= GPWRDN_STS_CHGINT_MSK; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); /* Enable Power Down Clamp */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn |= GPWRDN_PWRDNCLMP; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); /* Switch off VDD */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn |= GPWRDN_PWRDNSWTCH; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); /* Save gpwrdn register for further usage if stschng interrupt */ - hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + hsotg->gr_backup.gpwrdn = dwc2_readl(hsotg, GPWRDN); dev_dbg(hsotg->dev, "Hibernation completed\n"); return ret; @@ -5064,46 +5051,46 @@ int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, if (!reset) { /* Clear all pending interupts */ - dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, 0xffffffff, GINTSTS); } /* De-assert Restore */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn &= ~GPWRDN_RESTORE; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); if (!rem_wakeup) { - pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgcctl = dwc2_readl(hsotg, PCGCTL); pcgcctl &= ~PCGCTL_RSTPDWNMODULE; - dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgcctl, PCGCTL); } /* Restore GUSBCFG, DCFG and DCTL */ - dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); - dwc2_writel(dr->dcfg, hsotg->regs + DCFG); - dwc2_writel(dr->dctl, hsotg->regs + DCTL); + dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); + dwc2_writel(hsotg, dr->dcfg, DCFG); + dwc2_writel(hsotg, dr->dctl, DCTL); /* De-assert Wakeup Logic */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn &= ~GPWRDN_PMUACTV; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); if (rem_wakeup) { udelay(10); /* Start Remote Wakeup Signaling */ - dwc2_writel(dr->dctl | DCTL_RMTWKUPSIG, hsotg->regs + DCTL); + dwc2_writel(hsotg, dr->dctl | DCTL_RMTWKUPSIG, DCTL); } else { udelay(50); /* Set Device programming done bit */ - dctl = dwc2_readl(hsotg->regs + DCTL); + dctl = dwc2_readl(hsotg, DCTL); dctl |= DCTL_PWRONPRGDONE; - dwc2_writel(dctl, hsotg->regs + DCTL); + dwc2_writel(hsotg, dctl, DCTL); } /* Wait for interrupts which must be cleared */ mdelay(2); /* Clear all pending interupts */ - dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, 0xffffffff, GINTSTS); /* Restore global registers */ ret = dwc2_restore_global_registers(hsotg); @@ -5123,9 +5110,9 @@ int dwc2_gadget_exit_hibernation(struct dwc2_hsotg *hsotg, if (rem_wakeup) { mdelay(10); - dctl = dwc2_readl(hsotg->regs + DCTL); + dctl = dwc2_readl(hsotg, DCTL); dctl &= ~DCTL_RMTWKUPSIG; - dwc2_writel(dctl, hsotg->regs + DCTL); + dwc2_writel(hsotg, dctl, DCTL); } hsotg->hibernated = 0; diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index 6e2cdd7b93d4..2bd6e6bfc241 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -75,10 +75,10 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) u32 intmsk; /* Clear any pending OTG Interrupts */ - dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); + dwc2_writel(hsotg, 0xffffffff, GOTGINT); /* Clear any pending interrupts */ - dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, 0xffffffff, GINTSTS); /* Enable the interrupts in the GINTMSK */ intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; @@ -94,7 +94,7 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg) if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm) intmsk |= GINTSTS_LPMTRANRCVD; - dwc2_writel(intmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, intmsk, GINTMSK); } /* @@ -117,10 +117,10 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) } dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); - hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg = dwc2_readl(hsotg, HCFG); hcfg &= ~HCFG_FSLSPCLKSEL_MASK; hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; - dwc2_writel(hcfg, hsotg->regs + HCFG); + dwc2_writel(hsotg, hcfg, HCFG); } static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) @@ -135,10 +135,10 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) if (select_phy) { dev_dbg(hsotg->dev, "FS PHY selected\n"); - usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg = dwc2_readl(hsotg, GUSBCFG); if (!(usbcfg & GUSBCFG_PHYSEL)) { usbcfg |= GUSBCFG_PHYSEL; - dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + dwc2_writel(hsotg, usbcfg, GUSBCFG); /* Reset after a PHY select */ retval = dwc2_core_reset(hsotg, false); @@ -151,7 +151,7 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) } if (hsotg->params.activate_stm_fs_transceiver) { - ggpio = dwc2_readl(hsotg->regs + GGPIO); + ggpio = dwc2_readl(hsotg, GGPIO); if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) { dev_dbg(hsotg->dev, "Activating transceiver\n"); /* @@ -159,7 +159,7 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) * core configuration register. */ ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN; - dwc2_writel(ggpio, hsotg->regs + GGPIO); + dwc2_writel(hsotg, ggpio, GGPIO); } } } @@ -176,18 +176,18 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); /* Program GUSBCFG.OtgUtmiFsSel to I2C */ - usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg = dwc2_readl(hsotg, GUSBCFG); usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; - dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + dwc2_writel(hsotg, usbcfg, GUSBCFG); /* Program GI2CCTL.I2CEn */ - i2cctl = dwc2_readl(hsotg->regs + GI2CCTL); + i2cctl = dwc2_readl(hsotg, GI2CCTL); i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; i2cctl &= ~GI2CCTL_I2CEN; - dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); + dwc2_writel(hsotg, i2cctl, GI2CCTL); i2cctl |= GI2CCTL_I2CEN; - dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); + dwc2_writel(hsotg, i2cctl, GI2CCTL); } return retval; @@ -201,7 +201,7 @@ static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) if (!select_phy) return 0; - usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg = dwc2_readl(hsotg, GUSBCFG); usbcfg_old = usbcfg; /* @@ -236,7 +236,7 @@ static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) } if (usbcfg != usbcfg_old) { - dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + dwc2_writel(hsotg, usbcfg, GUSBCFG); /* Reset after setting the PHY parameters */ retval = dwc2_core_reset(hsotg, false); @@ -273,15 +273,15 @@ static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && hsotg->params.ulpi_fs_ls) { dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); - usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg = dwc2_readl(hsotg, GUSBCFG); usbcfg |= GUSBCFG_ULPI_FS_LS; usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; - dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + dwc2_writel(hsotg, usbcfg, GUSBCFG); } else { - usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg = dwc2_readl(hsotg, GUSBCFG); usbcfg &= ~GUSBCFG_ULPI_FS_LS; usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; - dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + dwc2_writel(hsotg, usbcfg, GUSBCFG); } return retval; @@ -289,7 +289,7 @@ static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) { - u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG); switch (hsotg->hw_params.arch) { case GHWCFG2_EXT_DMA_ARCH: @@ -316,7 +316,7 @@ static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) else hsotg->params.dma_desc_enable = false; - dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); + dwc2_writel(hsotg, ahbcfg, GAHBCFG); return 0; } @@ -325,7 +325,7 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) { u32 usbcfg; - usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg = dwc2_readl(hsotg, GUSBCFG); usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); switch (hsotg->hw_params.op_mode) { @@ -353,7 +353,7 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) break; } - dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + dwc2_writel(hsotg, usbcfg, GUSBCFG); } static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg) @@ -390,16 +390,16 @@ static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) dev_dbg(hsotg->dev, "%s()\n", __func__); /* Disable all interrupts */ - dwc2_writel(0, hsotg->regs + GINTMSK); - dwc2_writel(0, hsotg->regs + HAINTMSK); + dwc2_writel(hsotg, 0, GINTMSK); + dwc2_writel(hsotg, 0, HAINTMSK); /* Enable the common interrupts */ dwc2_enable_common_interrupts(hsotg); /* Enable host mode interrupts without disturbing common interrupts */ - intmsk = dwc2_readl(hsotg->regs + GINTMSK); + intmsk = dwc2_readl(hsotg, GINTMSK); intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; - dwc2_writel(intmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, intmsk, GINTMSK); } /** @@ -409,12 +409,12 @@ static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) */ static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) { - u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); + u32 intmsk = dwc2_readl(hsotg, GINTMSK); /* Disable host mode interrupts without disturbing common interrupts */ intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT); - dwc2_writel(intmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, intmsk, GINTMSK); } /* @@ -494,37 +494,37 @@ static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) dwc2_calculate_dynamic_fifo(hsotg); /* Rx FIFO */ - grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); + grxfsiz = dwc2_readl(hsotg, GRXFSIZ); dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); grxfsiz &= ~GRXFSIZ_DEPTH_MASK; grxfsiz |= params->host_rx_fifo_size << GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; - dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); + dwc2_writel(hsotg, grxfsiz, GRXFSIZ); dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", - dwc2_readl(hsotg->regs + GRXFSIZ)); + dwc2_readl(hsotg, GRXFSIZ)); /* Non-periodic Tx FIFO */ dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", - dwc2_readl(hsotg->regs + GNPTXFSIZ)); + dwc2_readl(hsotg, GNPTXFSIZ)); nptxfsiz = params->host_nperio_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; nptxfsiz |= params->host_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; - dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); + dwc2_writel(hsotg, nptxfsiz, GNPTXFSIZ); dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", - dwc2_readl(hsotg->regs + GNPTXFSIZ)); + dwc2_readl(hsotg, GNPTXFSIZ)); /* Periodic Tx FIFO */ dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", - dwc2_readl(hsotg->regs + HPTXFSIZ)); + dwc2_readl(hsotg, HPTXFSIZ)); hptxfsiz = params->host_perio_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; hptxfsiz |= (params->host_rx_fifo_size + params->host_nperio_tx_fifo_size) << FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; - dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); + dwc2_writel(hsotg, hptxfsiz, HPTXFSIZ); dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", - dwc2_readl(hsotg->regs + HPTXFSIZ)); + dwc2_readl(hsotg, HPTXFSIZ)); if (hsotg->params.en_multiple_tx_fifo && hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) { @@ -533,14 +533,14 @@ static void dwc2_config_fifos(struct dwc2_hsotg *hsotg) * Global DFIFOCFG calculation for Host mode - * include RxFIFO, NPTXFIFO and HPTXFIFO */ - dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); + dfifocfg = dwc2_readl(hsotg, GDFIFOCFG); dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; dfifocfg |= (params->host_rx_fifo_size + params->host_nperio_tx_fifo_size + params->host_perio_tx_fifo_size) << GDFIFOCFG_EPINFOBASE_SHIFT & GDFIFOCFG_EPINFOBASE_MASK; - dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); + dwc2_writel(hsotg, dfifocfg, GDFIFOCFG); } } @@ -560,8 +560,8 @@ u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) u32 hprt0; int clock = 60; /* default value */ - usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); - hprt0 = dwc2_readl(hsotg->regs + HPRT0); + usbcfg = dwc2_readl(hsotg, GUSBCFG); + hprt0 = dwc2_readl(hsotg, HPRT0); if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16)) @@ -603,7 +603,6 @@ u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg) */ void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) { - u32 __iomem *fifo = hsotg->regs + HCFIFO(0); u32 *data_buf = (u32 *)dest; int word_count = (bytes + 3) / 4; int i; @@ -617,7 +616,7 @@ void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes) dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); for (i = 0; i < word_count; i++, data_buf++) - *data_buf = dwc2_readl(fifo); + *data_buf = dwc2_readl(hsotg, HCFIFO(0)); } /** @@ -646,10 +645,10 @@ static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg, if (!chan) return; - hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); - hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); - hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); - hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); + hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); + hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num)); + hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num)); + hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num)); dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", @@ -797,7 +796,7 @@ static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg, break; } - dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); + dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num)); if (dbg_hc(chan)) dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); } @@ -834,7 +833,7 @@ static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg, } } - dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); + dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num)); if (dbg_hc(chan)) dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); } @@ -855,16 +854,16 @@ static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg, } /* Enable the top level host channel interrupt */ - intmsk = dwc2_readl(hsotg->regs + HAINTMSK); + intmsk = dwc2_readl(hsotg, HAINTMSK); intmsk |= 1 << chan->hc_num; - dwc2_writel(intmsk, hsotg->regs + HAINTMSK); + dwc2_writel(hsotg, intmsk, HAINTMSK); if (dbg_hc(chan)) dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); /* Make sure host channel interrupts are enabled */ - intmsk = dwc2_readl(hsotg->regs + GINTMSK); + intmsk = dwc2_readl(hsotg, GINTMSK); intmsk |= GINTSTS_HCHINT; - dwc2_writel(intmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, intmsk, GINTMSK); if (dbg_hc(chan)) dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); } @@ -893,7 +892,7 @@ static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) /* Clear old interrupt conditions for this host channel */ hcintmsk = 0xffffffff; hcintmsk &= ~HCINTMSK_RESERVED14_31; - dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); + dwc2_writel(hsotg, hcintmsk, HCINT(hc_num)); /* Enable channel interrupts required for this transfer */ dwc2_hc_enable_ints(hsotg, chan); @@ -910,7 +909,7 @@ static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) hcchar |= HCCHAR_LSPDDEV; hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; - dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); + dwc2_writel(hsotg, hcchar, HCCHAR(hc_num)); if (dbg_hc(chan)) { dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", hc_num, hcchar); @@ -964,7 +963,7 @@ static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) } } - dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); + dwc2_writel(hsotg, hcsplt, HCSPLT(hc_num)); } /** @@ -1034,14 +1033,14 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, u32 hcintmsk = HCINTMSK_CHHLTD; dev_vdbg(hsotg->dev, "dequeue/error\n"); - dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); + dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num)); /* * Make sure no other interrupts besides halt are currently * pending. Handling another interrupt could cause a crash due * to the QTD and QH state. */ - dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); + dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num)); /* * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR @@ -1050,7 +1049,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, */ chan->halt_status = halt_status; - hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); if (!(hcchar & HCCHAR_CHENA)) { /* * The channel is either already halted or it hasn't @@ -1078,7 +1077,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, return; } - hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); /* No need to set the bit in DDMA for disabling the channel */ /* TODO check it everywhere channel is disabled */ @@ -1101,7 +1100,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || chan->ep_type == USB_ENDPOINT_XFER_BULK) { dev_vdbg(hsotg->dev, "control/bulk\n"); - nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); + nptxsts = dwc2_readl(hsotg, GNPTXSTS); if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { dev_vdbg(hsotg->dev, "Disabling channel\n"); hcchar &= ~HCCHAR_CHENA; @@ -1109,7 +1108,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, } else { if (dbg_perio()) dev_vdbg(hsotg->dev, "isoc/intr\n"); - hptxsts = dwc2_readl(hsotg->regs + HPTXSTS); + hptxsts = dwc2_readl(hsotg, HPTXSTS); if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || hsotg->queuing_high_bandwidth) { if (dbg_perio()) @@ -1122,7 +1121,7 @@ void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, dev_vdbg(hsotg->dev, "DMA enabled\n"); } - dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); chan->halt_status = halt_status; if (hcchar & HCCHAR_CHENA) { @@ -1171,10 +1170,10 @@ void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) * Clear channel interrupt enables and any unhandled channel interrupt * conditions */ - dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); + dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num)); hcintmsk = 0xffffffff; hcintmsk &= ~HCINTMSK_RESERVED14_31; - dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); + dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num)); } /** @@ -1228,7 +1227,7 @@ static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg, !chan->do_split) ? chan->speed : USB_SPEED_HIGH; /* See how many bytes are in the periodic FIFO right now */ - fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) & + fifo_space = (dwc2_readl(hsotg, HPTXSTS) & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT; bytes_in_fifo = sizeof(u32) * (hsotg->params.host_perio_tx_fifo_size - @@ -1348,13 +1347,13 @@ static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg, if (((unsigned long)data_buf & 0x3) == 0) { /* xfer_buf is DWORD aligned */ for (i = 0; i < dword_count; i++, data_buf++) - dwc2_writel(*data_buf, data_fifo); + dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num)); } else { /* xfer_buf is not DWORD aligned */ for (i = 0; i < dword_count; i++, data_buf++) { u32 data = data_buf[0] | data_buf[1] << 8 | data_buf[2] << 16 | data_buf[3] << 24; - dwc2_writel(data, data_fifo); + dwc2_writel(hsotg, data, HCFIFO(chan->hc_num)); } } @@ -1383,12 +1382,12 @@ static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, hctsiz = TSIZ_DOPNG; hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; - dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); + dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num)); - hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); hcchar |= HCCHAR_CHENA; hcchar &= ~HCCHAR_CHDIS; - dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); } /** @@ -1548,7 +1547,7 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & TSIZ_SC_MC_PID_MASK; - dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); + dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num)); if (dbg_hc(chan)) { dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", hctsiz, chan->hc_num); @@ -1576,7 +1575,7 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, } else { dma_addr = chan->xfer_dma; } - dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num)); + dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num)); if (dbg_hc(chan)) dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", @@ -1585,13 +1584,13 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, /* Start the split */ if (chan->do_split) { - u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); + u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num)); hcsplt |= HCSPLT_SPLTENA; - dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); + dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num)); } - hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); hcchar &= ~HCCHAR_MULTICNT_MASK; hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK; dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); @@ -1610,7 +1609,7 @@ static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg, (hcchar & HCCHAR_MULTICNT_MASK) >> HCCHAR_MULTICNT_SHIFT); - dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); if (dbg_hc(chan)) dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, chan->hc_num); @@ -1668,18 +1667,18 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); } - dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); + dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num)); dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, chan->desc_list_sz, DMA_TO_DEVICE); - dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num)); + dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num)); if (dbg_hc(chan)) dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", &chan->desc_list_addr, chan->hc_num); - hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); hcchar &= ~HCCHAR_MULTICNT_MASK; hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & HCCHAR_MULTICNT_MASK; @@ -1698,7 +1697,7 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, (hcchar & HCCHAR_MULTICNT_MASK) >> HCCHAR_MULTICNT_SHIFT); - dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); if (dbg_hc(chan)) dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, chan->hc_num); @@ -1755,7 +1754,7 @@ static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, * transfer completes, the extra requests for the channel will * be flushed. */ - u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); hcchar |= HCCHAR_CHENA; @@ -1763,7 +1762,7 @@ static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, if (dbg_hc(chan)) dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", hcchar); - dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num)); chan->requests++; return 1; } @@ -1773,7 +1772,7 @@ static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg, if (chan->xfer_count < chan->xfer_len) { if (chan->ep_type == USB_ENDPOINT_XFER_INT || chan->ep_type == USB_ENDPOINT_XFER_ISOC) { - u32 hcchar = dwc2_readl(hsotg->regs + + u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num)); dwc2_hc_set_even_odd_frame(hsotg, chan, @@ -1887,7 +1886,7 @@ void dwc2_hcd_start(struct dwc2_hsotg *hsotg) */ hprt0 = dwc2_read_hprt0(hsotg); hprt0 |= HPRT0_RST; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); } queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, @@ -1908,11 +1907,11 @@ static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) channel = hsotg->hc_ptr_array[i]; if (!list_empty(&channel->hc_list_entry)) continue; - hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + hcchar = dwc2_readl(hsotg, HCCHAR(i)); if (hcchar & HCCHAR_CHENA) { hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); hcchar |= HCCHAR_CHDIS; - dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + dwc2_writel(hsotg, hcchar, HCCHAR(i)); } } } @@ -1921,11 +1920,11 @@ static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg) channel = hsotg->hc_ptr_array[i]; if (!list_empty(&channel->hc_list_entry)) continue; - hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + hcchar = dwc2_readl(hsotg, HCCHAR(i)); if (hcchar & HCCHAR_CHENA) { /* Halt the channel */ hcchar |= HCCHAR_CHDIS; - dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + dwc2_writel(hsotg, hcchar, HCCHAR(i)); } dwc2_hc_cleanup(hsotg, channel); @@ -1985,11 +1984,11 @@ void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) * interrupt mask and status bits and disabling subsequent host * channel interrupts. */ - intr = dwc2_readl(hsotg->regs + GINTMSK); + intr = dwc2_readl(hsotg, GINTMSK); intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); - dwc2_writel(intr, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, intr, GINTMSK); intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; - dwc2_writel(intr, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, intr, GINTSTS); /* * Turn off the vbus power only if the core has transitioned to device @@ -1999,7 +1998,7 @@ void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) if (dwc2_is_device_mode(hsotg)) { if (hsotg->op_state != OTG_STATE_A_SUSPEND) { dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); - dwc2_writel(0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, 0, HPRT0); } dwc2_disable_host_interrupts(hsotg); @@ -2027,7 +2026,7 @@ void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) * and won't get any future interrupts to handle the connect. */ if (!force) { - hprt0 = dwc2_readl(hsotg->regs + HPRT0); + hprt0 = dwc2_readl(hsotg, HPRT0); if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS)) dwc2_hcd_connect(hsotg); } @@ -2071,7 +2070,7 @@ void dwc2_hcd_stop(struct dwc2_hsotg *hsotg) /* Turn off the vbus power */ dev_dbg(hsotg->dev, "PortPower off\n"); - dwc2_writel(0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, 0, HPRT0); } /* Caller must hold driver lock */ @@ -2095,7 +2094,7 @@ static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, if ((dev_speed == USB_SPEED_LOW) && (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { - u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); + u32 hprt0 = dwc2_readl(hsotg, HPRT0); u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; if (prtspd == HPRT0_SPD_FULL_SPEED) @@ -2114,7 +2113,7 @@ static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, return retval; } - intr_mask = dwc2_readl(hsotg->regs + GINTMSK); + intr_mask = dwc2_readl(hsotg, GINTMSK); if (!(intr_mask & GINTSTS_SOF)) { enum dwc2_transaction_type tr_type; @@ -2279,7 +2278,7 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); - usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg = dwc2_readl(hsotg, GUSBCFG); /* Set ULPI External VBUS bit if needed */ usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; @@ -2291,7 +2290,7 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) if (hsotg->params.ts_dline) usbcfg |= GUSBCFG_TERMSELDLPULSE; - dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + dwc2_writel(hsotg, usbcfg, GUSBCFG); /* * Reset the Controller @@ -2325,9 +2324,9 @@ int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup) dwc2_gusbcfg_init(hsotg); /* Program the GOTGCTL register */ - otgctl = dwc2_readl(hsotg->regs + GOTGCTL); + otgctl = dwc2_readl(hsotg, GOTGCTL); otgctl &= ~GOTGCTL_OTGVER; - dwc2_writel(otgctl, hsotg->regs + GOTGCTL); + dwc2_writel(hsotg, otgctl, GOTGCTL); /* Clear the SRP success bit for FS-I2c */ hsotg->srp_success = 0; @@ -2374,20 +2373,20 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) * introduced by the PHY in generating the linestate condition * can vary from one PHY to another. */ - usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg = dwc2_readl(hsotg, GUSBCFG); usbcfg |= GUSBCFG_TOUTCAL(7); - dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + dwc2_writel(hsotg, usbcfg, GUSBCFG); /* Restart the Phy Clock */ - dwc2_writel(0, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, 0, PCGCTL); /* Initialize Host Configuration Register */ dwc2_init_fs_ls_pclk_sel(hsotg); if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL || hsotg->params.speed == DWC2_SPEED_PARAM_LOW) { - hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg = dwc2_readl(hsotg, HCFG); hcfg |= HCFG_FSLSSUPP; - dwc2_writel(hcfg, hsotg->regs + HCFG); + dwc2_writel(hsotg, hcfg, HCFG); } /* @@ -2396,9 +2395,9 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) * and its value must not be changed during runtime. */ if (hsotg->params.reload_ctl) { - hfir = dwc2_readl(hsotg->regs + HFIR); + hfir = dwc2_readl(hsotg, HFIR); hfir |= HFIR_RLDCTRL; - dwc2_writel(hfir, hsotg->regs + HFIR); + dwc2_writel(hsotg, hfir, HFIR); } if (hsotg->params.dma_desc_enable) { @@ -2415,9 +2414,9 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) "falling back to buffer DMA mode.\n"); hsotg->params.dma_desc_enable = false; } else { - hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg = dwc2_readl(hsotg, HCFG); hcfg |= HCFG_DESCDMA; - dwc2_writel(hcfg, hsotg->regs + HCFG); + dwc2_writel(hsotg, hcfg, HCFG); } } @@ -2426,18 +2425,18 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) /* TODO - check this */ /* Clear Host Set HNP Enable in the OTG Control Register */ - otgctl = dwc2_readl(hsotg->regs + GOTGCTL); + otgctl = dwc2_readl(hsotg, GOTGCTL); otgctl &= ~GOTGCTL_HSTSETHNPEN; - dwc2_writel(otgctl, hsotg->regs + GOTGCTL); + dwc2_writel(hsotg, otgctl, GOTGCTL); /* Make sure the FIFOs are flushed */ dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); dwc2_flush_rx_fifo(hsotg); /* Clear Host Set HNP Enable in the OTG Control Register */ - otgctl = dwc2_readl(hsotg->regs + GOTGCTL); + otgctl = dwc2_readl(hsotg, GOTGCTL); otgctl &= ~GOTGCTL_HSTSETHNPEN; - dwc2_writel(otgctl, hsotg->regs + GOTGCTL); + dwc2_writel(hsotg, otgctl, GOTGCTL); if (!hsotg->params.dma_desc_enable) { int num_channels, i; @@ -2446,19 +2445,19 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) /* Flush out any leftover queued requests */ num_channels = hsotg->params.host_channels; for (i = 0; i < num_channels; i++) { - hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + hcchar = dwc2_readl(hsotg, HCCHAR(i)); hcchar &= ~HCCHAR_CHENA; hcchar |= HCCHAR_CHDIS; hcchar &= ~HCCHAR_EPDIR; - dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + dwc2_writel(hsotg, hcchar, HCCHAR(i)); } /* Halt all channels to put them into a known state */ for (i = 0; i < num_channels; i++) { - hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + hcchar = dwc2_readl(hsotg, HCCHAR(i)); hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; hcchar &= ~HCCHAR_EPDIR; - dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + dwc2_writel(hsotg, hcchar, HCCHAR(i)); dev_dbg(hsotg->dev, "%s: Halt channel %d\n", __func__, i); @@ -2482,7 +2481,7 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg) !!(hprt0 & HPRT0_PWR)); if (!(hprt0 & HPRT0_PWR)) { hprt0 |= HPRT0_PWR; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); } } @@ -3084,7 +3083,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) if (dbg_perio()) dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); - tx_status = dwc2_readl(hsotg->regs + HPTXSTS); + tx_status = dwc2_readl(hsotg, HPTXSTS); qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT; fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> @@ -3099,7 +3098,7 @@ static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg) qh_ptr = hsotg->periodic_sched_assigned.next; while (qh_ptr != &hsotg->periodic_sched_assigned) { - tx_status = dwc2_readl(hsotg->regs + HPTXSTS); + tx_status = dwc2_readl(hsotg, HPTXSTS); qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT; if (qspcavail == 0) { @@ -3169,10 +3168,10 @@ exit: * level to ensure that new requests are loaded as * soon as possible.) */ - gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk = dwc2_readl(hsotg, GINTMSK); if (!(gintmsk & GINTSTS_PTXFEMP)) { gintmsk |= GINTSTS_PTXFEMP; - dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, gintmsk, GINTMSK); } } else { /* @@ -3182,10 +3181,10 @@ exit: * handlers to queue more transactions as transfer * states change. */ - gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk = dwc2_readl(hsotg, GINTMSK); if (gintmsk & GINTSTS_PTXFEMP) { gintmsk &= ~GINTSTS_PTXFEMP; - dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, gintmsk, GINTMSK); } } } @@ -3214,7 +3213,7 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); - tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + tx_status = dwc2_readl(hsotg, GNPTXSTS); qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT; fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> @@ -3237,7 +3236,7 @@ static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg) * available in the request queue or the Tx FIFO */ do { - tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + tx_status = dwc2_readl(hsotg, GNPTXSTS); qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT; if (!hsotg->params.host_dma && qspcavail == 0) { @@ -3274,7 +3273,7 @@ next: } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); if (!hsotg->params.host_dma) { - tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + tx_status = dwc2_readl(hsotg, GNPTXSTS); qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT; fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> @@ -3294,9 +3293,9 @@ next: * level to ensure that new requests are loaded as * soon as possible.) */ - gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk = dwc2_readl(hsotg, GINTMSK); gintmsk |= GINTSTS_NPTXFEMP; - dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, gintmsk, GINTMSK); } else { /* * Disable the Tx FIFO empty interrupt since there are @@ -3305,9 +3304,9 @@ next: * handlers to queue more transactions as transfer * states change. */ - gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk = dwc2_readl(hsotg, GINTMSK); gintmsk &= ~GINTSTS_NPTXFEMP; - dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, gintmsk, GINTMSK); } } } @@ -3344,10 +3343,10 @@ void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg, * Ensure NP Tx FIFO empty interrupt is disabled when * there are no non-periodic transfers to process */ - u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + u32 gintmsk = dwc2_readl(hsotg, GINTMSK); gintmsk &= ~GINTSTS_NPTXFEMP; - dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, gintmsk, GINTMSK); } } } @@ -3362,7 +3361,7 @@ static void dwc2_conn_id_status_change(struct work_struct *work) dev_dbg(hsotg->dev, "%s()\n", __func__); - gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl = dwc2_readl(hsotg, GOTGCTL); dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", !!(gotgctl & GOTGCTL_CONID_B)); @@ -3388,7 +3387,7 @@ static void dwc2_conn_id_status_change(struct work_struct *work) * check it again and jump to host mode if that was * the case. */ - gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl = dwc2_readl(hsotg, GOTGCTL); if (!(gotgctl & GOTGCTL_CONID_B)) goto host; if (++count > 250) @@ -3448,9 +3447,9 @@ static void dwc2_wakeup_detected(struct timer_list *t) hprt0 = dwc2_read_hprt0(hsotg); dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); hprt0 &= ~HPRT0_RES; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", - dwc2_readl(hsotg->regs + HPRT0)); + dwc2_readl(hsotg, HPRT0)); dwc2_hcd_rem_wakeup(hsotg); hsotg->bus_suspended = false; @@ -3479,15 +3478,15 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) spin_lock_irqsave(&hsotg->lock, flags); if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { - gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl = dwc2_readl(hsotg, GOTGCTL); gotgctl |= GOTGCTL_HSTSETHNPEN; - dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + dwc2_writel(hsotg, gotgctl, GOTGCTL); hsotg->op_state = OTG_STATE_A_SUSPEND; } hprt0 = dwc2_read_hprt0(hsotg); hprt0 |= HPRT0_SUSP; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); hsotg->bus_suspended = true; @@ -3497,17 +3496,17 @@ static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex) */ if (!hsotg->params.power_down) { /* Suspend the Phy Clock */ - pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl = dwc2_readl(hsotg, PCGCTL); pcgctl |= PCGCTL_STOPPCLK; - dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgctl, PCGCTL); udelay(10); } /* For HNP the bus must be suspended for at least 200ms */ if (dwc2_host_is_b_hnp_enabled(hsotg)) { - pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl = dwc2_readl(hsotg, PCGCTL); pcgctl &= ~PCGCTL_STOPPCLK; - dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgctl, PCGCTL); spin_unlock_irqrestore(&hsotg->lock, flags); @@ -3531,9 +3530,9 @@ static void dwc2_port_resume(struct dwc2_hsotg *hsotg) * after registers restore. */ if (!hsotg->params.power_down) { - pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl = dwc2_readl(hsotg, PCGCTL); pcgctl &= ~PCGCTL_STOPPCLK; - dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgctl, PCGCTL); spin_unlock_irqrestore(&hsotg->lock, flags); msleep(20); spin_lock_irqsave(&hsotg->lock, flags); @@ -3542,7 +3541,7 @@ static void dwc2_port_resume(struct dwc2_hsotg *hsotg) hprt0 = dwc2_read_hprt0(hsotg); hprt0 |= HPRT0_RES; hprt0 &= ~HPRT0_SUSP; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); spin_unlock_irqrestore(&hsotg->lock, flags); msleep(USB_RESUME_TIMEOUT); @@ -3550,7 +3549,7 @@ static void dwc2_port_resume(struct dwc2_hsotg *hsotg) spin_lock_irqsave(&hsotg->lock, flags); hprt0 = dwc2_read_hprt0(hsotg); hprt0 &= ~(HPRT0_RES | HPRT0_SUSP); - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); hsotg->bus_suspended = false; spin_unlock_irqrestore(&hsotg->lock, flags); } @@ -3594,7 +3593,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); hprt0 = dwc2_read_hprt0(hsotg); hprt0 |= HPRT0_ENA; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); break; case USB_PORT_FEAT_SUSPEND: @@ -3614,7 +3613,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, "ClearPortFeature USB_PORT_FEAT_POWER\n"); hprt0 = dwc2_read_hprt0(hsotg); hprt0 &= ~HPRT0_PWR; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); break; case USB_PORT_FEAT_INDICATOR: @@ -3735,7 +3734,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, break; } - hprt0 = dwc2_readl(hsotg->regs + HPRT0); + hprt0 = dwc2_readl(hsotg, HPRT0); dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); if (hprt0 & HPRT0_CONNSTS) @@ -3776,9 +3775,9 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, dev_info(hsotg->dev, "Enabling descriptor DMA mode\n"); hsotg->params.dma_desc_enable = true; - hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg = dwc2_readl(hsotg, HCFG); hcfg |= HCFG_DESCDMA; - dwc2_writel(hcfg, hsotg->regs + HCFG); + dwc2_writel(hsotg, hcfg, HCFG); hsotg->new_connection = false; } } @@ -3825,7 +3824,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, "SetPortFeature - USB_PORT_FEAT_POWER\n"); hprt0 = dwc2_read_hprt0(hsotg); hprt0 |= HPRT0_PWR; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); break; case USB_PORT_FEAT_RESET: @@ -3835,11 +3834,11 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, hprt0 = dwc2_read_hprt0(hsotg); dev_dbg(hsotg->dev, "SetPortFeature - USB_PORT_FEAT_RESET\n"); - pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl = dwc2_readl(hsotg, PCGCTL); pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); - dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgctl, PCGCTL); /* ??? Original driver does this */ - dwc2_writel(0, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, 0, PCGCTL); hprt0 = dwc2_read_hprt0(hsotg); /* Clear suspend bit if resetting from suspend state */ @@ -3854,13 +3853,13 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, hprt0 |= HPRT0_PWR | HPRT0_RST; dev_dbg(hsotg->dev, "In host mode, hprt0=%08x\n", hprt0); - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); } /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ msleep(50); hprt0 &= ~HPRT0_RST; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); hsotg->lx_state = DWC2_L0; /* Now back to On state */ break; @@ -3876,7 +3875,7 @@ static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq, "SetPortFeature - USB_PORT_FEAT_TEST\n"); hprt0 &= ~HPRT0_TSTCTL_MASK; hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); break; default: @@ -3933,7 +3932,7 @@ static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port) int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) { - u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); + u32 hfnum = dwc2_readl(hsotg, HFNUM); #ifdef DWC2_DEBUG_SOF dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", @@ -3944,9 +3943,9 @@ int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us) { - u32 hprt = dwc2_readl(hsotg->regs + HPRT0); - u32 hfir = dwc2_readl(hsotg->regs + HFIR); - u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); + u32 hprt = dwc2_readl(hsotg, HPRT0); + u32 hfir = dwc2_readl(hsotg, HFIR); + u32 hfnum = dwc2_readl(hsotg, HFNUM); unsigned int us_per_frame; unsigned int frame_number; unsigned int remaining; @@ -4065,11 +4064,11 @@ void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) if (chan->xfer_started) { u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; - hfnum = dwc2_readl(hsotg->regs + HFNUM); - hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); - hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); - hcint = dwc2_readl(hsotg->regs + HCINT(i)); - hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); + hfnum = dwc2_readl(hsotg, HFNUM); + hcchar = dwc2_readl(hsotg, HCCHAR(i)); + hctsiz = dwc2_readl(hsotg, HCTSIZ(i)); + hcint = dwc2_readl(hsotg, HCINT(i)); + hcintmsk = dwc2_readl(hsotg, HCINTMSK(i)); dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); @@ -4117,12 +4116,12 @@ void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg) dev_dbg(hsotg->dev, " periodic_channels: %d\n", hsotg->periodic_channels); dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); - np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + np_tx_status = dwc2_readl(hsotg, GNPTXSTS); dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); - p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); + p_tx_status = dwc2_readl(hsotg, HPTXSTS); dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", @@ -4372,7 +4371,7 @@ static void dwc2_hcd_reset_func(struct work_struct *work) hprt0 = dwc2_read_hprt0(hsotg); hprt0 &= ~HPRT0_RST; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); hsotg->flags.b.port_reset_change = 1; spin_unlock_irqrestore(&hsotg->lock, flags); @@ -4482,7 +4481,7 @@ static int _dwc2_hcd_suspend(struct usb_hcd *hcd) hprt0 = dwc2_read_hprt0(hsotg); hprt0 |= HPRT0_SUSP; hprt0 &= ~HPRT0_PWR; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); dwc2_vbus_supply_exit(hsotg); } @@ -4573,8 +4572,8 @@ static int _dwc2_hcd_resume(struct usb_hcd *hcd) * Clear Port Enable and Port Status changes. * Enable Port Power. */ - dwc2_writel(HPRT0_PWR | HPRT0_CONNDET | - HPRT0_ENACHG, hsotg->regs + HPRT0); + dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET | + HPRT0_ENACHG, HPRT0); /* Wait for controller to detect Port Connect */ usleep_range(5000, 7000); } @@ -5094,17 +5093,17 @@ static void dwc2_hcd_free(struct dwc2_hsotg *hsotg) hsotg->status_buf = NULL; } - ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + ahbcfg = dwc2_readl(hsotg, GAHBCFG); /* Disable all interrupts */ ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; - dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); - dwc2_writel(0, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, ahbcfg, GAHBCFG); + dwc2_writel(hsotg, 0, GINTMSK); if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { - dctl = dwc2_readl(hsotg->regs + DCTL); + dctl = dwc2_readl(hsotg, DCTL); dctl |= DCTL_SFTDISCON; - dwc2_writel(dctl, hsotg->regs + DCTL); + dwc2_writel(hsotg, dctl, DCTL); } if (hsotg->wq_otg) { @@ -5147,7 +5146,7 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg) retval = -ENOMEM; - hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg = dwc2_readl(hsotg, HCFG); dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS @@ -5437,14 +5436,14 @@ int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg) /* Backup Host regs */ hr = &hsotg->hr_backup; - hr->hcfg = dwc2_readl(hsotg->regs + HCFG); - hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); + hr->hcfg = dwc2_readl(hsotg, HCFG); + hr->haintmsk = dwc2_readl(hsotg, HAINTMSK); for (i = 0; i < hsotg->params.host_channels; ++i) - hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i)); + hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i)); hr->hprt0 = dwc2_read_hprt0(hsotg); - hr->hfir = dwc2_readl(hsotg->regs + HFIR); - hr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); + hr->hfir = dwc2_readl(hsotg, HFIR); + hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); hr->valid = true; return 0; @@ -5473,15 +5472,15 @@ int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg) } hr->valid = false; - dwc2_writel(hr->hcfg, hsotg->regs + HCFG); - dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK); + dwc2_writel(hsotg, hr->hcfg, HCFG); + dwc2_writel(hsotg, hr->haintmsk, HAINTMSK); for (i = 0; i < hsotg->params.host_channels; ++i) - dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i)); + dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i)); - dwc2_writel(hr->hprt0, hsotg->regs + HPRT0); - dwc2_writel(hr->hfir, hsotg->regs + HFIR); - dwc2_writel(hr->hptxfsiz, hsotg->regs + HPTXFSIZ); + dwc2_writel(hsotg, hr->hprt0, HPRT0); + dwc2_writel(hsotg, hr->hfir, HFIR); + dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ); hsotg->frame_number = 0; return 0; @@ -5516,10 +5515,10 @@ int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) } /* Enter USB Suspend Mode */ - hprt0 = dwc2_readl(hsotg->regs + HPRT0); + hprt0 = dwc2_readl(hsotg, HPRT0); hprt0 |= HPRT0_SUSP; hprt0 &= ~HPRT0_ENA; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); /* Wait for the HPRT0.PrtSusp register field to be set */ if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000)) @@ -5532,56 +5531,56 @@ int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg) spin_lock_irqsave(&hsotg->lock, flags); hsotg->lx_state = DWC2_L2; - gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg = dwc2_readl(hsotg, GUSBCFG); if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */ /* Suspend the Phy Clock */ - pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgcctl = dwc2_readl(hsotg, PCGCTL); pcgcctl |= PCGCTL_STOPPCLK; - dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgcctl, PCGCTL); udelay(10); - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn |= GPWRDN_PMUACTV; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); } else { /* UTMI+ Interface */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn |= GPWRDN_PMUACTV; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); - pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgcctl = dwc2_readl(hsotg, PCGCTL); pcgcctl |= PCGCTL_STOPPCLK; - dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + dwc2_writel(hsotg, pcgcctl, PCGCTL); udelay(10); } /* Enable interrupts from wake up logic */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn |= GPWRDN_PMUINTSEL; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); /* Unmask host mode interrupts in GPWRDN */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn |= GPWRDN_DISCONN_DET_MSK; gpwrdn |= GPWRDN_LNSTSCHG_MSK; gpwrdn |= GPWRDN_STS_CHGINT_MSK; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); /* Enable Power Down Clamp */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn |= GPWRDN_PWRDNCLMP; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); /* Switch off VDD */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn |= GPWRDN_PWRDNSWTCH; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); hsotg->hibernated = 1; hsotg->bus_suspended = 1; @@ -5629,29 +5628,29 @@ int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, mdelay(100); /* Clear all pending interupts */ - dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, 0xffffffff, GINTSTS); /* De-assert Restore */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn &= ~GPWRDN_RESTORE; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); /* Restore GUSBCFG, HCFG */ - dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG); - dwc2_writel(hr->hcfg, hsotg->regs + HCFG); + dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG); + dwc2_writel(hsotg, hr->hcfg, HCFG); /* De-assert Wakeup Logic */ - gpwrdn = dwc2_readl(hsotg->regs + GPWRDN); + gpwrdn = dwc2_readl(hsotg, GPWRDN); gpwrdn &= ~GPWRDN_PMUACTV; - dwc2_writel(gpwrdn, hsotg->regs + GPWRDN); + dwc2_writel(hsotg, gpwrdn, GPWRDN); udelay(10); hprt0 = hr->hprt0; hprt0 |= HPRT0_PWR; hprt0 &= ~HPRT0_ENA; hprt0 &= ~HPRT0_SUSP; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); hprt0 = hr->hprt0; hprt0 |= HPRT0_PWR; @@ -5660,32 +5659,32 @@ int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup, if (reset) { hprt0 |= HPRT0_RST; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); /* Wait for Resume time and then program HPRT again */ mdelay(60); hprt0 &= ~HPRT0_RST; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); } else { hprt0 |= HPRT0_RES; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); /* Wait for Resume time and then program HPRT again */ mdelay(100); hprt0 &= ~HPRT0_RES; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); } /* Clear all interrupt status */ - hprt0 = dwc2_readl(hsotg->regs + HPRT0); + hprt0 = dwc2_readl(hsotg, HPRT0); hprt0 |= HPRT0_CONNDET; hprt0 |= HPRT0_ENACHG; hprt0 &= ~HPRT0_ENA; - dwc2_writel(hprt0, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0, HPRT0); - hprt0 = dwc2_readl(hsotg->regs + HPRT0); + hprt0 = dwc2_readl(hsotg, HPRT0); /* Clear all pending interupts */ - dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, 0xffffffff, GINTSTS); /* Restore global registers */ ret = dwc2_restore_global_registers(hsotg); diff --git a/drivers/usb/dwc2/hcd.h b/drivers/usb/dwc2/hcd.h index 5502a501f516..3f9bccc95add 100644 --- a/drivers/usb/dwc2/hcd.h +++ b/drivers/usb/dwc2/hcd.h @@ -469,10 +469,10 @@ static inline struct usb_hcd *dwc2_hsotg_to_hcd(struct dwc2_hsotg *hsotg) */ static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) { - u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); + u32 mask = dwc2_readl(hsotg, HCINTMSK(chnum)); mask &= ~intr; - dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum)); + dwc2_writel(hsotg, mask, HCINTMSK(chnum)); } void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan); @@ -487,7 +487,7 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, */ static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) { - u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); + u32 hprt0 = dwc2_readl(hsotg, HPRT0); hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); return hprt0; @@ -690,8 +690,8 @@ static inline u16 dwc2_micro_frame_num(u16 frame) */ static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) { - return dwc2_readl(hsotg->regs + GINTSTS) & - dwc2_readl(hsotg->regs + GINTMSK); + return dwc2_readl(hsotg, GINTSTS) & + dwc2_readl(hsotg, GINTMSK); } static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) diff --git a/drivers/usb/dwc2/hcd_ddma.c b/drivers/usb/dwc2/hcd_ddma.c index 74f11c823f79..a858b5f9c1d6 100644 --- a/drivers/usb/dwc2/hcd_ddma.c +++ b/drivers/usb/dwc2/hcd_ddma.c @@ -185,19 +185,19 @@ static void dwc2_per_sched_enable(struct dwc2_hsotg *hsotg, u32 fr_list_en) spin_lock_irqsave(&hsotg->lock, flags); - hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg = dwc2_readl(hsotg, HCFG); if (hcfg & HCFG_PERSCHEDENA) { /* already enabled */ spin_unlock_irqrestore(&hsotg->lock, flags); return; } - dwc2_writel(hsotg->frame_list_dma, hsotg->regs + HFLBADDR); + dwc2_writel(hsotg, hsotg->frame_list_dma, HFLBADDR); hcfg &= ~HCFG_FRLISTEN_MASK; hcfg |= fr_list_en | HCFG_PERSCHEDENA; dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n"); - dwc2_writel(hcfg, hsotg->regs + HCFG); + dwc2_writel(hsotg, hcfg, HCFG); spin_unlock_irqrestore(&hsotg->lock, flags); } @@ -209,7 +209,7 @@ static void dwc2_per_sched_disable(struct dwc2_hsotg *hsotg) spin_lock_irqsave(&hsotg->lock, flags); - hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg = dwc2_readl(hsotg, HCFG); if (!(hcfg & HCFG_PERSCHEDENA)) { /* already disabled */ spin_unlock_irqrestore(&hsotg->lock, flags); @@ -218,7 +218,7 @@ static void dwc2_per_sched_disable(struct dwc2_hsotg *hsotg) hcfg &= ~HCFG_PERSCHEDENA; dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n"); - dwc2_writel(hcfg, hsotg->regs + HCFG); + dwc2_writel(hsotg, hcfg, HCFG); spin_unlock_irqrestore(&hsotg->lock, flags); } diff --git a/drivers/usb/dwc2/hcd_intr.c b/drivers/usb/dwc2/hcd_intr.c index 8ce10caf3e19..88b5dcf3aefc 100644 --- a/drivers/usb/dwc2/hcd_intr.c +++ b/drivers/usb/dwc2/hcd_intr.c @@ -144,7 +144,7 @@ static void dwc2_sof_intr(struct dwc2_hsotg *hsotg) enum dwc2_transaction_type tr_type; /* Clear interrupt */ - dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS); + dwc2_writel(hsotg, GINTSTS_SOF, GINTSTS); #ifdef DEBUG_SOF dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n"); @@ -191,7 +191,7 @@ static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg) if (dbg_perio()) dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n"); - grxsts = dwc2_readl(hsotg->regs + GRXSTSP); + grxsts = dwc2_readl(hsotg, GRXSTSP); chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT; chan = hsotg->hc_ptr_array[chnum]; if (!chan) { @@ -274,11 +274,11 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); /* Every time when port enables calculate HFIR.FrInterval */ - hfir = dwc2_readl(hsotg->regs + HFIR); + hfir = dwc2_readl(hsotg, HFIR); hfir &= ~HFIR_FRINT_MASK; hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT & HFIR_FRINT_MASK; - dwc2_writel(hfir, hsotg->regs + HFIR); + dwc2_writel(hsotg, hfir, HFIR); /* Check if we need to adjust the PHY clock speed for low power */ if (!params->host_support_fs_ls_low_power) { @@ -287,7 +287,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, return; } - usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg = dwc2_readl(hsotg, GUSBCFG); prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) { @@ -295,11 +295,11 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) { /* Set PHY low power clock select for FS/LS devices */ usbcfg |= GUSBCFG_PHY_LP_CLK_SEL; - dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + dwc2_writel(hsotg, usbcfg, GUSBCFG); do_reset = 1; } - hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg = dwc2_readl(hsotg, HCFG); fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >> HCFG_FSLSPCLKSEL_SHIFT; @@ -312,7 +312,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ; hcfg &= ~HCFG_FSLSPCLKSEL_MASK; hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; - dwc2_writel(hcfg, hsotg->regs + HCFG); + dwc2_writel(hsotg, hcfg, HCFG); do_reset = 1; } } else { @@ -323,7 +323,7 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ; hcfg &= ~HCFG_FSLSPCLKSEL_MASK; hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; - dwc2_writel(hcfg, hsotg->regs + HCFG); + dwc2_writel(hsotg, hcfg, HCFG); do_reset = 1; } } @@ -331,14 +331,14 @@ static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0, /* Not low power */ if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) { usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL; - dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + dwc2_writel(hsotg, usbcfg, GUSBCFG); do_reset = 1; } } if (do_reset) { *hprt0_modify |= HPRT0_RST; - dwc2_writel(*hprt0_modify, hsotg->regs + HPRT0); + dwc2_writel(hsotg, *hprt0_modify, HPRT0); queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work, msecs_to_jiffies(60)); } else { @@ -359,7 +359,7 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg) dev_vdbg(hsotg->dev, "--Port Interrupt--\n"); - hprt0 = dwc2_readl(hsotg->regs + HPRT0); + hprt0 = dwc2_readl(hsotg, HPRT0); hprt0_modify = hprt0; /* @@ -374,7 +374,7 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg) * Set flag and clear if detected */ if (hprt0 & HPRT0_CONNDET) { - dwc2_writel(hprt0_modify | HPRT0_CONNDET, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0_modify | HPRT0_CONNDET, HPRT0); dev_vdbg(hsotg->dev, "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n", @@ -392,7 +392,7 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg) * Clear if detected - Set internal flag if disabled */ if (hprt0 & HPRT0_ENACHG) { - dwc2_writel(hprt0_modify | HPRT0_ENACHG, hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0_modify | HPRT0_ENACHG, HPRT0); dev_vdbg(hsotg->dev, " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n", hprt0, !!(hprt0 & HPRT0_ENA)); @@ -406,17 +406,17 @@ static void dwc2_port_intr(struct dwc2_hsotg *hsotg) hsotg->params.dma_desc_enable = false; hsotg->new_connection = false; - hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg = dwc2_readl(hsotg, HCFG); hcfg &= ~HCFG_DESCDMA; - dwc2_writel(hcfg, hsotg->regs + HCFG); + dwc2_writel(hsotg, hcfg, HCFG); } } } /* Overcurrent Change Interrupt */ if (hprt0 & HPRT0_OVRCURRCHG) { - dwc2_writel(hprt0_modify | HPRT0_OVRCURRCHG, - hsotg->regs + HPRT0); + dwc2_writel(hsotg, hprt0_modify | HPRT0_OVRCURRCHG, + HPRT0); dev_vdbg(hsotg->dev, " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n", hprt0); @@ -441,7 +441,7 @@ static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg, { u32 hctsiz, count, length; - hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum)); if (halt_status == DWC2_HC_XFER_COMPLETE) { if (chan->ep_is_in) { @@ -518,7 +518,7 @@ static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg, urb->status = 0; } - hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum)); dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len); @@ -541,7 +541,7 @@ void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, int chnum, struct dwc2_qtd *qtd) { - u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + u32 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum)); u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT; if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) { @@ -780,9 +780,9 @@ cleanup: } } - haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); + haintmsk = dwc2_readl(hsotg, HAINTMSK); haintmsk &= ~(1 << chan->hc_num); - dwc2_writel(haintmsk, hsotg->regs + HAINTMSK); + dwc2_writel(hsotg, haintmsk, HAINTMSK); /* Try to queue more transfers now that there's a free channel */ tr_type = dwc2_hcd_select_transactions(hsotg); @@ -829,9 +829,9 @@ static void dwc2_halt_channel(struct dwc2_hsotg *hsotg, * is enabled so that the non-periodic schedule will * be processed */ - gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk = dwc2_readl(hsotg, GINTMSK); gintmsk |= GINTSTS_NPTXFEMP; - dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, gintmsk, GINTMSK); } else { dev_vdbg(hsotg->dev, "isoc/intr\n"); /* @@ -848,9 +848,9 @@ static void dwc2_halt_channel(struct dwc2_hsotg *hsotg, * enabled so that the periodic schedule will be * processed */ - gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk = dwc2_readl(hsotg, GINTMSK); gintmsk |= GINTSTS_PTXFEMP; - dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, gintmsk, GINTMSK); } } } @@ -915,7 +915,7 @@ static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, enum dwc2_halt_status halt_status) { - u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + u32 hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum)); qtd->error_count = 0; @@ -959,7 +959,7 @@ static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg, qtd->isoc_split_offset += len; - hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum)); pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT; if (frame_desc->actual_length >= frame_desc->length || pid == 0) { @@ -1185,7 +1185,7 @@ static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg, urb->actual_length += xfer_length; - hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum)); dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n", @@ -1566,10 +1566,10 @@ static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg, dwc2_hc_handle_tt_clear(hsotg, chan, qtd); - hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); - hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum)); - hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); - hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum)); + hcchar = dwc2_readl(hsotg, HCCHAR(chnum)); + hcsplt = dwc2_readl(hsotg, HCSPLT(chnum)); + hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum)); + hc_dma = dwc2_readl(hsotg, HCDMA(chnum)); dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum); dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt); @@ -1781,10 +1781,10 @@ static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg, * This code is here only as a check. This condition should * never happen. Ignore the halt if it does occur. */ - hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); - hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); - hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); - hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum)); + hcchar = dwc2_readl(hsotg, HCCHAR(chnum)); + hctsiz = dwc2_readl(hsotg, HCTSIZ(chnum)); + hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum)); + hcsplt = dwc2_readl(hsotg, HCSPLT(chnum)); dev_dbg(hsotg->dev, "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n", __func__); @@ -1808,7 +1808,7 @@ static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg, * when the halt interrupt occurs. Halt the channel again if it does * occur. */ - hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); + hcchar = dwc2_readl(hsotg, HCCHAR(chnum)); if (hcchar & HCCHAR_CHDIS) { dev_warn(hsotg->dev, "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n", @@ -1868,7 +1868,7 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg, return; } - hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); + hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum)); if (chan->hcint & HCINTMSK_XFERCOMPL) { /* @@ -1963,7 +1963,7 @@ static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg, dev_err(hsotg->dev, "hcint 0x%08x, intsts 0x%08x\n", chan->hcint, - dwc2_readl(hsotg->regs + GINTSTS)); + dwc2_readl(hsotg, GINTSTS)); goto error; } } @@ -2036,11 +2036,11 @@ static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum) chan = hsotg->hc_ptr_array[chnum]; - hcint = dwc2_readl(hsotg->regs + HCINT(chnum)); - hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); + hcint = dwc2_readl(hsotg, HCINT(chnum)); + hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum)); if (!chan) { dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n"); - dwc2_writel(hcint, hsotg->regs + HCINT(chnum)); + dwc2_writel(hsotg, hcint, HCINT(chnum)); return; } @@ -2052,7 +2052,7 @@ static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum) hcint, hcintmsk, hcint & hcintmsk); } - dwc2_writel(hcint, hsotg->regs + HCINT(chnum)); + dwc2_writel(hsotg, hcint, HCINT(chnum)); /* * If we got an interrupt after someone called @@ -2187,7 +2187,7 @@ static void dwc2_hc_intr(struct dwc2_hsotg *hsotg) int i; struct dwc2_host_chan *chan, *chan_tmp; - haint = dwc2_readl(hsotg->regs + HAINT); + haint = dwc2_readl(hsotg, HAINT); if (dbg_perio()) { dev_vdbg(hsotg->dev, "%s()\n", __func__); @@ -2271,8 +2271,8 @@ irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg) "DWC OTG HCD Finished Servicing Interrupts\n"); dev_vdbg(hsotg->dev, "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n", - dwc2_readl(hsotg->regs + GINTSTS), - dwc2_readl(hsotg->regs + GINTMSK)); + dwc2_readl(hsotg, GINTSTS), + dwc2_readl(hsotg, GINTMSK)); } } diff --git a/drivers/usb/dwc2/hcd_queue.c b/drivers/usb/dwc2/hcd_queue.c index 301ced1618f8..40839591d2ec 100644 --- a/drivers/usb/dwc2/hcd_queue.c +++ b/drivers/usb/dwc2/hcd_queue.c @@ -1510,7 +1510,7 @@ static void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info); bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC); bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT); - u32 hprt = dwc2_readl(hsotg->regs + HPRT0); + u32 hprt = dwc2_readl(hsotg, HPRT0); u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED && dev_speed != USB_SPEED_HIGH); @@ -1747,9 +1747,9 @@ int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) if (status) return status; if (!hsotg->periodic_qh_count) { - intr_mask = dwc2_readl(hsotg->regs + GINTMSK); + intr_mask = dwc2_readl(hsotg, GINTMSK); intr_mask |= GINTSTS_SOF; - dwc2_writel(intr_mask, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, intr_mask, GINTMSK); } hsotg->periodic_qh_count++; @@ -1788,9 +1788,9 @@ void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) hsotg->periodic_qh_count--; if (!hsotg->periodic_qh_count && !hsotg->params.dma_desc_enable) { - intr_mask = dwc2_readl(hsotg->regs + GINTMSK); + intr_mask = dwc2_readl(hsotg, GINTMSK); intr_mask &= ~GINTSTS_SOF; - dwc2_writel(intr_mask, hsotg->regs + GINTMSK); + dwc2_writel(hsotg, intr_mask, GINTMSK); } } diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c index af075d4da895..bf7052e037d6 100644 --- a/drivers/usb/dwc2/params.c +++ b/drivers/usb/dwc2/params.c @@ -47,7 +47,6 @@ static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg) p->max_transfer_size = 65535; p->max_packet_count = 511; p->ahbcfg = 0x10; - p->uframe_sched = false; } static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) @@ -68,7 +67,6 @@ static void dwc2_set_his_params(struct dwc2_hsotg *hsotg) p->reload_ctl = false; p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT; - p->uframe_sched = false; p->change_speed_quirk = true; p->power_down = false; } @@ -112,7 +110,6 @@ static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg) p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI; p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 << GAHBCFG_HBSTLEN_SHIFT; - p->uframe_sched = false; } static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg) @@ -134,7 +131,6 @@ static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg) p->max_packet_count = 256; p->phy_type = DWC2_PHY_TYPE_PARAM_FS; p->i2c_enable = false; - p->uframe_sched = false; p->activate_stm_fs_transceiver = true; } @@ -654,8 +650,8 @@ static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) dwc2_force_mode(hsotg, true); - gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); - hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); + gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); + hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ); hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; @@ -679,13 +675,13 @@ static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg) dwc2_force_mode(hsotg, false); - gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); + gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ); fifo_count = dwc2_hsotg_tx_fifo_count(hsotg); for (fifo = 1; fifo <= fifo_count; fifo++) { hw->g_tx_fifo_size[fifo] = - (dwc2_readl(hsotg->regs + DPTXFSIZN(fifo)) & + (dwc2_readl(hsotg, DPTXFSIZN(fifo)) & FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT; } @@ -713,7 +709,7 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx */ - hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); + hw->snpsid = dwc2_readl(hsotg, GSNPSID); if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID && (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID && (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) { @@ -726,11 +722,11 @@ int dwc2_get_hwparams(struct dwc2_hsotg *hsotg) hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); - hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); - hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); - hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); - hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); - grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); + hwcfg1 = dwc2_readl(hsotg, GHWCFG1); + hwcfg2 = dwc2_readl(hsotg, GHWCFG2); + hwcfg3 = dwc2_readl(hsotg, GHWCFG3); + hwcfg4 = dwc2_readl(hsotg, GHWCFG4); + grxfsiz = dwc2_readl(hsotg, GRXFSIZ); /* hwcfg1 */ hw->dev_ep_dirs = hwcfg1; diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c index 4c0819554bcd..9a53a58e676e 100644 --- a/drivers/usb/dwc2/platform.c +++ b/drivers/usb/dwc2/platform.c @@ -353,6 +353,23 @@ static void dwc2_driver_shutdown(struct platform_device *dev) } /** + * dwc2_check_core_endianness() - Returns true if core and AHB have + * opposite endianness. + * @hsotg: Programming view of the DWC_otg controller. + */ +static bool dwc2_check_core_endianness(struct dwc2_hsotg *hsotg) +{ + u32 snpsid; + + snpsid = ioread32(hsotg->regs + GSNPSID); + if ((snpsid & GSNPSID_ID_MASK) == DWC2_OTG_ID || + (snpsid & GSNPSID_ID_MASK) == DWC2_FS_IOT_ID || + (snpsid & GSNPSID_ID_MASK) == DWC2_HS_IOT_ID) + return false; + return true; +} + +/** * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg * driver * @@ -395,6 +412,8 @@ static int dwc2_driver_probe(struct platform_device *dev) dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n", (unsigned long)res->start, hsotg->regs); + hsotg->needs_byte_swap = dwc2_check_core_endianness(hsotg); + retval = dwc2_lowlevel_hw_init(hsotg); if (retval) return retval; diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index 451012ea1294..518ead12458d 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -74,11 +74,16 @@ config USB_DWC3_PCI depends on USB_PCI && ACPI default USB_DWC3 help - If you're using the DesignWare Core IP with a PCIe, please say - 'Y' or 'M' here. + If you're using the DesignWare Core IP with a PCIe (but not HAPS + platform), please say 'Y' or 'M' here. - One such PCIe-based platform is Synopsys' PCIe HAPS model of - this IP. +config USB_DWC3_HAPS + tristate "Synopsys PCIe-based HAPS Platforms" + depends on USB_PCI + default USB_DWC3 + help + If you're using the DesignWare Core IP with a Synopsys PCIe HAPS + platform, please say 'Y' or 'M' here. config USB_DWC3_KEYSTONE tristate "Texas Instruments Keystone2 Platforms" diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 5c07d8f925e0..6e3ef6144e5d 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -45,6 +45,7 @@ endif obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o obj-$(CONFIG_USB_DWC3_PCI) += dwc3-pci.o +obj-$(CONFIG_USB_DWC3_HAPS) += dwc3-haps.o obj-$(CONFIG_USB_DWC3_KEYSTONE) += dwc3-keystone.o obj-$(CONFIG_USB_DWC3_OF_SIMPLE) += dwc3-of-simple.o obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 103807587dc6..88c80fcc39f5 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -78,6 +78,14 @@ static int dwc3_get_dr_mode(struct dwc3 *dwc) mode = USB_DR_MODE_HOST; else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) mode = USB_DR_MODE_PERIPHERAL; + + /* + * dwc_usb31 does not support OTG mode. If the controller + * supports DRD but the dr_mode is not specified or set to OTG, + * then set the mode to peripheral. + */ + if (mode == USB_DR_MODE_OTG && dwc3_is_usb31(dwc)) + mode = USB_DR_MODE_PERIPHERAL; } if (mode != dwc->dr_mode) { @@ -778,6 +786,98 @@ static void dwc3_core_setup_global_control(struct dwc3 *dwc) static int dwc3_core_get_phy(struct dwc3 *dwc); static int dwc3_core_ulpi_init(struct dwc3 *dwc); +/* set global incr burst type configuration registers */ +static void dwc3_set_incr_burst_type(struct dwc3 *dwc) +{ + struct device *dev = dwc->dev; + /* incrx_mode : for INCR burst type. */ + bool incrx_mode; + /* incrx_size : for size of INCRX burst. */ + u32 incrx_size; + u32 *vals; + u32 cfg; + int ntype; + int ret; + int i; + + cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0); + + /* + * Handle property "snps,incr-burst-type-adjustment". + * Get the number of value from this property: + * result <= 0, means this property is not supported. + * result = 1, means INCRx burst mode supported. + * result > 1, means undefined length burst mode supported. + */ + ntype = device_property_read_u32_array(dev, + "snps,incr-burst-type-adjustment", NULL, 0); + if (ntype <= 0) + return; + + vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL); + if (!vals) { + dev_err(dev, "Error to get memory\n"); + return; + } + + /* Get INCR burst type, and parse it */ + ret = device_property_read_u32_array(dev, + "snps,incr-burst-type-adjustment", vals, ntype); + if (ret) { + dev_err(dev, "Error to get property\n"); + return; + } + + incrx_size = *vals; + + if (ntype > 1) { + /* INCRX (undefined length) burst mode */ + incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE; + for (i = 1; i < ntype; i++) { + if (vals[i] > incrx_size) + incrx_size = vals[i]; + } + } else { + /* INCRX burst mode */ + incrx_mode = INCRX_BURST_MODE; + } + + /* Enable Undefined Length INCR Burst and Enable INCRx Burst */ + cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK; + if (incrx_mode) + cfg |= DWC3_GSBUSCFG0_INCRBRSTENA; + switch (incrx_size) { + case 256: + cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA; + break; + case 128: + cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA; + break; + case 64: + cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA; + break; + case 32: + cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA; + break; + case 16: + cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA; + break; + case 8: + cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA; + break; + case 4: + cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA; + break; + case 1: + break; + default: + dev_err(dev, "Invalid property\n"); + break; + } + + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); +} + /** * dwc3_core_init - Low-level initialization of DWC3 Core * @dwc: Pointer to our controller context structure @@ -840,6 +940,8 @@ static int dwc3_core_init(struct dwc3 *dwc) /* Adjust Frame Length */ dwc3_frame_length_adjustment(dwc); + dwc3_set_incr_burst_type(dwc); + usb_phy_set_suspend(dwc->usb2_phy, 0); usb_phy_set_suspend(dwc->usb3_phy, 0); ret = phy_power_on(dwc->usb2_generic_phy); @@ -883,6 +985,22 @@ static int dwc3_core_init(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); } + if (dwc->dr_mode == USB_DR_MODE_HOST || + dwc->dr_mode == USB_DR_MODE_OTG) { + reg = dwc3_readl(dwc->regs, DWC3_GUCTL); + + /* + * Enable Auto retry Feature to make the controller operating in + * Host mode on seeing transaction errors(CRC errors or internal + * overrun scenerios) on IN transfers to reply to the device + * with a non-terminating retry ACK (i.e, an ACK transcation + * packet with Retry=1 & Nump != 0) + */ + reg |= DWC3_GUCTL_HSTINAUTORETRY; + + dwc3_writel(dwc->regs, DWC3_GUCTL, reg); + } + /* * Must config both number of packets and max burst settings to enable * RX and/or TX threshold. diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 285ce0ef3b91..5bfb62533e0f 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -163,6 +163,17 @@ /* Bit fields */ +/* Global SoC Bus Configuration INCRx Register 0 */ +#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */ +#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */ +#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */ +#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */ +#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */ +#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */ +#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */ +#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */ +#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff + /* Global Debug Queue/FIFO Space Available Register */ #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f) #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0) @@ -227,6 +238,9 @@ #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) #define DWC3_GCTL_DSBLCLKGTNG BIT(0) +/* Global User Control Register */ +#define DWC3_GUCTL_HSTINAUTORETRY BIT(14) + /* Global User Control 1 Register */ #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) @@ -1157,6 +1171,9 @@ struct dwc3 { u16 imod_interval; }; +#define INCRX_BURST_MODE 0 +#define INCRX_UNDEF_LENGTH_BURST_MODE 1 + #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work)) /* -------------------------------------------------------------------------- */ diff --git a/drivers/usb/dwc3/dwc3-haps.c b/drivers/usb/dwc3/dwc3-haps.c new file mode 100644 index 000000000000..c9cc33881bef --- /dev/null +++ b/drivers/usb/dwc3/dwc3-haps.c @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * dwc3-haps.c - Synopsys HAPS PCI Specific glue layer + * + * Copyright (C) 2018 Synopsys, Inc. + * + * Authors: Thinh Nguyen <thinhn@synopsys.com>, + * John Youn <johnyoun@synopsys.com> + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/pci.h> +#include <linux/platform_device.h> +#include <linux/property.h> + +#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd +#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce +#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf + +/** + * struct dwc3_haps - Driver private structure + * @dwc3: child dwc3 platform_device + * @pci: our link to PCI bus + */ +struct dwc3_haps { + struct platform_device *dwc3; + struct pci_dev *pci; +}; + +static const struct property_entry initial_properties[] = { + PROPERTY_ENTRY_BOOL("snps,usb3_lpm_capable"), + PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), + PROPERTY_ENTRY_BOOL("snps,dis_enblslpm_quirk"), + PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), + { }, +}; + +static int dwc3_haps_probe(struct pci_dev *pci, + const struct pci_device_id *id) +{ + struct dwc3_haps *dwc; + struct device *dev = &pci->dev; + struct resource res[2]; + int ret; + + ret = pcim_enable_device(pci); + if (ret) { + dev_err(dev, "failed to enable pci device\n"); + return -ENODEV; + } + + pci_set_master(pci); + + dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); + if (!dwc) + return -ENOMEM; + + dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); + if (!dwc->dwc3) + return -ENOMEM; + + memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res)); + + res[0].start = pci_resource_start(pci, 0); + res[0].end = pci_resource_end(pci, 0); + res[0].name = "dwc_usb3"; + res[0].flags = IORESOURCE_MEM; + + res[1].start = pci->irq; + res[1].name = "dwc_usb3"; + res[1].flags = IORESOURCE_IRQ; + + ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); + if (ret) { + dev_err(dev, "couldn't add resources to dwc3 device\n"); + goto err; + } + + dwc->pci = pci; + dwc->dwc3->dev.parent = dev; + + ret = platform_device_add_properties(dwc->dwc3, initial_properties); + if (ret) + goto err; + + ret = platform_device_add(dwc->dwc3); + if (ret) { + dev_err(dev, "failed to register dwc3 device\n"); + goto err; + } + + pci_set_drvdata(pci, dwc); + + return 0; +err: + platform_device_put(dwc->dwc3); + return ret; +} + +static void dwc3_haps_remove(struct pci_dev *pci) +{ + struct dwc3_haps *dwc = pci_get_drvdata(pci); + + platform_device_unregister(dwc->dwc3); +} + +static const struct pci_device_id dwc3_haps_id_table[] = { + { + PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, + PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3), + }, + { + PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, + PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI), + }, + { + PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, + PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31), + }, + { } /* Terminating Entry */ +}; +MODULE_DEVICE_TABLE(pci, dwc3_haps_id_table); + +static struct pci_driver dwc3_haps_driver = { + .name = "dwc3-haps", + .id_table = dwc3_haps_id_table, + .probe = dwc3_haps_probe, + .remove = dwc3_haps_remove, +}; + +MODULE_AUTHOR("Thinh Nguyen <thinhn@synopsys.com>"); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Synopsys HAPS PCI Glue Layer"); + +module_pci_driver(dwc3_haps_driver); diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c index dbeff5e6ad14..40bf9e0bbc59 100644 --- a/drivers/usb/dwc3/dwc3-of-simple.c +++ b/drivers/usb/dwc3/dwc3-of-simple.c @@ -28,6 +28,7 @@ struct dwc3_of_simple { int num_clocks; struct reset_control *resets; bool pulse_resets; + bool need_reset; }; static int dwc3_of_simple_clk_init(struct dwc3_of_simple *simple, int count) @@ -93,6 +94,13 @@ static int dwc3_of_simple_probe(struct platform_device *pdev) platform_set_drvdata(pdev, simple); simple->dev = dev; + /* + * Some controllers need to toggle the usb3-otg reset before trying to + * initialize the PHY, otherwise the PHY times out. + */ + if (of_device_is_compatible(np, "rockchip,rk3399-dwc3")) + simple->need_reset = true; + if (of_device_is_compatible(np, "amlogic,meson-axg-dwc3") || of_device_is_compatible(np, "amlogic,meson-gxl-dwc3")) { shared_resets = true; @@ -201,9 +209,30 @@ static int dwc3_of_simple_runtime_resume(struct device *dev) return 0; } + +static int dwc3_of_simple_suspend(struct device *dev) +{ + struct dwc3_of_simple *simple = dev_get_drvdata(dev); + + if (simple->need_reset) + reset_control_assert(simple->resets); + + return 0; +} + +static int dwc3_of_simple_resume(struct device *dev) +{ + struct dwc3_of_simple *simple = dev_get_drvdata(dev); + + if (simple->need_reset) + reset_control_deassert(simple->resets); + + return 0; +} #endif static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(dwc3_of_simple_suspend, dwc3_of_simple_resume) SET_RUNTIME_PM_OPS(dwc3_of_simple_runtime_suspend, dwc3_of_simple_runtime_resume, NULL) }; diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c index f57e7c94b8e5..5edd79470368 100644 --- a/drivers/usb/dwc3/dwc3-pci.c +++ b/drivers/usb/dwc3/dwc3-pci.c @@ -16,12 +16,10 @@ #include <linux/pm_runtime.h> #include <linux/platform_device.h> #include <linux/gpio/consumer.h> +#include <linux/gpio/machine.h> #include <linux/acpi.h> #include <linux/delay.h> -#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd -#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce -#define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf #define PCI_DEVICE_ID_INTEL_BYT 0x0f37 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e #define PCI_DEVICE_ID_INTEL_BSW 0x22b7 @@ -41,12 +39,17 @@ #define PCI_INTEL_BXT_STATE_D0 0 #define PCI_INTEL_BXT_STATE_D3 3 +#define GP_RWBAR 1 +#define GP_RWREG1 0xa0 +#define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17) + /** * struct dwc3_pci - Driver private structure * @dwc3: child dwc3 platform_device * @pci: our link to PCI bus * @guid: _DSM GUID * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM + * @wakeup_work: work for asynchronous resume */ struct dwc3_pci { struct platform_device *dwc3; @@ -67,52 +70,74 @@ static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = { { }, }; -static int dwc3_pci_quirks(struct dwc3_pci *dwc) +static struct gpiod_lookup_table platform_bytcr_gpios = { + .dev_id = "0000:00:16.0", + .table = { + GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH), + GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH), + {} + }, +}; + +static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci) { - struct platform_device *dwc3 = dwc->dwc3; - struct pci_dev *pdev = dwc->pci; + void __iomem *reg; + u32 value; + + reg = pcim_iomap(pci, GP_RWBAR, 0); + if (IS_ERR(reg)) + return PTR_ERR(reg); + + value = readl(reg + GP_RWREG1); + if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE)) + goto unmap; /* ULPI refclk already enabled */ + + value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE; + writel(value, reg + GP_RWREG1); + /* This comes from the Intel Android x86 tree w/o any explanation */ + msleep(100); +unmap: + pcim_iounmap(pci, reg); + return 0; +} - if (pdev->vendor == PCI_VENDOR_ID_AMD && - pdev->device == PCI_DEVICE_ID_AMD_NL_USB) { - struct property_entry properties[] = { - PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), - PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), - PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), - PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), - PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), - PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), - PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), - PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), - PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), - PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), - PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), - /* - * FIXME these quirks should be removed when AMD NL - * tapes out - */ - PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), - PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), - PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), - PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), - { }, - }; - - return platform_device_add_properties(dwc3, properties); - } +static const struct property_entry dwc3_pci_intel_properties[] = { + PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), + PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), + {} +}; - if (pdev->vendor == PCI_VENDOR_ID_INTEL) { - int ret; +static const struct property_entry dwc3_pci_mrfld_properties[] = { + PROPERTY_ENTRY_STRING("dr_mode", "otg"), + PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), + {} +}; - struct property_entry properties[] = { - PROPERTY_ENTRY_STRING("dr_mode", "peripheral"), - PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), - { } - }; +static const struct property_entry dwc3_pci_amd_properties[] = { + PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), + PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf), + PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"), + PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"), + PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"), + PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"), + PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"), + PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"), + PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"), + PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"), + PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1), + /* FIXME these quirks should be removed when AMD NL tapes out */ + PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"), + PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"), + PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"), + PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), + {} +}; - ret = platform_device_add_properties(dwc3, properties); - if (ret < 0) - return ret; +static int dwc3_pci_quirks(struct dwc3_pci *dwc) +{ + struct pci_dev *pdev = dwc->pci; + if (pdev->vendor == PCI_VENDOR_ID_INTEL) { if (pdev->device == PCI_DEVICE_ID_INTEL_BXT || pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) { guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid); @@ -121,6 +146,12 @@ static int dwc3_pci_quirks(struct dwc3_pci *dwc) if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) { struct gpio_desc *gpio; + int ret; + + /* On BYT the FW does not always enable the refclock */ + ret = dwc3_byt_enable_ulpi_refclock(pdev); + if (ret) + return ret; ret = devm_acpi_dev_add_driver_gpios(&pdev->dev, acpi_dwc3_byt_gpios); @@ -128,44 +159,36 @@ static int dwc3_pci_quirks(struct dwc3_pci *dwc) dev_dbg(&pdev->dev, "failed to add mapping table\n"); /* + * A lot of BYT devices lack ACPI resource entries for + * the GPIOs, add a fallback mapping to the reference + * design GPIOs which all boards seem to use. + */ + gpiod_add_lookup_table(&platform_bytcr_gpios); + + /* * These GPIOs will turn on the USB2 PHY. Note that we have to * put the gpio descriptors again here because the phy driver * might want to grab them, too. */ - gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW); + gpio = devm_gpiod_get_optional(&pdev->dev, "cs", + GPIOD_OUT_LOW); if (IS_ERR(gpio)) return PTR_ERR(gpio); gpiod_set_value_cansleep(gpio, 1); - gpiod_put(gpio); - gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); + gpio = devm_gpiod_get_optional(&pdev->dev, "reset", + GPIOD_OUT_LOW); if (IS_ERR(gpio)) return PTR_ERR(gpio); if (gpio) { gpiod_set_value_cansleep(gpio, 1); - gpiod_put(gpio); usleep_range(10000, 11000); } } } - if (pdev->vendor == PCI_VENDOR_ID_SYNOPSYS && - (pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 || - pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI || - pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31)) { - struct property_entry properties[] = { - PROPERTY_ENTRY_BOOL("snps,usb3_lpm_capable"), - PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"), - PROPERTY_ENTRY_BOOL("snps,dis_enblslpm_quirk"), - PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"), - { }, - }; - - return platform_device_add_properties(dwc3, properties); - } - return 0; } @@ -185,9 +208,9 @@ static void dwc3_pci_resume_work(struct work_struct *work) } #endif -static int dwc3_pci_probe(struct pci_dev *pci, - const struct pci_device_id *id) +static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id) { + struct property_entry *p = (struct property_entry *)id->driver_data; struct dwc3_pci *dwc; struct resource res[2]; int ret; @@ -230,6 +253,10 @@ static int dwc3_pci_probe(struct pci_dev *pci, dwc->dwc3->dev.parent = dev; ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev)); + ret = platform_device_add_properties(dwc->dwc3, p); + if (ret < 0) + return ret; + ret = dwc3_pci_quirks(dwc); if (ret) goto err; @@ -257,6 +284,7 @@ static void dwc3_pci_remove(struct pci_dev *pci) { struct dwc3_pci *dwc = pci_get_drvdata(pci); + gpiod_remove_lookup_table(&platform_bytcr_gpios); #ifdef CONFIG_PM cancel_work_sync(&dwc->wakeup_work); #endif @@ -266,32 +294,47 @@ static void dwc3_pci_remove(struct pci_dev *pci) } static const struct pci_device_id dwc3_pci_id_table[] = { - { - PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, - PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3), - }, - { - PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, - PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI), - }, - { - PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, - PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31), - }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW), }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTLP), }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTH), }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT), }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT_M), }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL), }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBP), }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK), }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CNPLP), }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CNPH), }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICLLP), }, - { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB), }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW), + (kernel_ulong_t) &dwc3_pci_intel_properties }, + + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT), + (kernel_ulong_t) &dwc3_pci_intel_properties, }, + + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD), + (kernel_ulong_t) &dwc3_pci_mrfld_properties, }, + + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP), + (kernel_ulong_t) &dwc3_pci_intel_properties, }, + + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH), + (kernel_ulong_t) &dwc3_pci_intel_properties, }, + + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT), + (kernel_ulong_t) &dwc3_pci_intel_properties, }, + + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M), + (kernel_ulong_t) &dwc3_pci_intel_properties, }, + + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL), + (kernel_ulong_t) &dwc3_pci_intel_properties, }, + + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP), + (kernel_ulong_t) &dwc3_pci_intel_properties, }, + + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK), + (kernel_ulong_t) &dwc3_pci_intel_properties, }, + + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP), + (kernel_ulong_t) &dwc3_pci_intel_properties, }, + + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH), + (kernel_ulong_t) &dwc3_pci_intel_properties, }, + + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP), + (kernel_ulong_t) &dwc3_pci_intel_properties, }, + + { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB), + (kernel_ulong_t) &dwc3_pci_amd_properties, }, { } /* Terminating Entry */ }; MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table); diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 69bf137aab37..032ea7d709ba 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -1121,7 +1121,7 @@ static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep, req->request.short_not_ok, req->request.no_interrupt); } else if (req->request.zero && req->request.length && - (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) { + (IS_ALIGNED(req->request.length, maxp))) { struct dwc3 *dwc = dep->dwc; struct dwc3_trb *trb; diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h index db610c56f1d6..2aacd1afd9ff 100644 --- a/drivers/usb/dwc3/gadget.h +++ b/drivers/usb/dwc3/gadget.h @@ -25,7 +25,7 @@ struct dwc3; #define DWC3_DEPCFG_XFER_IN_PROGRESS_EN BIT(9) #define DWC3_DEPCFG_XFER_NOT_READY_EN BIT(10) #define DWC3_DEPCFG_FIFO_ERROR_EN BIT(11) -#define DWC3_DEPCFG_STREAM_EVENT_EN BIT(12) +#define DWC3_DEPCFG_STREAM_EVENT_EN BIT(13) #define DWC3_DEPCFG_BINTERVAL_M1(n) (((n) & 0xff) << 16) #define DWC3_DEPCFG_STREAM_CAPABLE BIT(24) #define DWC3_DEPCFG_EP_NUMBER(n) (((n) & 0x1f) << 25) diff --git a/drivers/usb/gadget/configfs.c b/drivers/usb/gadget/configfs.c index efba66ca0719..025129942894 100644 --- a/drivers/usb/gadget/configfs.c +++ b/drivers/usb/gadget/configfs.c @@ -1217,8 +1217,8 @@ static void purge_configs_funcs(struct gadget_info *gi) list_move_tail(&f->list, &cfg->func_list); if (f->unbind) { dev_dbg(&gi->cdev.gadget->dev, - "unbind function '%s'/%p\n", - f->name, f); + "unbind function '%s'/%p\n", + f->name, f); f->unbind(c, f); } } diff --git a/drivers/usb/gadget/function/f_mass_storage.c b/drivers/usb/gadget/function/f_mass_storage.c index acecd13dcbd9..ca8a4b53c59f 100644 --- a/drivers/usb/gadget/function/f_mass_storage.c +++ b/drivers/usb/gadget/function/f_mass_storage.c @@ -206,7 +206,6 @@ #include <linux/fcntl.h> #include <linux/file.h> #include <linux/fs.h> -#include <linux/kref.h> #include <linux/kthread.h> #include <linux/sched/signal.h> #include <linux/limits.h> @@ -312,8 +311,6 @@ struct fsg_common { void *private_data; char inquiry_string[INQUIRY_STRING_LEN]; - - struct kref ref; }; struct fsg_dev { @@ -2551,25 +2548,11 @@ static DEVICE_ATTR(file, 0, file_show, file_store); /****************************** FSG COMMON ******************************/ -static void fsg_common_release(struct kref *ref); - static void fsg_lun_release(struct device *dev) { /* Nothing needs to be done */ } -void fsg_common_get(struct fsg_common *common) -{ - kref_get(&common->ref); -} -EXPORT_SYMBOL_GPL(fsg_common_get); - -void fsg_common_put(struct fsg_common *common) -{ - kref_put(&common->ref, fsg_common_release); -} -EXPORT_SYMBOL_GPL(fsg_common_put); - static struct fsg_common *fsg_common_setup(struct fsg_common *common) { if (!common) { @@ -2582,7 +2565,6 @@ static struct fsg_common *fsg_common_setup(struct fsg_common *common) } init_rwsem(&common->filesem); spin_lock_init(&common->lock); - kref_init(&common->ref); init_completion(&common->thread_notifier); init_waitqueue_head(&common->io_wait); init_waitqueue_head(&common->fsg_wait); @@ -2870,9 +2852,8 @@ void fsg_common_set_inquiry_string(struct fsg_common *common, const char *vn, } EXPORT_SYMBOL_GPL(fsg_common_set_inquiry_string); -static void fsg_common_release(struct kref *ref) +static void fsg_common_release(struct fsg_common *common) { - struct fsg_common *common = container_of(ref, struct fsg_common, ref); int i; /* If the thread isn't already dead, tell it to exit now */ @@ -3308,7 +3289,9 @@ static ssize_t fsg_opts_num_buffers_store(struct config_item *item, if (ret) goto end; - fsg_common_set_num_buffers(opts->common, num); + ret = fsg_common_set_num_buffers(opts->common, num); + if (ret) + goto end; ret = len; end: @@ -3344,7 +3327,7 @@ static void fsg_free_inst(struct usb_function_instance *fi) struct fsg_opts *opts; opts = fsg_opts_from_func_inst(fi); - fsg_common_put(opts->common); + fsg_common_release(opts->common); kfree(opts); } @@ -3368,7 +3351,7 @@ static struct usb_function_instance *fsg_alloc_inst(void) rc = fsg_common_set_num_buffers(opts->common, CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS); if (rc) - goto release_opts; + goto release_common; pr_info(FSG_DRIVER_DESC ", version: " FSG_DRIVER_VERSION "\n"); @@ -3391,6 +3374,8 @@ static struct usb_function_instance *fsg_alloc_inst(void) release_buffers: fsg_common_free_buffers(opts->common); +release_common: + kfree(opts->common); release_opts: kfree(opts); return ERR_PTR(rc); diff --git a/drivers/usb/gadget/function/f_mass_storage.h b/drivers/usb/gadget/function/f_mass_storage.h index 58857fcf199f..3b8c4ce2a40a 100644 --- a/drivers/usb/gadget/function/f_mass_storage.h +++ b/drivers/usb/gadget/function/f_mass_storage.h @@ -115,10 +115,6 @@ fsg_opts_from_func_inst(const struct usb_function_instance *fi) return container_of(fi, struct fsg_opts, func_inst); } -void fsg_common_get(struct fsg_common *common); - -void fsg_common_put(struct fsg_common *common); - void fsg_common_set_sysfs(struct fsg_common *common, bool sysfs); int fsg_common_set_num_buffers(struct fsg_common *common, unsigned int n); diff --git a/drivers/usb/gadget/function/f_uvc.c b/drivers/usb/gadget/function/f_uvc.c index 439eba660e95..d8ce7868fe22 100644 --- a/drivers/usb/gadget/function/f_uvc.c +++ b/drivers/usb/gadget/function/f_uvc.c @@ -6,16 +6,17 @@ * Laurent Pinchart (laurent.pinchart@ideasonboard.com) */ -#include <linux/kernel.h> -#include <linux/module.h> #include <linux/device.h> #include <linux/errno.h> #include <linux/fs.h> +#include <linux/kernel.h> #include <linux/list.h> +#include <linux/module.h> #include <linux/mutex.h> #include <linux/string.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> +#include <linux/usb/g_uvc.h> #include <linux/usb/video.h> #include <linux/vmalloc.h> #include <linux/wait.h> @@ -30,6 +31,8 @@ #include "uvc_video.h" unsigned int uvc_gadget_trace_param; +module_param_named(trace, uvc_gadget_trace_param, uint, 0644); +MODULE_PARM_DESC(trace, "Trace level bitmask"); /* -------------------------------------------------------------------------- * Function descriptors @@ -410,10 +413,21 @@ uvc_function_disconnect(struct uvc_device *uvc) * USB probe and disconnect */ +static ssize_t function_name_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct uvc_device *uvc = dev_get_drvdata(dev); + + return sprintf(buf, "%s\n", uvc->func.fi->group.cg_item.ci_name); +} + +static DEVICE_ATTR_RO(function_name); + static int uvc_register_video(struct uvc_device *uvc) { struct usb_composite_dev *cdev = uvc->func.config->cdev; + int ret; /* TODO reference counting. */ uvc->vdev.v4l2_dev = &uvc->v4l2_dev; @@ -426,7 +440,17 @@ uvc_register_video(struct uvc_device *uvc) video_set_drvdata(&uvc->vdev, uvc); - return video_register_device(&uvc->vdev, VFL_TYPE_GRABBER, -1); + ret = video_register_device(&uvc->vdev, VFL_TYPE_GRABBER, -1); + if (ret < 0) + return ret; + + ret = device_create_file(&uvc->vdev.dev, &dev_attr_function_name); + if (ret < 0) { + video_unregister_device(&uvc->vdev); + return ret; + } + + return 0; } #define UVC_COPY_DESCRIPTOR(mem, dst, desc) \ @@ -864,6 +888,7 @@ static void uvc_unbind(struct usb_configuration *c, struct usb_function *f) INFO(cdev, "%s\n", __func__); + device_remove_file(&uvc->vdev.dev, &dev_attr_function_name); video_unregister_device(&uvc->vdev); v4l2_device_unregister(&uvc->v4l2_dev); diff --git a/drivers/usb/gadget/function/f_uvc.h b/drivers/usb/gadget/function/f_uvc.h index 81defe4557fe..a81a17765558 100644 --- a/drivers/usb/gadget/function/f_uvc.h +++ b/drivers/usb/gadget/function/f_uvc.h @@ -9,10 +9,7 @@ #ifndef _F_UVC_H_ #define _F_UVC_H_ -#include <linux/usb/composite.h> -#include <linux/usb/video.h> - -#include "uvc.h" +struct uvc_device; void uvc_function_setup_continue(struct uvc_device *uvc); @@ -21,4 +18,3 @@ void uvc_function_connect(struct uvc_device *uvc); void uvc_function_disconnect(struct uvc_device *uvc); #endif /* _F_UVC_H_ */ - diff --git a/drivers/usb/gadget/function/u_uvc.h b/drivers/usb/gadget/function/u_uvc.h index d00d3ded71c0..2ed292e94fbc 100644 --- a/drivers/usb/gadget/function/u_uvc.h +++ b/drivers/usb/gadget/function/u_uvc.h @@ -13,6 +13,7 @@ #ifndef U_UVC_H #define U_UVC_H +#include <linux/mutex.h> #include <linux/usb/composite.h> #include <linux/usb/video.h> @@ -20,7 +21,6 @@ struct f_uvc_opts { struct usb_function_instance func_inst; - unsigned int uvc_gadget_trace_param; unsigned int streaming_interval; unsigned int streaming_maxpacket; unsigned int streaming_maxburst; @@ -80,7 +80,4 @@ struct f_uvc_opts { int refcnt; }; -void uvc_set_trace_param(unsigned int trace); - #endif /* U_UVC_H */ - diff --git a/drivers/usb/gadget/function/uvc.h b/drivers/usb/gadget/function/uvc.h index a64e07e61f8c..93cf78b420fe 100644 --- a/drivers/usb/gadget/function/uvc.h +++ b/drivers/usb/gadget/function/uvc.h @@ -9,52 +9,26 @@ #ifndef _UVC_GADGET_H_ #define _UVC_GADGET_H_ -#include <linux/ioctl.h> -#include <linux/types.h> -#include <linux/usb/ch9.h> - -#define UVC_EVENT_FIRST (V4L2_EVENT_PRIVATE_START + 0) -#define UVC_EVENT_CONNECT (V4L2_EVENT_PRIVATE_START + 0) -#define UVC_EVENT_DISCONNECT (V4L2_EVENT_PRIVATE_START + 1) -#define UVC_EVENT_STREAMON (V4L2_EVENT_PRIVATE_START + 2) -#define UVC_EVENT_STREAMOFF (V4L2_EVENT_PRIVATE_START + 3) -#define UVC_EVENT_SETUP (V4L2_EVENT_PRIVATE_START + 4) -#define UVC_EVENT_DATA (V4L2_EVENT_PRIVATE_START + 5) -#define UVC_EVENT_LAST (V4L2_EVENT_PRIVATE_START + 5) - -struct uvc_request_data { - __s32 length; - __u8 data[60]; -}; +#include <linux/list.h> +#include <linux/mutex.h> +#include <linux/spinlock.h> +#include <linux/usb/composite.h> +#include <linux/videodev2.h> -struct uvc_event { - union { - enum usb_device_speed speed; - struct usb_ctrlrequest req; - struct uvc_request_data data; - }; -}; +#include <media/v4l2-device.h> +#include <media/v4l2-dev.h> +#include <media/v4l2-fh.h> -#define UVCIOC_SEND_RESPONSE _IOW('U', 1, struct uvc_request_data) +#include "uvc_queue.h" -#define UVC_INTF_CONTROL 0 -#define UVC_INTF_STREAMING 1 +struct usb_ep; +struct usb_request; +struct uvc_descriptor_header; /* ------------------------------------------------------------------------ * Debugging, printing and logging */ -#ifdef __KERNEL__ - -#include <linux/usb.h> /* For usb_endpoint_* */ -#include <linux/usb/composite.h> -#include <linux/usb/gadget.h> -#include <linux/videodev2.h> -#include <media/v4l2-fh.h> -#include <media/v4l2-device.h> - -#include "uvc_queue.h" - #define UVC_TRACE_PROBE (1 << 0) #define UVC_TRACE_DESCR (1 << 1) #define UVC_TRACE_CONTROL (1 << 2) @@ -184,7 +158,4 @@ extern void uvc_endpoint_stream(struct uvc_device *dev); extern void uvc_function_connect(struct uvc_device *uvc); extern void uvc_function_disconnect(struct uvc_device *uvc); -#endif /* __KERNEL__ */ - #endif /* _UVC_GADGET_H_ */ - diff --git a/drivers/usb/gadget/function/uvc_configfs.c b/drivers/usb/gadget/function/uvc_configfs.c index c9b8cc4aae5a..b51f0d278826 100644 --- a/drivers/usb/gadget/function/uvc_configfs.c +++ b/drivers/usb/gadget/function/uvc_configfs.c @@ -31,7 +31,11 @@ static struct configfs_attribute prefix##attr_##cname = { \ .show = prefix##cname##_show, \ } -static inline struct f_uvc_opts *to_f_uvc_opts(struct config_item *item); +static inline struct f_uvc_opts *to_f_uvc_opts(struct config_item *item) +{ + return container_of(to_config_group(item), struct f_uvc_opts, + func_inst.group); +} /* control/header/<NAME> */ DECLARE_UVC_HEADER_DESCRIPTOR(1); @@ -2105,12 +2109,6 @@ static const struct config_item_type uvcg_streaming_grp_type = { .ct_owner = THIS_MODULE, }; -static inline struct f_uvc_opts *to_f_uvc_opts(struct config_item *item) -{ - return container_of(to_config_group(item), struct f_uvc_opts, - func_inst.group); -} - static void uvc_attr_release(struct config_item *item) { struct f_uvc_opts *opts = to_f_uvc_opts(item); diff --git a/drivers/usb/gadget/function/uvc_queue.h b/drivers/usb/gadget/function/uvc_queue.h index f9f65b5c1062..2f0fff769843 100644 --- a/drivers/usb/gadget/function/uvc_queue.h +++ b/drivers/usb/gadget/function/uvc_queue.h @@ -2,13 +2,15 @@ #ifndef _UVC_QUEUE_H_ #define _UVC_QUEUE_H_ -#ifdef __KERNEL__ - -#include <linux/kernel.h> +#include <linux/list.h> #include <linux/poll.h> -#include <linux/videodev2.h> +#include <linux/spinlock.h> + #include <media/videobuf2-v4l2.h> +struct file; +struct mutex; + /* Maximum frame size in bytes, for sanity checking. */ #define UVC_MAX_FRAME_SIZE (16*1024*1024) /* Maximum number of video buffers. */ @@ -91,7 +93,5 @@ struct uvc_buffer *uvcg_queue_next_buffer(struct uvc_video_queue *queue, struct uvc_buffer *uvcg_queue_head(struct uvc_video_queue *queue); -#endif /* __KERNEL__ */ - #endif /* _UVC_QUEUE_H_ */ diff --git a/drivers/usb/gadget/function/uvc_v4l2.c b/drivers/usb/gadget/function/uvc_v4l2.c index 9a9019625496..7f1ca3b57823 100644 --- a/drivers/usb/gadget/function/uvc_v4l2.c +++ b/drivers/usb/gadget/function/uvc_v4l2.c @@ -6,10 +6,11 @@ * Laurent Pinchart (laurent.pinchart@ideasonboard.com) */ -#include <linux/kernel.h> #include <linux/device.h> #include <linux/errno.h> +#include <linux/kernel.h> #include <linux/list.h> +#include <linux/usb/g_uvc.h> #include <linux/videodev2.h> #include <linux/vmalloc.h> #include <linux/wait.h> diff --git a/drivers/usb/gadget/function/uvc_video.h b/drivers/usb/gadget/function/uvc_video.h index 6c20aa75f966..7d77122b0ff9 100644 --- a/drivers/usb/gadget/function/uvc_video.h +++ b/drivers/usb/gadget/function/uvc_video.h @@ -12,6 +12,8 @@ #ifndef __UVC_VIDEO_H__ #define __UVC_VIDEO_H__ +struct uvc_video; + int uvcg_video_pump(struct uvc_video *video); int uvcg_video_enable(struct uvc_video *video, int enable); diff --git a/drivers/usb/gadget/legacy/tcm_usb_gadget.c b/drivers/usb/gadget/legacy/tcm_usb_gadget.c index 682bf99dcf76..40870227999a 100644 --- a/drivers/usb/gadget/legacy/tcm_usb_gadget.c +++ b/drivers/usb/gadget/legacy/tcm_usb_gadget.c @@ -41,7 +41,7 @@ static struct usb_device_descriptor usbg_device_desc = { #define USB_G_STR_CONFIG USB_GADGET_FIRST_AVAIL_IDX static struct usb_string usbg_us_strings[] = { - [USB_GADGET_MANUFACTURER_IDX].s = "Target Manufactor", + [USB_GADGET_MANUFACTURER_IDX].s = "Target Manufacturer", [USB_GADGET_PRODUCT_IDX].s = "Target Product", [USB_GADGET_SERIAL_IDX].s = "000000000001", [USB_G_STR_CONFIG].s = "default config", diff --git a/drivers/usb/gadget/legacy/webcam.c b/drivers/usb/gadget/legacy/webcam.c index 6b86568c9157..a9f8eb8e1c76 100644 --- a/drivers/usb/gadget/legacy/webcam.c +++ b/drivers/usb/gadget/legacy/webcam.c @@ -30,9 +30,6 @@ static unsigned int streaming_maxburst; module_param(streaming_maxburst, uint, S_IRUGO|S_IWUSR); MODULE_PARM_DESC(streaming_maxburst, "0 - 15 (ss only)"); -static unsigned int trace; -module_param(trace, uint, S_IRUGO|S_IWUSR); -MODULE_PARM_DESC(trace, "Trace level bitmask"); /* -------------------------------------------------------------------------- * Device descriptor */ @@ -379,7 +376,6 @@ webcam_bind(struct usb_composite_dev *cdev) uvc_opts->streaming_interval = streaming_interval; uvc_opts->streaming_maxpacket = streaming_maxpacket; uvc_opts->streaming_maxburst = streaming_maxburst; - uvc_set_trace_param(trace); uvc_opts->fs_control = uvc_fs_control_cls; uvc_opts->ss_control = uvc_ss_control_cls; diff --git a/drivers/usb/gadget/udc/Kconfig b/drivers/usb/gadget/udc/Kconfig index 1df4dedffe86..0a16cbd4e528 100644 --- a/drivers/usb/gadget/udc/Kconfig +++ b/drivers/usb/gadget/udc/Kconfig @@ -193,6 +193,7 @@ config USB_RENESAS_USB3 tristate 'Renesas USB3.0 Peripheral controller' depends on ARCH_RENESAS || COMPILE_TEST depends on EXTCON + select USB_ROLE_SWITCH help Renesas USB3.0 Peripheral controller is a USB peripheral controller that supports super, high, and full speed USB 3.0 data transfers. diff --git a/drivers/usb/gadget/udc/core.c b/drivers/usb/gadget/udc/core.c index cab5e4f09924..af88b48c1cea 100644 --- a/drivers/usb/gadget/udc/core.c +++ b/drivers/usb/gadget/udc/core.c @@ -87,6 +87,8 @@ EXPORT_SYMBOL_GPL(usb_ep_set_maxpacket_limit); * configurable, with more generic names like "ep-a". (remember that for * USB, "in" means "towards the USB master".) * + * This routine must be called in process context. + * * returns zero, or a negative error code. */ int usb_ep_enable(struct usb_ep *ep) @@ -119,6 +121,8 @@ EXPORT_SYMBOL_GPL(usb_ep_enable); * gadget drivers must call usb_ep_enable() again before queueing * requests to the endpoint. * + * This routine must be called in process context. + * * returns zero, or a negative error code. */ int usb_ep_disable(struct usb_ep *ep) @@ -241,6 +245,8 @@ EXPORT_SYMBOL_GPL(usb_ep_free_request); * Note that @req's ->complete() callback must never be called from * within usb_ep_queue() as that can create deadlock situations. * + * This routine may be called in interrupt context. + * * Returns zero, or a negative error code. Endpoints that are not enabled * report errors; errors will also be * reported when the usb peripheral is disconnected. @@ -284,6 +290,8 @@ EXPORT_SYMBOL_GPL(usb_ep_queue); * at the head of the queue) except as part of disconnecting from usb. Such * restrictions prevent drivers from supporting configuration changes, * even to configuration zero (a "chapter 9" requirement). + * + * This routine may be called in interrupt context. */ int usb_ep_dequeue(struct usb_ep *ep, struct usb_request *req) { @@ -311,6 +319,8 @@ EXPORT_SYMBOL_GPL(usb_ep_dequeue); * current altsetting, see usb_ep_clear_halt(). When switching altsettings, * it's simplest to use usb_ep_enable() or usb_ep_disable() for the endpoints. * + * This routine may be called in interrupt context. + * * Returns zero, or a negative error code. On success, this call sets * underlying hardware state that blocks data transfers. * Attempts to halt IN endpoints will fail (returning -EAGAIN) if any @@ -336,6 +346,8 @@ EXPORT_SYMBOL_GPL(usb_ep_set_halt); * for endpoints that aren't reconfigured, after clearing any other state * in the endpoint's i/o queue. * + * This routine may be called in interrupt context. + * * Returns zero, or a negative error code. On success, this call clears * the underlying hardware state reflecting endpoint halt and data toggle. * Note that some hardware can't support this request (like pxa2xx_udc), @@ -360,6 +372,8 @@ EXPORT_SYMBOL_GPL(usb_ep_clear_halt); * requests. If the gadget driver clears the halt status, it will * automatically unwedge the endpoint. * + * This routine may be called in interrupt context. + * * Returns zero on success, else negative errno. */ int usb_ep_set_wedge(struct usb_ep *ep) @@ -388,6 +402,8 @@ EXPORT_SYMBOL_GPL(usb_ep_set_wedge); * written OUT to it by the host. Drivers that need precise handling for * fault reporting or recovery may need to use this call. * + * This routine may be called in interrupt context. + * * This returns the number of such bytes in the fifo, or a negative * errno if the endpoint doesn't use a FIFO or doesn't support such * precise handling. @@ -415,6 +431,8 @@ EXPORT_SYMBOL_GPL(usb_ep_fifo_status); * an endpoint fifo after abnormal transaction terminations. The call * must never be used except when endpoint is not being used for any * protocol translation. + * + * This routine may be called in interrupt context. */ void usb_ep_fifo_flush(struct usb_ep *ep) { diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c index 7cf98c793e04..1f879b3f2c96 100644 --- a/drivers/usb/gadget/udc/renesas_usb3.c +++ b/drivers/usb/gadget/udc/renesas_usb3.c @@ -23,6 +23,8 @@ #include <linux/uaccess.h> #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> +#include <linux/usb/of.h> +#include <linux/usb/role.h> /* register definitions */ #define USB3_AXI_INT_STA 0x008 @@ -335,6 +337,11 @@ struct renesas_usb3 { struct phy *phy; struct dentry *dentry; + struct usb_role_switch *role_sw; + struct device *host_dev; + struct work_struct role_work; + enum usb_role role; + struct renesas_usb3_ep *usb3_ep; int num_usb3_eps; @@ -651,6 +658,14 @@ static void usb3_check_vbus(struct renesas_usb3 *usb3) } } +static void renesas_usb3_role_work(struct work_struct *work) +{ + struct renesas_usb3 *usb3 = + container_of(work, struct renesas_usb3, role_work); + + usb_role_switch_set_role(usb3->role_sw, usb3->role); +} + static void usb3_set_mode(struct renesas_usb3 *usb3, bool host) { if (host) @@ -659,6 +674,16 @@ static void usb3_set_mode(struct renesas_usb3 *usb3, bool host) usb3_set_bit(usb3, DRD_CON_PERI_CON, USB3_DRD_CON); } +static void usb3_set_mode_by_role_sw(struct renesas_usb3 *usb3, bool host) +{ + if (usb3->role_sw) { + usb3->role = host ? USB_ROLE_HOST : USB_ROLE_DEVICE; + schedule_work(&usb3->role_work); + } else { + usb3_set_mode(usb3, host); + } +} + static void usb3_vbus_out(struct renesas_usb3 *usb3, bool enable) { if (enable) @@ -672,7 +697,7 @@ static void usb3_mode_config(struct renesas_usb3 *usb3, bool host, bool a_dev) unsigned long flags; spin_lock_irqsave(&usb3->lock, flags); - usb3_set_mode(usb3, host); + usb3_set_mode_by_role_sw(usb3, host); usb3_vbus_out(usb3, a_dev); /* for A-Peripheral or forced B-device mode */ if ((!host && a_dev) || @@ -2302,6 +2327,41 @@ static const struct usb_gadget_ops renesas_usb3_gadget_ops = { .set_selfpowered = renesas_usb3_set_selfpowered, }; +static enum usb_role renesas_usb3_role_switch_get(struct device *dev) +{ + struct renesas_usb3 *usb3 = dev_get_drvdata(dev); + enum usb_role cur_role; + + pm_runtime_get_sync(dev); + cur_role = usb3_is_host(usb3) ? USB_ROLE_HOST : USB_ROLE_DEVICE; + pm_runtime_put(dev); + + return cur_role; +} + +static int renesas_usb3_role_switch_set(struct device *dev, + enum usb_role role) +{ + struct renesas_usb3 *usb3 = dev_get_drvdata(dev); + struct device *host = usb3->host_dev; + enum usb_role cur_role = renesas_usb3_role_switch_get(dev); + + pm_runtime_get_sync(dev); + if (cur_role == USB_ROLE_HOST && role == USB_ROLE_DEVICE) { + device_release_driver(host); + usb3_set_mode(usb3, false); + } else if (cur_role == USB_ROLE_DEVICE && role == USB_ROLE_HOST) { + /* Must set the mode before device_attach of the host */ + usb3_set_mode(usb3, true); + /* This device_attach() might sleep */ + if (device_attach(host) < 0) + dev_err(dev, "device_attach(host) failed\n"); + } + pm_runtime_put(dev); + + return 0; +} + static ssize_t role_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { @@ -2405,6 +2465,8 @@ static int renesas_usb3_remove(struct platform_device *pdev) debugfs_remove_recursive(usb3->dentry); device_remove_file(&pdev->dev, &dev_attr_role); + usb_role_switch_unregister(usb3->role_sw); + usb_del_gadget_udc(&usb3->gadget); renesas_usb3_dma_free_prd(usb3, &pdev->dev); @@ -2562,6 +2624,12 @@ static const unsigned int renesas_usb3_cable[] = { EXTCON_NONE, }; +static const struct usb_role_switch_desc renesas_usb3_role_switch_desc = { + .set = renesas_usb3_role_switch_set, + .get = renesas_usb3_role_switch_get, + .allow_userspace_control = true, +}; + static int renesas_usb3_probe(struct platform_device *pdev) { struct renesas_usb3 *usb3; @@ -2647,6 +2715,20 @@ static int renesas_usb3_probe(struct platform_device *pdev) if (ret < 0) goto err_dev_create; + INIT_WORK(&usb3->role_work, renesas_usb3_role_work); + usb3->role_sw = usb_role_switch_register(&pdev->dev, + &renesas_usb3_role_switch_desc); + if (!IS_ERR(usb3->role_sw)) { + usb3->host_dev = usb_of_get_companion_dev(&pdev->dev); + if (!usb3->host_dev) { + /* If not found, this driver will not use a role sw */ + usb_role_switch_unregister(usb3->role_sw); + usb3->role_sw = NULL; + } + } else { + usb3->role_sw = NULL; + } + usb3->workaround_for_vbus = priv->workaround_for_vbus; renesas_usb3_debugfs_init(usb3, &pdev->dev); diff --git a/include/uapi/linux/usb/g_uvc.h b/include/uapi/linux/usb/g_uvc.h new file mode 100644 index 000000000000..3c9ee3020cbb --- /dev/null +++ b/include/uapi/linux/usb/g_uvc.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * g_uvc.h -- USB Video Class Gadget driver API + * + * Copyright (C) 2009-2010 Laurent Pinchart <laurent.pinchart@ideasonboard.com> + */ + +#ifndef __LINUX_USB_G_UVC_H +#define __LINUX_USB_G_UVC_H + +#include <linux/ioctl.h> +#include <linux/types.h> +#include <linux/usb/ch9.h> + +#define UVC_EVENT_FIRST (V4L2_EVENT_PRIVATE_START + 0) +#define UVC_EVENT_CONNECT (V4L2_EVENT_PRIVATE_START + 0) +#define UVC_EVENT_DISCONNECT (V4L2_EVENT_PRIVATE_START + 1) +#define UVC_EVENT_STREAMON (V4L2_EVENT_PRIVATE_START + 2) +#define UVC_EVENT_STREAMOFF (V4L2_EVENT_PRIVATE_START + 3) +#define UVC_EVENT_SETUP (V4L2_EVENT_PRIVATE_START + 4) +#define UVC_EVENT_DATA (V4L2_EVENT_PRIVATE_START + 5) +#define UVC_EVENT_LAST (V4L2_EVENT_PRIVATE_START + 5) + +struct uvc_request_data { + __s32 length; + __u8 data[60]; +}; + +struct uvc_event { + union { + enum usb_device_speed speed; + struct usb_ctrlrequest req; + struct uvc_request_data data; + }; +}; + +#define UVCIOC_SEND_RESPONSE _IOW('U', 1, struct uvc_request_data) + +#endif /* __LINUX_USB_G_UVC_H */ |