diff options
| author | Naveen Krishna Chatradhi <ch.naveen@samsung.com> | 2014-02-17 15:14:31 +0530 |
|---|---|---|
| committer | Tomasz Figa <t.figa@samsung.com> | 2014-05-14 19:23:26 +0200 |
| commit | 5b73721b60360163169a8eccd3c4285f4a605d07 (patch) | |
| tree | 34dfdb2e750fde2d75cbb7cde0b7f4848e7ecf95 | |
| parent | 91a1263fd2bab8704fa0a940c1ab6b813143ecc4 (diff) | |
clk: samsung: exynos5250/5420: Add gate clock for SSS module
This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250/5420.
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
[t.figa: Fixed sort order and group name.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5250.c | 1 | ||||
| -rw-r--r-- | drivers/clk/samsung/clk-exynos5420.c | 4 | ||||
| -rw-r--r-- | include/dt-bindings/clock/exynos5250.h | 1 |
3 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index e549e862524a..d1d53ca45e20 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -428,6 +428,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { * CMU_ACP */ GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0), + GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0), GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0), GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0), diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index c3e0894d0279..a8704540a214 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -27,6 +27,7 @@ #define DIV_CPU1 0x504 #define GATE_BUS_CPU 0x700 #define GATE_SCLK_CPU 0x800 +#define GATE_IP_G2D 0x8800 #define CPLL_LOCK 0x10020 #define DPLL_LOCK 0x10030 #define EPLL_LOCK 0x10040 @@ -515,6 +516,9 @@ static struct samsung_div_clock exynos5420_div_clks[] __initdata = { }; static struct samsung_gate_clock exynos5420_gate_clks[] __initdata = { + /* G2D */ + GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0), + /* TODO: Re-verify the CG bits for all the gate clocks */ GATE_A(CLK_MCT, "pclk_st", "aclk66_psgen", GATE_BUS_PERIS1, 2, 0, 0, "mct"), diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h index 922f2dca9bf0..f9b452bb3019 100644 --- a/include/dt-bindings/clock/exynos5250.h +++ b/include/dt-bindings/clock/exynos5250.h @@ -150,6 +150,7 @@ #define CLK_G2D 345 #define CLK_MDMA0 346 #define CLK_SMMU_MDMA0 347 +#define CLK_SSS 348 /* mux clocks */ #define CLK_MOUT_HDMI 1024 |