diff options
| author | Samuel Holland <samuel@sholland.org> | 2022-12-27 18:44:44 -0600 |
|---|---|---|
| committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2023-02-13 13:10:16 +0100 |
| commit | 674402b0098b66b8ba91fe93c0d27af703256098 (patch) | |
| tree | 1ab249b6d78c1c0b5c921ff8b2687644e238c6ae | |
| parent | 8932a9533a9cdd1fa2924a061dc87277991507ca (diff) | |
clocksource/drivers/riscv: Increase the clock source rating
RISC-V provides an architectural clock source via the time CSR. This
clock source exposes a 64-bit counter synchronized across all CPUs.
Because it is accessed using a CSR, it is much more efficient to read
than MMIO clock sources. For example, on the Allwinner D1, reading the
sun4i timer in a loop takes 131 cycles/iteration, while reading the
RISC-V time CSR takes only 5 cycles/iteration.
Adjust the RISC-V clock source rating so it is preferred over the
various platform-specific MMIO clock sources.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20221228004444.61568-1-samuel@sholland.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
| -rw-r--r-- | drivers/clocksource/timer-riscv.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 1b4b36df5484..adf7f98aab17 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -74,7 +74,7 @@ static u64 notrace riscv_sched_clock(void) static struct clocksource riscv_clocksource = { .name = "riscv_clocksource", - .rating = 300, + .rating = 400, .mask = CLOCKSOURCE_MASK(64), .flags = CLOCK_SOURCE_IS_CONTINUOUS, .read = riscv_clocksource_rdtime, |