diff options
| author | Kevin Cernekee <cernekee@gmail.com> | 2012-07-09 01:41:19 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2012-08-30 20:15:52 +0200 |
| commit | 6f9423454aa68bdf64099f3a30fafb2c64b25cda (patch) | |
| tree | 948b63c532988410e8764de864f74fe379b91bfe | |
| parent | 932e30b6ea8d2ce5a5d60b799f5c088547f105b3 (diff) | |
MIPS: BCM63XX: Add new IUDMA definitions needed for USBD
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4083/
Signed-off-by: John Crispin <blogic@openwrt.org>
| -rw-r--r-- | arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h | 4 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 12 |
2 files changed, 14 insertions, 2 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h index 358cf28ce2af..a5bbff31c898 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h @@ -11,6 +11,7 @@ struct bcm_enet_desc { u32 address; }; +/* control */ #define DMADESC_LENGTH_SHIFT 16 #define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT) #define DMADESC_OWNER_MASK (1 << 15) @@ -18,7 +19,10 @@ struct bcm_enet_desc { #define DMADESC_SOP_MASK (1 << 13) #define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK) #define DMADESC_WRAP_MASK (1 << 12) +#define DMADESC_USB_NOZERO_MASK (1 << 1) +#define DMADESC_USB_ZERO_MASK (1 << 0) +/* status */ #define DMADESC_UNDER_MASK (1 << 9) #define DMADESC_APPEND_CRC (1 << 8) #define DMADESC_OVSIZE_MASK (1 << 4) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 4ccc2a748aff..7a101125e482 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -670,6 +670,12 @@ #define ENETDMA_BUFALLOC_FORCE_SHIFT 31 #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT) +/* Global interrupt status */ +#define ENETDMA_GLB_IRQSTAT_REG (0x40) + +/* Global interrupt mask */ +#define ENETDMA_GLB_IRQMASK_REG (0x44) + /* Channel Configuration register */ #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10) #define ENETDMA_CHANCFG_EN_SHIFT 0 @@ -709,9 +715,11 @@ /* Channel Configuration register */ #define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10) #define ENETDMAC_CHANCFG_EN_SHIFT 0 -#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT) +#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT) #define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1 -#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT) +#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT) +#define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2 +#define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT) /* Interrupt Control/Status register */ #define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10) |