diff options
| author | Adam Ford <aford173@gmail.com> | 2024-02-11 17:15:08 -0600 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2024-02-25 11:22:52 +0800 |
| commit | 6fb464ff9a5f7581c3593796b08c28891276d0ad (patch) | |
| tree | d0ef003fd5b2a201fdeaec79c86793483714ae09 | |
| parent | 5ab5a11acbeda73446b4f3c55598b0444bb2de93 (diff) | |
arm64: dts: imx8mn: Slow default video_pll clock rate
Since commit 8208181fe536 ("clk: imx: composite-8m:
Add imx8m_divider_determine_rate") the lcdif controller has
had the ability to set the disp_pixel_clk rate which propagates
up the tree and sets the video_pll rate automatically.
By setting this value low, it will force the recalculation of
video_pll to the lowest rate needed by lcdif instead of
dividing a larger clock down to the desired clock speed. This
has the advantage of being able to lower the video_pll rate
from 594MHz to 148.5MHz when operating at 1080p. It can go even
lower when operating at lower resolutions and refresh rates.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 136e75c51251..932c8b05c75f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -1168,7 +1168,7 @@ <&clk IMX8MN_SYS_PLL1_800M>; assigned-clock-rates = <266000000>, <24000000>, - <594000000>, + <24000000>, <500000000>, <200000000>; #power-domain-cells = <1>; |