diff options
| author | Peter Zijlstra <peterz@infradead.org> | 2020-11-26 17:38:42 +0100 |
|---|---|---|
| committer | Dave Hansen <dave.hansen@linux.intel.com> | 2022-12-15 10:37:27 -0800 |
| commit | 7a9b8bdb6af3e19fb8e3dc7a3caf6a9ea1bed8cd (patch) | |
| tree | 4415416cdaf4e670a8502dcb320238a5456107f7 | |
| parent | 1180e732c985ed3c8866d2fd9e02b619848404a0 (diff) | |
x86/mm/pae: Don't (ab)use atomic64
PAE implies CX8, write readable code.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20221022114424.971450128%40infradead.org
| -rw-r--r-- | arch/x86/include/asm/pgtable-3level.h | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/arch/x86/include/asm/pgtable-3level.h b/arch/x86/include/asm/pgtable-3level.h index 94f50b0100a5..0a1b81dc72c0 100644 --- a/arch/x86/include/asm/pgtable-3level.h +++ b/arch/x86/include/asm/pgtable-3level.h @@ -2,8 +2,6 @@ #ifndef _ASM_X86_PGTABLE_3LEVEL_H #define _ASM_X86_PGTABLE_3LEVEL_H -#include <asm/atomic64_32.h> - /* * Intel Physical Address Extension (PAE) Mode - three-level page * tables on PPro+ CPUs. @@ -95,11 +93,12 @@ static inline void pud_clear(pud_t *pudp) #ifdef CONFIG_SMP static inline pte_t native_ptep_get_and_clear(pte_t *ptep) { - pte_t res; + pte_t old = *ptep; - res.pte = (pteval_t)arch_atomic64_xchg((atomic64_t *)ptep, 0); + do { + } while (!try_cmpxchg64(&ptep->pte, &old.pte, 0ULL)); - return res; + return old; } #else #define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp) |