diff options
| author | Zev Weiss <zev@bewilderbeest.net> | 2021-04-16 02:51:13 -0500 |
|---|---|---|
| committer | Joel Stanley <joel@jms.id.au> | 2021-07-01 12:43:16 +0930 |
| commit | 812bae32e5d50914f75a6e036d3bde39ca86b0c3 (patch) | |
| tree | 5944777b86b7c47aae0353b7d0f8246b4704ca00 | |
| parent | ca46ad2214473df1a6a9496be17156d65ba89b9f (diff) | |
ARM: dts: aspeed: Update e3c246d4i vuart properties
This device-tree was merged with a provisional vuart IRQ-polarity
property that was still under review and ended up taking a somewhat
different form. This patch updates it to match the final form of the
new vuart properties, which additionally allow specifying the SIRQ
number and LPC address.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Fixes: ca03042f0f12 ("serial: 8250_aspeed_vuart: add aspeed, lpc-io-reg and aspeed, lpc-interrupts DT properties")
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20210416075113.18047-1-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
| -rw-r--r-- | arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts index 33e413ca07e4..9b4cf5ebe6d5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts @@ -4,6 +4,7 @@ #include "aspeed-g5.dtsi" #include <dt-bindings/gpio/aspeed-gpio.h> #include <dt-bindings/i2c/i2c.h> +#include <dt-bindings/interrupt-controller/irq.h> /{ model = "ASRock E3C246D4I BMC"; @@ -73,7 +74,8 @@ &vuart { status = "okay"; - aspeed,sirq-active-high; + aspeed,lpc-io-reg = <0x2f8>; + aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; }; &mac0 { |