diff options
| author | Thierry Reding <treding@nvidia.com> | 2019-07-26 12:16:18 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-29 20:30:05 +0100 |
| commit | 939e7430dee4e1c0595124b8ccd1c8b5db162dd8 (patch) | |
| tree | 08bbb96bbd9772d9a4255acc33f6e6fb8f3eedbd | |
| parent | 1aaa7698670cb980280e034d76f1bc1ca193af43 (diff) | |
arm64: tegra: Fix base address for SOR1 on Tegra194
The SOR1 hardware block's registers start at physical address 0x15b40000
as correctly specified by the unit-address, but the reg property lists a
wrong value, likely because it was copy-and-pasted from SOR0 but not
correctly updated.
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index d15c4f0bf499..a84a8b4dd598 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1078,7 +1078,7 @@ sor1: sor@15b40000 { compatible = "nvidia,tegra194-sor"; - reg = <0x155c0000 0x40000>; + reg = <0x15b40000 0x40000>; interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; clocks = <&bpmp TEGRA194_CLK_SOR1_REF>, <&bpmp TEGRA194_CLK_SOR1_OUT>, |