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authorTimur Tabi <timur@freescale.com>2009-03-03 06:23:47 +0000
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-03-11 17:10:16 +1100
commit9dca4efe88a8987b6e8496facc74de0555cc6617 (patch)
treec0278646a73c40911121e23f839379d18e40517e
parentf8ff96db9be035a01065a8528c016d125945479a (diff)
powerpc: Add defintion for MSR[GS] to list of MSR bits
Add macros for the GS (guest state) bit to the list of MSR bit definitions. On PowerPC cores that support embedded hypervisor mode, GS is cleared if the system is running in hypervisor state (and MSR[PR] is cleared), and set if it's running in guest state. See the Power ISA 2.06 specification for more information. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-rw-r--r--arch/powerpc/include/asm/reg_booke.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 597debe780bd..a56f4d61aa72 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -10,6 +10,7 @@
#define __ASM_POWERPC_REG_BOOKE_H__
/* Machine State Register (MSR) Fields */
+#define MSR_GS (1<<28) /* Guest state */
#define MSR_UCLE (1<<26) /* User-mode cache lock enable */
#define MSR_SPE (1<<25) /* Enable SPE */
#define MSR_DWE (1<<10) /* Debug Wait Enable */