diff options
| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-02-11 10:56:02 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-02-18 10:34:08 +0100 |
| commit | a08903f0b0020cacf60b29d4708d7ebec5b041a4 (patch) | |
| tree | 7696ea789884bfb4aa40e5b83afe17dd00e00226 | |
| parent | 5a1cb35ba37ada76ae486fbac7b249322dd1a5c3 (diff) | |
clk: renesas: rzg2l: Update error message
Update the error message in `rzg2l_mod_clock_endisable()` to provide
clearer debugging information. Instead of printing only the register
address, include both the `CLK_ON_R(reg)` offset and the corresponding
`clk` name (`%pC`). This enhances readability and aids in debugging
clock enable failures.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250211105603.195905-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 91928db411dc..a6b87cc66cbb 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1239,8 +1239,8 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) error = readl_poll_timeout_atomic(priv->base + CLK_MON_R(reg), value, value & bitmask, 0, 10); if (error) - dev_err(dev, "Failed to enable CLK_ON %p\n", - priv->base + CLK_ON_R(reg)); + dev_err(dev, "Failed to enable CLK_ON 0x%x/%pC\n", + CLK_ON_R(reg), hw->clk); return error; } |