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authorFlorian Sylvestre <fsylvestre@baylibre.com>2024-01-11 11:14:50 +0100
committerVinod Koul <vkoul@kernel.org>2024-02-07 15:02:13 +0100
commita41baa4f0f7d215f4c95a053f593d9b1378963f7 (patch)
tree9a206385e0a81fed38ae7348da450a5053b511b8
parent5398be49d7c1d88ead4aba82703fef35894b36ba (diff)
dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5
This adds the bindings, for the MIPI CD-PHY module v0.5 embedded in some Mediatek soc, such as the mt8365 Signed-off-by: Florian Sylvestre <fsylvestre@baylibre.com> Signed-off-by: Julien Stephan <jstephan@baylibre.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240111101504.468169-2-jstephan@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml79
-rw-r--r--MAINTAINERS6
2 files changed, 85 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml b/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
new file mode 100644
index 000000000000..2127a5732f73
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2023 MediaTek, BayLibre
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Sensor Interface MIPI CSI CD-PHY
+
+maintainers:
+ - Julien Stephan <jstephan@baylibre.com>
+ - Andy Hsieh <andy.hsieh@mediatek.com>
+
+description:
+ The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
+ receivers. The number of PHYs depends on the SoC model.
+ Depending on the SoC model, each PHYs can be either CD-PHY or D-PHY only
+ capable.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8365-csi-rx
+
+ reg:
+ maxItems: 1
+
+ num-lanes:
+ enum: [2, 3, 4]
+
+ '#phy-cells':
+ enum: [0, 1]
+ description: |
+ If the PHY doesn't support mode selection then #phy-cells must be 0 and
+ PHY mode is described using phy-type property.
+ If the PHY supports mode selection, then #phy-cells must be 1 and mode
+ is set in the PHY cells. Supported modes are:
+ - PHY_TYPE_DPHY
+ - PHY_TYPE_CPHY
+ See include/dt-bindings/phy/phy.h for constants.
+
+ phy-type:
+ description:
+ If the PHY doesn't support mode selection then this set the operating mode.
+ See include/dt-bindings/phy/phy.h for constants.
+ const: 10
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - compatible
+ - reg
+ - num-lanes
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/phy/phy.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ csi0_rx: phy@11c10000 {
+ compatible = "mediatek,mt8365-csi-rx";
+ reg = <0 0x11c10000 0 0x2000>;
+ num-lanes = <2>;
+ #phy-cells = <1>;
+ };
+
+ csi1_rx: phy@11c12000 {
+ compatible = "mediatek,mt8365-csi-rx";
+ reg = <0 0x11c12000 0 0x2000>;
+ phy-type = <PHY_TYPE_DPHY>;
+ num-lanes = <2>;
+ #phy-cells = <0>;
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 8d1052fa6a69..074182e6ab3a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13741,6 +13741,12 @@ F: Documentation/devicetree/bindings/media/mediatek-vpu.txt
F: drivers/media/platform/mediatek/vcodec/
F: drivers/media/platform/mediatek/vpu/
+MEDIATEK MIPI-CSI CDPHY DRIVER
+M: Julien Stephan <jstephan@baylibre.com>
+M: Andy Hsieh <andy.hsieh@mediatek.com>
+S: Supported
+F: Documentation/devicetree/bindings/phy/mediatek,mt8365-csi-rx.yaml
+
MEDIATEK MMC/SD/SDIO DRIVER
M: Chaotian Jing <chaotian.jing@mediatek.com>
S: Maintained